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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [mips/] [vr5400.s] - Blame information for rev 205

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Line No. Rev Author Line
1 205 julius 
        .text
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stuff:
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        .ent stuff
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        /* Integer instructions.  */
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        mul     $4,$5,$6
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        mulu    $4,$5,$6
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        mulhi   $4,$5,$6
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        mulhiu  $4,$5,$6
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        muls    $4,$5,$6
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        mulsu   $4,$5,$6
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        mulshi  $4,$5,$6
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        mulshiu $4,$5,$6
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        macc    $4,$5,$6
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        maccu   $4,$5,$6
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        macchi  $4,$5,$6
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        macchiu $4,$5,$6
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        msac    $4,$5,$6
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        msacu   $4,$5,$6
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        msachi  $4,$5,$6
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        msachiu $4,$5,$6
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        ror     $4,$5,25
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        rorv    $4,$5,$6
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        dror    $4,$5,25
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        dror    $4,$5,57        /* Should expand to dror32 $4,$5,25.  */
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        dror32  $4,$5,25
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        drorv   $4,$5,$6
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        /* Debug instructions.  */
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        dbreak
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        dret
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        mfdr    $3,$3
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        mtdr    $3,$3
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        /* Coprocessor 0 instructions, minus standard ISA 3 ones.
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           That leaves just the performance monitoring registers.  */
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        mfpc    $4,1
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        mfps    $4,1
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        mtpc    $4,1
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        mtps    $4,1
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        /* Multimedia instructions.  */
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        .macro  nsel2 op
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        /* Test each form of each vector opcode.  */
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        \op     $f0,$f2
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        \op     $f4,$f6[2]
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        \op     $f6,15
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        .if 0    /* Which is right?? */
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        /* Test negative numbers in immediate-value slot.  */
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        \op     $f4,-3
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        .else
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        /* Test that it's recognized as an unsigned field.  */
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        \op     $f4,31
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        .endif
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        .endm
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        .macro  nsel3 op
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        /* Test each form of each vector opcode.  */
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        \op     $f0,$f2,$f4
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        \op     $f2,$f4,$f6[2]
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        \op     $f6,$f4,15
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        .if 0   /* Which is right?? */
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        /* Test negative numbers in immediate-value slot.  */
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        \op     $f4,$f6,-3
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        .else
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        /* Test that it's recognized as an unsigned field.  */
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        \op     $f4,$f6,31
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        .endif
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        .endm
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        nsel3   add.ob
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        nsel3   and.ob
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        nsel2   c.eq.ob
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        nsel2   c.le.ob
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        nsel2   c.lt.ob
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        nsel3   max.ob
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        nsel3   min.ob
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        nsel3   mul.ob
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        nsel2   mula.ob
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        nsel2   mull.ob
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        nsel2   muls.ob
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        nsel2   mulsl.ob
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        nsel3   nor.ob
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        nsel3   or.ob
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        nsel3   pickf.ob
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        nsel3   pickt.ob
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        nsel3   sub.ob
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        nsel3   xor.ob
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        /* ALNI, SHFL: Vector only.  */
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        alni.ob         $f0,$f2,$f4,5
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        shfl.mixh.ob    $f0,$f2,$f4
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        shfl.mixl.ob    $f0,$f2,$f4
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        shfl.pach.ob    $f0,$f2,$f4
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        shfl.pacl.ob    $f0,$f2,$f4
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        /* SLL,SRL: Scalar or immediate.  */
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        sll.ob  $f2,$f4,$f6[3]
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        sll.ob  $f4,$f6,14
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        srl.ob  $f2,$f4,$f6[3]
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        srl.ob  $f4,$f6,14
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        /* RZU: Immediate, must be 0, 8, or 16.  */
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        rzu.ob  $f2,13
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        /* No selector.  */
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        rach.ob $f2
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        racl.ob $f2
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        racm.ob $f2
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        wach.ob $f2
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        wacl.ob $f2,$f4
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        ror     $4,$5,$6
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        rol     $4,$5,15
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        dror    $4,$5,$6
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        drol    $4,$5,31
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        drol    $4,$5,62
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        .space  8
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        .end stuff

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