OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [mn10300/] [am33_7.s] - Blame information for rev 205

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
        .text
2
        .am33
3
        cmp_add 4,r1,r2,r3
4
        cmp_add 4,r1,2,r3
5
        cmp_sub 4,r1,r2,r3
6
        cmp_sub 4,r1,2,r3
7
        cmp_mov 4,r1,r2,r3
8
        cmp_mov 4,r1,2,r3
9
        cmp_asr 4,r1,r2,r3
10
        cmp_asr 4,r1,2,r3
11
        cmp_lsr 4,r1,r2,r3
12
        cmp_lsr 4,r1,2,r3
13
        cmp_asl 4,r1,r2,r3
14
        cmp_asl 4,r1,2,r3
15
        sub_add 4,r1,r2,r3
16
        sub_add 4,r1,2,r3
17
        sub_sub 4,r1,r2,r3
18
        sub_sub 4,r1,2,r3
19
        sub_cmp 4,r1,r2,r3
20
        sub_cmp 4,r1,2,r3
21
        sub_mov 4,r1,r2,r3
22
        sub_mov 4,r1,2,r3
23
        sub_asr 4,r1,r2,r3
24
        sub_asr 4,r1,2,r3
25
        sub_lsr 4,r1,r2,r3
26
        sub_lsr 4,r1,2,r3
27
        sub_asl 4,r1,r2,r3
28
        sub_asl 4,r1,2,r3
29
        mov_add 4,r1,r2,r3
30
        mov_add 4,r1,2,r3
31
        mov_sub 4,r1,r2,r3
32
        mov_sub 4,r1,2,r3
33
        mov_cmp 4,r1,r2,r3
34
        mov_cmp 4,r1,2,r3
35
        mov_mov 4,r1,r2,r3
36
        mov_mov 4,r1,2,r3
37
        mov_asr 4,r1,r2,r3
38
        mov_asr 4,r1,2,r3
39
        mov_lsr 4,r1,r2,r3
40
        mov_lsr 4,r1,2,r3
41
        mov_asl 4,r1,r2,r3
42
        mov_asl 4,r1,2,r3
43
        and_add r4,r1,r2,r3
44
        and_add r4,r1,2,r3
45
        and_sub r4,r1,r2,r3
46
        and_sub r4,r1,2,r3
47
        and_cmp r4,r1,r2,r3
48
        and_cmp r4,r1,2,r3
49
        and_mov r4,r1,r2,r3
50
        and_mov r4,r1,2,r3
51
        and_asr r4,r1,r2,r3
52
        and_asr r4,r1,2,r3
53
        and_lsr r4,r1,r2,r3
54
        and_lsr r4,r1,2,r3
55
        and_asl r4,r1,r2,r3
56
        and_asl r4,r1,2,r3
57
        dmach_add r4,r1,r2,r3
58
        dmach_add r4,r1,2,r3
59
        dmach_sub r4,r1,r2,r3
60
        dmach_sub r4,r1,2,r3
61
        dmach_cmp r4,r1,r2,r3
62
        dmach_cmp r4,r1,2,r3
63
        dmach_mov r4,r1,r2,r3
64
        dmach_mov r4,r1,2,r3
65
        dmach_asr r4,r1,r2,r3
66
        dmach_asr r4,r1,2,r3
67
        dmach_lsr r4,r1,r2,r3
68
        dmach_lsr r4,r1,2,r3
69
        dmach_asl r4,r1,r2,r3
70
        dmach_asl r4,r1,2,r3
71
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.