OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [ppc/] [astest2.d] - Blame information for rev 438

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius 
#objdump: -Dr
2 
#name: PowerPC test 2
3 
 
4 
.*: +file format elf32-powerpc
5 
 
6 
Disassembly of section \.text:
7 
 
8 
0+0000000 :
9 
   0:   60 00 00 00     nop
10 
   4:   60 00 00 00     nop
11 
   8:   60 00 00 00     nop
12 
   c:   48 00 00 04     b       10
13 
  10:   48 00 00 08     b       18
14 
  14:   48 00 00 00     b       14
15 
                        14: R_PPC_REL24 x
16 
  18:   48 00 00 04     b       1c
17 
                        18: R_PPC_REL24 \.data\+0x4
18 
  1c:   48 00 00 00     b       1c
19 
                        1c: R_PPC_REL24 z
20 
  20:   48 00 00 14     b       34
21 
                        20: R_PPC_REL24 z\+0x14
22 
  24:   48 00 00 04     b       28
23 
  28:   48 00 00 00     b       28
24 
                        28: R_PPC_REL24 a
25 
  2c:   48 00 00 50     b       7c
26 
  30:   48 00 00 04     b       34
27 
                        30: R_PPC_REL24 a\+0x4
28 
  34:   48 00 00 4c     b       80
29 
  38:   48 00 00 00     b       38
30 
                        38: R_PPC_LOCAL24PC     a
31 
  3c:   48 00 00 40     b       7c
32 
  40:   00 00 00 40     \.long 0x40
33 
                        40: R_PPC_ADDR32        \.text\+0x40
34 
  44:   00 00 00 4c     \.long 0x4c
35 
                        44: R_PPC_ADDR32        \.text\+0x4c
36 
  48:   00 00 00 00     \.long 0x0
37 
                        48: R_PPC_REL32 x
38 
  4c:   00 00 00 04     \.long 0x4
39 
                        4c: R_PPC_REL32 x\+0x4
40 
  50:   00 00 00 00     \.long 0x0
41 
                        50: R_PPC_REL32 z
42 
  54:   00 00 00 04     \.long 0x4
43 
                        54: R_PPC_REL32 \.data\+0x4
44 
  58:   00 00 00 00     \.long 0x0
45 
                        58: R_PPC_ADDR32        x
46 
  5c:   00 00 00 04     \.long 0x4
47 
                        5c: R_PPC_ADDR32        \.data\+0x4
48 
  60:   00 00 00 00     \.long 0x0
49 
                        60: R_PPC_ADDR32        z
50 
  64:   ff ff ff fc     fnmsub  f31,f31,f31,f31
51 
                        64: R_PPC_ADDR32        x\+0xf+ffffffc
52 
  68:   00 00 00 00     \.long 0x0
53 
                        68: R_PPC_ADDR32        \.data
54 
  6c:   ff ff ff fc     fnmsub  f31,f31,f31,f31
55 
                        6c: R_PPC_ADDR32        z\+0xf+ffffffc
56 
  70:   00 00 00 08     \.long 0x8
57 
  74:   00 00 00 08     \.long 0x8
58 
 
59 
0+0000078 :
60 
  78:   00 00 00 00     \.long 0x0
61 
                        78: R_PPC_ADDR32        a
62 
 
63 
0+000007c :
64 
  7c:   00 00 00 7c     \.long 0x7c
65 
                        7c: R_PPC_ADDR32        \.text\+0x7c
66 
  80:   00 00 00 7c     \.long 0x7c
67 
                        80: R_PPC_ADDR32        \.text\+0x7c
68 
  84:   ff ff ff fc     fnmsub  f31,f31,f31,f31
69 
  88:   00 00 00 7e     \.long 0x7e
70 
                        88: R_PPC_ADDR32        \.text\+0x7e
71 
  8c:   00 00 00 00     \.long 0x0
72 
  90:   60 00 00 00     nop
73 
  94:   40 a5 ff fc     ble-    cr1,90
74 
  98:   41 a9 ff f8     bgt-    cr2,90
75 
  9c:   40 8d ff f4     ble\+    cr3,90
76 
  a0:   41 91 ff f0     bgt\+    cr4,90
77 
  a4:   40 95 00 10     ble-    cr5,b4
78 
  a8:   41 99 00 0c     bgt-    cr6,b4
79 
  ac:   40 bd 00 08     ble\+    cr7,b4
80 
  b0:   41 a1 00 04     bgt\+    b4
81 
Disassembly of section \.data:
82 
 
83 
0+0000000 :
84 
   0:   00 00 00 00     \.long 0x0
85 
 
86 
0+0000004 :
87 
   4:   00 00 00 00     \.long 0x0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.