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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [tic54x/] [opcodes.s] - Blame information for rev 215

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        ;; opcodes tests
        .text
        .mmregs
        .global X, Y, Z
        .global _opcodes, _opcodes_end
        .label _opcodes_load
_opcodes:
        abdst   *ar3+, *ar4+
        abs     a
        abs     a,b
        add     *ar0+, a        ; Smem, src
        add     *ar1+, ts, a    ; Smem, TS, src 
        add     *ar2+, 16, a    ; Smem, 16, src [,dst] 
        add     *ar3+, a, b     ; Smem [,SHIFT], src [,dst] (-16<=SHIFT<=15)
 
        add     *ar4+, 1, a     ; Xmem, SHFT, src (0<=SHFT<=15) 
        add     *ar3+, *ar4+, a ; Xmem, Ymem, dst
        add     #-32768, a      ; #lk [,SHFT], src [,dst] (-32768<=lk<=32767)
 
        add     #0,16,a,b        ; #lk, 16, src, [,dst]
 
        add     a,-16,b         ; src [,SHIFT][,dst]
        add     a,asm,b         ; src, ASM [,dst] 
        addc    *ar0+,a
        addm    #1,*ar1+
 
        adds    *ar2+,a
        and     *ar3+,a         ; Smem,src
        and     #1,1,a,b        ; #lk[,SHFT],src[,dst]
 
        and     #1,#16,a,b      ; #lk,16,src[,dst]
 
        and     a               ; src[,SHIFT][,dst]
        andm    #1,*ar0+
 
        b       _opcodes_end
 
        bd      #_opcodes_end
        nop
        nop
 
        bacc    a
        baccd   b
        nop
        nop
 
        banz    _opcodes_end,*ar1+
 
        banzd   _opcodes_end,*ar2+
        nop
        nop
 
        bc      _opcodes_end, AEQ,AOV
 
        bcd     _opcodes_end, BIO,C,TC
        nop
        nop
 
        bit     *ar3+,1
        bitf    *ar4+,#-1
 
        bitt    *ar5+
        cala    a
        calad   b
        nop
        nop
 
        call    _opcodes_end
 
        calld   _opcodes_end
        nop
        nop
 
        cc      _opcodes_end, tc
 
        ccd     _opcodes_end, aeq
        nop
        nop
 
        cmpl    b,a
        cmpm    *ar0+,#1
 
        cmpr    1,ar1
        cmps    a,*ar2+
        dadd    *ar3-, a, b
        dadst   *ar4-, a
        delay   *ar5+
        dld     *ar6-, a
        drsub   *ar7-, b
        dsadt   *ar0-, a
        dst     a, *ar1-
        dsub    *ar2-, b
        dsubt   *ar3-, a
        exp     a
        firs    *ar3+,*ar4+,_opcodes_end
 
        frame   -128
        idle    2
        intr    15
        ld      *ar0+,a                 ; Smem,dst
        ld      *ar1+,ts,a              ; Smem,TS,dst
        ld      *ar2+,16,a              ; Smem,16,dst
        ld      *ar3+,1,a               ; Smem[,SHIFT],dst
 
        ld      *ar4+,1,a               ; Xmem,SHFT,dst
        ld      #1,b                    ; #K,dst
        ld      #32767,1,a              ; #lk,[,SHFT],dst
 
        ld      #32767,16,a             ; #lk,16,dst
 
        ld      a,asm,b                 ; src,ASM[,dst]
        ld      a,1,b                   ; src[,SHIFT],dst
        ld      *ar0+,t
        ld      *ar1+,dp
        ld      #_opcodes_end,dp        ; FIXME try to print label on disasm
                                        ; note: TI assembler doesn't shift 
                                        ; the address encoding. 
        ld      #15,asm
        ld      #7,arp
        ld      *ar2+,asm
        ldm     ar3,a
        ld      *ar2+,a || mac  *ar3+,b ; single-line parallell
        ld      *ar4+,b || macr *ar5+,a ; with optional DST_ specified
        ld      *ar2+,a                 ; double-line parallel
        || mas  *ar3+
        ld      *ar4+,b                 ; parallel spans
                                        ; inserted line
        || masr *ar5+
        ldr     *ar6+,a
        ldu     *ar7+,a
        lms     *ar3+,*ar4+
        ltd     *ar0+
        mac     *ar1+,a
        macr    *ar2+,a
        mac     *ar2+,*ar3+,a,b
        macr    *ar4+,*ar5+,a,b
        mac     #1,a,b
 
        mac     *ar0+,#1,a
 
        maca    *ar1+                   ; *ar6+,b (valid)
        maca    t,a,b
        macd    *ar2+,_opcodes_end,a
 
        macp    *ar3+,_opcodes_end,a
 
        macsu   *ar4+,*ar5+,a
        mar     *ar6+
        mas     *ar7+,a
        masr    *ar0+,a
        mas     *ar3+,*ar4+,a,b
        masr    *ar2+,*ar5+,a,b
        masa    *ar6+           ; *ar6+,b (valid)
        masa    t,a,b
        masar   t,a
        max     a
        min     b
        mpy     *ar7+,a
        mpy     *ar3+,*ar4+,b
        mpy     *ar0,#1,a
 
        mpy     #1,a
 
        mpya    *ar0+
        mpya    b
        mpyu    *ar1+,b
        mvdd    *ar2+,*ar3+
        mvdk    *ar4+,X
 
        mvdm    X,ar5
 
        mvdp    *ar6+,_opcodes_end
 
        mvkd    X,*ar7+
 
        mvmd    ar0,X
 
        mvmm    ar1,ar2
        mvpd    _opcodes_end,*ar3+
 
        neg     a,b
 
        nop
        norm    a
        or      *ar0+,b
        or      #(3+4),b
 
        or      #1,16,b
 
        or      b
        orm     #1,*ar1+
 
        poly    *ar2+
        popd    *ar3+
        popm    ar4
        portr   0,*ar5+
 
        portw   *ar6+,0
 
        pshd    *ar7+
        pshm    ar0
        rc      ANEQ
        rcd     AGT
        reada   *ar1+
        reset
        ret
        retd
        nop
        nop
        rete
        reted
        nop
        nop
        retf
        retfd
        rol     a
        roltc   a
        ror     b
        rpt     *ar0+
        nop
        rpt     #32
        nop
        rpt     #65535
        nop
        rptb    _opcodes_end-1
        nop
        rptbd   _opcodes_end-1
        nop
        nop
        rptz    a,#32767
        nop
        rsbx    1,15
        saccd   a,*ar3+,ALT
        sat     a
        sfta    a,15,b
        sftc    a
        sftl    a,15
        sqdst   *ar2+,*ar3+
        squr    *ar4+,b
        squr    a,a
        squra   *ar5+,a
        squrs   *ar6+,a
        srccd   *ar2+,ALEQ
        ssbx    1,15
        st      t,*ar0+
        st      trn,*ar1+
        st      #32767,*ar2+
 
        sth     a,*ar3+
        sth     a,asm,*ar4+
        sth     a,15,*ar5+
        sth     a,-16,*ar6+
 
        stl     a,*ar7+
        stl     a,asm,*ar0+
        stl     a,15,*ar1+
        stl     a,15,*ar2+
 
        stlm    a,ar3
        stm     #32767,ar4
 
        st      a,*ar5+
        || add  *ar4+,b
        st      a,*ar3+
        || ld   *ar2+,b
        st      a,*ar3+
        || ld   *ar4+,t
        st      a,*ar5+
        || mac  *ar2+,b
        st      a,*ar3+
        || masr *ar4+,b
        st      a,*ar3+
        || mpy  *ar4+,b
        st      a,*ar3+
        || sub  *ar4+,b
        strcd   *ar5+,BEQ
        sub     *ar0+,a
        sub     *ar1+,ts,a
        sub     *ar2+,16,a,b
        sub     *ar3+,a,b
 
        sub     *ar4+,15,a
        sub     *ar5+,*ar4+,b
        sub     #1,15,a,b
 
        sub     #1,16,a,b
 
        sub     a,-16,b
        sub     a,asm,b
        subb    *ar0+,a
        subc    *ar1+,a
        subs    *ar2+,a
        trap    15
        writa   *ar3+
        xc      1,AOV
        xor     *ar4+,a
        xor     #1,a
 
        xor     #1,16,a
 
        xor     a,1,b
        xorm    #1,*ar5+
_opcodes_end:
        .data
X:      .word   0
Y:      .word   1
*       .word   Z
        .end
 

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [tic54x/] [opcodes.s] - Blame information for rev 215

Line No.	Rev	Author	Line
1	215	jeremybenn	`;; opcodes tests`
2			`.text`
3			`.mmregs`
4			`.global X, Y, Z`
5			`.global _opcodes, _opcodes_end`
6			`.label _opcodes_load`
7			`_opcodes:`
8			`abdst ar3+, ar4+`
9			`abs a`
10			`abs a,b`
11			`add *ar0+, a ; Smem, src`
12			`add *ar1+, ts, a ; Smem, TS, src`
13			`add *ar2+, 16, a ; Smem, 16, src [,dst]`
14			`add *ar3+, a, b ; Smem [,SHIFT], src [,dst] (-16<=SHIFT<=15)`
15
16			`add *ar4+, 1, a ; Xmem, SHFT, src (0<=SHFT<=15)`
17			`add ar3+, ar4+, a ; Xmem, Ymem, dst`
18			`add #-32768, a ; #lk [,SHFT], src [,dst] (-32768<=lk<=32767)`
19
20			`add #0,16,a,b ; #lk, 16, src, [,dst]`
21
22			`add a,-16,b ; src [,SHIFT][,dst]`
23			`add a,asm,b ; src, ASM [,dst]`
24			`addc *ar0+,a`
25			`addm #1,*ar1+`
26
27			`adds *ar2+,a`
28			`and *ar3+,a ; Smem,src`
29			`and #1,1,a,b ; #lk[,SHFT],src[,dst]`
30
31			`and #1,#16,a,b ; #lk,16,src[,dst]`
32
33			`and a ; src[,SHIFT][,dst]`
34			`andm #1,*ar0+`
35
36			`b _opcodes_end`
37
38			`bd #_opcodes_end`
39			`nop`
40			`nop`
41
42			`bacc a`
43			`baccd b`
44			`nop`
45			`nop`
46
47			`banz _opcodes_end,*ar1+`
48
49			`banzd _opcodes_end,*ar2+`
50			`nop`
51			`nop`
52
53			`bc _opcodes_end, AEQ,AOV`
54
55			`bcd _opcodes_end, BIO,C,TC`
56			`nop`
57			`nop`
58
59			`bit *ar3+,1`
60			`bitf *ar4+,#-1`
61
62			`bitt *ar5+`
63			`cala a`
64			`calad b`
65			`nop`
66			`nop`
67
68			`call _opcodes_end`
69
70			`calld _opcodes_end`
71			`nop`
72			`nop`
73
74			`cc _opcodes_end, tc`
75
76			`ccd _opcodes_end, aeq`
77			`nop`
78			`nop`
79
80			`cmpl b,a`
81			`cmpm *ar0+,#1`
82
83			`cmpr 1,ar1`
84			`cmps a,*ar2+`
85			`dadd *ar3-, a, b`
86			`dadst *ar4-, a`
87			`delay *ar5+`
88			`dld *ar6-, a`
89			`drsub *ar7-, b`
90			`dsadt *ar0-, a`
91			`dst a, *ar1-`
92			`dsub *ar2-, b`
93			`dsubt *ar3-, a`
94			`exp a`
95			`firs ar3+,ar4+,_opcodes_end`
96
97			`frame -128`
98			`idle 2`
99			`intr 15`
100			`ld *ar0+,a ; Smem,dst`
101			`ld *ar1+,ts,a ; Smem,TS,dst`
102			`ld *ar2+,16,a ; Smem,16,dst`
103			`ld *ar3+,1,a ; Smem[,SHIFT],dst`
104
105			`ld *ar4+,1,a ; Xmem,SHFT,dst`
106			`ld #1,b ; #K,dst`
107			`ld #32767,1,a ; #lk,[,SHFT],dst`
108
109			`ld #32767,16,a ; #lk,16,dst`
110
111			`ld a,asm,b ; src,ASM[,dst]`
112			`ld a,1,b ; src[,SHIFT],dst`
113			`ld *ar0+,t`
114			`ld *ar1+,dp`
115			`ld #_opcodes_end,dp ; FIXME try to print label on disasm`
116			`; note: TI assembler doesn't shift`
117			`; the address encoding.`
118			`ld #15,asm`
119			`ld #7,arp`
120			`ld *ar2+,asm`
121			`ldm ar3,a`
122			`ld ar2+,a \|\| mac ar3+,b ; single-line parallell`
123			`ld ar4+,b \|\| macr ar5+,a ; with optional DST_ specified`
124			`ld *ar2+,a ; double-line parallel`
125			`\|\| mas *ar3+`
126			`ld *ar4+,b ; parallel spans`
127			`; inserted line`
128			`\|\| masr *ar5+`
129			`ldr *ar6+,a`
130			`ldu *ar7+,a`
131			`lms ar3+,ar4+`
132			`ltd *ar0+`
133			`mac *ar1+,a`
134			`macr *ar2+,a`
135			`mac ar2+,ar3+,a,b`
136			`macr ar4+,ar5+,a,b`
137			`mac #1,a,b`
138
139			`mac *ar0+,#1,a`
140
141			`maca ar1+ ; ar6+,b (valid)`
142			`maca t,a,b`
143			`macd *ar2+,_opcodes_end,a`
144
145			`macp *ar3+,_opcodes_end,a`
146
147			`macsu ar4+,ar5+,a`
148			`mar *ar6+`
149			`mas *ar7+,a`
150			`masr *ar0+,a`
151			`mas ar3+,ar4+,a,b`
152			`masr ar2+,ar5+,a,b`
153			`masa ar6+ ; ar6+,b (valid)`
154			`masa t,a,b`
155			`masar t,a`
156			`max a`
157			`min b`
158			`mpy *ar7+,a`
159			`mpy ar3+,ar4+,b`
160			`mpy *ar0,#1,a`
161
162			`mpy #1,a`
163
164			`mpya *ar0+`
165			`mpya b`
166			`mpyu *ar1+,b`
167			`mvdd ar2+,ar3+`
168			`mvdk *ar4+,X`
169
170			`mvdm X,ar5`
171
172			`mvdp *ar6+,_opcodes_end`
173
174			`mvkd X,*ar7+`
175
176			`mvmd ar0,X`
177
178			`mvmm ar1,ar2`
179			`mvpd _opcodes_end,*ar3+`
180
181			`neg a,b`
182
183			`nop`
184			`norm a`
185			`or *ar0+,b`
186			`or #(3+4),b`
187
188			`or #1,16,b`
189
190			`or b`
191			`orm #1,*ar1+`
192
193			`poly *ar2+`
194			`popd *ar3+`
195			`popm ar4`
196			`portr 0,*ar5+`
197
198			`portw *ar6+,0`
199
200			`pshd *ar7+`
201			`pshm ar0`
202			`rc ANEQ`
203			`rcd AGT`
204			`reada *ar1+`
205			`reset`
206			`ret`
207			`retd`
208			`nop`
209			`nop`
210			`rete`
211			`reted`
212			`nop`
213			`nop`
214			`retf`
215			`retfd`
216			`rol a`
217			`roltc a`
218			`ror b`
219			`rpt *ar0+`
220			`nop`
221			`rpt #32`
222			`nop`
223			`rpt #65535`
224			`nop`
225			`rptb _opcodes_end-1`
226			`nop`
227			`rptbd _opcodes_end-1`
228			`nop`
229			`nop`
230			`rptz a,#32767`
231			`nop`
232			`rsbx 1,15`
233			`saccd a,*ar3+,ALT`
234			`sat a`
235			`sfta a,15,b`
236			`sftc a`
237			`sftl a,15`
238			`sqdst ar2+,ar3+`
239			`squr *ar4+,b`
240			`squr a,a`
241			`squra *ar5+,a`
242			`squrs *ar6+,a`
243			`srccd *ar2+,ALEQ`
244			`ssbx 1,15`
245			`st t,*ar0+`
246			`st trn,*ar1+`
247			`st #32767,*ar2+`
248
249			`sth a,*ar3+`
250			`sth a,asm,*ar4+`
251			`sth a,15,*ar5+`
252			`sth a,-16,*ar6+`
253
254			`stl a,*ar7+`
255			`stl a,asm,*ar0+`
256			`stl a,15,*ar1+`
257			`stl a,15,*ar2+`
258
259			`stlm a,ar3`
260			`stm #32767,ar4`
261
262			`st a,*ar5+`
263			`\|\| add *ar4+,b`
264			`st a,*ar3+`
265			`\|\| ld *ar2+,b`
266			`st a,*ar3+`
267			`\|\| ld *ar4+,t`
268			`st a,*ar5+`
269			`\|\| mac *ar2+,b`
270			`st a,*ar3+`
271			`\|\| masr *ar4+,b`
272			`st a,*ar3+`
273			`\|\| mpy *ar4+,b`
274			`st a,*ar3+`
275			`\|\| sub *ar4+,b`
276			`strcd *ar5+,BEQ`
277			`sub *ar0+,a`
278			`sub *ar1+,ts,a`
279			`sub *ar2+,16,a,b`
280			`sub *ar3+,a,b`
281
282			`sub *ar4+,15,a`
283			`sub ar5+,ar4+,b`
284			`sub #1,15,a,b`
285
286			`sub #1,16,a,b`
287
288			`sub a,-16,b`
289			`sub a,asm,b`
290			`subb *ar0+,a`
291			`subc *ar1+,a`
292			`subs *ar2+,a`
293			`trap 15`
294			`writa *ar3+`
295			`xc 1,AOV`
296			`xor *ar4+,a`
297			`xor #1,a`
298
299			`xor #1,16,a`
300
301			`xor a,1,b`
302			`xorm #1,*ar5+`
303			`_opcodes_end:`
304			`.data`
305			`X: .word 0`
306			`Y: .word 1`
307			`* .word Z`
308			`.end`
309