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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [tic54x/] [opcodes.s] - Blame information for rev 215

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1 215 jeremybenn
        ;; opcodes tests
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        .text
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        .mmregs
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        .global X, Y, Z
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        .global _opcodes, _opcodes_end
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        .label _opcodes_load
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_opcodes:
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        abdst   *ar3+, *ar4+
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        abs     a
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        abs     a,b
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        add     *ar0+, a        ; Smem, src
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        add     *ar1+, ts, a    ; Smem, TS, src 
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        add     *ar2+, 16, a    ; Smem, 16, src [,dst] 
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        add     *ar3+, a, b     ; Smem [,SHIFT], src [,dst] (-16<=SHIFT<=15)
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        add     *ar4+, 1, a     ; Xmem, SHFT, src (0<=SHFT<=15) 
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        add     *ar3+, *ar4+, a ; Xmem, Ymem, dst
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        add     #-32768, a      ; #lk [,SHFT], src [,dst] (-32768<=lk<=32767)
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        add     #0,16,a,b        ; #lk, 16, src, [,dst]
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        add     a,-16,b         ; src [,SHIFT][,dst]
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        add     a,asm,b         ; src, ASM [,dst] 
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        addc    *ar0+,a
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        addm    #1,*ar1+
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        adds    *ar2+,a
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        and     *ar3+,a         ; Smem,src
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        and     #1,1,a,b        ; #lk[,SHFT],src[,dst]
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        and     #1,#16,a,b      ; #lk,16,src[,dst]
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        and     a               ; src[,SHIFT][,dst]
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        andm    #1,*ar0+
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        b       _opcodes_end
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        bd      #_opcodes_end
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        nop
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        nop
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        bacc    a
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        baccd   b
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        nop
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        nop
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        banz    _opcodes_end,*ar1+
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        banzd   _opcodes_end,*ar2+
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        nop
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        nop
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        bc      _opcodes_end, AEQ,AOV
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        bcd     _opcodes_end, BIO,C,TC
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        nop
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        nop
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59
        bit     *ar3+,1
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        bitf    *ar4+,#-1
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        bitt    *ar5+
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        cala    a
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        calad   b
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        nop
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        nop
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        call    _opcodes_end
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        calld   _opcodes_end
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        nop
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        nop
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        cc      _opcodes_end, tc
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        ccd     _opcodes_end, aeq
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        nop
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        nop
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        cmpl    b,a
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        cmpm    *ar0+,#1
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        cmpr    1,ar1
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        cmps    a,*ar2+
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        dadd    *ar3-, a, b
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        dadst   *ar4-, a
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        delay   *ar5+
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        dld     *ar6-, a
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        drsub   *ar7-, b
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        dsadt   *ar0-, a
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        dst     a, *ar1-
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        dsub    *ar2-, b
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        dsubt   *ar3-, a
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        exp     a
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        firs    *ar3+,*ar4+,_opcodes_end
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        frame   -128
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        idle    2
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        intr    15
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        ld      *ar0+,a                 ; Smem,dst
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        ld      *ar1+,ts,a              ; Smem,TS,dst
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        ld      *ar2+,16,a              ; Smem,16,dst
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        ld      *ar3+,1,a               ; Smem[,SHIFT],dst
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        ld      *ar4+,1,a               ; Xmem,SHFT,dst
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        ld      #1,b                    ; #K,dst
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        ld      #32767,1,a              ; #lk,[,SHFT],dst
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        ld      #32767,16,a             ; #lk,16,dst
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        ld      a,asm,b                 ; src,ASM[,dst]
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        ld      a,1,b                   ; src[,SHIFT],dst
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        ld      *ar0+,t
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        ld      *ar1+,dp
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        ld      #_opcodes_end,dp        ; FIXME try to print label on disasm
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                                        ; note: TI assembler doesn't shift 
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                                        ; the address encoding. 
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        ld      #15,asm
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        ld      #7,arp
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        ld      *ar2+,asm
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        ldm     ar3,a
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        ld      *ar2+,a || mac  *ar3+,b ; single-line parallell
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        ld      *ar4+,b || macr *ar5+,a ; with optional DST_ specified
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        ld      *ar2+,a                 ; double-line parallel
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        || mas  *ar3+
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        ld      *ar4+,b                 ; parallel spans
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                                        ; inserted line
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        || masr *ar5+
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        ldr     *ar6+,a
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        ldu     *ar7+,a
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        lms     *ar3+,*ar4+
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        ltd     *ar0+
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        mac     *ar1+,a
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        macr    *ar2+,a
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        mac     *ar2+,*ar3+,a,b
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        macr    *ar4+,*ar5+,a,b
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        mac     #1,a,b
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        mac     *ar0+,#1,a
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        maca    *ar1+                   ; *ar6+,b (valid)
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        maca    t,a,b
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        macd    *ar2+,_opcodes_end,a
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        macp    *ar3+,_opcodes_end,a
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        macsu   *ar4+,*ar5+,a
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        mar     *ar6+
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        mas     *ar7+,a
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        masr    *ar0+,a
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        mas     *ar3+,*ar4+,a,b
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        masr    *ar2+,*ar5+,a,b
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        masa    *ar6+           ; *ar6+,b (valid)
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        masa    t,a,b
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        masar   t,a
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        max     a
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        min     b
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        mpy     *ar7+,a
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        mpy     *ar3+,*ar4+,b
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        mpy     *ar0,#1,a
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162
        mpy     #1,a
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        mpya    *ar0+
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        mpya    b
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        mpyu    *ar1+,b
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        mvdd    *ar2+,*ar3+
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        mvdk    *ar4+,X
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170
        mvdm    X,ar5
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172
        mvdp    *ar6+,_opcodes_end
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        mvkd    X,*ar7+
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        mvmd    ar0,X
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178
        mvmm    ar1,ar2
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        mvpd    _opcodes_end,*ar3+
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181
        neg     a,b
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        nop
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        norm    a
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        or      *ar0+,b
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        or      #(3+4),b
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188
        or      #1,16,b
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190
        or      b
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        orm     #1,*ar1+
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193
        poly    *ar2+
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        popd    *ar3+
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        popm    ar4
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        portr   0,*ar5+
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198
        portw   *ar6+,0
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        pshd    *ar7+
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        pshm    ar0
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        rc      ANEQ
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        rcd     AGT
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        reada   *ar1+
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        reset
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        ret
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        retd
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        nop
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        nop
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        rete
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        reted
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        nop
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        nop
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        retf
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        retfd
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        rol     a
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        roltc   a
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        ror     b
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        rpt     *ar0+
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        nop
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        rpt     #32
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        nop
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        rpt     #65535
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        nop
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        rptb    _opcodes_end-1
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        nop
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        rptbd   _opcodes_end-1
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        nop
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        nop
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        rptz    a,#32767
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        nop
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        rsbx    1,15
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        saccd   a,*ar3+,ALT
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        sat     a
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        sfta    a,15,b
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        sftc    a
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        sftl    a,15
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        sqdst   *ar2+,*ar3+
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        squr    *ar4+,b
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        squr    a,a
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        squra   *ar5+,a
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        squrs   *ar6+,a
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        srccd   *ar2+,ALEQ
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        ssbx    1,15
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        st      t,*ar0+
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        st      trn,*ar1+
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        st      #32767,*ar2+
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        sth     a,*ar3+
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        sth     a,asm,*ar4+
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        sth     a,15,*ar5+
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        sth     a,-16,*ar6+
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        stl     a,*ar7+
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        stl     a,asm,*ar0+
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        stl     a,15,*ar1+
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        stl     a,15,*ar2+
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        stlm    a,ar3
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        stm     #32767,ar4
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262
        st      a,*ar5+
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        || add  *ar4+,b
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        st      a,*ar3+
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        || ld   *ar2+,b
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        st      a,*ar3+
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        || ld   *ar4+,t
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        st      a,*ar5+
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        || mac  *ar2+,b
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        st      a,*ar3+
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        || masr *ar4+,b
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        st      a,*ar3+
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        || mpy  *ar4+,b
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        st      a,*ar3+
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        || sub  *ar4+,b
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        strcd   *ar5+,BEQ
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        sub     *ar0+,a
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        sub     *ar1+,ts,a
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        sub     *ar2+,16,a,b
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        sub     *ar3+,a,b
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282
        sub     *ar4+,15,a
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        sub     *ar5+,*ar4+,b
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        sub     #1,15,a,b
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286
        sub     #1,16,a,b
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288
        sub     a,-16,b
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        sub     a,asm,b
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        subb    *ar0+,a
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        subc    *ar1+,a
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        subs    *ar2+,a
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        trap    15
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        writa   *ar3+
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        xc      1,AOV
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        xor     *ar4+,a
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        xor     #1,a
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299
        xor     #1,16,a
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301
        xor     a,1,b
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        xorm    #1,*ar5+
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_opcodes_end:
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        .data
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X:      .word   0
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Y:      .word   1
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*       .word   Z
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        .end
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