OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [include/] [gdb/] [sim-m32c.h] - Blame information for rev 373

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
/* This file defines the interface between the m32c simulator and gdb.
2
   Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
3
 
4
   This file is part of GDB.
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 3 of the License, or
9
   (at your option) any later version.
10
 
11
   This program is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
18
 
19
#ifndef SIM_M32C_H
20
#define SIM_M32C_H
21
 
22
enum m32c_sim_reg {
23
  m32c_sim_reg_r0_bank0,
24
  m32c_sim_reg_r1_bank0,
25
  m32c_sim_reg_r2_bank0,
26
  m32c_sim_reg_r3_bank0,
27
  m32c_sim_reg_a0_bank0,
28
  m32c_sim_reg_a1_bank0,
29
  m32c_sim_reg_fb_bank0,
30
  m32c_sim_reg_sb_bank0,
31
  m32c_sim_reg_r0_bank1,
32
  m32c_sim_reg_r1_bank1,
33
  m32c_sim_reg_r2_bank1,
34
  m32c_sim_reg_r3_bank1,
35
  m32c_sim_reg_a0_bank1,
36
  m32c_sim_reg_a1_bank1,
37
  m32c_sim_reg_fb_bank1,
38
  m32c_sim_reg_sb_bank1,
39
  m32c_sim_reg_usp,
40
  m32c_sim_reg_isp,
41
  m32c_sim_reg_pc,
42
  m32c_sim_reg_intb,
43
  m32c_sim_reg_flg,
44
  m32c_sim_reg_svf,
45
  m32c_sim_reg_svp,
46
  m32c_sim_reg_vct,
47
  m32c_sim_reg_dmd0,
48
  m32c_sim_reg_dmd1,
49
  m32c_sim_reg_dct0,
50
  m32c_sim_reg_dct1,
51
  m32c_sim_reg_drc0,
52
  m32c_sim_reg_drc1,
53
  m32c_sim_reg_dma0,
54
  m32c_sim_reg_dma1,
55
  m32c_sim_reg_dsa0,
56
  m32c_sim_reg_dsa1,
57
  m32c_sim_reg_dra0,
58
  m32c_sim_reg_dra1,
59
  m32c_sim_reg_num_regs
60
};
61
 
62
#endif /* SIM_M32C_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.