OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [ld/] [scripttempl/] [tic4xcoff.sc] - Blame information for rev 438

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
# In microcomputer (MC) mode, the vectors are mapped into the on-chip ROM,
2
# otherwise in microprocessor (MP) mode the vectors are mapped to address 0
3
# on the external bus.  In MC mode, the on-chip ROM contains a bootloader program
4
# that loads the internal RAM from the serial port or external ROM.
5
#
6
# Common configurations:
7
# 1. MC mode, no external memory (serial boot).
8
# 2. MC mode, external RAM (serial boot).
9
# 3. MC mode, external ROM.
10
# 4. MC mode, external ROM, external RAM.
11
# 5. MP mode, external ROM.
12
# 6. MP mode, external ROM, external RAM.
13
# 7. MP mode, external RAM (dual-port with hosting CPU or external debugger).
14
#
15
# Config  TEXT     DATA/BSS
16
# 1.      INT_RAM  INT_RAM   (mcmode,onchip)
17
# 2.      EXT_RAM  EXT_RAM   (mcmode,extram)
18
# 3.      INT_RAM  INT_RAM   (mcmode,onchip)
19
# 4.      EXT_RAM  EXT_RAM   (mcmode,extram)
20
# 5.      EXT_ROM  INT_RAM   (mpmode,onchip,extrom)
21
# 6.      EXT_ROM  EXT_RAM   (mpmode,extram,extrom)
22
# 7.      EXT_RAM  EXT_RAM   (mpmode,extram)
23
#
24
# In MC mode, TEXT and DATA are copied into RAM by the bootloader.
25
#
26
# In MP mode with external ROM, DATA needs to be copied into RAM at boot time.
27
#
28
# If there is external RAM it is better to use that and reserve the internal RAM
29
# for data buffers.  However, the address of the external RAM needs to be specified.
30
#
31
# This emulation assumes config 7.
32
 
33
case $OUTPUT_ARCH in
34
  tic3x) OUTPUT_ARCHNAME="TMS320C3x" ;;
35
  tic4x) OUTPUT_ARCHNAME="TMS320C4x" ;;
36
esac
37
 
38
case $ONCHIP in
39
  yes) RAM=RAM;
40
       STACK_SIZE_DEFAULT=128;
41
       HEAP_SIZE_DEFAULT=0;
42
       ;;
43
  *)   RAM=EXT0;
44
       STACK_SIZE_DEFAULT=0x1000;
45
       HEAP_SIZE_DEFAULT=0x4000;
46
       ;;
47
esac
48
 
49
TEXT_MEMORY=$RAM;
50
DATA_MEMORY=$RAM;
51
 
52
 
53
MEMORY_DEF="
54
/* C30 memory space.  */
55
MEMORY
56
{
57
   EXT0  :  org = 0x0000000, len = 0x800000  /* External address bus.  */
58
   XBUS  :  org = 0x0800000, len = 0x002000  /* Expansion bus.         */
59
   IOBUS :  org = 0x0804000, len = 0x002000  /* I/O BUS.               */
60
   RAM0  :  org = 0x0809800, len = 0x000400  /* Internal RAM block 0.  */
61
   RAM1  :  org = 0x0809a00, len = 0x000400  /* Internal RAM block 1.  */
62
   RAM   :  org = 0x0809800, len = 0x000800  /* Internal RAM.          */
63
   EXT1  :  org = 0x080a000, len = 0x7f6000  /* External address bus.  */
64
}
65
"
66
 
67
test -z "$ENTRY" && ENTRY=_start
68
 
69
cat <
70
${RELOCATING+/* Linker script for $OUTPUT_ARCHNAME executable.  */}
71
${RELOCATING-/* Linker script for $OUTPUT_ARCHNAME object file (ld -r).  */}
72
 
73
OUTPUT_FORMAT("${OUTPUT_FORMAT}")
74
OUTPUT_ARCH("${OUTPUT_ARCH}")
75
${LIB_SEARCH_DIRS}
76
${RELOCATING+ENTRY (${ENTRY})}
77
 
78
${RELOCATING+ __HEAP_SIZE = DEFINED(__HEAP_SIZE) ? __HEAP_SIZE : ${HEAP_SIZE_DEFAULT};}
79
${RELOCATING+ __STACK_SIZE  = DEFINED(__STACK_SIZE)  ? __STACK_SIZE  : ${STACK_SIZE_DEFAULT};}
80
 
81
${RELOCATING+${MEMORY_DEF}}
82
 
83
/* In the small memory model the .data and .bss sections must be contiguous
84
   when loaded and fit within the same page.   The DP register is loaded
85
   with the page address.  */
86
 
87
SECTIONS
88
{
89
  /* Reset, interrupt, and trap vectors.  */
90
  .vectors ${RELOCATING+ 0} : {
91
    *(.vectors)
92
  } ${RELOCATING+ > ${TEXT_MEMORY}}
93
  /* Constants.  */
94
  .const : {
95
    *(.const)
96
  } ${RELOCATING+ > ${TEXT_MEMORY}}
97
  /* Program code.  */
98
  .text : {
99
    ${RELOCATING+  __text =  .;}
100
    ${RELOCATING+ *(.init)}
101
    *(.text)
102
    ${CONSTRUCTING+ ___CTOR_LIST__ = .;}
103
    ${CONSTRUCTING+ LONG(___CTOR_END__ - ___CTOR_LIST__ - 2)}
104
    ${CONSTRUCTING+ *(.ctors)}
105
    ${CONSTRUCTING+ LONG(0);}
106
    ${CONSTRUCTING+ ___CTOR_END__  = .;}
107
    ${CONSTRUCTING+ ___DTOR_LIST__ = .;}
108
    ${CONSTRUCTING+ LONG(___DTOR_END__ - ___DTOR_LIST__ - 2)}
109
    ${CONSTRUCTING+ *(.dtors)}
110
    ${CONSTRUCTING+ LONG(0)}
111
    ${CONSTRUCTING+ ___DTOR_END__  = .;}
112
    ${RELOCATING+ *(.fini)}
113
    ${RELOCATING+  __etext =  .;}
114
  } ${RELOCATING+ > ${TEXT_MEMORY}}
115
  /* Global initialised variables.  */
116
  .data :
117
  {
118
    ${RELOCATING+  __data  =  .;}
119
    *(.data)
120
    ${RELOCATING+  __edata  = .;}
121
  } ${RELOCATING+ > ${DATA_MEMORY}}
122
  /* Global uninitialised variables.  */
123
  .bss : {
124
    ${RELOCATING+ __bss  =  .;}
125
    *(.bss)
126
    *(COMMON)
127
    ${RELOCATING+  __end  =  .;}
128
  } ${RELOCATING+ > ${DATA_MEMORY}}
129
  /* Heap.  */
130
  .heap :
131
  {
132
    ${RELOCATING+ __heap  =  .;}
133
    ${RELOCATING+ . += __HEAP_SIZE};
134
  } ${RELOCATING+ > ${DATA_MEMORY}}
135
  /* Stack (grows upward).  */
136
  .stack :
137
  {
138
    ${RELOCATING+ __stack  =  .;}
139
    *(.stack)
140
    ${RELOCATING+ .  =  . + __STACK_SIZE};
141
  } ${RELOCATING+ > ${DATA_MEMORY}}
142
  .stab 0 ${RELOCATING+(NOLOAD)} :
143
  {
144
    [ .stab ]
145
  }
146
  .stabstr 0 ${RELOCATING+(NOLOAD)} :
147
  {
148
    [ .stabstr ]
149
  }
150
}
151
EOF

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.