OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [ld/] [testsuite/] [ld-powerpc/] [relaxr.d] - Blame information for rev 620

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius 
 
2 
.*:     file format .*
3 
 
4 
Disassembly of section .text:
5 
 
6 
00000000 <_start>:
7 
   0:   48 00 00 15     bl      14 <_start\+0x14>
8 
   4:   48 00 00 21     bl      24 <_start\+0x24>
9 
   8:   48 00 00 0d     bl      14 <_start\+0x14>
10 
                        8: R_PPC_NONE   \*ABS\*
11 
   c:   48 00 00 19     bl      24 <_start\+0x24>
12 
                        c: R_PPC_NONE   \*ABS\*
13 
  10:   48 00 00 24     b       34 <_start\+0x34>
14 
  14:   3d 80 00 00     lis     r12,0
15 
                        16: R_PPC_ADDR16_HA     near
16 
  18:   39 8c 00 00     addi    r12,r12,0
17 
                        1a: R_PPC_ADDR16_LO     near
18 
  1c:   7d 89 03 a6     mtctr   r12
19 
  20:   4e 80 04 20     bctr
20 
  24:   3d 80 00 00     lis     r12,0
21 
                        26: R_PPC_ADDR16_HA     far
22 
  28:   39 8c 00 00     addi    r12,r12,0
23 
                        2a: R_PPC_ADDR16_LO     far
24 
  2c:   7d 89 03 a6     mtctr   r12
25 
  30:   4e 80 04 20     bctr

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.