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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [opcodes/] [cris-opc.c] - Blame information for rev 532

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/* cris-opc.c -- Table of opcodes for the CRIS processor.
2 
   Copyright 2000, 2001, 2004, 2005, 2007 Free Software Foundation, Inc.
3 
   Contributed by Axis Communications AB, Lund, Sweden.
4 
   Originally written for GAS 1.38.1 by Mikael Asker.
5 
   Reorganized by Hans-Peter Nilsson.
6 
 
7 
   This file is part of the GNU opcodes library.
8 
 
9 
   This library is free software; you can redistribute it and/or modify
10 
   it under the terms of the GNU General Public License as published by
11 
   the Free Software Foundation; either version 3, or (at your option)
12 
   any later version.
13 
 
14 
   It is distributed in the hope that it will be useful, but WITHOUT
15 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
   License for more details.
18 
 
19 
   You should have received a copy of the GNU General Public License
20 
   along with this program; if not, write to the Free Software
21 
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 
   MA 02110-1301, USA.  */
23 
 
24 
#include "opcode/cris.h"
25 
 
26 
#ifndef NULL
27 
#define NULL (0)
28 
#endif
29 
 
30 
/* This table isn't used for CRISv32 and the size of immediate operands.  */
31 
const struct cris_spec_reg
32 
cris_spec_regs[] =
33 
{
34 
  {"bz",  0,  1, cris_ver_v32p,     NULL},
35 
  {"p0",  0,  1, 0,                  NULL},
36 
  {"vr",  1,  1, 0,                 NULL},
37 
  {"p1",  1,  1, 0,                 NULL},
38 
  {"pid", 2,  1, cris_ver_v32p,    NULL},
39 
  {"p2",  2,  1, cris_ver_v32p,    NULL},
40 
  {"p2",  2,  1, cris_ver_warning, NULL},
41 
  {"srs", 3,  1, cris_ver_v32p,    NULL},
42 
  {"p3",  3,  1, cris_ver_v32p,    NULL},
43 
  {"p3",  3,  1, cris_ver_warning, NULL},
44 
  {"wz",  4,  2, cris_ver_v32p,    NULL},
45 
  {"p4",  4,  2, 0,                 NULL},
46 
  {"ccr", 5,  2, cris_ver_v0_10,   NULL},
47 
  {"exs", 5,  4, cris_ver_v32p,    NULL},
48 
  {"p5",  5,  2, cris_ver_v0_10,   NULL},
49 
  {"p5",  5,  4, cris_ver_v32p,    NULL},
50 
  {"dcr0",6,  2, cris_ver_v0_3,    NULL},
51 
  {"eda", 6,  4, cris_ver_v32p,    NULL},
52 
  {"p6",  6,  2, cris_ver_v0_3,    NULL},
53 
  {"p6",  6,  4, cris_ver_v32p,    NULL},
54 
  {"dcr1/mof", 7, 4, cris_ver_v10p,
55 
   "Register `dcr1/mof' with ambiguous size specified.  Guessing 4 bytes"},
56 
  {"dcr1/mof", 7, 2, cris_ver_v0_3,
57 
   "Register `dcr1/mof' with ambiguous size specified.  Guessing 2 bytes"},
58 
  {"mof", 7,  4, cris_ver_v10p,    NULL},
59 
  {"dcr1",7,  2, cris_ver_v0_3,    NULL},
60 
  {"p7",  7,  4, cris_ver_v10p,    NULL},
61 
  {"p7",  7,  2, cris_ver_v0_3,    NULL},
62 
  {"dz",  8,  4, cris_ver_v32p,    NULL},
63 
  {"p8",  8,  4, 0,                 NULL},
64 
  {"ibr", 9,  4, cris_ver_v0_10,   NULL},
65 
  {"ebp", 9,  4, cris_ver_v32p,    NULL},
66 
  {"p9",  9,  4, 0,                 NULL},
67 
  {"irp", 10, 4, cris_ver_v0_10,   NULL},
68 
  {"erp", 10, 4, cris_ver_v32p,    NULL},
69 
  {"p10", 10, 4, 0,                 NULL},
70 
  {"srp", 11, 4, 0,                 NULL},
71 
  {"p11", 11, 4, 0,                 NULL},
72 
  /* For disassembly use only.  Accept at assembly with a warning.  */
73 
  {"bar/dtp0", 12, 4, cris_ver_warning,
74 
   "Ambiguous register `bar/dtp0' specified"},
75 
  {"nrp", 12, 4, cris_ver_v32p,    NULL},
76 
  {"bar", 12, 4, cris_ver_v8_10,   NULL},
77 
  {"dtp0",12, 4, cris_ver_v0_3,    NULL},
78 
  {"p12", 12, 4, 0,                 NULL},
79 
  /* For disassembly use only.  Accept at assembly with a warning.  */
80 
  {"dccr/dtp1",13, 4, cris_ver_warning,
81 
   "Ambiguous register `dccr/dtp1' specified"},
82 
  {"ccs", 13, 4, cris_ver_v32p,    NULL},
83 
  {"dccr",13, 4, cris_ver_v8_10,   NULL},
84 
  {"dtp1",13, 4, cris_ver_v0_3,    NULL},
85 
  {"p13", 13, 4, 0,                 NULL},
86 
  {"brp", 14, 4, cris_ver_v3_10,   NULL},
87 
  {"usp", 14, 4, cris_ver_v32p,    NULL},
88 
  {"p14", 14, 4, cris_ver_v3p,     NULL},
89 
  {"usp", 15, 4, cris_ver_v10,     NULL},
90 
  {"spc", 15, 4, cris_ver_v32p,    NULL},
91 
  {"p15", 15, 4, cris_ver_v10p,    NULL},
92 
  {NULL, 0, 0, cris_ver_version_all, NULL}
93 
};
94 
 
95 
/* Add version specifiers to this table when necessary.
96 
   The (now) regular coding of register names suggests a simpler
97 
   implementation.  */
98 
const struct cris_support_reg cris_support_regs[] =
99 
{
100 
  {"s0", 0},
101 
  {"s1", 1},
102 
  {"s2", 2},
103 
  {"s3", 3},
104 
  {"s4", 4},
105 
  {"s5", 5},
106 
  {"s6", 6},
107 
  {"s7", 7},
108 
  {"s8", 8},
109 
  {"s9", 9},
110 
  {"s10", 10},
111 
  {"s11", 11},
112 
  {"s12", 12},
113 
  {"s13", 13},
114 
  {"s14", 14},
115 
  {"s15", 15},
116 
  {NULL, 0}
117 
};
118 
 
119 
/* All CRIS opcodes are 16 bits.
120 
 
121 
   - The match component is a mask saying which bits must match a
122 
     particular opcode in order for an instruction to be an instance
123 
     of that opcode.
124 
 
125 
   - The args component is a string containing characters symbolically
126 
     matching the operands of an instruction.  Used for both assembly
127 
     and disassembly.
128 
 
129 
     Operand-matching characters:
130 
     [ ] , space
131 
        Verbatim.
132 
     A  The string "ACR" (case-insensitive).
133 
     B  Not really an operand.  It causes a "BDAP -size,SP" prefix to be
134 
        output for the PUSH alias-instructions and recognizes a push-
135 
        prefix at disassembly.  This letter isn't recognized for v32.
136 
        Must be followed by a R or P letter.
137 
     !  Non-match pattern, will not match if there's a prefix insn.
138 
     b  Non-matching operand, used for branches with 16-bit
139 
        displacement. Only recognized by the disassembler.
140 
     c  5-bit unsigned immediate in bits <4:0>.
141 
     C  4-bit unsigned immediate in bits <3:0>.
142 
     d  At assembly, optionally (as in put other cases before this one)
143 
        ".d" or ".D" at the start of the operands, followed by one space
144 
        character.  At disassembly, nothing.
145 
     D  General register in bits <15:12> and <3:0>.
146 
     f  List of flags in bits <15:12> and <3:0>.
147 
     i  6-bit signed immediate in bits <5:0>.
148 
     I  6-bit unsigned immediate in bits <5:0>.
149 
     M  Size modifier (B, W or D) for CLEAR instructions.
150 
     m  Size modifier (B, W or D) in bits <5:4>
151 
     N  A 32-bit dword, like in the difference between s and y.
152 
        This has no effect on bits in the opcode.  Can also be expressed
153 
        as "[pc+]" in input.
154 
     n  As N, but PC-relative (to the start of the instruction).
155 
     o  [-128..127] word offset in bits <7:1> and <0>.  Used by 8-bit
156 
        branch instructions.
157 
     O  [-128..127] offset in bits <7:0>.  Also matches a comma and a
158 
        general register after the expression, in bits <15:12>.  Used
159 
        only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
160 
     P  Special register in bits <15:12>.
161 
     p  Indicates that the insn is a prefix insn.  Must be first
162 
        character.
163 
     Q  As O, but don't relax; force an 8-bit offset.
164 
     R  General register in bits <15:12>.
165 
     r  General register in bits <3:0>.
166 
     S  Source operand in bit <10> and a prefix; a 3-operand prefix
167 
        without side-effect.
168 
     s  Source operand in bits <10> and <3:0>, optionally with a
169 
        side-effect prefix, except [pc] (the name, not R15 as in ACR)
170 
        isn't allowed for v32 and higher.
171 
     T  Support register in bits <15:12>.
172 
     u  4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
173 
     U  Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
174 
        Not recognized at disassembly.
175 
     x  Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
176 
     y  Like 's' but do not allow an integer at assembly.
177 
     Y  The difference s-y; only an integer is allowed.
178 
     z  Size modifier (B or W) in bit <4>.  */
179 
 
180 
 
181 
/* Please note the order of the opcodes in this table is significant.
182 
   The assembler requires that all instances of the same mnemonic must
183 
   be consecutive.  If they aren't, the assembler might not recognize
184 
   them, or may indicate an internal error.
185 
 
186 
   The disassembler should not normally care about the order of the
187 
   opcodes, but will prefer an earlier alternative if the "match-score"
188 
   (see cris-dis.c) is computed as equal.
189 
 
190 
   It should not be significant for proper execution that this table is
191 
   in alphabetical order, but please follow that convention for an easy
192 
   overview.  */
193 
 
194 
const struct cris_opcode
195 
cris_opcodes[] =
196 
{
197 
  {"abs",     0x06B0, 0x0940,             "r,R",     0, SIZE_NONE,     0,
198 
   cris_abs_op},
199 
 
200 
  {"add",     0x0600, 0x09c0,             "m r,R",   0, SIZE_NONE,     0,
201 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
202 
 
203 
  {"add",     0x0A00, 0x01c0,             "m s,R",   0, SIZE_FIELD,    0,
204 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
205 
 
206 
  {"add",     0x0A00, 0x01c0,             "m S,D",   0, SIZE_NONE,
207 
   cris_ver_v0_10,
208 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
209 
 
210 
  {"add",     0x0a00, 0x05c0,             "m S,R,r", 0, SIZE_NONE,
211 
   cris_ver_v0_10,
212 
   cris_three_operand_add_sub_cmp_and_or_op},
213 
 
214 
  {"add",     0x0A00, 0x01c0,             "m s,R",   0, SIZE_FIELD,
215 
   cris_ver_v32p,
216 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
217 
 
218 
  {"addc",    0x0570, 0x0A80,             "r,R",     0, SIZE_FIX_32,
219 
   cris_ver_v32p,
220 
   cris_not_implemented_op},
221 
 
222 
  {"addc",    0x09A0, 0x0250,             "s,R",     0, SIZE_FIX_32,
223 
   cris_ver_v32p,
224 
   cris_not_implemented_op},
225 
 
226 
  {"addi",    0x0540, 0x0A80,             "x,r,A",   0, SIZE_NONE,
227 
   cris_ver_v32p,
228 
   cris_addi_op},
229 
 
230 
  {"addi",    0x0500, 0x0Ac0,             "x,r",     0, SIZE_NONE,     0,
231 
   cris_addi_op},
232 
 
233 
  /* This collates after "addo", but we want to disassemble as "addoq",
234 
     not "addo".  */
235 
  {"addoq",   0x0100, 0x0E00,             "Q,A",     0, SIZE_NONE,
236 
   cris_ver_v32p,
237 
   cris_not_implemented_op},
238 
 
239 
  {"addo",    0x0940, 0x0280,             "m s,R,A", 0, SIZE_FIELD_SIGNED,
240 
   cris_ver_v32p,
241 
   cris_not_implemented_op},
242 
 
243 
  /* This must be located after the insn above, lest we misinterpret
244 
     "addo.b -1,r0,acr" as "addo .b-1,r0,acr".  FIXME: Sounds like a
245 
     parser bug.  */
246 
  {"addo",   0x0100, 0x0E00,              "O,A",     0, SIZE_NONE,
247 
   cris_ver_v32p,
248 
   cris_not_implemented_op},
249 
 
250 
  {"addq",    0x0200, 0x0Dc0,             "I,R",     0, SIZE_NONE,     0,
251 
   cris_quick_mode_add_sub_op},
252 
 
253 
  {"adds",    0x0420, 0x0Bc0,             "z r,R",   0, SIZE_NONE,     0,
254 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
255 
 
256 
  /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
257 
  {"adds",    0x0820, 0x03c0,             "z s,R",   0, SIZE_FIELD,    0,
258 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
259 
 
260 
  {"adds",    0x0820, 0x03c0,             "z S,D",   0, SIZE_NONE,
261 
   cris_ver_v0_10,
262 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
263 
 
264 
  {"adds",    0x0820, 0x07c0,             "z S,R,r", 0, SIZE_NONE,
265 
   cris_ver_v0_10,
266 
   cris_three_operand_add_sub_cmp_and_or_op},
267 
 
268 
  {"addu",    0x0400, 0x0be0,             "z r,R",   0, SIZE_NONE,     0,
269 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
270 
 
271 
  /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
272 
  {"addu",    0x0800, 0x03e0,             "z s,R",   0, SIZE_FIELD,    0,
273 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
274 
 
275 
  {"addu",    0x0800, 0x03e0,             "z S,D",   0, SIZE_NONE,
276 
   cris_ver_v0_10,
277 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
278 
 
279 
  {"addu",    0x0800, 0x07e0,             "z S,R,r", 0, SIZE_NONE,
280 
   cris_ver_v0_10,
281 
   cris_three_operand_add_sub_cmp_and_or_op},
282 
 
283 
  {"and",     0x0700, 0x08C0,             "m r,R",   0, SIZE_NONE,     0,
284 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
285 
 
286 
  {"and",     0x0B00, 0x00C0,             "m s,R",   0, SIZE_FIELD,    0,
287 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
288 
 
289 
  {"and",     0x0B00, 0x00C0,             "m S,D",   0, SIZE_NONE,
290 
   cris_ver_v0_10,
291 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
292 
 
293 
  {"and",     0x0B00, 0x04C0,             "m S,R,r", 0, SIZE_NONE,
294 
   cris_ver_v0_10,
295 
   cris_three_operand_add_sub_cmp_and_or_op},
296 
 
297 
  {"andq",    0x0300, 0x0CC0,             "i,R",     0, SIZE_NONE,     0,
298 
   cris_quick_mode_and_cmp_move_or_op},
299 
 
300 
  {"asr",     0x0780, 0x0840,             "m r,R",   0, SIZE_NONE,     0,
301 
   cris_asr_op},
302 
 
303 
  {"asrq",    0x03a0, 0x0c40,             "c,R",     0, SIZE_NONE,     0,
304 
   cris_asrq_op},
305 
 
306 
  {"ax",      0x15B0, 0xEA4F,             "",        0, SIZE_NONE,     0,
307 
   cris_ax_ei_setf_op},
308 
 
309 
  /* FIXME: Should use branch #defines.  */
310 
  {"b",       0x0dff, 0x0200,             "b",       1, SIZE_NONE,     0,
311 
   cris_sixteen_bit_offset_branch_op},
312 
 
313 
  {"ba",
314 
   BA_QUICK_OPCODE,
315 
   0x0F00+(0xF-CC_A)*0x1000,              "o",       1, SIZE_NONE,     0,
316 
   cris_eight_bit_offset_branch_op},
317 
 
318 
  /* Needs to come after the usual "ba o", which might be relaxed to
319 
     this one.  */
320 
  {"ba",     BA_DWORD_OPCODE,
321 
   0xffff & (~BA_DWORD_OPCODE),           "n",       0, SIZE_FIX_32,
322 
   cris_ver_v32p,
323 
   cris_none_reg_mode_jump_op},
324 
 
325 
  {"bas",     0x0EBF, 0x0140,             "n,P",     0, SIZE_FIX_32,
326 
   cris_ver_v32p,
327 
   cris_none_reg_mode_jump_op},
328 
 
329 
  {"basc",     0x0EFF, 0x0100,            "n,P",     0, SIZE_FIX_32,
330 
   cris_ver_v32p,
331 
   cris_none_reg_mode_jump_op},
332 
 
333 
  {"bcc",
334 
   BRANCH_QUICK_OPCODE+CC_CC*0x1000,
335 
   0x0f00+(0xF-CC_CC)*0x1000,             "o",       1, SIZE_NONE,     0,
336 
   cris_eight_bit_offset_branch_op},
337 
 
338 
  {"bcs",
339 
   BRANCH_QUICK_OPCODE+CC_CS*0x1000,
340 
   0x0f00+(0xF-CC_CS)*0x1000,             "o",       1, SIZE_NONE,     0,
341 
   cris_eight_bit_offset_branch_op},
342 
 
343 
  {"bdap",
344 
   BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS,  "pm s,R",  0, SIZE_FIELD_SIGNED,
345 
   cris_ver_v0_10,
346 
   cris_bdap_prefix},
347 
 
348 
  {"bdap",
349 
   BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS,  "pO",      0, SIZE_NONE,
350 
   cris_ver_v0_10,
351 
   cris_quick_mode_bdap_prefix},
352 
 
353 
  {"beq",
354 
   BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
355 
   0x0f00+(0xF-CC_EQ)*0x1000,             "o",       1, SIZE_NONE,     0,
356 
   cris_eight_bit_offset_branch_op},
357 
 
358 
  /* This is deliberately put before "bext" to trump it, even though not
359 
     in alphabetical order, since we don't do excluding version checks
360 
     for v0..v10.  */
361 
  {"bwf",
362 
   BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
363 
   0x0f00+(0xF-CC_EXT)*0x1000,            "o",       1, SIZE_NONE,
364 
   cris_ver_v10,
365 
   cris_eight_bit_offset_branch_op},
366 
 
367 
  {"bext",
368 
   BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
369 
   0x0f00+(0xF-CC_EXT)*0x1000,            "o",       1, SIZE_NONE,
370 
   cris_ver_v0_3,
371 
   cris_eight_bit_offset_branch_op},
372 
 
373 
  {"bge",
374 
   BRANCH_QUICK_OPCODE+CC_GE*0x1000,
375 
   0x0f00+(0xF-CC_GE)*0x1000,             "o",       1, SIZE_NONE,     0,
376 
   cris_eight_bit_offset_branch_op},
377 
 
378 
  {"bgt",
379 
   BRANCH_QUICK_OPCODE+CC_GT*0x1000,
380 
   0x0f00+(0xF-CC_GT)*0x1000,             "o",       1, SIZE_NONE,     0,
381 
   cris_eight_bit_offset_branch_op},
382 
 
383 
  {"bhi",
384 
   BRANCH_QUICK_OPCODE+CC_HI*0x1000,
385 
   0x0f00+(0xF-CC_HI)*0x1000,             "o",       1, SIZE_NONE,     0,
386 
   cris_eight_bit_offset_branch_op},
387 
 
388 
  {"bhs",
389 
   BRANCH_QUICK_OPCODE+CC_HS*0x1000,
390 
   0x0f00+(0xF-CC_HS)*0x1000,             "o",       1, SIZE_NONE,     0,
391 
   cris_eight_bit_offset_branch_op},
392 
 
393 
  {"biap", BIAP_OPCODE, BIAP_Z_BITS,      "pm r,R",  0, SIZE_NONE,
394 
   cris_ver_v0_10,
395 
   cris_biap_prefix},
396 
 
397 
  {"ble",
398 
   BRANCH_QUICK_OPCODE+CC_LE*0x1000,
399 
   0x0f00+(0xF-CC_LE)*0x1000,             "o",       1, SIZE_NONE,     0,
400 
   cris_eight_bit_offset_branch_op},
401 
 
402 
  {"blo",
403 
   BRANCH_QUICK_OPCODE+CC_LO*0x1000,
404 
   0x0f00+(0xF-CC_LO)*0x1000,             "o",       1, SIZE_NONE,     0,
405 
   cris_eight_bit_offset_branch_op},
406 
 
407 
  {"bls",
408 
   BRANCH_QUICK_OPCODE+CC_LS*0x1000,
409 
   0x0f00+(0xF-CC_LS)*0x1000,             "o",       1, SIZE_NONE,     0,
410 
   cris_eight_bit_offset_branch_op},
411 
 
412 
  {"blt",
413 
   BRANCH_QUICK_OPCODE+CC_LT*0x1000,
414 
   0x0f00+(0xF-CC_LT)*0x1000,             "o",       1, SIZE_NONE,     0,
415 
   cris_eight_bit_offset_branch_op},
416 
 
417 
  {"bmi",
418 
   BRANCH_QUICK_OPCODE+CC_MI*0x1000,
419 
   0x0f00+(0xF-CC_MI)*0x1000,             "o",       1, SIZE_NONE,     0,
420 
   cris_eight_bit_offset_branch_op},
421 
 
422 
  {"bmod",    0x0ab0, 0x0140,             "s,R",     0, SIZE_FIX_32,
423 
   cris_ver_sim_v0_10,
424 
   cris_not_implemented_op},
425 
 
426 
  {"bmod",    0x0ab0, 0x0140,             "S,D",     0, SIZE_NONE,
427 
   cris_ver_sim_v0_10,
428 
   cris_not_implemented_op},
429 
 
430 
  {"bmod",    0x0ab0, 0x0540,             "S,R,r",   0, SIZE_NONE,
431 
   cris_ver_sim_v0_10,
432 
   cris_not_implemented_op},
433 
 
434 
  {"bne",
435 
   BRANCH_QUICK_OPCODE+CC_NE*0x1000,
436 
   0x0f00+(0xF-CC_NE)*0x1000,             "o",       1, SIZE_NONE,     0,
437 
   cris_eight_bit_offset_branch_op},
438 
 
439 
  {"bound",   0x05c0, 0x0A00,             "m r,R",   0, SIZE_NONE,     0,
440 
   cris_two_operand_bound_op},
441 
  /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
442 
  {"bound",   0x09c0, 0x0200,             "m s,R",   0, SIZE_FIELD,
443 
   cris_ver_v0_10,
444 
   cris_two_operand_bound_op},
445 
  /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
446 
  {"bound",   0x0dcf, 0x0200,             "m Y,R",   0, SIZE_FIELD,    0,
447 
   cris_two_operand_bound_op},
448 
  {"bound",   0x09c0, 0x0200,             "m S,D",   0, SIZE_NONE,
449 
   cris_ver_v0_10,
450 
   cris_two_operand_bound_op},
451 
  {"bound",   0x09c0, 0x0600,             "m S,R,r", 0, SIZE_NONE,
452 
   cris_ver_v0_10,
453 
   cris_three_operand_bound_op},
454 
 
455 
  {"bpl",
456 
   BRANCH_QUICK_OPCODE+CC_PL*0x1000,
457 
   0x0f00+(0xF-CC_PL)*0x1000,             "o",       1, SIZE_NONE,     0,
458 
   cris_eight_bit_offset_branch_op},
459 
 
460 
  {"break",   0xe930, 0x16c0,             "C",       0, SIZE_NONE,
461 
   cris_ver_v3p,
462 
   cris_break_op},
463 
 
464 
  {"bsb",
465 
   BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
466 
   0x0f00+(0xF-CC_EXT)*0x1000,            "o",       1, SIZE_NONE,
467 
   cris_ver_v32p,
468 
   cris_eight_bit_offset_branch_op},
469 
 
470 
  {"bsr",     0xBEBF, 0x4140,             "n",       0, SIZE_FIX_32,
471 
   cris_ver_v32p,
472 
   cris_none_reg_mode_jump_op},
473 
 
474 
  {"bsrc",     0xBEFF, 0x4100,            "n",       0, SIZE_FIX_32,
475 
   cris_ver_v32p,
476 
   cris_none_reg_mode_jump_op},
477 
 
478 
  {"bstore",  0x0af0, 0x0100,             "s,R",     0, SIZE_FIX_32,
479 
   cris_ver_warning,
480 
   cris_not_implemented_op},
481 
 
482 
  {"bstore",  0x0af0, 0x0100,             "S,D",     0, SIZE_NONE,
483 
   cris_ver_warning,
484 
   cris_not_implemented_op},
485 
 
486 
  {"bstore",  0x0af0, 0x0500,             "S,R,r",   0, SIZE_NONE,
487 
   cris_ver_warning,
488 
   cris_not_implemented_op},
489 
 
490 
  {"btst",    0x04F0, 0x0B00,             "r,R",     0, SIZE_NONE,     0,
491 
   cris_btst_nop_op},
492 
  {"btstq",   0x0380, 0x0C60,             "c,R",     0, SIZE_NONE,     0,
493 
   cris_btst_nop_op},
494 
 
495 
  {"bvc",
496 
   BRANCH_QUICK_OPCODE+CC_VC*0x1000,
497 
   0x0f00+(0xF-CC_VC)*0x1000,             "o",       1, SIZE_NONE,     0,
498 
   cris_eight_bit_offset_branch_op},
499 
 
500 
  {"bvs",
501 
   BRANCH_QUICK_OPCODE+CC_VS*0x1000,
502 
   0x0f00+(0xF-CC_VS)*0x1000,             "o",       1, SIZE_NONE,     0,
503 
   cris_eight_bit_offset_branch_op},
504 
 
505 
  {"clear",   0x0670, 0x3980,             "M r",     0, SIZE_NONE,     0,
506 
   cris_reg_mode_clear_op},
507 
 
508 
  {"clear",   0x0A70, 0x3180,             "M y",     0, SIZE_NONE,     0,
509 
   cris_none_reg_mode_clear_test_op},
510 
 
511 
  {"clear",   0x0A70, 0x3180,             "M S",     0, SIZE_NONE,
512 
   cris_ver_v0_10,
513 
   cris_none_reg_mode_clear_test_op},
514 
 
515 
  {"clearf",  0x05F0, 0x0A00,             "f",       0, SIZE_NONE,     0,
516 
   cris_clearf_di_op},
517 
 
518 
  {"cmp",     0x06C0, 0x0900,             "m r,R",   0, SIZE_NONE,     0,
519 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
520 
 
521 
  {"cmp",     0x0Ac0, 0x0100,             "m s,R",   0, SIZE_FIELD,    0,
522 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
523 
 
524 
  {"cmp",     0x0Ac0, 0x0100,             "m S,D",   0, SIZE_NONE,
525 
   cris_ver_v0_10,
526 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
527 
 
528 
  {"cmpq",    0x02C0, 0x0D00,             "i,R",     0, SIZE_NONE,     0,
529 
   cris_quick_mode_and_cmp_move_or_op},
530 
 
531 
  /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
532 
  {"cmps",    0x08e0, 0x0300,             "z s,R",   0, SIZE_FIELD,    0,
533 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
534 
 
535 
  {"cmps",    0x08e0, 0x0300,             "z S,D",   0, SIZE_NONE,
536 
   cris_ver_v0_10,
537 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
538 
 
539 
  /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
540 
  {"cmpu",    0x08c0, 0x0320,             "z s,R" ,  0, SIZE_FIELD,    0,
541 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
542 
 
543 
  {"cmpu",    0x08c0, 0x0320,             "z S,D",   0, SIZE_NONE,
544 
   cris_ver_v0_10,
545 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
546 
 
547 
  {"di",      0x25F0, 0xDA0F,             "",        0, SIZE_NONE,     0,
548 
   cris_clearf_di_op},
549 
 
550 
  {"dip",     DIP_OPCODE, DIP_Z_BITS,     "ps",      0, SIZE_FIX_32,
551 
   cris_ver_v0_10,
552 
   cris_dip_prefix},
553 
 
554 
  {"div",     0x0980, 0x0640,             "m R,r",   0, SIZE_FIELD,    0,
555 
   cris_not_implemented_op},
556 
 
557 
  {"dstep",   0x06f0, 0x0900,             "r,R",     0, SIZE_NONE,     0,
558 
   cris_dstep_logshift_mstep_neg_not_op},
559 
 
560 
  {"ei",      0x25B0, 0xDA4F,             "",        0, SIZE_NONE,     0,
561 
   cris_ax_ei_setf_op},
562 
 
563 
  {"fidxd",    0x0ab0, 0xf540,            "[r]",     0, SIZE_NONE,
564 
   cris_ver_v32p,
565 
   cris_not_implemented_op},
566 
 
567 
  {"fidxi",    0x0d30, 0xF2C0,            "[r]",     0, SIZE_NONE,
568 
   cris_ver_v32p,
569 
   cris_not_implemented_op},
570 
 
571 
  {"ftagd",    0x1AB0, 0xE540,            "[r]",     0, SIZE_NONE,
572 
   cris_ver_v32p,
573 
   cris_not_implemented_op},
574 
 
575 
  {"ftagi",    0x1D30, 0xE2C0,            "[r]",     0, SIZE_NONE,
576 
   cris_ver_v32p,
577 
   cris_not_implemented_op},
578 
 
579 
  {"halt",    0xF930, 0x06CF,             "",        0, SIZE_NONE,
580 
   cris_ver_v32p,
581 
   cris_not_implemented_op},
582 
 
583 
  {"jas",    0x09B0, 0x0640,              "r,P",     0, SIZE_NONE,
584 
   cris_ver_v32p,
585 
   cris_reg_mode_jump_op},
586 
 
587 
  {"jas",    0x0DBF, 0x0240,              "N,P",     0, SIZE_FIX_32,
588 
   cris_ver_v32p,
589 
   cris_reg_mode_jump_op},
590 
 
591 
  {"jasc",    0x0B30, 0x04C0,             "r,P",     0, SIZE_NONE,
592 
   cris_ver_v32p,
593 
   cris_reg_mode_jump_op},
594 
 
595 
  {"jasc",    0x0F3F, 0x00C0,             "N,P",     0, SIZE_FIX_32,
596 
   cris_ver_v32p,
597 
   cris_reg_mode_jump_op},
598 
 
599 
  {"jbrc",    0x69b0, 0x9640,             "r",       0, SIZE_NONE,
600 
   cris_ver_v8_10,
601 
   cris_reg_mode_jump_op},
602 
 
603 
  {"jbrc",    0x6930, 0x92c0,             "s",       0, SIZE_FIX_32,
604 
   cris_ver_v8_10,
605 
   cris_none_reg_mode_jump_op},
606 
 
607 
  {"jbrc",    0x6930, 0x92c0,             "S",       0, SIZE_NONE,
608 
   cris_ver_v8_10,
609 
   cris_none_reg_mode_jump_op},
610 
 
611 
  {"jir",     0xA9b0, 0x5640,             "r",       0, SIZE_NONE,
612 
   cris_ver_v8_10,
613 
   cris_reg_mode_jump_op},
614 
 
615 
  {"jir",     0xA930, 0x52c0,             "s",       0, SIZE_FIX_32,
616 
   cris_ver_v8_10,
617 
   cris_none_reg_mode_jump_op},
618 
 
619 
  {"jir",     0xA930, 0x52c0,             "S",       0, SIZE_NONE,
620 
   cris_ver_v8_10,
621 
   cris_none_reg_mode_jump_op},
622 
 
623 
  {"jirc",    0x29b0, 0xd640,             "r",       0, SIZE_NONE,
624 
   cris_ver_v8_10,
625 
   cris_reg_mode_jump_op},
626 
 
627 
  {"jirc",    0x2930, 0xd2c0,             "s",       0, SIZE_FIX_32,
628 
   cris_ver_v8_10,
629 
   cris_none_reg_mode_jump_op},
630 
 
631 
  {"jirc",    0x2930, 0xd2c0,             "S",       0, SIZE_NONE,
632 
   cris_ver_v8_10,
633 
   cris_none_reg_mode_jump_op},
634 
 
635 
  {"jsr",     0xB9b0, 0x4640,             "r",       0, SIZE_NONE,     0,
636 
   cris_reg_mode_jump_op},
637 
 
638 
  {"jsr",     0xB930, 0x42c0,             "s",       0, SIZE_FIX_32,
639 
   cris_ver_v0_10,
640 
   cris_none_reg_mode_jump_op},
641 
 
642 
  {"jsr",     0xBDBF, 0x4240,             "N",       0, SIZE_FIX_32,
643 
   cris_ver_v32p,
644 
   cris_none_reg_mode_jump_op},
645 
 
646 
  {"jsr",     0xB930, 0x42c0,             "S",       0, SIZE_NONE,
647 
   cris_ver_v0_10,
648 
   cris_none_reg_mode_jump_op},
649 
 
650 
  {"jsrc",    0x39b0, 0xc640,             "r",       0, SIZE_NONE,
651 
   cris_ver_v8_10,
652 
   cris_reg_mode_jump_op},
653 
 
654 
  {"jsrc",    0x3930, 0xc2c0,             "s",       0, SIZE_FIX_32,
655 
   cris_ver_v8_10,
656 
   cris_none_reg_mode_jump_op},
657 
 
658 
  {"jsrc",    0x3930, 0xc2c0,             "S",       0, SIZE_NONE,
659 
   cris_ver_v8_10,
660 
   cris_none_reg_mode_jump_op},
661 
 
662 
  {"jsrc",    0xBB30, 0x44C0,             "r",       0, SIZE_NONE,
663 
   cris_ver_v32p,
664 
   cris_reg_mode_jump_op},
665 
 
666 
  {"jsrc",    0xBF3F, 0x40C0,             "N",       0, SIZE_FIX_32,
667 
   cris_ver_v32p,
668 
   cris_reg_mode_jump_op},
669 
 
670 
  {"jump",    0x09b0, 0xF640,             "r",       0, SIZE_NONE,     0,
671 
   cris_reg_mode_jump_op},
672 
 
673 
  {"jump",
674 
   JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "s",       0, SIZE_FIX_32,
675 
   cris_ver_v0_10,
676 
   cris_none_reg_mode_jump_op},
677 
 
678 
  {"jump",
679 
   JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "S",       0, SIZE_NONE,
680 
   cris_ver_v0_10,
681 
   cris_none_reg_mode_jump_op},
682 
 
683 
  {"jump",    0x09F0, 0x060F,             "P",       0, SIZE_NONE,
684 
   cris_ver_v32p,
685 
   cris_none_reg_mode_jump_op},
686 
 
687 
  {"jump",
688 
   JUMP_PC_INCR_OPCODE_V32,
689 
   (0xffff & ~JUMP_PC_INCR_OPCODE_V32),   "N",       0, SIZE_FIX_32,
690 
   cris_ver_v32p,
691 
   cris_none_reg_mode_jump_op},
692 
 
693 
  {"jmpu",    0x8930, 0x72c0,             "s",       0, SIZE_FIX_32,
694 
   cris_ver_v10,
695 
   cris_none_reg_mode_jump_op},
696 
 
697 
  {"jmpu",    0x8930, 0x72c0,              "S",      0, SIZE_NONE,
698 
   cris_ver_v10,
699 
   cris_none_reg_mode_jump_op},
700 
 
701 
  {"lapc",    0x0970, 0x0680,             "U,R",    0, SIZE_NONE,
702 
   cris_ver_v32p,
703 
   cris_not_implemented_op},
704 
 
705 
  {"lapc",    0x0D7F, 0x0280,             "dn,R",    0, SIZE_FIX_32,
706 
   cris_ver_v32p,
707 
   cris_not_implemented_op},
708 
 
709 
  {"lapcq",   0x0970, 0x0680,             "u,R",     0, SIZE_NONE,
710 
   cris_ver_v32p,
711 
   cris_addi_op},
712 
 
713 
  {"lsl",     0x04C0, 0x0B00,             "m r,R",   0, SIZE_NONE,     0,
714 
   cris_dstep_logshift_mstep_neg_not_op},
715 
 
716 
  {"lslq",    0x03c0, 0x0C20,             "c,R",     0, SIZE_NONE,     0,
717 
   cris_dstep_logshift_mstep_neg_not_op},
718 
 
719 
  {"lsr",     0x07C0, 0x0800,             "m r,R",   0, SIZE_NONE,     0,
720 
   cris_dstep_logshift_mstep_neg_not_op},
721 
 
722 
  {"lsrq",    0x03e0, 0x0C00,             "c,R",     0, SIZE_NONE,     0,
723 
   cris_dstep_logshift_mstep_neg_not_op},
724 
 
725 
  {"lz",      0x0730, 0x08C0,             "r,R",     0, SIZE_NONE,
726 
   cris_ver_v3p,
727 
   cris_not_implemented_op},
728 
 
729 
  {"mcp",      0x07f0, 0x0800,            "P,r",     0, SIZE_NONE,
730 
   cris_ver_v32p,
731 
   cris_not_implemented_op},
732 
 
733 
  {"move",    0x0640, 0x0980,             "m r,R",   0, SIZE_NONE,     0,
734 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
735 
 
736 
  {"move",    0x0A40, 0x0180,             "m s,R",   0, SIZE_FIELD,    0,
737 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
738 
 
739 
  {"move",    0x0A40, 0x0180,             "m S,D",   0, SIZE_NONE,
740 
   cris_ver_v0_10,
741 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
742 
 
743 
  {"move",    0x0630, 0x09c0,             "r,P",     0, SIZE_NONE,     0,
744 
   cris_move_to_preg_op},
745 
 
746 
  {"move",    0x0670, 0x0980,             "P,r",     0, SIZE_NONE,     0,
747 
   cris_reg_mode_move_from_preg_op},
748 
 
749 
  {"move",    0x0BC0, 0x0000,             "m R,y",   0, SIZE_FIELD,    0,
750 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
751 
 
752 
  {"move",    0x0BC0, 0x0000,             "m D,S",   0, SIZE_NONE,
753 
   cris_ver_v0_10,
754 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
755 
 
756 
  {"move",
757 
   MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
758 
   "s,P",   0, SIZE_SPEC_REG, 0,
759 
   cris_move_to_preg_op},
760 
 
761 
  {"move",    0x0A30, 0x01c0,             "S,P",     0, SIZE_NONE,
762 
   cris_ver_v0_10,
763 
   cris_move_to_preg_op},
764 
 
765 
  {"move",    0x0A70, 0x0180,             "P,y",     0, SIZE_SPEC_REG, 0,
766 
   cris_none_reg_mode_move_from_preg_op},
767 
 
768 
  {"move",    0x0A70, 0x0180,             "P,S",     0, SIZE_NONE,
769 
   cris_ver_v0_10,
770 
   cris_none_reg_mode_move_from_preg_op},
771 
 
772 
  {"move",    0x0B70, 0x0480,             "r,T",     0, SIZE_NONE,
773 
   cris_ver_v32p,
774 
   cris_not_implemented_op},
775 
 
776 
  {"move",    0x0F70, 0x0080,             "T,r",     0, SIZE_NONE,
777 
   cris_ver_v32p,
778 
   cris_not_implemented_op},
779 
 
780 
  {"movem",   0x0BF0, 0x0000,             "R,y",     0, SIZE_FIX_32,   0,
781 
   cris_move_reg_to_mem_movem_op},
782 
 
783 
  {"movem",   0x0BF0, 0x0000,             "D,S",     0, SIZE_NONE,
784 
   cris_ver_v0_10,
785 
   cris_move_reg_to_mem_movem_op},
786 
 
787 
  {"movem",   0x0BB0, 0x0040,             "s,R",     0, SIZE_FIX_32,   0,
788 
   cris_move_mem_to_reg_movem_op},
789 
 
790 
  {"movem",   0x0BB0, 0x0040,             "S,D",     0, SIZE_NONE,
791 
   cris_ver_v0_10,
792 
   cris_move_mem_to_reg_movem_op},
793 
 
794 
  {"moveq",   0x0240, 0x0D80,             "i,R",     0, SIZE_NONE,     0,
795 
   cris_quick_mode_and_cmp_move_or_op},
796 
 
797 
  {"movs",    0x0460, 0x0B80,             "z r,R",   0, SIZE_NONE,     0,
798 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
799 
 
800 
  /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
801 
  {"movs",    0x0860, 0x0380,             "z s,R",   0, SIZE_FIELD,    0,
802 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
803 
 
804 
  {"movs",    0x0860, 0x0380,             "z S,D",   0, SIZE_NONE,
805 
   cris_ver_v0_10,
806 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
807 
 
808 
  {"movu",    0x0440, 0x0Ba0,             "z r,R",   0, SIZE_NONE,     0,
809 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
810 
 
811 
  /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
812 
  {"movu",    0x0840, 0x03a0,             "z s,R",   0, SIZE_FIELD,    0,
813 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
814 
 
815 
  {"movu",    0x0840, 0x03a0,             "z S,D",   0, SIZE_NONE,
816 
   cris_ver_v0_10,
817 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
818 
 
819 
  {"mstep",   0x07f0, 0x0800,             "r,R",     0, SIZE_NONE,
820 
   cris_ver_v0_10,
821 
   cris_dstep_logshift_mstep_neg_not_op},
822 
 
823 
  {"muls",    0x0d00, 0x02c0,             "m r,R",   0, SIZE_NONE,
824 
   cris_ver_v10p,
825 
   cris_muls_op},
826 
 
827 
  {"mulu",    0x0900, 0x06c0,             "m r,R",   0, SIZE_NONE,
828 
   cris_ver_v10p,
829 
   cris_mulu_op},
830 
 
831 
  {"neg",     0x0580, 0x0A40,             "m r,R",   0, SIZE_NONE,     0,
832 
   cris_dstep_logshift_mstep_neg_not_op},
833 
 
834 
  {"nop",     NOP_OPCODE, NOP_Z_BITS,     "",        0, SIZE_NONE,
835 
   cris_ver_v0_10,
836 
   cris_btst_nop_op},
837 
 
838 
  {"nop",     NOP_OPCODE_V32, NOP_Z_BITS_V32, "",    0, SIZE_NONE,
839 
   cris_ver_v32p,
840 
   cris_btst_nop_op},
841 
 
842 
  {"not",     0x8770, 0x7880,             "r",       0, SIZE_NONE,     0,
843 
   cris_dstep_logshift_mstep_neg_not_op},
844 
 
845 
  {"or",      0x0740, 0x0880,             "m r,R",   0, SIZE_NONE,     0,
846 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
847 
 
848 
  {"or",      0x0B40, 0x0080,             "m s,R",   0, SIZE_FIELD,    0,
849 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
850 
 
851 
  {"or",      0x0B40, 0x0080,             "m S,D",   0, SIZE_NONE,
852 
   cris_ver_v0_10,
853 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
854 
 
855 
  {"or",      0x0B40, 0x0480,             "m S,R,r", 0, SIZE_NONE,
856 
   cris_ver_v0_10,
857 
   cris_three_operand_add_sub_cmp_and_or_op},
858 
 
859 
  {"orq",     0x0340, 0x0C80,             "i,R",     0, SIZE_NONE,     0,
860 
   cris_quick_mode_and_cmp_move_or_op},
861 
 
862 
  {"pop",     0x0E6E, 0x0191,             "!R",      0, SIZE_NONE,
863 
   cris_ver_v0_10,
864 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
865 
 
866 
  {"pop",     0x0e3e, 0x01c1,             "!P",      0, SIZE_NONE,
867 
   cris_ver_v0_10,
868 
   cris_none_reg_mode_move_from_preg_op},
869 
 
870 
  {"push",    0x0FEE, 0x0011,             "BR",      0, SIZE_NONE,
871 
   cris_ver_v0_10,
872 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
873 
 
874 
  {"push",    0x0E7E, 0x0181,             "BP",      0, SIZE_NONE,
875 
   cris_ver_v0_10,
876 
   cris_move_to_preg_op},
877 
 
878 
  {"rbf",     0x3b30, 0xc0c0,             "y",       0, SIZE_NONE,
879 
   cris_ver_v10,
880 
   cris_not_implemented_op},
881 
 
882 
  {"rbf",     0x3b30, 0xc0c0,             "S",       0, SIZE_NONE,
883 
   cris_ver_v10,
884 
   cris_not_implemented_op},
885 
 
886 
  {"rfe",     0x2930, 0xD6CF,             "",        0, SIZE_NONE,
887 
   cris_ver_v32p,
888 
   cris_not_implemented_op},
889 
 
890 
  {"rfg",     0x4930, 0xB6CF,             "",        0, SIZE_NONE,
891 
   cris_ver_v32p,
892 
   cris_not_implemented_op},
893 
 
894 
  {"rfn",     0x5930, 0xA6CF,             "",        0, SIZE_NONE,
895 
   cris_ver_v32p,
896 
   cris_not_implemented_op},
897 
 
898 
  {"ret",     0xB67F, 0x4980,             "",        1, SIZE_NONE,
899 
   cris_ver_v0_10,
900 
   cris_reg_mode_move_from_preg_op},
901 
 
902 
  {"ret",     0xB9F0, 0x460F,             "",        1, SIZE_NONE,
903 
   cris_ver_v32p,
904 
   cris_reg_mode_move_from_preg_op},
905 
 
906 
  {"retb",    0xe67f, 0x1980,             "",        1, SIZE_NONE,
907 
   cris_ver_v0_10,
908 
   cris_reg_mode_move_from_preg_op},
909 
 
910 
  {"rete",     0xA9F0, 0x560F,            "",        1, SIZE_NONE,
911 
   cris_ver_v32p,
912 
   cris_reg_mode_move_from_preg_op},
913 
 
914 
  {"reti",    0xA67F, 0x5980,             "",        1, SIZE_NONE,
915 
   cris_ver_v0_10,
916 
   cris_reg_mode_move_from_preg_op},
917 
 
918 
  {"retn",     0xC9F0, 0x360F,            "",        1, SIZE_NONE,
919 
   cris_ver_v32p,
920 
   cris_reg_mode_move_from_preg_op},
921 
 
922 
  {"sbfs",    0x3b70, 0xc080,             "y",       0, SIZE_NONE,
923 
   cris_ver_v10,
924 
   cris_not_implemented_op},
925 
 
926 
  {"sbfs",    0x3b70, 0xc080,             "S",       0, SIZE_NONE,
927 
   cris_ver_v10,
928 
   cris_not_implemented_op},
929 
 
930 
  {"sa",
931 
   0x0530+CC_A*0x1000,
932 
   0x0AC0+(0xf-CC_A)*0x1000,              "r",       0, SIZE_NONE,     0,
933 
   cris_scc_op},
934 
 
935 
  {"ssb",
936 
   0x0530+CC_EXT*0x1000,
937 
   0x0AC0+(0xf-CC_EXT)*0x1000,            "r",       0, SIZE_NONE,
938 
   cris_ver_v32p,
939 
   cris_scc_op},
940 
 
941 
  {"scc",
942 
   0x0530+CC_CC*0x1000,
943 
   0x0AC0+(0xf-CC_CC)*0x1000,             "r",       0, SIZE_NONE,     0,
944 
   cris_scc_op},
945 
 
946 
  {"scs",
947 
   0x0530+CC_CS*0x1000,
948 
   0x0AC0+(0xf-CC_CS)*0x1000,             "r",       0, SIZE_NONE,     0,
949 
   cris_scc_op},
950 
 
951 
  {"seq",
952 
   0x0530+CC_EQ*0x1000,
953 
   0x0AC0+(0xf-CC_EQ)*0x1000,             "r",       0, SIZE_NONE,     0,
954 
   cris_scc_op},
955 
 
956 
  {"setf",    0x05b0, 0x0A40,             "f",       0, SIZE_NONE,     0,
957 
   cris_ax_ei_setf_op},
958 
 
959 
  {"sfe",    0x3930, 0xC6CF,              "",        0, SIZE_NONE,
960 
   cris_ver_v32p,
961 
   cris_not_implemented_op},
962 
 
963 
  /* Need to have "swf" in front of "sext" so it is the one displayed in
964 
     disassembly.  */
965 
  {"swf",
966 
   0x0530+CC_EXT*0x1000,
967 
   0x0AC0+(0xf-CC_EXT)*0x1000,            "r",       0, SIZE_NONE,
968 
   cris_ver_v10,
969 
   cris_scc_op},
970 
 
971 
  {"sext",
972 
   0x0530+CC_EXT*0x1000,
973 
   0x0AC0+(0xf-CC_EXT)*0x1000,            "r",       0, SIZE_NONE,
974 
   cris_ver_v0_3,
975 
   cris_scc_op},
976 
 
977 
  {"sge",
978 
   0x0530+CC_GE*0x1000,
979 
   0x0AC0+(0xf-CC_GE)*0x1000,             "r",       0, SIZE_NONE,     0,
980 
   cris_scc_op},
981 
 
982 
  {"sgt",
983 
   0x0530+CC_GT*0x1000,
984 
   0x0AC0+(0xf-CC_GT)*0x1000,             "r",       0, SIZE_NONE,     0,
985 
   cris_scc_op},
986 
 
987 
  {"shi",
988 
   0x0530+CC_HI*0x1000,
989 
   0x0AC0+(0xf-CC_HI)*0x1000,             "r",       0, SIZE_NONE,     0,
990 
   cris_scc_op},
991 
 
992 
  {"shs",
993 
   0x0530+CC_HS*0x1000,
994 
   0x0AC0+(0xf-CC_HS)*0x1000,             "r",       0, SIZE_NONE,     0,
995 
   cris_scc_op},
996 
 
997 
  {"sle",
998 
   0x0530+CC_LE*0x1000,
999 
   0x0AC0+(0xf-CC_LE)*0x1000,             "r",       0, SIZE_NONE,     0,
1000 
   cris_scc_op},
1001 
 
1002 
  {"slo",
1003 
   0x0530+CC_LO*0x1000,
1004 
   0x0AC0+(0xf-CC_LO)*0x1000,             "r",       0, SIZE_NONE,     0,
1005 
   cris_scc_op},
1006 
 
1007 
  {"sls",
1008 
   0x0530+CC_LS*0x1000,
1009 
   0x0AC0+(0xf-CC_LS)*0x1000,             "r",       0, SIZE_NONE,     0,
1010 
   cris_scc_op},
1011 
 
1012 
  {"slt",
1013 
   0x0530+CC_LT*0x1000,
1014 
   0x0AC0+(0xf-CC_LT)*0x1000,             "r",       0, SIZE_NONE,     0,
1015 
   cris_scc_op},
1016 
 
1017 
  {"smi",
1018 
   0x0530+CC_MI*0x1000,
1019 
   0x0AC0+(0xf-CC_MI)*0x1000,             "r",       0, SIZE_NONE,     0,
1020 
   cris_scc_op},
1021 
 
1022 
  {"sne",
1023 
   0x0530+CC_NE*0x1000,
1024 
   0x0AC0+(0xf-CC_NE)*0x1000,             "r",       0, SIZE_NONE,     0,
1025 
   cris_scc_op},
1026 
 
1027 
  {"spl",
1028 
   0x0530+CC_PL*0x1000,
1029 
   0x0AC0+(0xf-CC_PL)*0x1000,             "r",       0, SIZE_NONE,     0,
1030 
   cris_scc_op},
1031 
 
1032 
  {"sub",     0x0680, 0x0940,             "m r,R",   0, SIZE_NONE,     0,
1033 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
1034 
 
1035 
  {"sub",     0x0a80, 0x0140,             "m s,R",   0, SIZE_FIELD,    0,
1036 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1037 
 
1038 
  {"sub",     0x0a80, 0x0140,             "m S,D",   0, SIZE_NONE,
1039 
   cris_ver_v0_10,
1040 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1041 
 
1042 
  {"sub",     0x0a80, 0x0540,             "m S,R,r", 0, SIZE_NONE,
1043 
   cris_ver_v0_10,
1044 
   cris_three_operand_add_sub_cmp_and_or_op},
1045 
 
1046 
  {"subq",    0x0280, 0x0d40,             "I,R",     0, SIZE_NONE,     0,
1047 
   cris_quick_mode_add_sub_op},
1048 
 
1049 
  {"subs",    0x04a0, 0x0b40,             "z r,R",   0, SIZE_NONE,     0,
1050 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
1051 
 
1052 
  /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
1053 
  {"subs",    0x08a0, 0x0340,             "z s,R",   0, SIZE_FIELD,    0,
1054 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1055 
 
1056 
  {"subs",    0x08a0, 0x0340,             "z S,D",   0, SIZE_NONE,
1057 
   cris_ver_v0_10,
1058 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1059 
 
1060 
  {"subs",    0x08a0, 0x0740,             "z S,R,r", 0, SIZE_NONE,
1061 
   cris_ver_v0_10,
1062 
   cris_three_operand_add_sub_cmp_and_or_op},
1063 
 
1064 
  {"subu",    0x0480, 0x0b60,             "z r,R",   0, SIZE_NONE,     0,
1065 
   cris_reg_mode_add_sub_cmp_and_or_move_op},
1066 
 
1067 
  /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
1068 
  {"subu",    0x0880, 0x0360,             "z s,R",   0, SIZE_FIELD,    0,
1069 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1070 
 
1071 
  {"subu",    0x0880, 0x0360,             "z S,D",   0, SIZE_NONE,
1072 
   cris_ver_v0_10,
1073 
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1074 
 
1075 
  {"subu",    0x0880, 0x0760,             "z S,R,r", 0, SIZE_NONE,
1076 
   cris_ver_v0_10,
1077 
   cris_three_operand_add_sub_cmp_and_or_op},
1078 
 
1079 
  {"svc",
1080 
   0x0530+CC_VC*0x1000,
1081 
   0x0AC0+(0xf-CC_VC)*0x1000,             "r",       0, SIZE_NONE,     0,
1082 
   cris_scc_op},
1083 
 
1084 
  {"svs",
1085 
   0x0530+CC_VS*0x1000,
1086 
   0x0AC0+(0xf-CC_VS)*0x1000,             "r",       0, SIZE_NONE,     0,
1087 
   cris_scc_op},
1088 
 
1089 
  /* The insn "swapn" is the same as "not" and will be disassembled as
1090 
     such, but the swap* family of mnmonics are generally v8-and-higher
1091 
     only, so count it in.  */
1092 
  {"swapn",   0x8770, 0x7880,             "r",       0, SIZE_NONE,
1093 
   cris_ver_v8p,
1094 
   cris_not_implemented_op},
1095 
 
1096 
  {"swapw",   0x4770, 0xb880,             "r",       0, SIZE_NONE,
1097 
   cris_ver_v8p,
1098 
   cris_not_implemented_op},
1099 
 
1100 
  {"swapnw",  0xc770, 0x3880,             "r",       0, SIZE_NONE,
1101 
   cris_ver_v8p,
1102 
   cris_not_implemented_op},
1103 
 
1104 
  {"swapb",   0x2770, 0xd880,             "r",       0, SIZE_NONE,
1105 
   cris_ver_v8p,
1106 
   cris_not_implemented_op},
1107 
 
1108 
  {"swapnb",  0xA770, 0x5880,             "r",       0, SIZE_NONE,
1109 
   cris_ver_v8p,
1110 
   cris_not_implemented_op},
1111 
 
1112 
  {"swapwb",  0x6770, 0x9880,             "r",       0, SIZE_NONE,
1113 
   cris_ver_v8p,
1114 
   cris_not_implemented_op},
1115 
 
1116 
  {"swapnwb", 0xE770, 0x1880,             "r",       0, SIZE_NONE,
1117 
   cris_ver_v8p,
1118 
   cris_not_implemented_op},
1119 
 
1120 
  {"swapr",   0x1770, 0xe880,             "r",       0, SIZE_NONE,
1121 
   cris_ver_v8p,
1122 
   cris_not_implemented_op},
1123 
 
1124 
  {"swapnr",  0x9770, 0x6880,             "r",       0, SIZE_NONE,
1125 
   cris_ver_v8p,
1126 
   cris_not_implemented_op},
1127 
 
1128 
  {"swapwr",  0x5770, 0xa880,             "r",       0, SIZE_NONE,
1129 
   cris_ver_v8p,
1130 
   cris_not_implemented_op},
1131 
 
1132 
  {"swapnwr", 0xd770, 0x2880,             "r",       0, SIZE_NONE,
1133 
   cris_ver_v8p,
1134 
   cris_not_implemented_op},
1135 
 
1136 
  {"swapbr",  0x3770, 0xc880,             "r",       0, SIZE_NONE,
1137 
   cris_ver_v8p,
1138 
   cris_not_implemented_op},
1139 
 
1140 
  {"swapnbr", 0xb770, 0x4880,             "r",       0, SIZE_NONE,
1141 
   cris_ver_v8p,
1142 
   cris_not_implemented_op},
1143 
 
1144 
  {"swapwbr", 0x7770, 0x8880,             "r",       0, SIZE_NONE,
1145 
   cris_ver_v8p,
1146 
   cris_not_implemented_op},
1147 
 
1148 
  {"swapnwbr", 0xf770, 0x0880,            "r",       0, SIZE_NONE,
1149 
   cris_ver_v8p,
1150 
   cris_not_implemented_op},
1151 
 
1152 
  {"test",    0x0640, 0x0980,             "m D",     0, SIZE_NONE,
1153 
   cris_ver_v0_10,
1154 
   cris_reg_mode_test_op},
1155 
 
1156 
  {"test",    0x0b80, 0xf040,             "m y",     0, SIZE_FIELD,    0,
1157 
   cris_none_reg_mode_clear_test_op},
1158 
 
1159 
  {"test",    0x0b80, 0xf040,             "m S",     0, SIZE_NONE,
1160 
   cris_ver_v0_10,
1161 
   cris_none_reg_mode_clear_test_op},
1162 
 
1163 
  {"xor",     0x07B0, 0x0840,             "r,R",     0, SIZE_NONE,     0,
1164 
   cris_xor_op},
1165 
 
1166 
  {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
1167 
};
1168 
 
1169 
/* Condition-names, indexed by the CC_* numbers as found in cris.h. */
1170 
const char * const
1171 
cris_cc_strings[] =
1172 
{
1173 
  "hs",
1174 
  "lo",
1175 
  "ne",
1176 
  "eq",
1177 
  "vc",
1178 
  "vs",
1179 
  "pl",
1180 
  "mi",
1181 
  "ls",
1182 
  "hi",
1183 
  "ge",
1184 
  "lt",
1185 
  "gt",
1186 
  "le",
1187 
  "a",
1188 
  /* This is a placeholder.  In v0, this would be "ext".  In v32, this
1189 
     is "sb".  See cris_conds15.  */
1190 
  "wf"
1191 
};
1192 
 
1193 
/* Different names and semantics for condition 1111 (0xf).  */
1194 
const struct cris_cond15 cris_cond15s[] =
1195 
{
1196 
  /* FIXME: In what version did condition "ext" disappear?  */
1197 
  {"ext", cris_ver_v0_3},
1198 
  {"wf", cris_ver_v10},
1199 
  {"sb", cris_ver_v32p},
1200 
  {NULL, 0}
1201 
};
1202 
 
1203 
 
1204 
/*
1205 
 * Local variables:
1206 
 * eval: (c-set-style "gnu")
1207 
 * indent-tabs-mode: t
1208 
 * End:
1209 
 */

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