OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [opcodes/] [ia64-opc-i.c] - Blame information for rev 205

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius 
/* ia64-opc-i.c -- IA-64 `I' opcode table.
2 
   Copyright 1998, 1999, 2000, 2002, 2005, 2006, 2007, 2009
3 
   Free Software Foundation, Inc.
4 
   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 
 
6 
   This file is part of the GNU opcodes library.
7 
 
8 
   This library is free software; you can redistribute it and/or modify
9 
   it under the terms of the GNU General Public License as published by
10 
   the Free Software Foundation; either version 3, or (at your option)
11 
   any later version.
12 
 
13 
   It is distributed in the hope that it will be useful, but WITHOUT
14 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16 
   License for more details.
17 
 
18 
   You should have received a copy of the GNU General Public License
19 
   along with this file; see the file COPYING.  If not, write to the
20 
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 
   MA 02110-1301, USA.  */
22 
 
23 
#include "ia64-opc.h"
24 
 
25 
#define I0      IA64_TYPE_I, 0
26 
#define I       IA64_TYPE_I, 1
27 
#define I2      IA64_TYPE_I, 2
28 
 
29 
/* instruction bit fields: */
30 
#define bC(x)           (((ia64_insn) ((x) & 0x1)) << 12)
31 
#define bIh(x)          (((ia64_insn) ((x) & 0x1)) << 23)
32 
#define bTa(x)          (((ia64_insn) ((x) & 0x1)) << 33)
33 
#define bTag13(x)       (((ia64_insn) ((x) & 0x1)) << 33)
34 
#define bTb(x)          (((ia64_insn) ((x) & 0x1)) << 36)
35 
#define bVc(x)          (((ia64_insn) ((x) & 0x1)) << 20)
36 
#define bVe(x)          (((ia64_insn) ((x) & 0x1)) << 32)
37 
#define bWh(x)          (((ia64_insn) ((x) & 0x3)) << 20)
38 
#define bX(x)           (((ia64_insn) ((x) & 0x1)) << 33)
39 
#define bXb(x)          (((ia64_insn) ((x) & 0x1)) << 22)
40 
#define bXc(x)          (((ia64_insn) ((x) & 0x1)) << 19)
41 
#define bX2(x)          (((ia64_insn) ((x) & 0x3)) << 34)
42 
#define bX2a(x)         (((ia64_insn) ((x) & 0x3)) << 34)
43 
#define bX2b(x)         (((ia64_insn) ((x) & 0x3)) << 28)
44 
#define bX2c(x)         (((ia64_insn) ((x) & 0x3)) << 30)
45 
#define bX3(x)          (((ia64_insn) ((x) & 0x7)) << 33)
46 
#define bX6(x)          (((ia64_insn) ((x) & 0x3f)) << 27)
47 
#define bYa(x)          (((ia64_insn) ((x) & 0x1)) << 13)
48 
#define bYb(x)          (((ia64_insn) ((x) & 0x1)) << 26)
49 
#define bZa(x)          (((ia64_insn) ((x) & 0x1)) << 36)
50 
#define bZb(x)          (((ia64_insn) ((x) & 0x1)) << 33)
51 
 
52 
/* instruction bit masks: */
53 
#define mC      bC (-1)
54 
#define mIh     bIh (-1)
55 
#define mTa     bTa (-1)
56 
#define mTag13  bTag13 (-1)
57 
#define mTb     bTb (-1)
58 
#define mVc     bVc (-1)
59 
#define mVe     bVe (-1)
60 
#define mWh     bWh (-1)
61 
#define mX      bX (-1)
62 
#define mXb     bXb (-1)
63 
#define mXc     bXc (-1)
64 
#define mX2     bX2 (-1)
65 
#define mX2a    bX2a (-1)
66 
#define mX2b    bX2b (-1)
67 
#define mX2c    bX2c (-1)
68 
#define mX3     bX3 (-1)
69 
#define mX6     bX6 (-1)
70 
#define mYa     bYa (-1)
71 
#define mYb     bYb (-1)
72 
#define mZa     bZa (-1)
73 
#define mZb     bZb (-1)
74 
 
75 
#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \
76 
        (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \
77 
        (mOp | mZa | mZb | mVe | mX2a | mX2b)
78 
#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \
79 
  (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \
80 
        (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c)
81 
#define OpX2X(a,b,c)            (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX)
82 
#define OpX2XYa(a,b,c,d)        (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \
83 
                                (mOp | mX2 | mX | mYa)
84 
#define OpX2XYb(a,b,c,d)        (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \
85 
                                (mOp | mX2 | mX | mYb)
86 
#define OpX2TaTbYaC(a,b,c,d,e,f) \
87 
        (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
88 
        (mOp | mX2 | mTa | mTb | mYa | mC)
89 
#define OpX2TaTbYaXcC(a,b,c,d,e,f,g) \
90 
        (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bXc (f) | bC (g)), \
91 
        (mOp | mX2 | mTa | mTb | mYa | mXc | mC)
92 
#define OpX3(a,b)               (bOp (a) | bX3 (b)), (mOp | mX3)
93 
#define OpX3X6(a,b,c)           (bOp (a) | bX3 (b) | bX6(c)), \
94 
                                (mOp | mX3 | mX6)
95 
#define OpX3X6Yb(a,b,c,d)       (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \
96 
                                (mOp | mX3 | mX6 | mYb)
97 
#define OpX3XbIhWh(a,b,c,d,e) \
98 
  (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
99 
  (mOp | mX3 | mXb | mIh | mWh)
100 
#define OpX3XbIhWhTag13(a,b,c,d,e,f) \
101 
     (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
102 
     (mOp | mX3 | mXb | mIh | mWh | mTag13)
103 
 
104 
#define FULL17 ((ia64_insn)0x10ff001fc0LL)
105 
 
106 
/* Used to initialise unused fields in ia64_opcode struct,
107 
   in order to stop gcc from complaining.  */
108 
#define EMPTY 0,0,NULL
109 
 
110 
struct ia64_opcode ia64_opcodes_i[] =
111 
  {
112 
    /* I-type instruction encodings (sorted according to major opcode).  */
113 
 
114 
    {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL},
115 
    {"nop.i",   I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL},
116 
    {"hint.i",  I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL},
117 
    {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
118 
 
119 
    {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL},
120 
#define MOV(a,b,c,d) \
121 
    I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY
122 
    {"mov.sptk",                MOV (7, 0, 0, 0)},
123 
    {"mov.sptk.imp",            MOV (7, 0, 1, 0)},
124 
    {"mov",                     MOV (7, 0, 0, 1)},
125 
    {"mov.imp",                 MOV (7, 0, 1, 1)},
126 
    {"mov.dptk",                MOV (7, 0, 0, 2)},
127 
    {"mov.dptk.imp",            MOV (7, 0, 1, 2)},
128 
    {"mov.ret.sptk",            MOV (7, 1, 0, 0)},
129 
    {"mov.ret.sptk.imp",        MOV (7, 1, 1, 0)},
130 
    {"mov.ret",                 MOV (7, 1, 0, 1)},
131 
    {"mov.ret.imp",             MOV (7, 1, 1, 1)},
132 
    {"mov.ret.dptk",            MOV (7, 1, 0, 2)},
133 
    {"mov.ret.dptk.imp",        MOV (7, 1, 1, 2)},
134 
#undef MOV
135 
    {"mov",     I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY},
136 
    {"mov",     I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY},
137 
    /* Don't remove one of the seemingly redundant FULL17-s.  */
138 
    {"mov",     I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL},
139 
    {"mov",     I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY},
140 
    {"mov",     I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY},
141 
    {"mov",     I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY},
142 
    {"mov.i",   I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY},
143 
    {"mov.i",   I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY},
144 
    {"mov.i",   I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY},
145 
    {"zxt1",    I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY},
146 
    {"zxt2",    I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY},
147 
    {"zxt4",    I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY},
148 
    {"sxt1",    I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY},
149 
    {"sxt2",    I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY},
150 
    {"sxt4",    I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY},
151 
    {"czx1.l",  I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY},
152 
    {"czx2.l",  I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY},
153 
    {"czx1.r",  I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY},
154 
    {"czx2.r",  I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY},
155 
 
156 
    {"dep",     I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY},
157 
 
158 
    {"shrp",    I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY},
159 
 
160 
    {"shr.u",   I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6},
161 
     PSEUDO | LEN_EQ_64MCNT, 0, NULL},
162 
    {"extr.u",  I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY},
163 
 
164 
    {"shr",     I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6},
165 
     PSEUDO | LEN_EQ_64MCNT, 0, NULL},
166 
    {"extr",    I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY},
167 
 
168 
    {"shl",     I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
169 
     PSEUDO | LEN_EQ_64MCNT, 0, NULL},
170 
    {"dep.z",   I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
171 
    {"dep.z",   I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY},
172 
    {"dep",     I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY},
173 
#define TF(a,b,c) \
174 
        I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY
175 
#define TFCM(a,b,c) \
176 
        I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL
177 
    {"tf.z",             TF   (0, 0, 0)},
178 
    {"tf.nz",            TFCM (0, 0, 0)},
179 
    {"tf.z.unc",         TF   (0, 0, 1)},
180 
    {"tf.nz.unc",        TFCM (0, 0, 1)},
181 
    {"tf.z.and",         TF   (0, 1, 0)},
182 
    {"tf.nz.andcm",      TFCM (0, 1, 0)},
183 
    {"tf.nz.and",        TF   (0, 1, 1)},
184 
    {"tf.z.andcm",       TFCM (0, 1, 1)},
185 
    {"tf.z.or",          TF   (1, 0, 0)},
186 
    {"tf.nz.orcm",       TFCM (1, 0, 0)},
187 
    {"tf.nz.or",         TF   (1, 0, 1)},
188 
    {"tf.z.orcm",        TFCM (1, 0, 1)},
189 
    {"tf.z.or.andcm",    TF   (1, 1, 0)},
190 
    {"tf.nz.and.orcm",   TFCM (1, 1, 0)},
191 
    {"tf.nz.or.andcm",   TF   (1, 1, 1)},
192 
    {"tf.z.and.orcm",    TFCM (1, 1, 1)},
193 
#undef TF
194 
#undef TFCM
195 
#define TBIT(a,b,c,d) \
196 
        I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY
197 
#define TBITCM(a,b,c,d) \
198 
        I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL
199 
    {"tbit.z",           TBIT   (0, 0, 0, 0)},
200 
    {"tbit.nz",          TBITCM (0, 0, 0, 0)},
201 
    {"tbit.z.unc",       TBIT   (0, 0, 0, 1)},
202 
    {"tbit.nz.unc",      TBITCM (0, 0, 0, 1)},
203 
    {"tbit.z.and",       TBIT   (0, 1, 0, 0)},
204 
    {"tbit.nz.andcm",    TBITCM (0, 1, 0, 0)},
205 
    {"tbit.nz.and",      TBIT   (0, 1, 0, 1)},
206 
    {"tbit.z.andcm",     TBITCM (0, 1, 0, 1)},
207 
    {"tbit.z.or",        TBIT   (1, 0, 0, 0)},
208 
    {"tbit.nz.orcm",     TBITCM (1, 0, 0, 0)},
209 
    {"tbit.nz.or",       TBIT   (1, 0, 0, 1)},
210 
    {"tbit.z.orcm",      TBITCM (1, 0, 0, 1)},
211 
    {"tbit.z.or.andcm",  TBIT   (1, 1, 0, 0)},
212 
    {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)},
213 
    {"tbit.nz.or.andcm", TBIT   (1, 1, 0, 1)},
214 
    {"tbit.z.and.orcm",  TBITCM (1, 1, 0, 1)},
215 
#undef TBIT
216 
#undef TBITCM
217 
#define TNAT(a,b,c,d) \
218 
        I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY
219 
#define TNATCM(a,b,c,d) \
220 
        I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL
221 
    {"tnat.z",           TNAT   (0, 0, 1, 0)},
222 
    {"tnat.nz",          TNATCM (0, 0, 1, 0)},
223 
    {"tnat.z.unc",       TNAT   (0, 0, 1, 1)},
224 
    {"tnat.nz.unc",      TNATCM (0, 0, 1, 1)},
225 
    {"tnat.z.and",       TNAT   (0, 1, 1, 0)},
226 
    {"tnat.nz.andcm",    TNATCM (0, 1, 1, 0)},
227 
    {"tnat.nz.and",      TNAT   (0, 1, 1, 1)},
228 
    {"tnat.z.andcm",     TNATCM (0, 1, 1, 1)},
229 
    {"tnat.z.or",        TNAT   (1, 0, 1, 0)},
230 
    {"tnat.nz.orcm",     TNATCM (1, 0, 1, 0)},
231 
    {"tnat.nz.or",       TNAT   (1, 0, 1, 1)},
232 
    {"tnat.z.orcm",      TNATCM (1, 0, 1, 1)},
233 
    {"tnat.z.or.andcm",  TNAT   (1, 1, 1, 0)},
234 
    {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)},
235 
    {"tnat.nz.or.andcm", TNAT   (1, 1, 1, 1)},
236 
    {"tnat.z.and.orcm",  TNATCM (1, 1, 1, 1)},
237 
#undef TNAT
238 
#undef TNATCM
239 
 
240 
    {"pmpyshr2",   I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY},
241 
    {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY},
242 
    {"pmpy2.r",    I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}, EMPTY},
243 
    {"pmpy2.l",    I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}, EMPTY},
244 
    {"mix1.r",     I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
245 
    {"mix2.r",     I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
246 
    {"mix4.r",     I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
247 
    {"mix1.l",     I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
248 
    {"mix2.l",     I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
249 
    {"mix4.l",     I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
250 
    {"pack2.uss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}, EMPTY},
251 
    {"pack2.sss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
252 
    {"pack4.sss",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
253 
    {"unpack1.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
254 
    {"unpack2.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
255 
    {"unpack4.h",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
256 
    {"unpack1.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
257 
    {"unpack2.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
258 
    {"unpack4.l",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
259 
    {"pmin1.u",    I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}, EMPTY},
260 
    {"pmax1.u",    I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}, EMPTY},
261 
    {"pmin2",      I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}, EMPTY},
262 
    {"pmax2",      I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}, EMPTY},
263 
    {"psad1",      I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}, EMPTY},
264 
    {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}, EMPTY},
265 
    {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}, EMPTY},
266 
    {"pshr2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
267 
    {"pshr4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
268 
    {"shr",     I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
269 
    {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
270 
    {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
271 
    {"shr.u",   I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
272 
    {"pshr2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
273 
    {"pshr4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
274 
    {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
275 
    {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
276 
    {"pshl2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
277 
    {"pshl4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
278 
    {"shl",     I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
279 
    {"pshl2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
280 
    {"pshl4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
281 
    {"popcnt",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY},
282 
 
283 
    {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
284 
  };
285 
 
286 
#undef I0
287 
#undef I
288 
#undef I2
289 
#undef L
290 
#undef bC
291 
#undef bIh
292 
#undef bTa
293 
#undef bTag13
294 
#undef bTb
295 
#undef bVc
296 
#undef bVe
297 
#undef bWh
298 
#undef bX
299 
#undef bXb
300 
#undef bX2
301 
#undef bX2a
302 
#undef bX2b
303 
#undef bX2c
304 
#undef bX3
305 
#undef bX6
306 
#undef bY
307 
#undef bZa
308 
#undef bZb
309 
#undef mC
310 
#undef mIh
311 
#undef mTa
312 
#undef mTag13
313 
#undef mTb
314 
#undef mVc
315 
#undef mVe
316 
#undef mWh
317 
#undef mX
318 
#undef mXb
319 
#undef mX2
320 
#undef mX2a
321 
#undef mX2b
322 
#undef mX2c
323 
#undef mX3
324 
#undef mX6
325 
#undef mY
326 
#undef mZa
327 
#undef mZb
328 
#undef OpZaZbVeX2aX2b
329 
#undef OpZaZbVeX2aX2bX2c
330 
#undef OpX2X
331 
#undef OpX2XYa
332 
#undef OpX2XYb
333 
#undef OpX2TaTbYaC
334 
#undef OpX3
335 
#undef OpX3X6
336 
#undef OpX3XbIhWh
337 
#undef OpX3XbIhWhTag13
338 
#undef EMPTY

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.