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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [opcodes/] [ppc-opc.c] - Blame information for rev 205

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/* ppc-opc.c -- PowerPC opcode list
2
   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3
   2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4
   Written by Ian Lance Taylor, Cygnus Support
5
 
6
   This file is part of the GNU opcodes library.
7
 
8
   This library is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3, or (at your option)
11
   any later version.
12
 
13
   It is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this file; see the file COPYING.  If not, write to the
20
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21
   MA 02110-1301, USA.  */
22
 
23
#include <stdio.h>
24
#include "sysdep.h"
25
#include "opcode/ppc.h"
26
#include "opintl.h"
27
 
28
/* This file holds the PowerPC opcode table.  The opcode table
29
   includes almost all of the extended instruction mnemonics.  This
30
   permits the disassembler to use them, and simplifies the assembler
31
   logic, at the cost of increasing the table size.  The table is
32
   strictly constant data, so the compiler should be able to put it in
33
   the .text section.
34
 
35
   This file also holds the operand table.  All knowledge about
36
   inserting operands into instructions and vice-versa is kept in this
37
   file.  */
38
 
39
/* Local insertion and extraction functions.  */
40
 
41
static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
42
static long extract_bat (unsigned long, ppc_cpu_t, int *);
43
static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
44
static long extract_bba (unsigned long, ppc_cpu_t, int *);
45
static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
46
static long extract_bdm (unsigned long, ppc_cpu_t, int *);
47
static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
48
static long extract_bdp (unsigned long, ppc_cpu_t, int *);
49
static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
50
static long extract_bo (unsigned long, ppc_cpu_t, int *);
51
static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
52
static long extract_boe (unsigned long, ppc_cpu_t, int *);
53
static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
54
static long extract_fxm (unsigned long, ppc_cpu_t, int *);
55
static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
56
static long extract_mbe (unsigned long, ppc_cpu_t, int *);
57
static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
58
static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
59
static long extract_nb (unsigned long, ppc_cpu_t, int *);
60
static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
61
static long extract_nsi (unsigned long, ppc_cpu_t, int *);
62
static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
63
static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
64
static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
65
static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
66
static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
67
static long extract_rbs (unsigned long, ppc_cpu_t, int *);
68
static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
69
static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
70
static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
71
static long extract_spr (unsigned long, ppc_cpu_t, int *);
72
static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
73
static long extract_sprg (unsigned long, ppc_cpu_t, int *);
74
static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
75
static long extract_tbr (unsigned long, ppc_cpu_t, int *);
76
static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
77
static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
78
static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
79
static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
80
static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
81
static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
82
static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
83
static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
84
static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
85
static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
86
static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
87
static long extract_dm (unsigned long, ppc_cpu_t, int *);
88
 
89
/* The operands table.
90
 
91
   The fields are bitm, shift, insert, extract, flags.
92
 
93
   We used to put parens around the various additions, like the one
94
   for BA just below.  However, that caused trouble with feeble
95
   compilers with a limit on depth of a parenthesized expression, like
96
   (reportedly) the compiler in Microsoft Developer Studio 5.  So we
97
   omit the parens, since the macros are never used in a context where
98
   the addition will be ambiguous.  */
99
 
100
const struct powerpc_operand powerpc_operands[] =
101
{
102
  /* The zero index is used to indicate the end of the list of
103
     operands.  */
104
#define UNUSED 0
105
  { 0, 0, NULL, NULL, 0 },
106
 
107
  /* The BA field in an XL form instruction.  */
108
#define BA UNUSED + 1
109
  /* The BI field in a B form or XL form instruction.  */
110
#define BI BA
111
#define BI_MASK (0x1f << 16)
112
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
113
 
114
  /* The BA field in an XL form instruction when it must be the same
115
     as the BT field in the same instruction.  */
116
#define BAT BA + 1
117
  { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
118
 
119
  /* The BB field in an XL form instruction.  */
120
#define BB BAT + 1
121
#define BB_MASK (0x1f << 11)
122
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
123
 
124
  /* The BB field in an XL form instruction when it must be the same
125
     as the BA field in the same instruction.  */
126
#define BBA BB + 1
127
  { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
128
 
129
  /* The BD field in a B form instruction.  The lower two bits are
130
     forced to zero.  */
131
#define BD BBA + 1
132
  { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
133
 
134
  /* The BD field in a B form instruction when absolute addressing is
135
     used.  */
136
#define BDA BD + 1
137
  { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
138
 
139
  /* The BD field in a B form instruction when the - modifier is used.
140
     This sets the y bit of the BO field appropriately.  */
141
#define BDM BDA + 1
142
  { 0xfffc, 0, insert_bdm, extract_bdm,
143
      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
144
 
145
  /* The BD field in a B form instruction when the - modifier is used
146
     and absolute address is used.  */
147
#define BDMA BDM + 1
148
  { 0xfffc, 0, insert_bdm, extract_bdm,
149
      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
150
 
151
  /* The BD field in a B form instruction when the + modifier is used.
152
     This sets the y bit of the BO field appropriately.  */
153
#define BDP BDMA + 1
154
  { 0xfffc, 0, insert_bdp, extract_bdp,
155
      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
156
 
157
  /* The BD field in a B form instruction when the + modifier is used
158
     and absolute addressing is used.  */
159
#define BDPA BDP + 1
160
  { 0xfffc, 0, insert_bdp, extract_bdp,
161
      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
162
 
163
  /* The BF field in an X or XL form instruction.  */
164
#define BF BDPA + 1
165
  /* The CRFD field in an X form instruction.  */
166
#define CRFD BF
167
  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
168
 
169
  /* The BF field in an X or XL form instruction.  */
170
#define BFF BF + 1
171
  { 0x7, 23, NULL, NULL, 0 },
172
 
173
  /* An optional BF field.  This is used for comparison instructions,
174
     in which an omitted BF field is taken as zero.  */
175
#define OBF BFF + 1
176
  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
177
 
178
  /* The BFA field in an X or XL form instruction.  */
179
#define BFA OBF + 1
180
  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
181
 
182
  /* The BO field in a B form instruction.  Certain values are
183
     illegal.  */
184
#define BO BFA + 1
185
#define BO_MASK (0x1f << 21)
186
  { 0x1f, 21, insert_bo, extract_bo, 0 },
187
 
188
  /* The BO field in a B form instruction when the + or - modifier is
189
     used.  This is like the BO field, but it must be even.  */
190
#define BOE BO + 1
191
  { 0x1e, 21, insert_boe, extract_boe, 0 },
192
 
193
#define BH BOE + 1
194
  { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
195
 
196
  /* The BT field in an X or XL form instruction.  */
197
#define BT BH + 1
198
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
199
 
200
  /* The condition register number portion of the BI field in a B form
201
     or XL form instruction.  This is used for the extended
202
     conditional branch mnemonics, which set the lower two bits of the
203
     BI field.  This field is optional.  */
204
#define CR BT + 1
205
  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
206
 
207
  /* The CRB field in an X form instruction.  */
208
#define CRB CR + 1
209
  /* The MB field in an M form instruction.  */
210
#define MB CRB
211
#define MB_MASK (0x1f << 6)
212
  { 0x1f, 6, NULL, NULL, 0 },
213
 
214
  /* The CRFS field in an X form instruction.  */
215
#define CRFS CRB + 1
216
  { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
217
 
218
  /* The CT field in an X form instruction.  */
219
#define CT CRFS + 1
220
  /* The MO field in an mbar instruction.  */
221
#define MO CT
222
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
223
 
224
  /* The D field in a D form instruction.  This is a displacement off
225
     a register, and implies that the next operand is a register in
226
     parentheses.  */
227
#define D CT + 1
228
  { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
229
 
230
  /* The DQ field in a DQ form instruction.  This is like D, but the
231
     lower four bits are forced to zero. */
232
#define DQ D + 1
233
  { 0xfff0, 0, NULL, NULL,
234
    PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
235
 
236
  /* The DS field in a DS form instruction.  This is like D, but the
237
     lower two bits are forced to zero.  */
238
#define DS DQ + 1
239
  { 0xfffc, 0, NULL, NULL,
240
    PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
241
 
242
  /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
243
#define DUIS DS + 1
244
  { 0x3ff, 11, NULL, NULL, 0 },
245
 
246
  /* The E field in a wrteei instruction.  */
247
  /* And the W bit in the pair singles instructions.  */
248
#define E DUIS + 1
249
#define PSW E
250
  { 0x1, 15, NULL, NULL, 0 },
251
 
252
  /* The FL1 field in a POWER SC form instruction.  */
253
#define FL1 E + 1
254
  /* The U field in an X form instruction.  */
255
#define U FL1
256
  { 0xf, 12, NULL, NULL, 0 },
257
 
258
  /* The FL2 field in a POWER SC form instruction.  */
259
#define FL2 FL1 + 1
260
  { 0x7, 2, NULL, NULL, 0 },
261
 
262
  /* The FLM field in an XFL form instruction.  */
263
#define FLM FL2 + 1
264
  { 0xff, 17, NULL, NULL, 0 },
265
 
266
  /* The FRA field in an X or A form instruction.  */
267
#define FRA FLM + 1
268
#define FRA_MASK (0x1f << 16)
269
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
270
 
271
  /* The FRB field in an X or A form instruction.  */
272
#define FRB FRA + 1
273
#define FRB_MASK (0x1f << 11)
274
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
275
 
276
  /* The FRC field in an A form instruction.  */
277
#define FRC FRB + 1
278
#define FRC_MASK (0x1f << 6)
279
  { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
280
 
281
  /* The FRS field in an X form instruction or the FRT field in a D, X
282
     or A form instruction.  */
283
#define FRS FRC + 1
284
#define FRT FRS
285
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
286
 
287
  /* The FXM field in an XFX instruction.  */
288
#define FXM FRS + 1
289
  { 0xff, 12, insert_fxm, extract_fxm, 0 },
290
 
291
  /* Power4 version for mfcr.  */
292
#define FXM4 FXM + 1
293
  { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
294
 
295
  /* The L field in a D or X form instruction.  */
296
#define L FXM4 + 1
297
  { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
298
 
299
  /* The LEV field in a POWER SVC form instruction.  */
300
#define SVC_LEV L + 1
301
  { 0x7f, 5, NULL, NULL, 0 },
302
 
303
  /* The LEV field in an SC form instruction.  */
304
#define LEV SVC_LEV + 1
305
  { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
306
 
307
  /* The LI field in an I form instruction.  The lower two bits are
308
     forced to zero.  */
309
#define LI LEV + 1
310
  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
311
 
312
  /* The LI field in an I form instruction when used as an absolute
313
     address.  */
314
#define LIA LI + 1
315
  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
316
 
317
  /* The LS or WC field in an X (sync or wait) form instruction.  */
318
#define LS LIA + 1
319
#define WC LS
320
  { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
321
 
322
  /* The ME field in an M form instruction.  */
323
#define ME LS + 1
324
#define ME_MASK (0x1f << 1)
325
  { 0x1f, 1, NULL, NULL, 0 },
326
 
327
  /* The MB and ME fields in an M form instruction expressed a single
328
     operand which is a bitmask indicating which bits to select.  This
329
     is a two operand form using PPC_OPERAND_NEXT.  See the
330
     description in opcode/ppc.h for what this means.  */
331
#define MBE ME + 1
332
  { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
333
  { -1, 0, insert_mbe, extract_mbe, 0 },
334
 
335
  /* The MB or ME field in an MD or MDS form instruction.  The high
336
     bit is wrapped to the low end.  */
337
#define MB6 MBE + 2
338
#define ME6 MB6
339
#define MB6_MASK (0x3f << 5)
340
  { 0x3f, 5, insert_mb6, extract_mb6, 0 },
341
 
342
  /* The NB field in an X form instruction.  The value 32 is stored as
343
     0.  */
344
#define NB MB6 + 1
345
  { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
346
 
347
  /* The NSI field in a D form instruction.  This is the same as the
348
     SI field, only negated.  */
349
#define NSI NB + 1
350
  { 0xffff, 0, insert_nsi, extract_nsi,
351
      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
352
 
353
  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
354
#define RA NSI + 1
355
#define RA_MASK (0x1f << 16)
356
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
357
 
358
  /* As above, but 0 in the RA field means zero, not r0.  */
359
#define RA0 RA + 1
360
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
361
 
362
  /* The RA field in the DQ form lq instruction, which has special
363
     value restrictions.  */
364
#define RAQ RA0 + 1
365
  { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
366
 
367
  /* The RA field in a D or X form instruction which is an updating
368
     load, which means that the RA field may not be zero and may not
369
     equal the RT field.  */
370
#define RAL RAQ + 1
371
  { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
372
 
373
  /* The RA field in an lmw instruction, which has special value
374
     restrictions.  */
375
#define RAM RAL + 1
376
  { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
377
 
378
  /* The RA field in a D or X form instruction which is an updating
379
     store or an updating floating point load, which means that the RA
380
     field may not be zero.  */
381
#define RAS RAM + 1
382
  { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
383
 
384
  /* The RA field of the tlbwe instruction, which is optional.  */
385
#define RAOPT RAS + 1
386
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
387
 
388
  /* The RB field in an X, XO, M, or MDS form instruction.  */
389
#define RB RAOPT + 1
390
#define RB_MASK (0x1f << 11)
391
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
392
 
393
  /* The RB field in an X form instruction when it must be the same as
394
     the RS field in the instruction.  This is used for extended
395
     mnemonics like mr.  */
396
#define RBS RB + 1
397
  { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
398
 
399
  /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
400
     instruction or the RT field in a D, DS, X, XFX or XO form
401
     instruction.  */
402
#define RS RBS + 1
403
#define RT RS
404
#define RT_MASK (0x1f << 21)
405
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
406
 
407
  /* The RS and RT fields of the DS form stq instruction, which have
408
     special value restrictions.  */
409
#define RSQ RS + 1
410
#define RTQ RSQ
411
  { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
412
 
413
  /* The RS field of the tlbwe instruction, which is optional.  */
414
#define RSO RSQ + 1
415
#define RTO RSO
416
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
417
 
418
  /* The SH field in an X or M form instruction.  */
419
#define SH RSO + 1
420
#define SH_MASK (0x1f << 11)
421
  /* The other UIMM field in a EVX form instruction.  */
422
#define EVUIMM SH
423
  { 0x1f, 11, NULL, NULL, 0 },
424
 
425
  /* The SH field in an MD form instruction.  This is split.  */
426
#define SH6 SH + 1
427
#define SH6_MASK ((0x1f << 11) | (1 << 1))
428
  { 0x3f, -1, insert_sh6, extract_sh6, 0 },
429
 
430
  /* The SH field of the tlbwe instruction, which is optional.  */
431
#define SHO SH6 + 1
432
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
433
 
434
  /* The SI field in a D form instruction.  */
435
#define SI SHO + 1
436
  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
437
 
438
  /* The SI field in a D form instruction when we accept a wide range
439
     of positive values.  */
440
#define SISIGNOPT SI + 1
441
  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
442
 
443
  /* The SPR field in an XFX form instruction.  This is flipped--the
444
     lower 5 bits are stored in the upper 5 and vice- versa.  */
445
#define SPR SISIGNOPT + 1
446
#define PMR SPR
447
#define SPR_MASK (0x3ff << 11)
448
  { 0x3ff, 11, insert_spr, extract_spr, 0 },
449
 
450
  /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
451
#define SPRBAT SPR + 1
452
#define SPRBAT_MASK (0x3 << 17)
453
  { 0x3, 17, NULL, NULL, 0 },
454
 
455
  /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
456
#define SPRG SPRBAT + 1
457
  { 0x1f, 16, insert_sprg, extract_sprg, 0 },
458
 
459
  /* The SR field in an X form instruction.  */
460
#define SR SPRG + 1
461
  { 0xf, 16, NULL, NULL, 0 },
462
 
463
  /* The STRM field in an X AltiVec form instruction.  */
464
#define STRM SR + 1
465
  /* The T field in a tlbilx form instruction.  */
466
#define T STRM
467
  { 0x3, 21, NULL, NULL, 0 },
468
 
469
  /* The SV field in a POWER SC form instruction.  */
470
#define SV STRM + 1
471
  { 0x3fff, 2, NULL, NULL, 0 },
472
 
473
  /* The TBR field in an XFX form instruction.  This is like the SPR
474
     field, but it is optional.  */
475
#define TBR SV + 1
476
  { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
477
 
478
  /* The TO field in a D or X form instruction.  */
479
#define TO TBR + 1
480
#define DUI TO
481
#define TO_MASK (0x1f << 21)
482
  { 0x1f, 21, NULL, NULL, 0 },
483
 
484
  /* The UI field in a D form instruction.  */
485
#define UI TO + 1
486
  { 0xffff, 0, NULL, NULL, 0 },
487
 
488
  /* The VA field in a VA, VX or VXR form instruction.  */
489
#define VA UI + 1
490
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
491
 
492
  /* The VB field in a VA, VX or VXR form instruction.  */
493
#define VB VA + 1
494
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
495
 
496
  /* The VC field in a VA form instruction.  */
497
#define VC VB + 1
498
  { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
499
 
500
  /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
501
#define VD VC + 1
502
#define VS VD
503
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
504
 
505
  /* The SIMM field in a VX form instruction, and TE in Z form.  */
506
#define SIMM VD + 1
507
#define TE SIMM
508
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
509
 
510
  /* The UIMM field in a VX form instruction.  */
511
#define UIMM SIMM + 1
512
  { 0x1f, 16, NULL, NULL, 0 },
513
 
514
  /* The SHB field in a VA form instruction.  */
515
#define SHB UIMM + 1
516
  { 0xf, 6, NULL, NULL, 0 },
517
 
518
  /* The other UIMM field in a half word EVX form instruction.  */
519
#define EVUIMM_2 SHB + 1
520
  { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
521
 
522
  /* The other UIMM field in a word EVX form instruction.  */
523
#define EVUIMM_4 EVUIMM_2 + 1
524
  { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
525
 
526
  /* The other UIMM field in a double EVX form instruction.  */
527
#define EVUIMM_8 EVUIMM_4 + 1
528
  { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
529
 
530
  /* The WS field.  */
531
#define WS EVUIMM_8 + 1
532
  { 0x7, 11, NULL, NULL, 0 },
533
 
534
  /* PowerPC paired singles extensions.  */
535
  /* W bit in the pair singles instructions for x type instructions.  */
536
#define PSWM WS + 1
537
  {  0x1, 10, 0, 0, 0 },
538
 
539
  /* IDX bits for quantization in the pair singles instructions.  */
540
#define PSQ PSWM + 1
541
  {  0x7, 12, 0, 0, 0 },
542
 
543
  /* IDX bits for quantization in the pair singles x-type instructions.  */
544
#define PSQM PSQ + 1
545
  {  0x7, 7, 0, 0, 0 },
546
 
547
  /* Smaller D field for quantization in the pair singles instructions.  */
548
#define PSD PSQM + 1
549
  {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
550
 
551
#define A_L PSD + 1
552
#define W A_L
553
#define MTMSRD_L W
554
  { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
555
 
556
#define RMC MTMSRD_L + 1
557
  { 0x3, 9, NULL, NULL, 0 },
558
 
559
#define R RMC + 1
560
  { 0x1, 16, NULL, NULL, 0 },
561
 
562
#define SP R + 1
563
  { 0x3, 19, NULL, NULL, 0 },
564
 
565
#define S SP + 1
566
  { 0x1, 20, NULL, NULL, 0 },
567
 
568
  /* SH field starting at bit position 16.  */
569
#define SH16 S + 1
570
  /* The DCM and DGM fields in a Z form instruction.  */
571
#define DCM SH16
572
#define DGM DCM
573
  { 0x3f, 10, NULL, NULL, 0 },
574
 
575
  /* The EH field in larx instruction.  */
576
#define EH SH16 + 1
577
  { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
578
 
579
  /* The L field in an mtfsf or XFL form instruction.  */
580
#define XFL_L EH + 1
581
  { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
582
 
583
  /* Xilinx APU related masks and macros */
584
#define FCRT XFL_L + 1
585
#define FCRT_MASK (0x1f << 21)
586
  { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
587
 
588
  /* Xilinx FSL related masks and macros */
589
#define FSL FCRT + 1
590
#define FSL_MASK (0x1f << 11)
591
  { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
592
 
593
  /* Xilinx UDI related masks and macros */
594
#define URT FSL + 1
595
  { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
596
 
597
#define URA URT + 1
598
  { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
599
 
600
#define URB URA + 1
601
  { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
602
 
603
#define URC URB + 1
604
  { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
605
 
606
  /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
607
#define XS6 URC + 1
608
#define XT6 XS6
609
  { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
610
 
611
  /* The XA field in an XX3 form instruction.  This is split.  */
612
#define XA6 XT6 + 1
613
  { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
614
 
615
  /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
616
#define XB6 XA6 + 1
617
  { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
618
 
619
  /* The XB field in an XX3 form instruction when it must be the same as
620
     the XA field in the instruction.  This is used in extended mnemonics
621
     like xvmovdp.  This is split.  */
622
#define XB6S XB6 + 1
623
  { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
624
 
625
  /* The XC field in an XX4 form instruction.  This is split.  */
626
#define XC6 XB6S + 1
627
  { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
628
 
629
  /* The DM or SHW field in an XX3 form instruction.  */
630
#define DM XC6 + 1
631
#define SHW DM
632
  { 0x3, 8, NULL, NULL, 0 },
633
 
634
  /* The DM field in an extended mnemonic XX3 form instruction.  */
635
#define DMEX DM + 1
636
  { 0x3, 8, insert_dm, extract_dm, 0 },
637
 
638
  /* The UIM field in an XX2 form instruction.  */
639
#define UIM DMEX + 1
640
  { 0x3, 16, NULL, NULL, 0 },
641
 
642
#define ERAT_T UIM + 1
643
  { 0x7, 21, NULL, NULL, 0 },
644
};
645
 
646
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
647
                                           / sizeof (powerpc_operands[0]));
648
 
649
/* The functions used to insert and extract complicated operands.  */
650
 
651
/* The BA field in an XL form instruction when it must be the same as
652
   the BT field in the same instruction.  This operand is marked FAKE.
653
   The insertion function just copies the BT field into the BA field,
654
   and the extraction function just checks that the fields are the
655
   same.  */
656
 
657
static unsigned long
658
insert_bat (unsigned long insn,
659
            long value ATTRIBUTE_UNUSED,
660
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
661
            const char **errmsg ATTRIBUTE_UNUSED)
662
{
663
  return insn | (((insn >> 21) & 0x1f) << 16);
664
}
665
 
666
static long
667
extract_bat (unsigned long insn,
668
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
669
             int *invalid)
670
{
671
  if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
672
    *invalid = 1;
673
  return 0;
674
}
675
 
676
/* The BB field in an XL form instruction when it must be the same as
677
   the BA field in the same instruction.  This operand is marked FAKE.
678
   The insertion function just copies the BA field into the BB field,
679
   and the extraction function just checks that the fields are the
680
   same.  */
681
 
682
static unsigned long
683
insert_bba (unsigned long insn,
684
            long value ATTRIBUTE_UNUSED,
685
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
686
            const char **errmsg ATTRIBUTE_UNUSED)
687
{
688
  return insn | (((insn >> 16) & 0x1f) << 11);
689
}
690
 
691
static long
692
extract_bba (unsigned long insn,
693
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
694
             int *invalid)
695
{
696
  if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
697
    *invalid = 1;
698
  return 0;
699
}
700
 
701
/* The BD field in a B form instruction when the - modifier is used.
702
   This modifier means that the branch is not expected to be taken.
703
   For chips built to versions of the architecture prior to version 2
704
   (ie. not Power4 compatible), we set the y bit of the BO field to 1
705
   if the offset is negative.  When extracting, we require that the y
706
   bit be 1 and that the offset be positive, since if the y bit is 0
707
   we just want to print the normal form of the instruction.
708
   Power4 compatible targets use two bits, "a", and "t", instead of
709
   the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
710
   "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
711
   in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
712
   for branch on CTR.  We only handle the taken/not-taken hint here.
713
   Note that we don't relax the conditions tested here when
714
   disassembling with -Many because insns using extract_bdm and
715
   extract_bdp always occur in pairs.  One or the other will always
716
   be valid.  */
717
 
718
static unsigned long
719
insert_bdm (unsigned long insn,
720
            long value,
721
            ppc_cpu_t dialect,
722
            const char **errmsg ATTRIBUTE_UNUSED)
723
{
724
  if ((dialect & PPC_OPCODE_POWER4) == 0)
725
    {
726
      if ((value & 0x8000) != 0)
727
        insn |= 1 << 21;
728
    }
729
  else
730
    {
731
      if ((insn & (0x14 << 21)) == (0x04 << 21))
732
        insn |= 0x02 << 21;
733
      else if ((insn & (0x14 << 21)) == (0x10 << 21))
734
        insn |= 0x08 << 21;
735
    }
736
  return insn | (value & 0xfffc);
737
}
738
 
739
static long
740
extract_bdm (unsigned long insn,
741
             ppc_cpu_t dialect,
742
             int *invalid)
743
{
744
  if ((dialect & PPC_OPCODE_POWER4) == 0)
745
    {
746
      if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
747
        *invalid = 1;
748
    }
749
  else
750
    {
751
      if ((insn & (0x17 << 21)) != (0x06 << 21)
752
          && (insn & (0x1d << 21)) != (0x18 << 21))
753
        *invalid = 1;
754
    }
755
 
756
  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
757
}
758
 
759
/* The BD field in a B form instruction when the + modifier is used.
760
   This is like BDM, above, except that the branch is expected to be
761
   taken.  */
762
 
763
static unsigned long
764
insert_bdp (unsigned long insn,
765
            long value,
766
            ppc_cpu_t dialect,
767
            const char **errmsg ATTRIBUTE_UNUSED)
768
{
769
  if ((dialect & PPC_OPCODE_POWER4) == 0)
770
    {
771
      if ((value & 0x8000) == 0)
772
        insn |= 1 << 21;
773
    }
774
  else
775
    {
776
      if ((insn & (0x14 << 21)) == (0x04 << 21))
777
        insn |= 0x03 << 21;
778
      else if ((insn & (0x14 << 21)) == (0x10 << 21))
779
        insn |= 0x09 << 21;
780
    }
781
  return insn | (value & 0xfffc);
782
}
783
 
784
static long
785
extract_bdp (unsigned long insn,
786
             ppc_cpu_t dialect,
787
             int *invalid)
788
{
789
  if ((dialect & PPC_OPCODE_POWER4) == 0)
790
    {
791
      if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
792
        *invalid = 1;
793
    }
794
  else
795
    {
796
      if ((insn & (0x17 << 21)) != (0x07 << 21)
797
          && (insn & (0x1d << 21)) != (0x19 << 21))
798
        *invalid = 1;
799
    }
800
 
801
  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
802
}
803
 
804
/* Check for legal values of a BO field.  */
805
 
806
static int
807
valid_bo (long value, ppc_cpu_t dialect, int extract)
808
{
809
  if ((dialect & PPC_OPCODE_POWER4) == 0)
810
    {
811
      int valid;
812
      /* Certain encodings have bits that are required to be zero.
813
         These are (z must be zero, y may be anything):
814
             001zy
815
             011zy
816
             1z00y
817
             1z01y
818
             1z1zz
819
      */
820
      switch (value & 0x14)
821
        {
822
        default:
823
        case 0:
824
          valid = 1;
825
          break;
826
        case 0x4:
827
          valid = (value & 0x2) == 0;
828
          break;
829
        case 0x10:
830
          valid = (value & 0x8) == 0;
831
          break;
832
        case 0x14:
833
          valid = value == 0x14;
834
          break;
835
        }
836
      /* When disassembling with -Many, accept power4 encodings too.  */
837
      if (valid
838
          || (dialect & PPC_OPCODE_ANY) == 0
839
          || !extract)
840
        return valid;
841
    }
842
 
843
  /* Certain encodings have bits that are required to be zero.
844
     These are (z must be zero, a & t may be anything):
845
         0000z
846
         0001z
847
         0100z
848
         0101z
849
         001at
850
         011at
851
         1a00t
852
         1a01t
853
         1z1zz
854
  */
855
  if ((value & 0x14) == 0)
856
    return (value & 0x1) == 0;
857
  else if ((value & 0x14) == 0x14)
858
    return value == 0x14;
859
  else
860
    return 1;
861
}
862
 
863
/* The BO field in a B form instruction.  Warn about attempts to set
864
   the field to an illegal value.  */
865
 
866
static unsigned long
867
insert_bo (unsigned long insn,
868
           long value,
869
           ppc_cpu_t dialect,
870
           const char **errmsg)
871
{
872
  if (!valid_bo (value, dialect, 0))
873
    *errmsg = _("invalid conditional option");
874
  return insn | ((value & 0x1f) << 21);
875
}
876
 
877
static long
878
extract_bo (unsigned long insn,
879
            ppc_cpu_t dialect,
880
            int *invalid)
881
{
882
  long value;
883
 
884
  value = (insn >> 21) & 0x1f;
885
  if (!valid_bo (value, dialect, 1))
886
    *invalid = 1;
887
  return value;
888
}
889
 
890
/* The BO field in a B form instruction when the + or - modifier is
891
   used.  This is like the BO field, but it must be even.  When
892
   extracting it, we force it to be even.  */
893
 
894
static unsigned long
895
insert_boe (unsigned long insn,
896
            long value,
897
            ppc_cpu_t dialect,
898
            const char **errmsg)
899
{
900
  if (!valid_bo (value, dialect, 0))
901
    *errmsg = _("invalid conditional option");
902
  else if ((value & 1) != 0)
903
    *errmsg = _("attempt to set y bit when using + or - modifier");
904
 
905
  return insn | ((value & 0x1f) << 21);
906
}
907
 
908
static long
909
extract_boe (unsigned long insn,
910
             ppc_cpu_t dialect,
911
             int *invalid)
912
{
913
  long value;
914
 
915
  value = (insn >> 21) & 0x1f;
916
  if (!valid_bo (value, dialect, 1))
917
    *invalid = 1;
918
  return value & 0x1e;
919
}
920
 
921
/* FXM mask in mfcr and mtcrf instructions.  */
922
 
923
static unsigned long
924
insert_fxm (unsigned long insn,
925
            long value,
926
            ppc_cpu_t dialect,
927
            const char **errmsg)
928
{
929
  /* If we're handling the mfocrf and mtocrf insns ensure that exactly
930
     one bit of the mask field is set.  */
931
  if ((insn & (1 << 20)) != 0)
932
    {
933
      if (value == 0 || (value & -value) != value)
934
        {
935
          *errmsg = _("invalid mask field");
936
          value = 0;
937
        }
938
    }
939
 
940
  /* If the optional field on mfcr is missing that means we want to use
941
     the old form of the instruction that moves the whole cr.  In that
942
     case we'll have VALUE zero.  There doesn't seem to be a way to
943
     distinguish this from the case where someone writes mfcr %r3,0.  */
944
  else if (value == 0)
945
    ;
946
 
947
  /* If only one bit of the FXM field is set, we can use the new form
948
     of the instruction, which is faster.  Unlike the Power4 branch hint
949
     encoding, this is not backward compatible.  Do not generate the
950
     new form unless -mpower4 has been given, or -many and the two
951
     operand form of mfcr was used.  */
952
  else if ((value & -value) == value
953
           && ((dialect & PPC_OPCODE_POWER4) != 0
954
               || ((dialect & PPC_OPCODE_ANY) != 0
955
                   && (insn & (0x3ff << 1)) == 19 << 1)))
956
    insn |= 1 << 20;
957
 
958
  /* Any other value on mfcr is an error.  */
959
  else if ((insn & (0x3ff << 1)) == 19 << 1)
960
    {
961
      *errmsg = _("ignoring invalid mfcr mask");
962
      value = 0;
963
    }
964
 
965
  return insn | ((value & 0xff) << 12);
966
}
967
 
968
static long
969
extract_fxm (unsigned long insn,
970
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
971
             int *invalid)
972
{
973
  long mask = (insn >> 12) & 0xff;
974
 
975
  /* Is this a Power4 insn?  */
976
  if ((insn & (1 << 20)) != 0)
977
    {
978
      /* Exactly one bit of MASK should be set.  */
979
      if (mask == 0 || (mask & -mask) != mask)
980
        *invalid = 1;
981
    }
982
 
983
  /* Check that non-power4 form of mfcr has a zero MASK.  */
984
  else if ((insn & (0x3ff << 1)) == 19 << 1)
985
    {
986
      if (mask != 0)
987
        *invalid = 1;
988
    }
989
 
990
  return mask;
991
}
992
 
993
/* The MB and ME fields in an M form instruction expressed as a single
994
   operand which is itself a bitmask.  The extraction function always
995
   marks it as invalid, since we never want to recognize an
996
   instruction which uses a field of this type.  */
997
 
998
static unsigned long
999
insert_mbe (unsigned long insn,
1000
            long value,
1001
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1002
            const char **errmsg)
1003
{
1004
  unsigned long uval, mask;
1005
  int mb, me, mx, count, last;
1006
 
1007
  uval = value;
1008
 
1009
  if (uval == 0)
1010
    {
1011
      *errmsg = _("illegal bitmask");
1012
      return insn;
1013
    }
1014
 
1015
  mb = 0;
1016
  me = 32;
1017
  if ((uval & 1) != 0)
1018
    last = 1;
1019
  else
1020
    last = 0;
1021
  count = 0;
1022
 
1023
  /* mb: location of last 0->1 transition */
1024
  /* me: location of last 1->0 transition */
1025
  /* count: # transitions */
1026
 
1027
  for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1028
    {
1029
      if ((uval & mask) && !last)
1030
        {
1031
          ++count;
1032
          mb = mx;
1033
          last = 1;
1034
        }
1035
      else if (!(uval & mask) && last)
1036
        {
1037
          ++count;
1038
          me = mx;
1039
          last = 0;
1040
        }
1041
    }
1042
  if (me == 0)
1043
    me = 32;
1044
 
1045
  if (count != 2 && (count != 0 || ! last))
1046
    *errmsg = _("illegal bitmask");
1047
 
1048
  return insn | (mb << 6) | ((me - 1) << 1);
1049
}
1050
 
1051
static long
1052
extract_mbe (unsigned long insn,
1053
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1054
             int *invalid)
1055
{
1056
  long ret;
1057
  int mb, me;
1058
  int i;
1059
 
1060
  *invalid = 1;
1061
 
1062
  mb = (insn >> 6) & 0x1f;
1063
  me = (insn >> 1) & 0x1f;
1064
  if (mb < me + 1)
1065
    {
1066
      ret = 0;
1067
      for (i = mb; i <= me; i++)
1068
        ret |= 1L << (31 - i);
1069
    }
1070
  else if (mb == me + 1)
1071
    ret = ~0;
1072
  else /* (mb > me + 1) */
1073
    {
1074
      ret = ~0;
1075
      for (i = me + 1; i < mb; i++)
1076
        ret &= ~(1L << (31 - i));
1077
    }
1078
  return ret;
1079
}
1080
 
1081
/* The MB or ME field in an MD or MDS form instruction.  The high bit
1082
   is wrapped to the low end.  */
1083
 
1084
static unsigned long
1085
insert_mb6 (unsigned long insn,
1086
            long value,
1087
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1088
            const char **errmsg ATTRIBUTE_UNUSED)
1089
{
1090
  return insn | ((value & 0x1f) << 6) | (value & 0x20);
1091
}
1092
 
1093
static long
1094
extract_mb6 (unsigned long insn,
1095
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1096
             int *invalid ATTRIBUTE_UNUSED)
1097
{
1098
  return ((insn >> 6) & 0x1f) | (insn & 0x20);
1099
}
1100
 
1101
/* The NB field in an X form instruction.  The value 32 is stored as
1102
   0.  */
1103
 
1104
static long
1105
extract_nb (unsigned long insn,
1106
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1107
            int *invalid ATTRIBUTE_UNUSED)
1108
{
1109
  long ret;
1110
 
1111
  ret = (insn >> 11) & 0x1f;
1112
  if (ret == 0)
1113
    ret = 32;
1114
  return ret;
1115
}
1116
 
1117
/* The NSI field in a D form instruction.  This is the same as the SI
1118
   field, only negated.  The extraction function always marks it as
1119
   invalid, since we never want to recognize an instruction which uses
1120
   a field of this type.  */
1121
 
1122
static unsigned long
1123
insert_nsi (unsigned long insn,
1124
            long value,
1125
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1126
            const char **errmsg ATTRIBUTE_UNUSED)
1127
{
1128
  return insn | (-value & 0xffff);
1129
}
1130
 
1131
static long
1132
extract_nsi (unsigned long insn,
1133
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1134
             int *invalid)
1135
{
1136
  *invalid = 1;
1137
  return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1138
}
1139
 
1140
/* The RA field in a D or X form instruction which is an updating
1141
   load, which means that the RA field may not be zero and may not
1142
   equal the RT field.  */
1143
 
1144
static unsigned long
1145
insert_ral (unsigned long insn,
1146
            long value,
1147
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1148
            const char **errmsg)
1149
{
1150
  if (value == 0
1151
      || (unsigned long) value == ((insn >> 21) & 0x1f))
1152
    *errmsg = "invalid register operand when updating";
1153
  return insn | ((value & 0x1f) << 16);
1154
}
1155
 
1156
/* The RA field in an lmw instruction, which has special value
1157
   restrictions.  */
1158
 
1159
static unsigned long
1160
insert_ram (unsigned long insn,
1161
            long value,
1162
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1163
            const char **errmsg)
1164
{
1165
  if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1166
    *errmsg = _("index register in load range");
1167
  return insn | ((value & 0x1f) << 16);
1168
}
1169
 
1170
/* The RA field in the DQ form lq instruction, which has special
1171
   value restrictions.  */
1172
 
1173
static unsigned long
1174
insert_raq (unsigned long insn,
1175
            long value,
1176
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1177
            const char **errmsg)
1178
{
1179
  long rtvalue = (insn & RT_MASK) >> 21;
1180
 
1181
  if (value == rtvalue)
1182
    *errmsg = _("source and target register operands must be different");
1183
  return insn | ((value & 0x1f) << 16);
1184
}
1185
 
1186
/* The RA field in a D or X form instruction which is an updating
1187
   store or an updating floating point load, which means that the RA
1188
   field may not be zero.  */
1189
 
1190
static unsigned long
1191
insert_ras (unsigned long insn,
1192
            long value,
1193
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1194
            const char **errmsg)
1195
{
1196
  if (value == 0)
1197
    *errmsg = _("invalid register operand when updating");
1198
  return insn | ((value & 0x1f) << 16);
1199
}
1200
 
1201
/* The RB field in an X form instruction when it must be the same as
1202
   the RS field in the instruction.  This is used for extended
1203
   mnemonics like mr.  This operand is marked FAKE.  The insertion
1204
   function just copies the BT field into the BA field, and the
1205
   extraction function just checks that the fields are the same.  */
1206
 
1207
static unsigned long
1208
insert_rbs (unsigned long insn,
1209
            long value ATTRIBUTE_UNUSED,
1210
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1211
            const char **errmsg ATTRIBUTE_UNUSED)
1212
{
1213
  return insn | (((insn >> 21) & 0x1f) << 11);
1214
}
1215
 
1216
static long
1217
extract_rbs (unsigned long insn,
1218
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1219
             int *invalid)
1220
{
1221
  if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1222
    *invalid = 1;
1223
  return 0;
1224
}
1225
 
1226
/* The SH field in an MD form instruction.  This is split.  */
1227
 
1228
static unsigned long
1229
insert_sh6 (unsigned long insn,
1230
            long value,
1231
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1232
            const char **errmsg ATTRIBUTE_UNUSED)
1233
{
1234
  return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1235
}
1236
 
1237
static long
1238
extract_sh6 (unsigned long insn,
1239
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1240
             int *invalid ATTRIBUTE_UNUSED)
1241
{
1242
  return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1243
}
1244
 
1245
/* The SPR field in an XFX form instruction.  This is flipped--the
1246
   lower 5 bits are stored in the upper 5 and vice- versa.  */
1247
 
1248
static unsigned long
1249
insert_spr (unsigned long insn,
1250
            long value,
1251
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1252
            const char **errmsg ATTRIBUTE_UNUSED)
1253
{
1254
  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1255
}
1256
 
1257
static long
1258
extract_spr (unsigned long insn,
1259
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1260
             int *invalid ATTRIBUTE_UNUSED)
1261
{
1262
  return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1263
}
1264
 
1265
/* Some dialects have 8 SPRG registers instead of the standard 4.  */
1266
 
1267
static unsigned long
1268
insert_sprg (unsigned long insn,
1269
             long value,
1270
             ppc_cpu_t dialect,
1271
             const char **errmsg)
1272
{
1273
  if (value > 7
1274
      || (value > 3
1275
          && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
1276
    *errmsg = _("invalid sprg number");
1277
 
1278
  /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1279
     user mode.  Anything else must use spr 272..279.  */
1280
  if (value <= 3 || (insn & 0x100) != 0)
1281
    value |= 0x10;
1282
 
1283
  return insn | ((value & 0x17) << 16);
1284
}
1285
 
1286
static long
1287
extract_sprg (unsigned long insn,
1288
              ppc_cpu_t dialect,
1289
              int *invalid)
1290
{
1291
  unsigned long val = (insn >> 16) & 0x1f;
1292
 
1293
  /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1294
     If not BOOKE or 405, then both use only 272..275.  */
1295
  if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
1296
      || (val - 0x10 > 7 && (insn & 0x100) != 0)
1297
      || val <= 3
1298
      || (val & 8) != 0)
1299
    *invalid = 1;
1300
  return val & 7;
1301
}
1302
 
1303
/* The TBR field in an XFX instruction.  This is just like SPR, but it
1304
   is optional.  When TBR is omitted, it must be inserted as 268 (the
1305
   magic number of the TB register).  These functions treat 0
1306
   (indicating an omitted optional operand) as 268.  This means that
1307
   ``mftb 4,0'' is not handled correctly.  This does not matter very
1308
   much, since the architecture manual does not define mftb as
1309
   accepting any values other than 268 or 269.  */
1310
 
1311
#define TB (268)
1312
 
1313
static unsigned long
1314
insert_tbr (unsigned long insn,
1315
            long value,
1316
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1317
            const char **errmsg ATTRIBUTE_UNUSED)
1318
{
1319
  if (value == 0)
1320
    value = TB;
1321
  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1322
}
1323
 
1324
static long
1325
extract_tbr (unsigned long insn,
1326
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1327
             int *invalid ATTRIBUTE_UNUSED)
1328
{
1329
  long ret;
1330
 
1331
  ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1332
  if (ret == TB)
1333
    ret = 0;
1334
  return ret;
1335
}
1336
 
1337
/* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
1338
 
1339
static unsigned long
1340
insert_xt6 (unsigned long insn,
1341
            long value,
1342
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1343
            const char **errmsg ATTRIBUTE_UNUSED)
1344
{
1345
  return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1346
}
1347
 
1348
static long
1349
extract_xt6 (unsigned long insn,
1350
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1351
             int *invalid ATTRIBUTE_UNUSED)
1352
{
1353
  return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1354
}
1355
 
1356
/* The XA field in an XX3 form instruction.  This is split.  */
1357
 
1358
static unsigned long
1359
insert_xa6 (unsigned long insn,
1360
            long value,
1361
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1362
            const char **errmsg ATTRIBUTE_UNUSED)
1363
{
1364
  return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1365
}
1366
 
1367
static long
1368
extract_xa6 (unsigned long insn,
1369
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1370
             int *invalid ATTRIBUTE_UNUSED)
1371
{
1372
  return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1373
}
1374
 
1375
/* The XB field in an XX3 form instruction.  This is split.  */
1376
 
1377
static unsigned long
1378
insert_xb6 (unsigned long insn,
1379
            long value,
1380
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1381
            const char **errmsg ATTRIBUTE_UNUSED)
1382
{
1383
  return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1384
}
1385
 
1386
static long
1387
extract_xb6 (unsigned long insn,
1388
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1389
             int *invalid ATTRIBUTE_UNUSED)
1390
{
1391
  return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1392
}
1393
 
1394
/* The XB field in an XX3 form instruction when it must be the same as
1395
   the XA field in the instruction.  This is used for extended
1396
   mnemonics like xvmovdp.  This operand is marked FAKE.  The insertion
1397
   function just copies the XA field into the XB field, and the
1398
   extraction function just checks that the fields are the same.  */
1399
 
1400
static unsigned long
1401
insert_xb6s (unsigned long insn,
1402
            long value ATTRIBUTE_UNUSED,
1403
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1404
            const char **errmsg ATTRIBUTE_UNUSED)
1405
{
1406
  return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1407
}
1408
 
1409
static long
1410
extract_xb6s (unsigned long insn,
1411
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1412
             int *invalid)
1413
{
1414
  if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1415
      || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1416
    *invalid = 1;
1417
  return 0;
1418
}
1419
 
1420
/* The XC field in an XX4 form instruction.  This is split.  */
1421
 
1422
static unsigned long
1423
insert_xc6 (unsigned long insn,
1424
            long value,
1425
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1426
            const char **errmsg ATTRIBUTE_UNUSED)
1427
{
1428
  return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1429
}
1430
 
1431
static long
1432
extract_xc6 (unsigned long insn,
1433
             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1434
             int *invalid ATTRIBUTE_UNUSED)
1435
{
1436
  return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
1437
}
1438
 
1439
static unsigned long
1440
insert_dm (unsigned long insn,
1441
           long value,
1442
           ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1443
           const char **errmsg)
1444
{
1445
  if (value != 0 && value != 1)
1446
    *errmsg = _("invalid constant");
1447
  return insn | (((value) ? 3 : 0) << 8);
1448
}
1449
 
1450
static long
1451
extract_dm (unsigned long insn,
1452
            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1453
            int *invalid)
1454
{
1455
  long value;
1456
 
1457
  value = (insn >> 8) & 3;
1458
  if (value != 0 && value != 3)
1459
    *invalid = 1;
1460
  return (value) ? 1 : 0;
1461
}
1462
 
1463
/* Macros used to form opcodes.  */
1464
 
1465
/* The main opcode.  */
1466
#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1467
#define OP_MASK OP (0x3f)
1468
 
1469
/* The main opcode combined with a trap code in the TO field of a D
1470
   form instruction.  Used for extended mnemonics for the trap
1471
   instructions.  */
1472
#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1473
#define OPTO_MASK (OP_MASK | TO_MASK)
1474
 
1475
/* The main opcode combined with a comparison size bit in the L field
1476
   of a D form or X form instruction.  Used for extended mnemonics for
1477
   the comparison instructions.  */
1478
#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1479
#define OPL_MASK OPL (0x3f,1)
1480
 
1481
/* An A form instruction.  */
1482
#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1483
#define A_MASK A (0x3f, 0x1f, 1)
1484
 
1485
/* An A_MASK with the FRB field fixed.  */
1486
#define AFRB_MASK (A_MASK | FRB_MASK)
1487
 
1488
/* An A_MASK with the FRC field fixed.  */
1489
#define AFRC_MASK (A_MASK | FRC_MASK)
1490
 
1491
/* An A_MASK with the FRA and FRC fields fixed.  */
1492
#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1493
 
1494
/* An AFRAFRC_MASK, but with L bit clear.  */
1495
#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1496
 
1497
/* A B form instruction.  */
1498
#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1499
#define B_MASK B (0x3f, 1, 1)
1500
 
1501
/* A B form instruction setting the BO field.  */
1502
#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1503
#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1504
 
1505
/* A BBO_MASK with the y bit of the BO field removed.  This permits
1506
   matching a conditional branch regardless of the setting of the y
1507
   bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1508
#define Y_MASK   (((unsigned long) 1) << 21)
1509
#define AT1_MASK (((unsigned long) 3) << 21)
1510
#define AT2_MASK (((unsigned long) 9) << 21)
1511
#define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1512
#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1513
 
1514
/* A B form instruction setting the BO field and the condition bits of
1515
   the BI field.  */
1516
#define BBOCB(op, bo, cb, aa, lk) \
1517
  (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1518
#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1519
 
1520
/* A BBOCB_MASK with the y bit of the BO field removed.  */
1521
#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1522
#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1523
#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1524
 
1525
/* A BBOYCB_MASK in which the BI field is fixed.  */
1526
#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1527
#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1528
 
1529
/* An Context form instruction.  */
1530
#define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1531
#define CTX_MASK CTX(0x3f, 0x7)
1532
 
1533
/* An User Context form instruction.  */
1534
#define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1535
#define UCTX_MASK UCTX(0x3f, 0x1f)
1536
 
1537
/* The main opcode mask with the RA field clear.  */
1538
#define DRA_MASK (OP_MASK | RA_MASK)
1539
 
1540
/* A DS form instruction.  */
1541
#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1542
#define DS_MASK DSO (0x3f, 3)
1543
 
1544
/* An EVSEL form instruction.  */
1545
#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1546
#define EVSEL_MASK EVSEL(0x3f, 0xff)
1547
 
1548
/* An M form instruction.  */
1549
#define M(op, rc) (OP (op) | ((rc) & 1))
1550
#define M_MASK M (0x3f, 1)
1551
 
1552
/* An M form instruction with the ME field specified.  */
1553
#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1554
 
1555
/* An M_MASK with the MB and ME fields fixed.  */
1556
#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1557
 
1558
/* An M_MASK with the SH and ME fields fixed.  */
1559
#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1560
 
1561
/* An MD form instruction.  */
1562
#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1563
#define MD_MASK MD (0x3f, 0x7, 1)
1564
 
1565
/* An MD_MASK with the MB field fixed.  */
1566
#define MDMB_MASK (MD_MASK | MB6_MASK)
1567
 
1568
/* An MD_MASK with the SH field fixed.  */
1569
#define MDSH_MASK (MD_MASK | SH6_MASK)
1570
 
1571
/* An MDS form instruction.  */
1572
#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1573
#define MDS_MASK MDS (0x3f, 0xf, 1)
1574
 
1575
/* An MDS_MASK with the MB field fixed.  */
1576
#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1577
 
1578
/* An SC form instruction.  */
1579
#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1580
#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1581
 
1582
/* An VX form instruction.  */
1583
#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1584
 
1585
/* The mask for an VX form instruction.  */
1586
#define VX_MASK VX(0x3f, 0x7ff)
1587
 
1588
/* An VA form instruction.  */
1589
#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1590
 
1591
/* The mask for an VA form instruction.  */
1592
#define VXA_MASK VXA(0x3f, 0x3f)
1593
 
1594
/* An VXR form instruction.  */
1595
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1596
 
1597
/* The mask for a VXR form instruction.  */
1598
#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1599
 
1600
/* An X form instruction.  */
1601
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1602
 
1603
/* An XX2 form instruction.  */
1604
#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
1605
 
1606
/* An XX3 form instruction.  */
1607
#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
1608
 
1609
/* An XX3 form instruction with the RC bit specified.  */
1610
#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
1611
 
1612
/* An XX4 form instruction.  */
1613
#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
1614
 
1615
/* A Z form instruction.  */
1616
#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1617
 
1618
/* An X form instruction with the RC bit specified.  */
1619
#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1620
 
1621
/* A Z form instruction with the RC bit specified.  */
1622
#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1623
 
1624
/* The mask for an X form instruction.  */
1625
#define X_MASK XRC (0x3f, 0x3ff, 1)
1626
 
1627
/* An X form wait instruction with everything filled in except the WC field.  */
1628
#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
1629
 
1630
/* The mask for an XX1 form instruction.  */
1631
#define XX1_MASK X (0x3f, 0x3ff)
1632
 
1633
/* The mask for an XX2 form instruction.  */
1634
#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
1635
 
1636
/* The mask for an XX2 form instruction with the UIM bits specified.  */
1637
#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
1638
 
1639
/* The mask for an XX2 form instruction with the BF bits specified.  */
1640
#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
1641
 
1642
/* The mask for an XX3 form instruction.  */
1643
#define XX3_MASK XX3 (0x3f, 0xff)
1644
 
1645
/* The mask for an XX3 form instruction with the BF bits specified.  */
1646
#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
1647
 
1648
/* The mask for an XX3 form instruction with the DM or SHW bits specified.  */
1649
#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
1650
#define XX3SHW_MASK XX3DM_MASK
1651
 
1652
/* The mask for an XX4 form instruction.  */
1653
#define XX4_MASK XX4 (0x3f, 0x3)
1654
 
1655
/* An X form wait instruction with everything filled in except the WC field.  */
1656
#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
1657
 
1658
/* The mask for a Z form instruction.  */
1659
#define Z_MASK ZRC (0x3f, 0x1ff, 1)
1660
#define Z2_MASK ZRC (0x3f, 0xff, 1)
1661
 
1662
/* An X_MASK with the RA field fixed.  */
1663
#define XRA_MASK (X_MASK | RA_MASK)
1664
 
1665
/* An XRA_MASK with the W field clear.  */
1666
#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1667
 
1668
/* An X_MASK with the RB field fixed.  */
1669
#define XRB_MASK (X_MASK | RB_MASK)
1670
 
1671
/* An X_MASK with the RT field fixed.  */
1672
#define XRT_MASK (X_MASK | RT_MASK)
1673
 
1674
/* An XRT_MASK mask with the L bits clear.  */
1675
#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1676
 
1677
/* An X_MASK with the RA and RB fields fixed.  */
1678
#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1679
 
1680
/* An XRARB_MASK, but with the L bit clear.  */
1681
#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1682
 
1683
/* An X_MASK with the RT and RA fields fixed.  */
1684
#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1685
 
1686
/* An XRTRA_MASK, but with L bit clear.  */
1687
#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1688
 
1689
/* An X form instruction with the L bit specified.  */
1690
#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1691
 
1692
/* An X form instruction with the L bits specified.  */
1693
#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1694
 
1695
/* An X form instruction with RT fields specified */
1696
#define XRT(op, xop, rt) (X ((op), (xop)) \
1697
        | ((((unsigned long)(rt)) & 0x1f) << 21))
1698
 
1699
/* An X form instruction with RT and RA fields specified */
1700
#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
1701
        | ((((unsigned long)(rt)) & 0x1f) << 21) \
1702
        | ((((unsigned long)(ra)) & 0x1f) << 16))
1703
 
1704
/* The mask for an X form comparison instruction.  */
1705
#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1706
 
1707
/* The mask for an X form comparison instruction with the L field
1708
   fixed.  */
1709
#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1710
 
1711
/* An X form trap instruction with the TO field specified.  */
1712
#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1713
#define XTO_MASK (X_MASK | TO_MASK)
1714
 
1715
/* An X form tlb instruction with the SH field specified.  */
1716
#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1717
#define XTLB_MASK (X_MASK | SH_MASK)
1718
 
1719
/* An X form sync instruction.  */
1720
#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1721
 
1722
/* An X form sync instruction with everything filled in except the LS field.  */
1723
#define XSYNC_MASK (0xff9fffff)
1724
 
1725
/* An X_MASK, but with the EH bit clear.  */
1726
#define XEH_MASK (X_MASK & ~((unsigned long )1))
1727
 
1728
/* An X form AltiVec dss instruction.  */
1729
#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1730
#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1731
 
1732
/* An XFL form instruction.  */
1733
#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1734
#define XFL_MASK XFL (0x3f, 0x3ff, 1)
1735
 
1736
/* An X form isel instruction.  */
1737
#define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1738
#define XISEL_MASK      XISEL(0x3f, 0x1f)
1739
 
1740
/* An XL form instruction with the LK field set to 0.  */
1741
#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1742
 
1743
/* An XL form instruction which uses the LK field.  */
1744
#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1745
 
1746
/* The mask for an XL form instruction.  */
1747
#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1748
 
1749
/* An XL form instruction which explicitly sets the BO field.  */
1750
#define XLO(op, bo, xop, lk) \
1751
  (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1752
#define XLO_MASK (XL_MASK | BO_MASK)
1753
 
1754
/* An XL form instruction which explicitly sets the y bit of the BO
1755
   field.  */
1756
#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1757
#define XLYLK_MASK (XL_MASK | Y_MASK)
1758
 
1759
/* An XL form instruction which sets the BO field and the condition
1760
   bits of the BI field.  */
1761
#define XLOCB(op, bo, cb, xop, lk) \
1762
  (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1763
#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1764
 
1765
/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1766
#define XLBB_MASK (XL_MASK | BB_MASK)
1767
#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1768
#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1769
 
1770
/* A mask for branch instructions using the BH field.  */
1771
#define XLBH_MASK (XL_MASK | (0x1c << 11))
1772
 
1773
/* An XL_MASK with the BO and BB fields fixed.  */
1774
#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1775
 
1776
/* An XL_MASK with the BO, BI and BB fields fixed.  */
1777
#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1778
 
1779
/* An XO form instruction.  */
1780
#define XO(op, xop, oe, rc) \
1781
  (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1782
#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1783
 
1784
/* An XO_MASK with the RB field fixed.  */
1785
#define XORB_MASK (XO_MASK | RB_MASK)
1786
 
1787
/* An XOPS form instruction for paired singles.  */
1788
#define XOPS(op, xop, rc) \
1789
  (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1790
#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1791
 
1792
 
1793
/* An XS form instruction.  */
1794
#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1795
#define XS_MASK XS (0x3f, 0x1ff, 1)
1796
 
1797
/* A mask for the FXM version of an XFX form instruction.  */
1798
#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1799
 
1800
/* An XFX form instruction with the FXM field filled in.  */
1801
#define XFXM(op, xop, fxm, p4) \
1802
  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1803
   | ((unsigned long)(p4) << 20))
1804
 
1805
/* An XFX form instruction with the SPR field filled in.  */
1806
#define XSPR(op, xop, spr) \
1807
  (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1808
#define XSPR_MASK (X_MASK | SPR_MASK)
1809
 
1810
/* An XFX form instruction with the SPR field filled in except for the
1811
   SPRBAT field.  */
1812
#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1813
 
1814
/* An XFX form instruction with the SPR field filled in except for the
1815
   SPRG field.  */
1816
#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1817
 
1818
/* An X form instruction with everything filled in except the E field.  */
1819
#define XE_MASK (0xffff7fff)
1820
 
1821
/* An X form user context instruction.  */
1822
#define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1823
#define XUC_MASK      XUC(0x3f, 0x1f)
1824
 
1825
/* An XW form instruction.  */
1826
#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1827
/* The mask for a G form instruction. rc not supported at present.  */
1828
#define XW_MASK XW (0x3f, 0x3f, 0)
1829
 
1830
/* An APU form instruction.  */
1831
#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
1832
 
1833
/* The mask for an APU form instruction.  */
1834
#define APU_MASK APU (0x3f, 0x3ff, 1)
1835
#define APU_RT_MASK (APU_MASK | RT_MASK)
1836
#define APU_RA_MASK (APU_MASK | RA_MASK)
1837
 
1838
/* The BO encodings used in extended conditional branch mnemonics.  */
1839
#define BODNZF  (0x0)
1840
#define BODNZFP (0x1)
1841
#define BODZF   (0x2)
1842
#define BODZFP  (0x3)
1843
#define BODNZT  (0x8)
1844
#define BODNZTP (0x9)
1845
#define BODZT   (0xa)
1846
#define BODZTP  (0xb)
1847
 
1848
#define BOF     (0x4)
1849
#define BOFP    (0x5)
1850
#define BOFM4   (0x6)
1851
#define BOFP4   (0x7)
1852
#define BOT     (0xc)
1853
#define BOTP    (0xd)
1854
#define BOTM4   (0xe)
1855
#define BOTP4   (0xf)
1856
 
1857
#define BODNZ   (0x10)
1858
#define BODNZP  (0x11)
1859
#define BODZ    (0x12)
1860
#define BODZP   (0x13)
1861
#define BODNZM4 (0x18)
1862
#define BODNZP4 (0x19)
1863
#define BODZM4  (0x1a)
1864
#define BODZP4  (0x1b)
1865
 
1866
#define BOU     (0x14)
1867
 
1868
/* The BI condition bit encodings used in extended conditional branch
1869
   mnemonics.  */
1870
#define CBLT    (0)
1871
#define CBGT    (1)
1872
#define CBEQ    (2)
1873
#define CBSO    (3)
1874
 
1875
/* The TO encodings used in extended trap mnemonics.  */
1876
#define TOLGT   (0x1)
1877
#define TOLLT   (0x2)
1878
#define TOEQ    (0x4)
1879
#define TOLGE   (0x5)
1880
#define TOLNL   (0x5)
1881
#define TOLLE   (0x6)
1882
#define TOLNG   (0x6)
1883
#define TOGT    (0x8)
1884
#define TOGE    (0xc)
1885
#define TONL    (0xc)
1886
#define TOLT    (0x10)
1887
#define TOLE    (0x14)
1888
#define TONG    (0x14)
1889
#define TONE    (0x18)
1890
#define TOU     (0x1f)
1891
 
1892
/* Smaller names for the flags so each entry in the opcodes table will
1893
   fit on a single line.  */
1894
#define PPCNONE 0
1895
#undef  PPC
1896
#define PPC     PPC_OPCODE_PPC
1897
#define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1898
#define POWER4  PPC_OPCODE_POWER4
1899
#define POWER5  PPC_OPCODE_POWER5
1900
#define POWER6  PPC_OPCODE_POWER6
1901
#define POWER7  PPC_OPCODE_POWER7
1902
#define CELL    PPC_OPCODE_CELL
1903
#define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1904
#define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1905
#define PPC403  PPC_OPCODE_403
1906
#define PPC405  PPC_OPCODE_405
1907
#define PPC440  PPC_OPCODE_440
1908
#define PPC464  PPC440
1909
#define PPC476  PPC_OPCODE_476
1910
#define PPC750  PPC
1911
#define PPC7450 PPC
1912
#define PPC860  PPC
1913
#define PPCPS   PPC_OPCODE_PPCPS
1914
#define PPCVEC  PPC_OPCODE_ALTIVEC
1915
#define PPCVSX  PPC_OPCODE_VSX
1916
#define POWER   PPC_OPCODE_POWER
1917
#define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1918
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1919
#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1920
#define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1921
#define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1922
#define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1923
#define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1924
#define MFDEC1  PPC_OPCODE_POWER
1925
#define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1926
#define BOOKE   PPC_OPCODE_BOOKE
1927
#define CLASSIC PPC_OPCODE_CLASSIC
1928
#define PPCE300 PPC_OPCODE_E300
1929
#define PPCSPE  PPC_OPCODE_SPE
1930
#define PPCISEL PPC_OPCODE_ISEL
1931
#define PPCEFS  PPC_OPCODE_EFS
1932
#define PPCBRLK PPC_OPCODE_BRLOCK
1933
#define PPCPMR  PPC_OPCODE_PMR
1934
#define PPCCHLK PPC_OPCODE_CACHELCK
1935
#define PPCRFMCI        PPC_OPCODE_RFMCI
1936
#define E500MC  PPC_OPCODE_E500MC
1937
#define PPCA2   PPC_OPCODE_A2
1938
 
1939
/* The opcode table.
1940
 
1941
   The format of the opcode table is:
1942
 
1943
   NAME         OPCODE          MASK         FLAGS      {OPERANDS}
1944
 
1945
   NAME is the name of the instruction.
1946
   OPCODE is the instruction opcode.
1947
   MASK is the opcode mask; this is used to tell the disassembler
1948
     which bits in the actual opcode must match OPCODE.
1949
   FLAGS are flags indicated what processors support the instruction.
1950
   OPERANDS is the list of operands.
1951
 
1952
   The disassembler reads the table in order and prints the first
1953
   instruction which matches, so this table is sorted to put more
1954
   specific instructions before more general instructions.
1955
 
1956
   This table must be sorted by major opcode.  Please try to keep it
1957
   vaguely sorted within major opcode too, except of course where
1958
   constrained otherwise by disassembler operation.  */
1959
 
1960
const struct powerpc_opcode powerpc_opcodes[] = {
1961
{"attn",        X(0,256),        X_MASK,   POWER4|PPCA2, PPC476,         {0}},
1962
{"tdlgti",      OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1963
{"tdllti",      OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1964
{"tdeqi",       OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1965
{"tdlgei",      OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1966
{"tdlnli",      OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1967
{"tdllei",      OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1968
{"tdlngi",      OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1969
{"tdgti",       OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1970
{"tdgei",       OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1971
{"tdnli",       OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1972
{"tdlti",       OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1973
{"tdlei",       OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1974
{"tdngi",       OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1975
{"tdnei",       OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1976
{"tdi",         OP(2),          OP_MASK,     PPC64,     PPCNONE,        {TO, RA, SI}},
1977
 
1978
{"twlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1979
{"tlgti",       OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1980
{"twllti",      OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1981
{"tllti",       OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1982
{"tweqi",       OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1983
{"teqi",        OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1984
{"twlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1985
{"tlgei",       OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1986
{"twlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1987
{"tlnli",       OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1988
{"twllei",      OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1989
{"tllei",       OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1990
{"twlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1991
{"tlngi",       OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1992
{"twgti",       OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1993
{"tgti",        OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1994
{"twgei",       OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1995
{"tgei",        OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1996
{"twnli",       OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1997
{"tnli",        OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1998
{"twlti",       OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1999
{"tlti",        OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2000
{"twlei",       OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2001
{"tlei",        OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2002
{"twngi",       OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2003
{"tngi",        OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2004
{"twnei",       OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2005
{"tnei",        OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2006
{"twi",         OP(3),          OP_MASK,     PPCCOM,    PPCNONE,        {TO, RA, SI}},
2007
{"ti",          OP(3),          OP_MASK,     PWRCOM,    PPCNONE,        {TO, RA, SI}},
2008
 
2009
{"ps_cmpu0",    X  (4,   0), X_MASK|(3<<21), PPCPS,      PPCNONE,        {BF, FRA, FRB}},
2010
{"vaddubm",     VX (4,   0),     VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2011
{"vmaxub",      VX (4,   2),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2012
{"vrlb",        VX (4,   4),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2013
{"vcmpequb",    VXR(4,   6,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2014
{"vmuloub",     VX (4,   8),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2015
{"vaddfp",      VX (4,  10),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2016
{"psq_lx",      XW (4,   6,0),   XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2017
{"vmrghb",      VX (4,  12),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2018
{"psq_stx",     XW (4,   7,0),   XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2019
{"vpkuhum",     VX (4,  14),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2020
{"mulhhwu",     XRC(4,   8,0),   X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2021
{"mulhhwu.",    XRC(4,   8,1),  X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2022
{"ps_sum0",     A  (4,  10,0),   A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2023
{"ps_sum0.",    A  (4,  10,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2024
{"ps_sum1",     A  (4,  11,0),   A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2025
{"ps_sum1.",    A  (4,  11,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2026
{"ps_muls0",    A  (4,  12,0),   AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2027
{"machhwu",     XO (4,  12,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2028
{"ps_muls0.",   A  (4,  12,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2029
{"machhwu.",    XO (4,  12,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2030
{"ps_muls1",    A  (4,  13,0),   AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2031
{"ps_muls1.",   A  (4,  13,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2032
{"ps_madds0",   A  (4,  14,0),   A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2033
{"ps_madds0.",  A  (4,  14,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2034
{"ps_madds1",   A  (4,  15,0),   A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2035
{"ps_madds1.",  A  (4,  15,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2036
{"vmhaddshs",   VXA(4,  32),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2037
{"vmhraddshs",  VXA(4,  33),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2038
{"vmladduhm",   VXA(4,  34),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2039
{"ps_div",      A  (4,  18,0),   AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2040
{"vmsumubm",    VXA(4,  36),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2041
{"ps_div.",     A  (4,  18,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2042
{"vmsummbm",    VXA(4,  37),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2043
{"vmsumuhm",    VXA(4,  38),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2044
{"vmsumuhs",    VXA(4,  39),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2045
{"ps_sub",      A  (4,  20,0),   AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2046
{"vmsumshm",    VXA(4,  40),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2047
{"ps_sub.",     A  (4,  20,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2048
{"vmsumshs",    VXA(4,  41),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2049
{"ps_add",      A  (4,  21,0),   AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2050
{"vsel",        VXA(4,  42),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2051
{"ps_add.",     A  (4,  21,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2052
{"vperm",       VXA(4,  43),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2053
{"vsldoi",      VXA(4,  44),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, SHB}},
2054
{"ps_sel",      A  (4,  23,0),   A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2055
{"vmaddfp",     VXA(4,  46),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VC, VB}},
2056
{"ps_sel.",     A  (4,  23,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2057
{"vnmsubfp",    VXA(4,  47),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VC, VB}},
2058
{"ps_res",      A  (4,  24,0), AFRAFRC_MASK, PPCPS,      PPCNONE,        {FRT, FRB}},
2059
{"ps_res.",     A  (4,  24,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2060
{"ps_mul",      A  (4,  25,0), AFRB_MASK,    PPCPS,      PPCNONE,        {FRT, FRA, FRC}},
2061
{"ps_mul.",     A  (4,  25,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2062
{"ps_rsqrte",   A  (4,  26,0), AFRAFRC_MASK, PPCPS,      PPCNONE,        {FRT, FRB}},
2063
{"ps_rsqrte.",  A  (4,  26,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2064
{"ps_msub",     A  (4,  28,0),   A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2065
{"ps_msub.",    A  (4,  28,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2066
{"ps_madd",     A  (4,  29,0),   A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2067
{"ps_madd.",    A  (4,  29,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2068
{"ps_nmsub",    A  (4,  30,0),   A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2069
{"ps_nmsub.",   A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2070
{"ps_nmadd",    A  (4,  31,0),   A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2071
{"ps_nmadd.",   A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2072
{"ps_cmpo0",    X  (4,  32), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2073
{"vadduhm",     VX (4,  64),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2074
{"vmaxuh",      VX (4,  66),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2075
{"vrlh",        VX (4,  68),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2076
{"vcmpequh",    VXR(4,  70,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2077
{"vmulouh",     VX (4,  72),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2078
{"vsubfp",      VX (4,  74),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2079
{"psq_lux",     XW (4,  38,0),   XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2080
{"vmrghh",      VX (4,  76),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2081
{"psq_stux",    XW (4,  39,0),   XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2082
{"vpkuwum",     VX (4,  78),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2083
{"ps_neg",      XRC(4,  40,0),   XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2084
{"mulhhw",      XRC(4,  40,0),   X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2085
{"ps_neg.",     XRC(4,  40,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2086
{"mulhhw.",     XRC(4,  40,1),  X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2087
{"machhw",      XO (4,  44,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2088
{"machhw.",     XO (4,  44,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2089
{"nmachhw",     XO (4,  46,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2090
{"nmachhw.",    XO (4,  46,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2091
{"ps_cmpu1",    X  (4,  64), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2092
{"vadduwm",     VX (4,  128),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2093
{"vmaxuw",      VX (4,  130),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2094
{"vrlw",        VX (4,  132),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2095
{"vcmpequw",    VXR(4,  134,0), VXR_MASK,    PPCVEC,     PPCNONE,        {VD, VA, VB}},
2096
{"vmrghw",      VX (4,  140),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2097
{"vpkuhus",     VX (4,  142),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2098
{"ps_mr",       XRC(4,  72,0),   XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2099
{"ps_mr.",      XRC(4,  72,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2100
{"machhwsu",    XO (4,  76,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2101
{"machhwsu.",   XO (4,  76,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2102
{"ps_cmpo1",    X  (4,  96), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2103
{"vcmpeqfp",    VXR(4, 198,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2104
{"vpkuwus",     VX (4, 206),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2105
{"machhws",     XO (4, 108,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2106
{"machhws.",    XO (4, 108,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2107
{"nmachhws",    XO (4, 110,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2108
{"nmachhws.",   XO (4, 110,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2109
{"vmaxsb",      VX (4, 258),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2110
{"vslb",        VX (4, 260),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2111
{"vmulosb",     VX (4, 264),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2112
{"vrefp",       VX (4, 266),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2113
{"vmrglb",      VX (4, 268),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2114
{"vpkshus",     VX (4, 270),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2115
{"ps_nabs",     XRC(4, 136,0),   XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2116
{"mulchwu",     XRC(4, 136,0),   X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2117
{"ps_nabs.",    XRC(4, 136,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2118
{"mulchwu.",    XRC(4, 136,1),  X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2119
{"macchwu",     XO (4, 140,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2120
{"macchwu.",    XO (4, 140,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2121
{"vmaxsh",      VX (4, 322),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2122
{"vslh",        VX (4, 324),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2123
{"vmulosh",     VX (4, 328),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2124
{"vrsqrtefp",   VX (4, 330),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2125
{"vmrglh",      VX (4, 332),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2126
{"vpkswus",     VX (4, 334),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2127
{"mulchw",      XRC(4, 168,0),   X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2128
{"mulchw.",     XRC(4, 168,1),  X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2129
{"macchw",      XO (4, 172,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2130
{"macchw.",     XO (4, 172,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2131
{"nmacchw",     XO (4, 174,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2132
{"nmacchw.",    XO (4, 174,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2133
{"vaddcuw",     VX (4, 384),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2134
{"vmaxsw",      VX (4, 386),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2135
{"vslw",        VX (4, 388),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2136
{"vexptefp",    VX (4, 394),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2137
{"vmrglw",      VX (4, 396),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2138
{"vpkshss",     VX (4, 398),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2139
{"macchwsu",    XO (4, 204,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2140
{"macchwsu.",   XO (4, 204,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2141
{"vsl",         VX (4, 452),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2142
{"vcmpgefp",    VXR(4, 454,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2143
{"vlogefp",     VX (4, 458),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2144
{"vpkswss",     VX (4, 462),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2145
{"macchws",     XO (4, 236,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2146
{"macchws.",    XO (4, 236,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2147
{"nmacchws",    XO (4, 238,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2148
{"nmacchws.",   XO (4, 238,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2149
{"evaddw",      VX (4, 512),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2150
{"vaddubs",     VX (4, 512),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2151
{"evaddiw",     VX (4, 514),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
2152
{"vminub",      VX (4, 514),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2153
{"evsubfw",     VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2154
{"evsubw",      VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, RA}},
2155
{"vsrb",        VX (4, 516),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2156
{"evsubifw",    VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, UIMM, RB}},
2157
{"evsubiw",     VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
2158
{"vcmpgtub",    VXR(4, 518,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2159
{"evabs",       VX (4, 520),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2160
{"vmuleub",     VX (4, 520),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2161
{"evneg",       VX (4, 521),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2162
{"evextsb",     VX (4, 522),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2163
{"vrfin",       VX (4, 522),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2164
{"evextsh",     VX (4, 523),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2165
{"evrndw",      VX (4, 524),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2166
{"vspltb",      VX (4, 524),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2167
{"evcntlzw",    VX (4, 525),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2168
{"evcntlsw",    VX (4, 526),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2169
{"vupkhsb",     VX (4, 526),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2170
{"brinc",       VX (4, 527),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2171
{"ps_abs",      XRC(4, 264,0),   XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2172
{"ps_abs.",     XRC(4, 264,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2173
{"evand",       VX (4, 529),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2174
{"evandc",      VX (4, 530),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2175
{"evxor",       VX (4, 534),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2176
{"evmr",        VX (4, 535),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, BBA}},
2177
{"evor",        VX (4, 535),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2178
{"evnor",       VX (4, 536),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2179
{"evnot",       VX (4, 536),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, BBA}},
2180
{"get",         APU(4, 268,0),   APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2181
{"eveqv",       VX (4, 537),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2182
{"evorc",       VX (4, 539),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2183
{"evnand",      VX (4, 542),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2184
{"evsrwu",      VX (4, 544),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2185
{"evsrws",      VX (4, 545),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2186
{"evsrwiu",     VX (4, 546),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2187
{"evsrwis",     VX (4, 547),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2188
{"evslw",       VX (4, 548),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2189
{"evslwi",      VX (4, 550),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2190
{"evrlw",       VX (4, 552),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2191
{"evsplati",    VX (4, 553),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, SIMM}},
2192
{"evrlwi",      VX (4, 554),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2193
{"evsplatfi",   VX (4, 555),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, SIMM}},
2194
{"evmergehi",   VX (4, 556),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2195
{"evmergelo",   VX (4, 557),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2196
{"evmergehilo", VX (4, 558),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2197
{"evmergelohi", VX (4, 559),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2198
{"evcmpgtu",    VX (4, 560),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2199
{"evcmpgts",    VX (4, 561),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2200
{"evcmpltu",    VX (4, 562),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2201
{"evcmplts",    VX (4, 563),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2202
{"evcmpeq",     VX (4, 564),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2203
{"cget",        APU(4, 284,0),   APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2204
{"vadduhs",     VX (4, 576),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2205
{"vminuh",      VX (4, 578),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2206
{"vsrh",        VX (4, 580),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2207
{"vcmpgtuh",    VXR(4, 582,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2208
{"vmuleuh",     VX (4, 584),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2209
{"vrfiz",       VX (4, 586),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2210
{"vsplth",      VX (4, 588),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2211
{"vupkhsh",     VX (4, 590),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2212
{"nget",        APU(4, 300,0),   APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2213
{"evsel",       EVSEL(4,79),    EVSEL_MASK,  PPCSPE,    PPCNONE,        {RS, RA, RB, CRFS}},
2214
{"ncget",       APU(4, 316,0),   APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2215
{"evfsadd",     VX (4, 640),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2216
{"vadduws",     VX (4, 640),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2217
{"evfssub",     VX (4, 641),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2218
{"vminuw",      VX (4, 642),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2219
{"evfsabs",     VX (4, 644),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2220
{"vsrw",        VX (4, 644),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2221
{"evfsnabs",    VX (4, 645),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2222
{"evfsneg",     VX (4, 646),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2223
{"vcmpgtuw",    VXR(4, 646,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2224
{"evfsmul",     VX (4, 648),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2225
{"evfsdiv",     VX (4, 649),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2226
{"vrfip",       VX (4, 650),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2227
{"evfscmpgt",   VX (4, 652),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2228
{"vspltw",      VX (4, 652),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2229
{"evfscmplt",   VX (4, 653),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2230
{"evfscmpeq",   VX (4, 654),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2231
{"vupklsb",     VX (4, 654),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2232
{"evfscfui",    VX (4, 656),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2233
{"evfscfsi",    VX (4, 657),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2234
{"evfscfuf",    VX (4, 658),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2235
{"evfscfsf",    VX (4, 659),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2236
{"evfsctui",    VX (4, 660),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2237
{"evfsctsi",    VX (4, 661),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2238
{"evfsctuf",    VX (4, 662),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2239
{"evfsctsf",    VX (4, 663),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2240
{"evfsctuiz",   VX (4, 664),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2241
{"put",         APU(4, 332,0),   APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2242
{"evfsctsiz",   VX (4, 666),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2243
{"evfststgt",   VX (4, 668),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2244
{"evfststlt",   VX (4, 669),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2245
{"evfststeq",   VX (4, 670),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2246
{"cput",        APU(4, 348,0),   APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2247
{"efsadd",      VX (4, 704),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2248
{"efssub",      VX (4, 705),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2249
{"efsabs",      VX (4, 708),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2250
{"vsr",         VX (4, 708),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2251
{"efsnabs",     VX (4, 709),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2252
{"efsneg",      VX (4, 710),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2253
{"vcmpgtfp",    VXR(4, 710,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2254
{"efsmul",      VX (4, 712),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2255
{"efsdiv",      VX (4, 713),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2256
{"vrfim",       VX (4, 714),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2257
{"efscmpgt",    VX (4, 716),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2258
{"efscmplt",    VX (4, 717),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2259
{"efscmpeq",    VX (4, 718),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2260
{"vupklsh",     VX (4, 718),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2261
{"efscfd",      VX (4, 719),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2262
{"efscfui",     VX (4, 720),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2263
{"efscfsi",     VX (4, 721),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2264
{"efscfuf",     VX (4, 722),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2265
{"efscfsf",     VX (4, 723),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2266
{"efsctui",     VX (4, 724),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2267
{"efsctsi",     VX (4, 725),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2268
{"efsctuf",     VX (4, 726),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2269
{"efsctsf",     VX (4, 727),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2270
{"efsctuiz",    VX (4, 728),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2271
{"nput",        APU(4, 364,0),   APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2272
{"efsctsiz",    VX (4, 730),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2273
{"efststgt",    VX (4, 732),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2274
{"efststlt",    VX (4, 733),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2275
{"efststeq",    VX (4, 734),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2276
{"efdadd",      VX (4, 736),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2277
{"efdsub",      VX (4, 737),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2278
{"efdcfuid",    VX (4, 738),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2279
{"efdcfsid",    VX (4, 739),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2280
{"efdabs",      VX (4, 740),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2281
{"efdnabs",     VX (4, 741),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2282
{"efdneg",      VX (4, 742),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2283
{"efdmul",      VX (4, 744),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2284
{"efddiv",      VX (4, 745),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2285
{"efdctuidz",   VX (4, 746),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2286
{"efdctsidz",   VX (4, 747),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2287
{"efdcmpgt",    VX (4, 748),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2288
{"efdcmplt",    VX (4, 749),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2289
{"efdcmpeq",    VX (4, 750),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2290
{"efdcfs",      VX (4, 751),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2291
{"efdcfui",     VX (4, 752),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2292
{"efdcfsi",     VX (4, 753),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2293
{"efdcfuf",     VX (4, 754),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2294
{"efdcfsf",     VX (4, 755),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2295
{"efdctui",     VX (4, 756),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2296
{"efdctsi",     VX (4, 757),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2297
{"efdctuf",     VX (4, 758),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2298
{"efdctsf",     VX (4, 759),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2299
{"efdctuiz",    VX (4, 760),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2300
{"ncput",       APU(4, 380,0),   APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2301
{"efdctsiz",    VX (4, 762),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2302
{"efdtstgt",    VX (4, 764),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2303
{"efdtstlt",    VX (4, 765),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2304
{"efdtsteq",    VX (4, 766),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2305
{"evlddx",      VX (4, 768),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2306
{"vaddsbs",     VX (4, 768),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2307
{"evldd",       VX (4, 769),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2308
{"evldwx",      VX (4, 770),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2309
{"vminsb",      VX (4, 770),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2310
{"evldw",       VX (4, 771),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2311
{"evldhx",      VX (4, 772),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2312
{"vsrab",       VX (4, 772),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2313
{"evldh",       VX (4, 773),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2314
{"vcmpgtsb",    VXR(4, 774,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2315
{"evlhhesplatx",VX (4, 776),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2316
{"vmulesb",     VX (4, 776),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2317
{"evlhhesplat", VX (4, 777),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2318
{"vcfux",       VX (4, 778),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2319
{"evlhhousplatx",VX(4, 780),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2320
{"vspltisb",    VX (4, 780),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2321
{"evlhhousplat",VX (4, 781),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2322
{"evlhhossplatx",VX(4, 782),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2323
{"vpkpx",       VX (4, 782),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2324
{"evlhhossplat",VX (4, 783),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2325
{"mullhwu",     XRC(4, 392,0),   X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2326
{"evlwhex",     VX (4, 784),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2327
{"mullhwu.",    XRC(4, 392,1),  X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2328
{"evlwhe",      VX (4, 785),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2329
{"evlwhoux",    VX (4, 788),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2330
{"evlwhou",     VX (4, 789),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2331
{"evlwhosx",    VX (4, 790),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2332
{"evlwhos",     VX (4, 791),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2333
{"maclhwu",     XO (4, 396,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2334
{"evlwwsplatx", VX (4, 792),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2335
{"maclhwu.",    XO (4, 396,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2336
{"evlwwsplat",  VX (4, 793),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2337
{"evlwhsplatx", VX (4, 796),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2338
{"evlwhsplat",  VX (4, 797),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2339
{"evstddx",     VX (4, 800),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2340
{"evstdd",      VX (4, 801),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2341
{"evstdwx",     VX (4, 802),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2342
{"evstdw",      VX (4, 803),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2343
{"evstdhx",     VX (4, 804),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2344
{"evstdh",      VX (4, 805),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2345
{"evstwhex",    VX (4, 816),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2346
{"evstwhe",     VX (4, 817),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2347
{"evstwhox",    VX (4, 820),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2348
{"evstwho",     VX (4, 821),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2349
{"evstwwex",    VX (4, 824),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2350
{"evstwwe",     VX (4, 825),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2351
{"evstwwox",    VX (4, 828),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2352
{"evstwwo",     VX (4, 829),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2353
{"vaddshs",     VX (4, 832),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2354
{"vminsh",      VX (4, 834),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2355
{"vsrah",       VX (4, 836),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2356
{"vcmpgtsh",    VXR(4, 838,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2357
{"vmulesh",     VX (4, 840),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2358
{"vcfsx",       VX (4, 842),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2359
{"vspltish",    VX (4, 844),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2360
{"vupkhpx",     VX (4, 846),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2361
{"mullhw",      XRC(4, 424,0),   X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2362
{"mullhw.",     XRC(4, 424,1),  X_MASK,  PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2363
{"maclhw",      XO (4, 428,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2364
{"maclhw.",     XO (4, 428,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2365
{"nmaclhw",     XO (4, 430,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2366
{"nmaclhw.",    XO (4, 430,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2367
{"vaddsws",     VX (4, 896),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2368
{"vminsw",      VX (4, 898),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2369
{"vsraw",       VX (4, 900),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2370
{"vcmpgtsw",    VXR(4, 902,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2371
{"vctuxs",      VX (4, 906),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2372
{"vspltisw",    VX (4, 908),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2373
{"maclhwsu",    XO (4, 460,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2374
{"maclhwsu.",   XO (4, 460,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2375
{"vcmpbfp",     VXR(4, 966,0),   VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2376
{"vctsxs",      VX (4, 970),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2377
{"vupklpx",     VX (4, 974),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2378
{"maclhws",     XO (4, 492,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2379
{"maclhws.",    XO (4, 492,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2380
{"nmaclhws",    XO (4, 494,0,0),XO_MASK, PPC405|PPC440,   PPCNONE,        {RT, RA, RB}},
2381
{"nmaclhws.",   XO (4, 494,0,1),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2382
{"vsububm",     VX (4,1024),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2383
{"vavgub",      VX (4,1026),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2384
{"evmhessf",    VX (4,1027),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2385
{"vand",        VX (4,1028),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2386
{"vcmpequb.",   VXR(4,   6,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2387
{"udi0fcm.",    APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,          {URT, URA, URB}},
2388
{"udi0fcm",     APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2389
{"evmhossf",    VX (4,1031),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2390
{"evmheumi",    VX (4,1032),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2391
{"evmhesmi",    VX (4,1033),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2392
{"vmaxfp",      VX (4,1034),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2393
{"evmhesmf",    VX (4,1035),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2394
{"evmhoumi",    VX (4,1036),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2395
{"vslo",        VX (4,1036),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2396
{"evmhosmi",    VX (4,1037),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2397
{"evmhosmf",    VX (4,1039),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2398
{"machhwuo",    XO (4,  12,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2399
{"machhwuo.",   XO (4,  12,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2400
{"ps_merge00",  XOPS(4,528,0),   XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2401
{"ps_merge00.", XOPS(4,528,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2402
{"evmhessfa",   VX (4,1059),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2403
{"evmhossfa",   VX (4,1063),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2404
{"evmheumia",   VX (4,1064),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2405
{"evmhesmia",   VX (4,1065),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2406
{"evmhesmfa",   VX (4,1067),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2407
{"evmhoumia",   VX (4,1068),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2408
{"evmhosmia",   VX (4,1069),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2409
{"evmhosmfa",   VX (4,1071),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2410
{"vsubuhm",     VX (4,1088),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2411
{"vavguh",      VX (4,1090),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2412
{"vandc",       VX (4,1092),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2413
{"vcmpequh.",   VXR(4,  70,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2414
{"udi1fcm.",    APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,          {URT, URA, URB}},
2415
{"udi1fcm",     APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2416
{"evmwhssf",    VX (4,1095),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2417
{"evmwlumi",    VX (4,1096),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2418
{"vminfp",      VX (4,1098),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2419
{"evmwhumi",    VX (4,1100),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2420
{"vsro",        VX (4,1100),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2421
{"evmwhsmi",    VX (4,1101),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2422
{"evmwhsmf",    VX (4,1103),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2423
{"evmwssf",     VX (4,1107),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2424
{"machhwo",     XO (4,  44,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2425
{"evmwumi",     VX (4,1112),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2426
{"machhwo.",    XO (4,  44,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2427
{"evmwsmi",     VX (4,1113),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2428
{"evmwsmf",     VX (4,1115),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2429
{"nmachhwo",    XO (4,  46,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2430
{"nmachhwo.",   XO (4,  46,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2431
{"ps_merge01",  XOPS(4,560,0),   XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2432
{"ps_merge01.", XOPS(4,560,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2433
{"evmwhssfa",   VX (4,1127),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2434
{"evmwlumia",   VX (4,1128),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2435
{"evmwhumia",   VX (4,1132),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2436
{"evmwhsmia",   VX (4,1133),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2437
{"evmwhsmfa",   VX (4,1135),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2438
{"evmwssfa",    VX (4,1139),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2439
{"evmwumia",    VX (4,1144),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2440
{"evmwsmia",    VX (4,1145),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2441
{"evmwsmfa",    VX (4,1147),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2442
{"vsubuwm",     VX (4,1152),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2443
{"vavguw",      VX (4,1154),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2444
{"vor",         VX (4,1156),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2445
{"vcmpequw.",   VXR(4, 134,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2446
{"udi2fcm.",    APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,          {URT, URA, URB}},
2447
{"udi2fcm",     APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2448
{"machhwsuo",   XO (4,  76,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2449
{"machhwsuo.",  XO (4,  76,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2450
{"ps_merge10",  XOPS(4,592,0),   XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2451
{"ps_merge10.", XOPS(4,592,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2452
{"evaddusiaaw", VX (4,1216),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2453
{"evaddssiaaw", VX (4,1217),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2454
{"evsubfusiaaw",VX (4,1218),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2455
{"evsubfssiaaw",VX (4,1219),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2456
{"evmra",       VX (4,1220),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2457
{"vxor",        VX (4,1220),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2458
{"evdivws",     VX (4,1222),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2459
{"vcmpeqfp.",   VXR(4, 198,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2460
{"udi3fcm.",    APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,          {URT, URA, URB}},
2461
{"udi3fcm",     APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2462
{"evdivwu",     VX (4,1223),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2463
{"evaddumiaaw", VX (4,1224),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2464
{"evaddsmiaaw", VX (4,1225),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2465
{"evsubfumiaaw",VX (4,1226),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2466
{"evsubfsmiaaw",VX (4,1227),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2467
{"machhwso",    XO (4, 108,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2468
{"machhwso.",   XO (4, 108,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2469
{"nmachhwso",   XO (4, 110,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2470
{"nmachhwso.",  XO (4, 110,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2471
{"ps_merge11",  XOPS(4,624,0),   XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2472
{"ps_merge11.", XOPS(4,624,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2473
{"evmheusiaaw", VX (4,1280),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2474
{"evmhessiaaw", VX (4,1281),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2475
{"vavgsb",      VX (4,1282),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2476
{"evmhessfaaw", VX (4,1283),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2477
{"evmhousiaaw", VX (4,1284),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2478
{"vnor",        VX (4,1284),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2479
{"evmhossiaaw", VX (4,1285),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2480
{"udi4fcm.",    APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,          {URT, URA, URB}},
2481
{"udi4fcm",     APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2482
{"evmhossfaaw", VX (4,1287),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2483
{"evmheumiaaw", VX (4,1288),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2484
{"evmhesmiaaw", VX (4,1289),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2485
{"evmhesmfaaw", VX (4,1291),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2486
{"evmhoumiaaw", VX (4,1292),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2487
{"evmhosmiaaw", VX (4,1293),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2488
{"evmhosmfaaw", VX (4,1295),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2489
{"macchwuo",    XO (4, 140,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2490
{"macchwuo.",   XO (4, 140,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2491
{"evmhegumiaa", VX (4,1320),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2492
{"evmhegsmiaa", VX (4,1321),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2493
{"evmhegsmfaa", VX (4,1323),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2494
{"evmhogumiaa", VX (4,1324),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2495
{"evmhogsmiaa", VX (4,1325),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2496
{"evmhogsmfaa", VX (4,1327),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2497
{"evmwlusiaaw", VX (4,1344),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2498
{"evmwlssiaaw", VX (4,1345),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2499
{"vavgsh",      VX (4,1346),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2500
{"udi5fcm.",    APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,          {URT, URA, URB}},
2501
{"udi5fcm",     APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2502
{"evmwlumiaaw", VX (4,1352),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2503
{"evmwlsmiaaw", VX (4,1353),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2504
{"evmwssfaa",   VX (4,1363),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2505
{"macchwo",     XO (4, 172,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2506
{"evmwumiaa",   VX (4,1368),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2507
{"macchwo.",    XO (4, 172,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2508
{"evmwsmiaa",   VX (4,1369),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2509
{"evmwsmfaa",   VX (4,1371),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2510
{"nmacchwo",    XO (4, 174,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2511
{"nmacchwo.",   XO (4, 174,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2512
{"evmheusianw", VX (4,1408),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2513
{"vsubcuw",     VX (4,1408),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2514
{"evmhessianw", VX (4,1409),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2515
{"vavgsw",      VX (4,1410),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2516
{"evmhessfanw", VX (4,1411),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2517
{"evmhousianw", VX (4,1412),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2518
{"evmhossianw", VX (4,1413),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2519
{"udi6fcm.",    APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,          {URT, URA, URB}},
2520
{"udi6fcm",     APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2521
{"evmhossfanw", VX (4,1415),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2522
{"evmheumianw", VX (4,1416),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2523
{"evmhesmianw", VX (4,1417),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2524
{"evmhesmfanw", VX (4,1419),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2525
{"evmhoumianw", VX (4,1420),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2526
{"evmhosmianw", VX (4,1421),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2527
{"evmhosmfanw", VX (4,1423),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2528
{"macchwsuo",   XO (4, 204,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2529
{"macchwsuo.",  XO (4, 204,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2530
{"evmhegumian", VX (4,1448),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2531
{"evmhegsmian", VX (4,1449),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2532
{"evmhegsmfan", VX (4,1451),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2533
{"evmhogumian", VX (4,1452),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2534
{"evmhogsmian", VX (4,1453),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2535
{"evmhogsmfan", VX (4,1455),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2536
{"evmwlusianw", VX (4,1472),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2537
{"evmwlssianw", VX (4,1473),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2538
{"vcmpgefp.",   VXR(4, 454,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2539
{"udi7fcm.",    APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,          {URT, URA, URB}},
2540
{"udi7fcm",     APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2541
{"evmwlumianw", VX (4,1480),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2542
{"evmwlsmianw", VX (4,1481),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2543
{"evmwssfan",   VX (4,1491),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2544
{"macchwso",    XO (4, 236,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2545
{"evmwumian",   VX (4,1496),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2546
{"macchwso.",   XO (4, 236,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2547
{"evmwsmian",   VX (4,1497),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2548
{"evmwsmfan",   VX (4,1499),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2549
{"nmacchwso",   XO (4, 238,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2550
{"nmacchwso.",  XO (4, 238,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2551
{"vsububs",     VX (4,1536),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2552
{"mfvscr",      VX (4,1540),    VX_MASK,     PPCVEC,    PPCNONE,        {VD}},
2553
{"vcmpgtub.",   VXR(4, 518,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2554
{"udi8fcm.",    APU(4, 771,0),   APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2555
{"udi8fcm",     APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2556
{"vsum4ubs",    VX (4,1544),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2557
{"vsubuhs",     VX (4,1600),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2558
{"mtvscr",      VX (4,1604),    VX_MASK,     PPCVEC,    PPCNONE,        {VB}},
2559
{"vcmpgtuh.",   VXR(4, 582,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2560
{"vsum4shs",    VX (4,1608),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2561
{"udi9fcm.",    APU(4, 804,0),   APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2562
{"udi9fcm",     APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2563
{"vsubuws",     VX (4,1664),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2564
{"vcmpgtuw.",   VXR(4, 646,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2565
{"udi10fcm.",   APU(4, 835,0),   APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2566
{"udi10fcm",    APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2567
{"vsum2sws",    VX (4,1672),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2568
{"vcmpgtfp.",   VXR(4, 710,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2569
{"udi11fcm.",   APU(4, 867,0),   APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2570
{"udi11fcm",    APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2571
{"vsubsbs",     VX (4,1792),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2572
{"vcmpgtsb.",   VXR(4, 774,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2573
{"udi12fcm.",   APU(4, 899,0),   APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2574
{"udi12fcm",    APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2575
{"vsum4sbs",    VX (4,1800),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2576
{"maclhwuo",    XO (4, 396,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2577
{"maclhwuo.",   XO (4, 396,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2578
{"vsubshs",     VX (4,1856),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2579
{"vcmpgtsh.",   VXR(4, 838,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2580
{"udi13fcm.",   APU(4, 931,0),   APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2581
{"udi13fcm",    APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2582
{"maclhwo",     XO (4, 428,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2583
{"maclhwo.",    XO (4, 428,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2584
{"nmaclhwo",    XO (4, 430,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2585
{"nmaclhwo.",   XO (4, 430,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2586
{"vsubsws",     VX (4,1920),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2587
{"vcmpgtsw.",   VXR(4, 902,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2588
{"udi14fcm.",   APU(4, 963,0),   APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2589
{"udi14fcm",    APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2590
{"vsumsws",     VX (4,1928),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2591
{"maclhwsuo",   XO (4, 460,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2592
{"maclhwsuo.",  XO (4, 460,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2593
{"vcmpbfp.",    VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2594
{"udi15fcm.",   APU(4, 995,0),   APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2595
{"udi15fcm",    APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2596
{"maclhwso",    XO (4, 492,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2597
{"maclhwso.",   XO (4, 492,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2598
{"nmaclhwso",   XO (4, 494,1,0),XO_MASK, PPC405|PPC440,  PPCNONE,        {RT, RA, RB}},
2599
{"nmaclhwso.",  XO (4, 494,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
2600
{"dcbz_l",      X  (4,1014),    XRT_MASK,    PPCPS,     PPCNONE,        {RA, RB}},
2601
 
2602
{"mulli",       OP(7),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2603
{"muli",        OP(7),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2604
 
2605
{"subfic",      OP(8),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2606
{"sfi",         OP(8),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2607
 
2608
{"dozi",        OP(9),          OP_MASK,     M601,      PPCNONE,        {RT, RA, SI}},
2609
 
2610
{"cmplwi",      OPL(10,0),       OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, UI}},
2611
{"cmpldi",      OPL(10,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, UI}},
2612
{"cmpli",       OP(10),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, UI}},
2613
{"cmpli",       OP(10),         OP_MASK,     PWRCOM,    PPCNONE,        {BF, RA, UI}},
2614
 
2615
{"cmpwi",       OPL(11,0),       OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, SI}},
2616
{"cmpdi",       OPL(11,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, SI}},
2617
{"cmpi",        OP(11),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, SI}},
2618
{"cmpi",        OP(11),         OP_MASK,     PWRCOM,    PPCNONE,        {BF, RA, SI}},
2619
 
2620
{"addic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2621
{"ai",          OP(12),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2622
{"subic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
2623
 
2624
{"addic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2625
{"ai.",         OP(13),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2626
{"subic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
2627
 
2628
{"li",          OP(14),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SI}},
2629
{"lil",         OP(14),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SI}},
2630
{"addi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SI}},
2631
{"cal",         OP(14),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
2632
{"subi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
2633
{"la",          OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
2634
 
2635
{"lis",         OP(15),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SISIGNOPT}},
2636
{"liu",         OP(15),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SISIGNOPT}},
2637
{"addis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
2638
{"cau",         OP(15),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
2639
{"subis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
2640
 
2641
{"bdnz-",    BBO(16,BODNZ,0,0),           BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2642
{"bdnz+",    BBO(16,BODNZ,0,0),           BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2643
{"bdnz",     BBO(16,BODNZ,0,0),           BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
2644
{"bdn",      BBO(16,BODNZ,0,0),           BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
2645
{"bdnzl-",   BBO(16,BODNZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2646
{"bdnzl+",   BBO(16,BODNZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2647
{"bdnzl",    BBO(16,BODNZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
2648
{"bdnl",     BBO(16,BODNZ,0,1),          BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
2649
{"bdnza-",   BBO(16,BODNZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2650
{"bdnza+",   BBO(16,BODNZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2651
{"bdnza",    BBO(16,BODNZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
2652
{"bdna",     BBO(16,BODNZ,1,0),          BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
2653
{"bdnzla-",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2654
{"bdnzla+",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2655
{"bdnzla",   BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
2656
{"bdnla",    BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
2657
{"bdz-",     BBO(16,BODZ,0,0),            BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2658
{"bdz+",     BBO(16,BODZ,0,0),            BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2659
{"bdz",      BBO(16,BODZ,0,0),            BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
2660
{"bdzl-",    BBO(16,BODZ,0,1),           BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2661
{"bdzl+",    BBO(16,BODZ,0,1),           BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2662
{"bdzl",     BBO(16,BODZ,0,1),           BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
2663
{"bdza-",    BBO(16,BODZ,1,0),           BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2664
{"bdza+",    BBO(16,BODZ,1,0),           BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2665
{"bdza",     BBO(16,BODZ,1,0),           BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
2666
{"bdzla-",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2667
{"bdzla+",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2668
{"bdzla",    BBO(16,BODZ,1,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
2669
 
2670
{"bge-",     BBOCB(16,BOF,CBLT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2671
{"bge+",     BBOCB(16,BOF,CBLT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2672
{"bge",      BBOCB(16,BOF,CBLT,0,0),      BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2673
{"bnl-",     BBOCB(16,BOF,CBLT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2674
{"bnl+",     BBOCB(16,BOF,CBLT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2675
{"bnl",      BBOCB(16,BOF,CBLT,0,0),      BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2676
{"bgel-",    BBOCB(16,BOF,CBLT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2677
{"bgel+",    BBOCB(16,BOF,CBLT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2678
{"bgel",     BBOCB(16,BOF,CBLT,0,1),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2679
{"bnll-",    BBOCB(16,BOF,CBLT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2680
{"bnll+",    BBOCB(16,BOF,CBLT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2681
{"bnll",     BBOCB(16,BOF,CBLT,0,1),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2682
{"bgea-",    BBOCB(16,BOF,CBLT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2683
{"bgea+",    BBOCB(16,BOF,CBLT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2684
{"bgea",     BBOCB(16,BOF,CBLT,1,0),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2685
{"bnla-",    BBOCB(16,BOF,CBLT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2686
{"bnla+",    BBOCB(16,BOF,CBLT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2687
{"bnla",     BBOCB(16,BOF,CBLT,1,0),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2688
{"bgela-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2689
{"bgela+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2690
{"bgela",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2691
{"bnlla-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2692
{"bnlla+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2693
{"bnlla",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2694
{"ble-",     BBOCB(16,BOF,CBGT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2695
{"ble+",     BBOCB(16,BOF,CBGT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2696
{"ble",      BBOCB(16,BOF,CBGT,0,0),      BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2697
{"bng-",     BBOCB(16,BOF,CBGT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2698
{"bng+",     BBOCB(16,BOF,CBGT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2699
{"bng",      BBOCB(16,BOF,CBGT,0,0),      BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2700
{"blel-",    BBOCB(16,BOF,CBGT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2701
{"blel+",    BBOCB(16,BOF,CBGT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2702
{"blel",     BBOCB(16,BOF,CBGT,0,1),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2703
{"bngl-",    BBOCB(16,BOF,CBGT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2704
{"bngl+",    BBOCB(16,BOF,CBGT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2705
{"bngl",     BBOCB(16,BOF,CBGT,0,1),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2706
{"blea-",    BBOCB(16,BOF,CBGT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2707
{"blea+",    BBOCB(16,BOF,CBGT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2708
{"blea",     BBOCB(16,BOF,CBGT,1,0),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2709
{"bnga-",    BBOCB(16,BOF,CBGT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2710
{"bnga+",    BBOCB(16,BOF,CBGT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2711
{"bnga",     BBOCB(16,BOF,CBGT,1,0),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2712
{"blela-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2713
{"blela+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2714
{"blela",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2715
{"bngla-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2716
{"bngla+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2717
{"bngla",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2718
{"bne-",     BBOCB(16,BOF,CBEQ,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2719
{"bne+",     BBOCB(16,BOF,CBEQ,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2720
{"bne",      BBOCB(16,BOF,CBEQ,0,0),      BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2721
{"bnel-",    BBOCB(16,BOF,CBEQ,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2722
{"bnel+",    BBOCB(16,BOF,CBEQ,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2723
{"bnel",     BBOCB(16,BOF,CBEQ,0,1),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2724
{"bnea-",    BBOCB(16,BOF,CBEQ,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2725
{"bnea+",    BBOCB(16,BOF,CBEQ,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2726
{"bnea",     BBOCB(16,BOF,CBEQ,1,0),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2727
{"bnela-",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2728
{"bnela+",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2729
{"bnela",    BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2730
{"bns-",     BBOCB(16,BOF,CBSO,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2731
{"bns+",     BBOCB(16,BOF,CBSO,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2732
{"bns",      BBOCB(16,BOF,CBSO,0,0),      BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2733
{"bnu-",     BBOCB(16,BOF,CBSO,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2734
{"bnu+",     BBOCB(16,BOF,CBSO,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2735
{"bnu",      BBOCB(16,BOF,CBSO,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2736
{"bnsl-",    BBOCB(16,BOF,CBSO,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2737
{"bnsl+",    BBOCB(16,BOF,CBSO,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2738
{"bnsl",     BBOCB(16,BOF,CBSO,0,1),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2739
{"bnul-",    BBOCB(16,BOF,CBSO,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2740
{"bnul+",    BBOCB(16,BOF,CBSO,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2741
{"bnul",     BBOCB(16,BOF,CBSO,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2742
{"bnsa-",    BBOCB(16,BOF,CBSO,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2743
{"bnsa+",    BBOCB(16,BOF,CBSO,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2744
{"bnsa",     BBOCB(16,BOF,CBSO,1,0),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2745
{"bnua-",    BBOCB(16,BOF,CBSO,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2746
{"bnua+",    BBOCB(16,BOF,CBSO,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2747
{"bnua",     BBOCB(16,BOF,CBSO,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2748
{"bnsla-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2749
{"bnsla+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2750
{"bnsla",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2751
{"bnula-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2752
{"bnula+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2753
{"bnula",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2754
 
2755
{"blt-",     BBOCB(16,BOT,CBLT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2756
{"blt+",     BBOCB(16,BOT,CBLT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2757
{"blt",      BBOCB(16,BOT,CBLT,0,0),      BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2758
{"bltl-",    BBOCB(16,BOT,CBLT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2759
{"bltl+",    BBOCB(16,BOT,CBLT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2760
{"bltl",     BBOCB(16,BOT,CBLT,0,1),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2761
{"blta-",    BBOCB(16,BOT,CBLT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2762
{"blta+",    BBOCB(16,BOT,CBLT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2763
{"blta",     BBOCB(16,BOT,CBLT,1,0),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2764
{"bltla-",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2765
{"bltla+",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2766
{"bltla",    BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2767
{"bgt-",     BBOCB(16,BOT,CBGT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2768
{"bgt+",     BBOCB(16,BOT,CBGT,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2769
{"bgt",      BBOCB(16,BOT,CBGT,0,0),      BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2770
{"bgtl-",    BBOCB(16,BOT,CBGT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2771
{"bgtl+",    BBOCB(16,BOT,CBGT,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2772
{"bgtl",     BBOCB(16,BOT,CBGT,0,1),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2773
{"bgta-",    BBOCB(16,BOT,CBGT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2774
{"bgta+",    BBOCB(16,BOT,CBGT,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2775
{"bgta",     BBOCB(16,BOT,CBGT,1,0),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2776
{"bgtla-",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2777
{"bgtla+",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2778
{"bgtla",    BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2779
{"beq-",     BBOCB(16,BOT,CBEQ,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2780
{"beq+",     BBOCB(16,BOT,CBEQ,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2781
{"beq",      BBOCB(16,BOT,CBEQ,0,0),      BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2782
{"beql-",    BBOCB(16,BOT,CBEQ,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2783
{"beql+",    BBOCB(16,BOT,CBEQ,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2784
{"beql",     BBOCB(16,BOT,CBEQ,0,1),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2785
{"beqa-",    BBOCB(16,BOT,CBEQ,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2786
{"beqa+",    BBOCB(16,BOT,CBEQ,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2787
{"beqa",     BBOCB(16,BOT,CBEQ,1,0),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2788
{"beqla-",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2789
{"beqla+",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2790
{"beqla",    BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2791
{"bso-",     BBOCB(16,BOT,CBSO,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2792
{"bso+",     BBOCB(16,BOT,CBSO,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2793
{"bso",      BBOCB(16,BOT,CBSO,0,0),      BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2794
{"bun-",     BBOCB(16,BOT,CBSO,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2795
{"bun+",     BBOCB(16,BOT,CBSO,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2796
{"bun",      BBOCB(16,BOT,CBSO,0,0),      BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2797
{"bsol-",    BBOCB(16,BOT,CBSO,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2798
{"bsol+",    BBOCB(16,BOT,CBSO,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2799
{"bsol",     BBOCB(16,BOT,CBSO,0,1),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2800
{"bunl-",    BBOCB(16,BOT,CBSO,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2801
{"bunl+",    BBOCB(16,BOT,CBSO,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2802
{"bunl",     BBOCB(16,BOT,CBSO,0,1),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2803
{"bsoa-",    BBOCB(16,BOT,CBSO,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2804
{"bsoa+",    BBOCB(16,BOT,CBSO,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2805
{"bsoa",     BBOCB(16,BOT,CBSO,1,0),     BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2806
{"buna-",    BBOCB(16,BOT,CBSO,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2807
{"buna+",    BBOCB(16,BOT,CBSO,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2808
{"buna",     BBOCB(16,BOT,CBSO,1,0),     BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2809
{"bsola-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2810
{"bsola+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2811
{"bsola",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2812
{"bunla-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2813
{"bunla+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2814
{"bunla",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2815
 
2816
{"bdnzf-",   BBO(16,BODNZF,0,0),  BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2817
{"bdnzf+",   BBO(16,BODNZF,0,0),  BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2818
{"bdnzf",    BBO(16,BODNZF,0,0),  BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2819
{"bdnzfl-",  BBO(16,BODNZF,0,1), BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2820
{"bdnzfl+",  BBO(16,BODNZF,0,1), BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2821
{"bdnzfl",   BBO(16,BODNZF,0,1), BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2822
{"bdnzfa-",  BBO(16,BODNZF,1,0), BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2823
{"bdnzfa+",  BBO(16,BODNZF,1,0), BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2824
{"bdnzfa",   BBO(16,BODNZF,1,0), BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2825
{"bdnzfla-", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2826
{"bdnzfla+", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2827
{"bdnzfla",  BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2828
{"bdzf-",    BBO(16,BODZF,0,0),           BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2829
{"bdzf+",    BBO(16,BODZF,0,0),           BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2830
{"bdzf",     BBO(16,BODZF,0,0),           BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2831
{"bdzfl-",   BBO(16,BODZF,0,1),          BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2832
{"bdzfl+",   BBO(16,BODZF,0,1),          BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2833
{"bdzfl",    BBO(16,BODZF,0,1),          BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2834
{"bdzfa-",   BBO(16,BODZF,1,0),          BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2835
{"bdzfa+",   BBO(16,BODZF,1,0),          BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2836
{"bdzfa",    BBO(16,BODZF,1,0),          BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2837
{"bdzfla-",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2838
{"bdzfla+",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2839
{"bdzfla",   BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2840
 
2841
{"bf-",      BBO(16,BOF,0,0),             BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2842
{"bf+",      BBO(16,BOF,0,0),             BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2843
{"bf",       BBO(16,BOF,0,0),             BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2844
{"bbf",      BBO(16,BOF,0,0),             BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2845
{"bfl-",     BBO(16,BOF,0,1),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2846
{"bfl+",     BBO(16,BOF,0,1),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2847
{"bfl",      BBO(16,BOF,0,1),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2848
{"bbfl",     BBO(16,BOF,0,1),            BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2849
{"bfa-",     BBO(16,BOF,1,0),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2850
{"bfa+",     BBO(16,BOF,1,0),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2851
{"bfa",      BBO(16,BOF,1,0),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2852
{"bbfa",     BBO(16,BOF,1,0),            BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2853
{"bfla-",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2854
{"bfla+",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2855
{"bfla",     BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2856
{"bbfla",    BBO(16,BOF,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2857
 
2858
{"bdnzt-",   BBO(16,BODNZT,0,0),  BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2859
{"bdnzt+",   BBO(16,BODNZT,0,0),  BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2860
{"bdnzt",    BBO(16,BODNZT,0,0),  BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2861
{"bdnztl-",  BBO(16,BODNZT,0,1), BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2862
{"bdnztl+",  BBO(16,BODNZT,0,1), BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2863
{"bdnztl",   BBO(16,BODNZT,0,1), BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2864
{"bdnzta-",  BBO(16,BODNZT,1,0), BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2865
{"bdnzta+",  BBO(16,BODNZT,1,0), BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2866
{"bdnzta",   BBO(16,BODNZT,1,0), BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2867
{"bdnztla-", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2868
{"bdnztla+", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2869
{"bdnztla",  BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2870
{"bdzt-",    BBO(16,BODZT,0,0),           BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2871
{"bdzt+",    BBO(16,BODZT,0,0),           BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2872
{"bdzt",     BBO(16,BODZT,0,0),           BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2873
{"bdztl-",   BBO(16,BODZT,0,1),          BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2874
{"bdztl+",   BBO(16,BODZT,0,1),          BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2875
{"bdztl",    BBO(16,BODZT,0,1),          BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2876
{"bdzta-",   BBO(16,BODZT,1,0),          BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2877
{"bdzta+",   BBO(16,BODZT,1,0),          BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2878
{"bdzta",    BBO(16,BODZT,1,0),          BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2879
{"bdztla-",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2880
{"bdztla+",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2881
{"bdztla",   BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2882
 
2883
{"bt-",      BBO(16,BOT,0,0),             BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2884
{"bt+",      BBO(16,BOT,0,0),             BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2885
{"bt",       BBO(16,BOT,0,0),             BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2886
{"bbt",      BBO(16,BOT,0,0),             BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2887
{"btl-",     BBO(16,BOT,0,1),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2888
{"btl+",     BBO(16,BOT,0,1),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2889
{"btl",      BBO(16,BOT,0,1),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2890
{"bbtl",     BBO(16,BOT,0,1),            BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2891
{"bta-",     BBO(16,BOT,1,0),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2892
{"bta+",     BBO(16,BOT,1,0),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2893
{"bta",      BBO(16,BOT,1,0),            BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2894
{"bbta",     BBO(16,BOT,1,0),            BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2895
{"btla-",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2896
{"btla+",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2897
{"btla",     BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2898
{"bbtla",    BBO(16,BOT,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2899
 
2900
{"bc-",         B(16,0,0),        B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
2901
{"bc+",         B(16,0,0),        B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
2902
{"bc",          B(16,0,0),        B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
2903
{"bcl-",        B(16,0,1),       B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
2904
{"bcl+",        B(16,0,1),       B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
2905
{"bcl",         B(16,0,1),       B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
2906
{"bca-",        B(16,1,0),       B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
2907
{"bca+",        B(16,1,0),       B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
2908
{"bca",         B(16,1,0),       B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
2909
{"bcla-",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
2910
{"bcla+",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
2911
{"bcla",        B(16,1,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
2912
 
2913
{"svc",         SC(17,0,0),       SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
2914
{"svcl",        SC(17,0,1),      SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
2915
{"sc",          SC(17,1,0),      SC_MASK,     PPC,       PPCNONE,        {LEV}},
2916
{"svca",        SC(17,1,0),      SC_MASK,     PWRCOM,    PPCNONE,        {SV}},
2917
{"svcla",       SC(17,1,1),     SC_MASK,     POWER,     PPCNONE,        {SV}},
2918
 
2919
{"b",           B(18,0,0),        B_MASK,      COM,       PPCNONE,        {LI}},
2920
{"bl",          B(18,0,1),       B_MASK,      COM,       PPCNONE,        {LI}},
2921
{"ba",          B(18,1,0),       B_MASK,      COM,       PPCNONE,        {LIA}},
2922
{"bla",         B(18,1,1),      B_MASK,      COM,       PPCNONE,        {LIA}},
2923
 
2924
{"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM,  PPCNONE,        {BF, BFA}},
2925
 
2926
{"bdnzlr",   XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2927
{"bdnzlr-",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2928
{"bdnzlrl",  XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2929
{"bdnzlrl-", XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2930
{"bdnzlr+",  XLO(19,BODNZP,16,0),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2931
{"bdnzlrl+", XLO(19,BODNZP,16,1),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2932
{"bdzlr",    XLO(19,BODZ,16,0),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2933
{"bdzlr-",   XLO(19,BODZ,16,0),          XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2934
{"bdzlrl",   XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2935
{"bdzlrl-",  XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2936
{"bdzlr+",   XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2937
{"bdzlrl+",  XLO(19,BODZP,16,1),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2938
{"blr",      XLO(19,BOU,16,0),           XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2939
{"br",       XLO(19,BOU,16,0),           XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
2940
{"blrl",     XLO(19,BOU,16,1),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2941
{"brl",      XLO(19,BOU,16,1),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
2942
{"bdnzlr-",  XLO(19,BODNZM4,16,0),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2943
{"bdnzlrl-", XLO(19,BODNZM4,16,1),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2944
{"bdnzlr+",  XLO(19,BODNZP4,16,0),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2945
{"bdnzlrl+", XLO(19,BODNZP4,16,1),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2946
{"bdzlr-",   XLO(19,BODZM4,16,0),        XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2947
{"bdzlrl-",  XLO(19,BODZM4,16,1),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2948
{"bdzlr+",   XLO(19,BODZP4,16,0),        XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2949
{"bdzlrl+",  XLO(19,BODZP4,16,1),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2950
 
2951
{"bgelr",    XLOCB(19,BOF,CBLT,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2952
{"bgelr-",   XLOCB(19,BOF,CBLT,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2953
{"bger",     XLOCB(19,BOF,CBLT,16,0),    XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2954
{"bnllr",    XLOCB(19,BOF,CBLT,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2955
{"bnllr-",   XLOCB(19,BOF,CBLT,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2956
{"bnlr",     XLOCB(19,BOF,CBLT,16,0),    XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2957
{"bgelrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2958
{"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2959
{"bgerl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2960
{"bnllrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2961
{"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2962
{"bnlrl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2963
{"blelr",    XLOCB(19,BOF,CBGT,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2964
{"blelr-",   XLOCB(19,BOF,CBGT,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2965
{"bler",     XLOCB(19,BOF,CBGT,16,0),    XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2966
{"bnglr",    XLOCB(19,BOF,CBGT,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2967
{"bnglr-",   XLOCB(19,BOF,CBGT,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2968
{"bngr",     XLOCB(19,BOF,CBGT,16,0),    XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2969
{"blelrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2970
{"blelrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2971
{"blerl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2972
{"bnglrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2973
{"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2974
{"bngrl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2975
{"bnelr",    XLOCB(19,BOF,CBEQ,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2976
{"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2977
{"bner",     XLOCB(19,BOF,CBEQ,16,0),    XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2978
{"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2979
{"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2980
{"bnerl",    XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2981
{"bnslr",    XLOCB(19,BOF,CBSO,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2982
{"bnslr-",   XLOCB(19,BOF,CBSO,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2983
{"bnsr",     XLOCB(19,BOF,CBSO,16,0),    XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2984
{"bnulr",    XLOCB(19,BOF,CBSO,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2985
{"bnulr-",   XLOCB(19,BOF,CBSO,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2986
{"bnslrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2987
{"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2988
{"bnsrl",    XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2989
{"bnulrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2990
{"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2991
{"bgelr+",   XLOCB(19,BOFP,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2992
{"bnllr+",   XLOCB(19,BOFP,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2993
{"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2994
{"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2995
{"blelr+",   XLOCB(19,BOFP,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2996
{"bnglr+",   XLOCB(19,BOFP,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2997
{"blelrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2998
{"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2999
{"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3000
{"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3001
{"bnslr+",   XLOCB(19,BOFP,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3002
{"bnulr+",   XLOCB(19,BOFP,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3003
{"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3004
{"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3005
{"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3006
{"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3007
{"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3008
{"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3009
{"blelr-",   XLOCB(19,BOFM4,CBGT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3010
{"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3011
{"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3012
{"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3013
{"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3014
{"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3015
{"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3016
{"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3017
{"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3018
{"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3019
{"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3020
{"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3021
{"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3022
{"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3023
{"blelr+",   XLOCB(19,BOFP4,CBGT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3024
{"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3025
{"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3026
{"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3027
{"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3028
{"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3029
{"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3030
{"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3031
{"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3032
{"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3033
{"bltlr",    XLOCB(19,BOT,CBLT,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3034
{"bltlr-",   XLOCB(19,BOT,CBLT,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3035
{"bltr",     XLOCB(19,BOT,CBLT,16,0),    XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3036
{"bltlrl",   XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3037
{"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3038
{"bltrl",    XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3039
{"bgtlr",    XLOCB(19,BOT,CBGT,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3040
{"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3041
{"bgtr",     XLOCB(19,BOT,CBGT,16,0),    XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3042
{"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3043
{"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3044
{"bgtrl",    XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3045
{"beqlr",    XLOCB(19,BOT,CBEQ,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3046
{"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3047
{"beqr",     XLOCB(19,BOT,CBEQ,16,0),    XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3048
{"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3049
{"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3050
{"beqrl",    XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3051
{"bsolr",    XLOCB(19,BOT,CBSO,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3052
{"bsolr-",   XLOCB(19,BOT,CBSO,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3053
{"bsor",     XLOCB(19,BOT,CBSO,16,0),    XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3054
{"bunlr",    XLOCB(19,BOT,CBSO,16,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3055
{"bunlr-",   XLOCB(19,BOT,CBSO,16,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3056
{"bsolrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3057
{"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3058
{"bsorl",    XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3059
{"bunlrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3060
{"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3061
{"bltlr+",   XLOCB(19,BOTP,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3062
{"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3063
{"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3064
{"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3065
{"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3066
{"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3067
{"bsolr+",   XLOCB(19,BOTP,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3068
{"bunlr+",   XLOCB(19,BOTP,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3069
{"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3070
{"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3071
{"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3072
{"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3073
{"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3074
{"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3075
{"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3076
{"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3077
{"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3078
{"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3079
{"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3080
{"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3081
{"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3082
{"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3083
{"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3084
{"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3085
{"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3086
{"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3087
{"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3088
{"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3089
{"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3090
{"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3091
 
3092
{"bdnzflr",  XLO(19,BODNZF,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3093
{"bdnzflr-", XLO(19,BODNZF,16,0),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3094
{"bdnzflrl", XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3095
{"bdnzflrl-",XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3096
{"bdnzflr+", XLO(19,BODNZFP,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3097
{"bdnzflrl+",XLO(19,BODNZFP,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3098
{"bdzflr",   XLO(19,BODZF,16,0), XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3099
{"bdzflr-",  XLO(19,BODZF,16,0), XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3100
{"bdzflrl",  XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3101
{"bdzflrl-", XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3102
{"bdzflr+",  XLO(19,BODZFP,16,0),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3103
{"bdzflrl+", XLO(19,BODZFP,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3104
{"bflr",     XLO(19,BOF,16,0),           XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3105
{"bflr-",    XLO(19,BOF,16,0),           XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3106
{"bbfr",     XLO(19,BOF,16,0),           XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3107
{"bflrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3108
{"bflrl-",   XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3109
{"bbfrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3110
{"bflr+",    XLO(19,BOFP,16,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3111
{"bflrl+",   XLO(19,BOFP,16,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3112
{"bflr-",    XLO(19,BOFM4,16,0), XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3113
{"bflrl-",   XLO(19,BOFM4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3114
{"bflr+",    XLO(19,BOFP4,16,0), XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3115
{"bflrl+",   XLO(19,BOFP4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3116
{"bdnztlr",  XLO(19,BODNZT,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3117
{"bdnztlr-", XLO(19,BODNZT,16,0),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3118
{"bdnztlrl", XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3119
{"bdnztlrl-",XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3120
{"bdnztlr+", XLO(19,BODNZTP,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3121
{"bdnztlrl+",XLO(19,BODNZTP,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3122
{"bdztlr",   XLO(19,BODZT,16,0), XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3123
{"bdztlr-",  XLO(19,BODZT,16,0), XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3124
{"bdztlrl",  XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3125
{"bdztlrl-", XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3126
{"bdztlr+",  XLO(19,BODZTP,16,0),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3127
{"bdztlrl+", XLO(19,BODZTP,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3128
{"btlr",     XLO(19,BOT,16,0),           XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3129
{"btlr-",    XLO(19,BOT,16,0),           XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3130
{"bbtr",     XLO(19,BOT,16,0),           XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3131
{"btlrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3132
{"btlrl-",   XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3133
{"bbtrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3134
{"btlr+",    XLO(19,BOTP,16,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3135
{"btlrl+",   XLO(19,BOTP,16,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3136
{"btlr-",    XLO(19,BOTM4,16,0), XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3137
{"btlrl-",   XLO(19,BOTM4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3138
{"btlr+",    XLO(19,BOTP4,16,0), XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3139
{"btlrl+",   XLO(19,BOTP4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3140
 
3141
{"bclr-",    XLYLK(19,16,0,0),            XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3142
{"bclrl-",   XLYLK(19,16,0,1),           XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3143
{"bclr+",    XLYLK(19,16,1,0),           XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3144
{"bclrl+",   XLYLK(19,16,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3145
{"bclr",     XLLK(19,16,0),              XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3146
{"bcr",      XLLK(19,16,0),              XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3147
{"bclrl",    XLLK(19,16,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3148
{"bcrl",     XLLK(19,16,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3149
 
3150
{"rfid",        XL(19,18),      0xffffffff,  PPC64,     PPCNONE,        {0}},
3151
 
3152
{"crnot",       XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3153
{"crnor",       XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3154
{"rfmci",       X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
3155
 
3156
{"rfdi",        XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
3157
{"rfi",         XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
3158
{"rfci",        XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
3159
 
3160
{"rfsvc",       XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
3161
 
3162
{"rfgi",        XL(19,102),   0xffffffff, E500MC|PPCA2, PPCNONE,        {0}},
3163
 
3164
{"crandc",      XL(19,129),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3165
 
3166
{"isync",       XL(19,150),     0xffffffff,  PPCCOM,    PPCNONE,        {0}},
3167
{"ics",         XL(19,150),     0xffffffff,  PWRCOM,    PPCNONE,        {0}},
3168
 
3169
{"crclr",       XL(19,193),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3170
{"crxor",       XL(19,193),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3171
 
3172
{"dnh",         X(19,198),      X_MASK,      E500MC,    PPCNONE,        {DUI, DUIS}},
3173
 
3174
{"crnand",      XL(19,225),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3175
 
3176
{"crand",       XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3177
 
3178
{"hrfid",       XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
3179
 
3180
{"crset",       XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3181
{"creqv",       XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3182
 
3183
{"doze",        XL(19,402),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3184
 
3185
{"crorc",       XL(19,417),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3186
 
3187
{"nap",         XL(19,434),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3188
 
3189
{"crmove",      XL(19,449),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3190
{"cror",        XL(19,449),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3191
 
3192
{"sleep",       XL(19,466),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3193
{"rvwinkle",    XL(19,498),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3194
 
3195
{"bctr",    XLO(19,BOU,528,0),           XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3196
{"bctrl",   XLO(19,BOU,528,1),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3197
 
3198
{"bgectr",  XLOCB(19,BOF,CBLT,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3199
{"bgectr-", XLOCB(19,BOF,CBLT,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3200
{"bnlctr",  XLOCB(19,BOF,CBLT,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3201
{"bnlctr-", XLOCB(19,BOF,CBLT,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3202
{"bgectrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3203
{"bgectrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3204
{"bnlctrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3205
{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3206
{"blectr",  XLOCB(19,BOF,CBGT,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3207
{"blectr-", XLOCB(19,BOF,CBGT,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3208
{"bngctr",  XLOCB(19,BOF,CBGT,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3209
{"bngctr-", XLOCB(19,BOF,CBGT,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3210
{"blectrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3211
{"blectrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3212
{"bngctrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3213
{"bngctrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3214
{"bnectr",  XLOCB(19,BOF,CBEQ,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3215
{"bnectr-", XLOCB(19,BOF,CBEQ,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3216
{"bnectrl", XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3217
{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3218
{"bnsctr",  XLOCB(19,BOF,CBSO,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3219
{"bnsctr-", XLOCB(19,BOF,CBSO,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3220
{"bnuctr",  XLOCB(19,BOF,CBSO,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3221
{"bnuctr-", XLOCB(19,BOF,CBSO,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3222
{"bnsctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3223
{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3224
{"bnuctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3225
{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3226
{"bgectr+", XLOCB(19,BOFP,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3227
{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3228
{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3229
{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3230
{"blectr+", XLOCB(19,BOFP,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3231
{"bngctr+", XLOCB(19,BOFP,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3232
{"blectrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3233
{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3234
{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3235
{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3236
{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3237
{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3238
{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3239
{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3240
{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3241
{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3242
{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3243
{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3244
{"blectr-", XLOCB(19,BOFM4,CBGT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3245
{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3246
{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3247
{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3248
{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3249
{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3250
{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3251
{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3252
{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3253
{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3254
{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3255
{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3256
{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3257
{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3258
{"blectr+", XLOCB(19,BOFP4,CBGT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3259
{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3260
{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3261
{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3262
{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3263
{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3264
{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3265
{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3266
{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3267
{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3268
{"bltctr",  XLOCB(19,BOT,CBLT,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3269
{"bltctr-", XLOCB(19,BOT,CBLT,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3270
{"bltctrl", XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3271
{"bltctrl-",XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3272
{"bgtctr",  XLOCB(19,BOT,CBGT,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3273
{"bgtctr-", XLOCB(19,BOT,CBGT,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3274
{"bgtctrl", XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3275
{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3276
{"beqctr",  XLOCB(19,BOT,CBEQ,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3277
{"beqctr-", XLOCB(19,BOT,CBEQ,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3278
{"beqctrl", XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3279
{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3280
{"bsoctr",  XLOCB(19,BOT,CBSO,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3281
{"bsoctr-", XLOCB(19,BOT,CBSO,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3282
{"bunctr",  XLOCB(19,BOT,CBSO,528,0),    XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3283
{"bunctr-", XLOCB(19,BOT,CBSO,528,0),    XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3284
{"bsoctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3285
{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3286
{"bunctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3287
{"bunctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3288
{"bltctr+", XLOCB(19,BOTP,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3289
{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3290
{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3291
{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3292
{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3293
{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3294
{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3295
{"bunctr+", XLOCB(19,BOTP,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3296
{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3297
{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3298
{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3299
{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3300
{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3301
{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3302
{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3303
{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3304
{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3305
{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3306
{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3307
{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3308
{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3309
{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3310
{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3311
{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3312
{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3313
{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3314
{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3315
{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0),  XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3316
{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3317
{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3318
 
3319
{"bfctr",   XLO(19,BOF,528,0),           XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3320
{"bfctr-",  XLO(19,BOF,528,0),           XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3321
{"bfctrl",  XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3322
{"bfctrl-", XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3323
{"bfctr+",  XLO(19,BOFP,528,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3324
{"bfctrl+", XLO(19,BOFP,528,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3325
{"bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3326
{"bfctrl-", XLO(19,BOFM4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3327
{"bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3328
{"bfctrl+", XLO(19,BOFP4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3329
{"btctr",   XLO(19,BOT,528,0),           XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3330
{"btctr-",  XLO(19,BOT,528,0),           XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3331
{"btctrl",  XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3332
{"btctrl-", XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3333
{"btctr+",  XLO(19,BOTP,528,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3334
{"btctrl+", XLO(19,BOTP,528,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3335
{"btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3336
{"btctrl-", XLO(19,BOTM4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3337
{"btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3338
{"btctrl+", XLO(19,BOTP4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3339
 
3340
{"bcctr-",  XLYLK(19,528,0,0),            XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3341
{"bcctrl-", XLYLK(19,528,0,1),           XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3342
{"bcctr+",  XLYLK(19,528,1,0),           XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3343
{"bcctrl+", XLYLK(19,528,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3344
{"bcctr",   XLLK(19,528,0),              XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3345
{"bcc",     XLLK(19,528,0),              XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3346
{"bcctrl",  XLLK(19,528,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3347
{"bccl",    XLLK(19,528,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3348
 
3349
{"rlwimi",      M(20,0), M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3350
{"rlimi",       M(20,0), M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3351
 
3352
{"rlwimi.",     M(20,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3353
{"rlimi.",      M(20,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3354
 
3355
{"rotlwi",      MME(21,31,0),    MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
3356
{"clrlwi",      MME(21,31,0),    MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
3357
{"rlwinm",      M(21,0), M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3358
{"rlinm",       M(21,0), M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3359
{"rotlwi.",     MME(21,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
3360
{"clrlwi.",     MME(21,31,1),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
3361
{"rlwinm.",     M(21,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3362
{"rlinm.",      M(21,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3363
 
3364
{"rlmi",        M(22,0), M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
3365
{"rlmi.",       M(22,1),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
3366
 
3367
{"rotlw",       MME(23,31,0),    MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
3368
{"rlwnm",       M(23,0), M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3369
{"rlnm",        M(23,0), M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3370
{"rotlw.",      MME(23,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
3371
{"rlwnm.",      M(23,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3372
{"rlnm.",       M(23,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3373
 
3374
{"nop",         OP(24),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
3375
{"ori",         OP(24),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3376
{"oril",        OP(24),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3377
 
3378
{"oris",        OP(25),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3379
{"oriu",        OP(25),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3380
 
3381
{"xori",        OP(26),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3382
{"xoril",       OP(26),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3383
 
3384
{"xoris",       OP(27),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3385
{"xoriu",       OP(27),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3386
 
3387
{"andi.",       OP(28),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3388
{"andil.",      OP(28),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3389
 
3390
{"andis.",      OP(29),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3391
{"andiu.",      OP(29),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3392
 
3393
{"rotldi",      MD(30,0,0),       MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
3394
{"clrldi",      MD(30,0,0),       MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
3395
{"rldicl",      MD(30,0,0),       MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3396
{"rotldi.",     MD(30,0,1),      MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
3397
{"clrldi.",     MD(30,0,1),      MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
3398
{"rldicl.",     MD(30,0,1),      MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3399
 
3400
{"rldicr",      MD(30,1,0),      MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
3401
{"rldicr.",     MD(30,1,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
3402
 
3403
{"rldic",       MD(30,2,0),      MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3404
{"rldic.",      MD(30,2,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3405
 
3406
{"rldimi",      MD(30,3,0),      MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3407
{"rldimi.",     MD(30,3,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3408
 
3409
{"rotld",       MDS(30,8,0),     MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
3410
{"rldcl",       MDS(30,8,0),     MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
3411
{"rotld.",      MDS(30,8,1),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
3412
{"rldcl.",      MDS(30,8,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
3413
 
3414
{"rldcr",       MDS(30,9,0),     MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
3415
{"rldcr.",      MDS(30,9,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
3416
 
3417
{"cmpw",        XOPL(31,0,0),     XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
3418
{"cmpd",        XOPL(31,0,1),    XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
3419
{"cmp",         X(31,0), XCMP_MASK,   PPC,       PPCNONE,        {BF, L, RA, RB}},
3420
{"cmp",         X(31,0), XCMPL_MASK,  PWRCOM,    PPCNONE,        {BF, RA, RB}},
3421
 
3422
{"twlgt",       XTO(31,4,TOLGT), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3423
{"tlgt",        XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3424
{"twllt",       XTO(31,4,TOLLT), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3425
{"tllt",        XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3426
{"tweq",        XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3427
{"teq",         XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3428
{"twlge",       XTO(31,4,TOLGE), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3429
{"tlge",        XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3430
{"twlnl",       XTO(31,4,TOLNL), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3431
{"tlnl",        XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3432
{"twlle",       XTO(31,4,TOLLE), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3433
{"tlle",        XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3434
{"twlng",       XTO(31,4,TOLNG), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3435
{"tlng",        XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3436
{"twgt",        XTO(31,4,TOGT),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3437
{"tgt",         XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3438
{"twge",        XTO(31,4,TOGE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3439
{"tge",         XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3440
{"twnl",        XTO(31,4,TONL),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3441
{"tnl",         XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3442
{"twlt",        XTO(31,4,TOLT),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3443
{"tlt",         XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3444
{"twle",        XTO(31,4,TOLE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3445
{"tle",         XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3446
{"twng",        XTO(31,4,TONG),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3447
{"tng",         XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3448
{"twne",        XTO(31,4,TONE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3449
{"tne",         XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3450
{"trap",        XTO(31,4,TOU),   0xffffffff, PPCCOM,    PPCNONE,        {0}},
3451
{"tw",          X(31,4),         X_MASK,     PPCCOM,    PPCNONE,        {TO, RA, RB}},
3452
{"t",           X(31,4),         X_MASK,     PWRCOM,    PPCNONE,        {TO, RA, RB}},
3453
 
3454
{"lvsl",        X(31,6),        X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3455
{"lvebx",       X(31,7),        X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3456
{"lbfcmx",      APU(31,7,0),     APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3457
 
3458
{"subfc",       XO(31,8,0,0),     XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3459
{"sf",          XO(31,8,0,0),     XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3460
{"subc",        XO(31,8,0,0),     XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
3461
{"subfc.",      XO(31,8,0,1),    XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3462
{"sf.",         XO(31,8,0,1),    XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3463
{"subc.",       XO(31,8,0,1),    XO_MASK,     PPCCOM,    PPCNONE,        {RT, RB, RA}},
3464
 
3465
{"mulhdu",      XO(31,9,0,0),     XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3466
{"mulhdu.",     XO(31,9,0,1),    XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3467
 
3468
{"addc",        XO(31,10,0,0),    XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3469
{"a",           XO(31,10,0,0),    XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3470
{"addc.",       XO(31,10,0,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3471
{"a.",          XO(31,10,0,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3472
 
3473
{"mulhwu",      XO(31,11,0,0),    XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3474
{"mulhwu.",     XO(31,11,0,1),   XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3475
 
3476
{"isellt",      X(31,15),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3477
 
3478
{"tlbilxlpid",  XTO(31,18,0),    XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
3479
{"tlbilxpid",   XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
3480
{"tlbilxva",    XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {RA0, RB}},
3481
{"tlbilx",      X(31,18),       X_MASK,   E500MC|PPCA2, PPCNONE,        {T, RA0, RB}},
3482
 
3483
{"mfcr",        XFXM(31,19,0,0), XFXFXM_MASK, POWER4,     PPCNONE,        {RT, FXM4}},
3484
{"mfcr",        XFXM(31,19,0,0), XRARB_MASK, COM, POWER4,         {RT}},
3485
{"mfocrf",      XFXM(31,19,0,1), XFXFXM_MASK, COM,       PPCNONE,        {RT, FXM}},
3486
 
3487
{"lwarx",       X(31,20),       XEH_MASK,    PPC,       PPCNONE,        {RT, RA0, RB, EH}},
3488
 
3489
{"ldx",         X(31,21),       X_MASK,      PPC64,     PPCNONE,        {RT, RA0, RB}},
3490
 
3491
{"icbt",        X(31,22),       X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}},
3492
 
3493
{"lwzx",        X(31,23),       X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
3494
{"lx",          X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
3495
 
3496
{"slw",         XRC(31,24,0),    X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
3497
{"sl",          XRC(31,24,0),    X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
3498
{"slw.",        XRC(31,24,1),   X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
3499
{"sl.",         XRC(31,24,1),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
3500
 
3501
{"cntlzw",      XRC(31,26,0),    XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
3502
{"cntlz",       XRC(31,26,0),    XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
3503
{"cntlzw.",     XRC(31,26,1),   XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
3504
{"cntlz.",      XRC(31,26,1),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
3505
 
3506
{"sld",         XRC(31,27,0),    X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
3507
{"sld.",        XRC(31,27,1),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
3508
 
3509
{"and",         XRC(31,28,0),    X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3510
{"and.",        XRC(31,28,1),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3511
 
3512
{"maskg",       XRC(31,29,0),    X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
3513
{"maskg.",      XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
3514
 
3515
{"ldepx",       X(31,29),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3516
{"lwepx",       X(31,31),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3517
 
3518
{"cmplw",       XOPL(31,32,0),   XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
3519
{"cmpld",       XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
3520
{"cmpl",        X(31,32),       XCMP_MASK,   PPC,       PPCNONE,        {BF, L, RA, RB}},
3521
{"cmpl",        X(31,32),       XCMPL_MASK,  PWRCOM,    PPCNONE,        {BF, RA, RB}},
3522
 
3523
{"lvsr",        X(31,38),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3524
{"lvehx",       X(31,39),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3525
{"lhfcmx",      APU(31,39,0),    APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3526
 
3527
{"iselgt",      X(31,47),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3528
 
3529
{"lvewx",       X(31,71),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3530
 
3531
{"addg6s",      XO(31,74,0,0),    XO_MASK,     POWER6,    PPCNONE,        {RT, RA, RB}},
3532
 
3533
{"iseleq",      X(31,79),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3534
 
3535
{"isel",        XISEL(31,15),   XISEL_MASK,  PPCISEL,   PPCNONE,        {RT, RA, RB, CRB}},
3536
 
3537
{"subf",        XO(31,40,0,0),    XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3538
{"sub",         XO(31,40,0,0),    XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
3539
{"subf.",       XO(31,40,0,1),   XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3540
{"sub.",        XO(31,40,0,1),   XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
3541
 
3542
{"eratilx",     X(31,51),       X_MASK,      PPCA2,     PPCNONE,        {ERAT_T, RA, RB}},
3543
 
3544
{"lbarx",       X(31,52),       XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
3545
 
3546
{"ldux",        X(31,53),       X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
3547
 
3548
{"dcbst",       X(31,54),       XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
3549
 
3550
{"lwzux",       X(31,55),       X_MASK,      PPCCOM,    PPCNONE,        {RT, RAL, RB}},
3551
{"lux",         X(31,55),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
3552
 
3553
{"cntlzd",      XRC(31,58,0),    XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
3554
{"cntlzd.",     XRC(31,58,1),   XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
3555
 
3556
{"andc",        XRC(31,60,0),    X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3557
{"andc.",       XRC(31,60,1),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3558
 
3559
{"waitrsv",     X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3560
{"waitimpl",    X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3561
{"wait",        X(31,62),         XWC_MASK,   POWER7|E500MC|PPCA2, PPCNONE, {WC}},
3562
 
3563
{"dcbstep",     XRT(31,63,0),    XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
3564
 
3565
{"tdlgt",       XTO(31,68,TOLGT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3566
{"tdllt",       XTO(31,68,TOLLT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3567
{"tdeq",        XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3568
{"tdlge",       XTO(31,68,TOLGE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3569
{"tdlnl",       XTO(31,68,TOLNL), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3570
{"tdlle",       XTO(31,68,TOLLE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3571
{"tdlng",       XTO(31,68,TOLNG), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3572
{"tdgt",        XTO(31,68,TOGT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3573
{"tdge",        XTO(31,68,TOGE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3574
{"tdnl",        XTO(31,68,TONL),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3575
{"tdlt",        XTO(31,68,TOLT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3576
{"tdle",        XTO(31,68,TOLE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3577
{"tdng",        XTO(31,68,TONG),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3578
{"tdne",        XTO(31,68,TONE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3579
{"td",          X(31,68),       X_MASK,      PPC64,     PPCNONE,        {TO, RA, RB}},
3580
 
3581
{"lwfcmx",      APU(31,71,0),    APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3582
{"mulhd",       XO(31,73,0,0),    XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3583
{"mulhd.",      XO(31,73,0,1),   XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3584
 
3585
{"mulhw",       XO(31,75,0,0),    XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3586
{"mulhw.",      XO(31,75,0,1),   XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3587
 
3588
{"dlmzb",       XRC(31,78,0),    X_MASK,  PPC403|PPC440, PPCNONE,        {RA, RS, RB}},
3589
{"dlmzb.",      XRC(31,78,1),   X_MASK,  PPC403|PPC440, PPCNONE,        {RA, RS, RB}},
3590
 
3591
{"mtsrd",       X(31,82),  XRB_MASK|(1<<20), PPC64,     PPCNONE,        {SR, RS}},
3592
 
3593
{"mfmsr",       X(31,83),       XRARB_MASK,  COM,       PPCNONE,        {RT}},
3594
 
3595
{"ldarx",       X(31,84),       XEH_MASK,    PPC64,     PPCNONE,        {RT, RA0, RB, EH}},
3596
 
3597
{"dcbfl",       XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA, RB}},
3598
{"dcbf",        X(31,86),       XLRT_MASK,   PPC,       PPCNONE,        {RA, RB, L}},
3599
 
3600
{"lbzx",        X(31,87),       X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
3601
 
3602
{"lbepx",       X(31,95),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3603
 
3604
{"lvx",         X(31,103),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3605
{"lqfcmx",      APU(31,103,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3606
 
3607
{"neg",         XO(31,104,0,0),   XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
3608
{"neg.",        XO(31,104,0,1),  XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
3609
 
3610
{"mul",         XO(31,107,0,0),   XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3611
{"mul.",        XO(31,107,0,1),  XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3612
 
3613
{"mtsrdin",     X(31,114),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
3614
 
3615
{"lharx",       X(31,116),      XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
3616
 
3617
{"clf",         X(31,118),      XTO_MASK,    POWER,     PPCNONE,        {RA, RB}},
3618
 
3619
{"lbzux",       X(31,119),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
3620
 
3621
{"popcntb",     X(31,122),      XRB_MASK,    POWER5,    PPCNONE,        {RA, RS}},
3622
 
3623
{"not",         XRC(31,124,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
3624
{"nor",         XRC(31,124,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3625
{"not.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
3626
{"nor.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3627
 
3628
{"dcbfep",      XRT(31,127,0),   XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
3629
 
3630
{"wrtee",       X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
3631
 
3632
{"dcbtstls",    X(31,134),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
3633
 
3634
{"stvebx",      X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3635
{"stbfcmx",     APU(31,135,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3636
 
3637
{"subfe",       XO(31,136,0,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3638
{"sfe",         XO(31,136,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3639
{"subfe.",      XO(31,136,0,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3640
{"sfe.",        XO(31,136,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3641
 
3642
{"adde",        XO(31,138,0,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3643
{"ae",          XO(31,138,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3644
{"adde.",       XO(31,138,0,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3645
{"ae.",         XO(31,138,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3646
 
3647
{"dcbtstlse",   X(31,142),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
3648
 
3649
{"mtcr",        XFXM(31,144,0xff,0), XRARB_MASK, COM,    PPCNONE,        {RS}},
3650
{"mtcrf",       XFXM(31,144,0,0), XFXFXM_MASK, COM,       PPCNONE,        {FXM, RS}},
3651
{"mtocrf",      XFXM(31,144,0,1), XFXFXM_MASK, COM,      PPCNONE,        {FXM, RS}},
3652
 
3653
{"mtmsr",       X(31,146),      XRLARB_MASK, COM,       PPCNONE,        {RS, A_L}},
3654
 
3655
{"eratsx",      XRC(31,147,0),   X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3656
{"eratsx.",     XRC(31,147,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3657
 
3658
{"stdx",        X(31,149),      X_MASK,      PPC64,     PPCNONE,        {RS, RA0, RB}},
3659
 
3660
{"stwcx.",      XRC(31,150,1),  X_MASK,      PPC,       PPCNONE,        {RS, RA0, RB}},
3661
 
3662
{"stwx",        X(31,151),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
3663
{"stx",         X(31,151),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA, RB}},
3664
 
3665
{"slq",         XRC(31,152,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3666
{"slq.",        XRC(31,152,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3667
 
3668
{"sle",         XRC(31,153,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3669
{"sle.",        XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3670
 
3671
{"prtyw",       X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
3672
 
3673
{"stdepx",      X(31,157),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3674
 
3675
{"stwepx",      X(31,159),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3676
 
3677
{"wrteei",      X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}},
3678
 
3679
{"dcbtls",      X(31,166),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
3680
 
3681
{"stvehx",      X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3682
{"sthfcmx",     APU(31,167,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3683
 
3684
{"dcbtlse",     X(31,174),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
3685
 
3686
{"mtmsrd",      X(31,178),      XRLARB_MASK, PPC64,     PPCNONE,        {RS, A_L}},
3687
 
3688
{"eratre",      X(31,179),      X_MASK,      PPCA2,     PPCNONE,        {RT, RA, WS}},
3689
 
3690
{"stdux",       X(31,181),      X_MASK,      PPC64,     PPCNONE,        {RS, RAS, RB}},
3691
 
3692
{"wchkall",     X(31,182),      X_MASK,      PPCA2,     PPCNONE,        {OBF}},
3693
 
3694
{"stwux",       X(31,183),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RAS, RB}},
3695
{"stux",        X(31,183),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
3696
 
3697
{"sliq",        XRC(31,184,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3698
{"sliq.",       XRC(31,184,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3699
 
3700
{"prtyd",       X(31,186),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
3701
 
3702
{"stvewx",      X(31,199),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3703
{"stwfcmx",     APU(31,199,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3704
 
3705
{"subfze",      XO(31,200,0,0),   XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3706
{"sfze",        XO(31,200,0,0),   XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3707
{"subfze.",     XO(31,200,0,1),  XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3708
{"sfze.",       XO(31,200,0,1),  XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3709
 
3710
{"addze",       XO(31,202,0,0),   XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3711
{"aze",         XO(31,202,0,0),   XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3712
{"addze.",      XO(31,202,0,1),  XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3713
{"aze.",        XO(31,202,0,1),  XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3714
 
3715
{"msgsnd",      XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE,     {RB}},
3716
 
3717
{"mtsr",        X(31,210), XRB_MASK|(1<<20), COM32,     PPCNONE,        {SR, RS}},
3718
 
3719
{"eratwe",      X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
3720
 
3721
{"ldawx.",      XRC(31,212,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3722
 
3723
{"stdcx.",      XRC(31,214,1),  X_MASK,      PPC64,     PPCNONE,        {RS, RA0, RB}},
3724
 
3725
{"stbx",        X(31,215),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
3726
 
3727
{"sllq",        XRC(31,216,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3728
{"sllq.",       XRC(31,216,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3729
 
3730
{"sleq",        XRC(31,217,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3731
{"sleq.",       XRC(31,217,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3732
 
3733
{"stbepx",      X(31,223),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3734
 
3735
{"icblc",       X(31,230),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
3736
 
3737
{"stvx",        X(31,231),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3738
{"stqfcmx",     APU(31,231,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3739
 
3740
{"subfme",      XO(31,232,0,0),   XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3741
{"sfme",        XO(31,232,0,0),   XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3742
{"subfme.",     XO(31,232,0,1),  XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3743
{"sfme.",       XO(31,232,0,1),  XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3744
 
3745
{"mulld",       XO(31,233,0,0),   XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3746
{"mulld.",      XO(31,233,0,1),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3747
 
3748
{"addme",       XO(31,234,0,0),   XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3749
{"ame",         XO(31,234,0,0),   XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3750
{"addme.",      XO(31,234,0,1),  XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3751
{"ame.",        XO(31,234,0,1),  XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3752
 
3753
{"mullw",       XO(31,235,0,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3754
{"muls",        XO(31,235,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3755
{"mullw.",      XO(31,235,0,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3756
{"muls.",       XO(31,235,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3757
 
3758
{"icblce",      X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
3759
{"msgclr",      XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE,       {RB}},
3760
{"mtsrin",      X(31,242),      XRA_MASK,    PPC32,     PPCNONE,        {RS, RB}},
3761
{"mtsri",       X(31,242),      XRA_MASK,    POWER32,   PPCNONE,        {RS, RB}},
3762
 
3763
{"dcbtstt",     XRT(31,246,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA, RB}},
3764
{"dcbtst",      X(31,246),      X_MASK,      POWER4,    PPCNONE,        {RA, RB, CT}},
3765
{"dcbtst",      X(31,246),      X_MASK,      PPC,       POWER4,         {CT, RA, RB}},
3766
 
3767
{"stbux",       X(31,247),      X_MASK,      COM,       PPCNONE,        {RS, RAS, RB}},
3768
 
3769
{"slliq",       XRC(31,248,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3770
{"slliq.",      XRC(31,248,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3771
 
3772
{"bpermd",      X(31,252),      X_MASK,   POWER7|PPCA2, PPCNONE,        {RA, RS, RB}},
3773
 
3774
{"dcbtstep",    XRT(31,255,0),   X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3775
 
3776
{"mfdcrx",      X(31,259),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {RS, RA}},
3777
{"mfdcrx.",     XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
3778
 
3779
{"icbt",        X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
3780
 
3781
{"ldfcmx",      APU(31,263,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3782
{"doz",         XO(31,264,0,0),   XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3783
{"doz.",        XO(31,264,0,1),  XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3784
 
3785
{"add",         XO(31,266,0,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3786
{"cax",         XO(31,266,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3787
{"add.",        XO(31,266,0,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3788
{"cax.",        XO(31,266,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3789
 
3790
{"ehpriv",      X(31,270),      0xffffffff, E500MC|PPCA2, PPCNONE,      {0}},
3791
 
3792
{"tlbiel",      X(31,274),      XRTLRA_MASK, POWER4,    PPC476,         {RB, L}},
3793
 
3794
{"mfapidi",     X(31,275),      X_MASK,      BOOKE,     PPCNONE,        {RT, RA}},
3795
 
3796
{"lscbx",       XRC(31,277,0),   X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
3797
{"lscbx.",      XRC(31,277,1),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
3798
 
3799
{"dcbtt",       XRT(31,278,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA, RB}},
3800
{"dcbt",        X(31,278),      X_MASK,      POWER4,    PPCNONE,        {RA, RB, CT}},
3801
{"dcbt",        X(31,278),      X_MASK,      PPC,       POWER4,         {CT, RA, RB}},
3802
 
3803
{"lhzx",        X(31,279),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
3804
 
3805
{"cdtbcd",      X(31,282),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
3806
 
3807
{"eqv",         XRC(31,284,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3808
{"eqv.",        XRC(31,284,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3809
 
3810
{"lhepx",       X(31,287),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3811
 
3812
{"mfdcrux",     X(31,291),      X_MASK,      PPC464,    PPCNONE,        {RS, RA}},
3813
 
3814
{"tlbie",       X(31,306),      XRTLRA_MASK, PPC,       PPCNONE,        {RB, L}},
3815
{"tlbi",        X(31,306),      XRT_MASK,    POWER,     PPCNONE,        {RA0, RB}},
3816
 
3817
{"eciwx",       X(31,310),      X_MASK,      PPC,       PPCNONE,        {RT, RA, RB}},
3818
 
3819
{"lhzux",       X(31,311),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
3820
 
3821
{"cbcdtd",      X(31,314),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
3822
 
3823
{"xor",         XRC(31,316,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3824
{"xor.",        XRC(31,316,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3825
 
3826
{"dcbtep",      XRT(31,319,0),   X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3827
 
3828
{"mfexisr",     XSPR(31,323, 64), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3829
{"mfexier",     XSPR(31,323, 66), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3830
{"mfbr0",       XSPR(31,323,128), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3831
{"mfbr1",       XSPR(31,323,129), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3832
{"mfbr2",       XSPR(31,323,130), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3833
{"mfbr3",       XSPR(31,323,131), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3834
{"mfbr4",       XSPR(31,323,132), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3835
{"mfbr5",       XSPR(31,323,133), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3836
{"mfbr6",       XSPR(31,323,134), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3837
{"mfbr7",       XSPR(31,323,135), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3838
{"mfbear",      XSPR(31,323,144), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3839
{"mfbesr",      XSPR(31,323,145), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3840
{"mfiocr",      XSPR(31,323,160), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3841
{"mfdmacr0",    XSPR(31,323,192), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3842
{"mfdmact0",    XSPR(31,323,193), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3843
{"mfdmada0",    XSPR(31,323,194), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3844
{"mfdmasa0",    XSPR(31,323,195), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3845
{"mfdmacc0",    XSPR(31,323,196), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3846
{"mfdmacr1",    XSPR(31,323,200), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3847
{"mfdmact1",    XSPR(31,323,201), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3848
{"mfdmada1",    XSPR(31,323,202), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3849
{"mfdmasa1",    XSPR(31,323,203), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3850
{"mfdmacc1",    XSPR(31,323,204), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3851
{"mfdmacr2",    XSPR(31,323,208), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3852
{"mfdmact2",    XSPR(31,323,209), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3853
{"mfdmada2",    XSPR(31,323,210), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3854
{"mfdmasa2",    XSPR(31,323,211), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3855
{"mfdmacc2",    XSPR(31,323,212), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3856
{"mfdmacr3",    XSPR(31,323,216), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3857
{"mfdmact3",    XSPR(31,323,217), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3858
{"mfdmada3",    XSPR(31,323,218), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3859
{"mfdmasa3",    XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3860
{"mfdmacc3",    XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3861
{"mfdmasr",     XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3862
{"mfdcr",       X(31,323),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RT, SPR}},
3863
{"mfdcr.",      XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
3864
 
3865
{"dcread",      X(31,326),      X_MASK,      PPC476,    PPCNONE,        {RT, RA, RB}},
3866
 
3867
{"div",         XO(31,331,0,0),   XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3868
{"div.",        XO(31,331,0,1),  XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3869
 
3870
{"lxvdsx",      X(31,332),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
3871
 
3872
{"mfpmr",       X(31,334),      X_MASK, PPCPMR|PPCE300, PPCNONE,        {RT, PMR}},
3873
 
3874
{"mfmq",        XSPR(31,339,  0), XSPR_MASK, M601,       PPCNONE,        {RT}},
3875
{"mfxer",       XSPR(31,339,  1), XSPR_MASK, COM,       PPCNONE,        {RT}},
3876
{"mfrtcu",      XSPR(31,339,  4), XSPR_MASK, COM,       PPCNONE,        {RT}},
3877
{"mfrtcl",      XSPR(31,339,  5), XSPR_MASK, COM,       PPCNONE,        {RT}},
3878
{"mfdec",       XSPR(31,339,  6), XSPR_MASK, MFDEC1,    PPCNONE,        {RT}},
3879
{"mflr",        XSPR(31,339,  8), XSPR_MASK, COM,       PPCNONE,        {RT}},
3880
{"mfctr",       XSPR(31,339,  9), XSPR_MASK, COM,       PPCNONE,        {RT}},
3881
{"mftid",       XSPR(31,339, 17), XSPR_MASK, POWER,     PPCNONE,        {RT}},
3882
{"mfdsisr",     XSPR(31,339, 18), XSPR_MASK, COM,       PPCNONE,        {RT}},
3883
{"mfdar",       XSPR(31,339, 19), XSPR_MASK, COM,       PPCNONE,        {RT}},
3884
{"mfdec",       XSPR(31,339, 22), XSPR_MASK, MFDEC2,    PPCNONE,        {RT}},
3885
{"mfsdr0",      XSPR(31,339, 24), XSPR_MASK, POWER,     PPCNONE,        {RT}},
3886
{"mfsdr1",      XSPR(31,339, 25), XSPR_MASK, COM,       PPCNONE,        {RT}},
3887
{"mfsrr0",      XSPR(31,339, 26), XSPR_MASK, COM,       PPCNONE,        {RT}},
3888
{"mfsrr1",      XSPR(31,339, 27), XSPR_MASK, COM,       PPCNONE,        {RT}},
3889
{"mfcfar",      XSPR(31,339, 28), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
3890
{"mfpid",       XSPR(31,339, 48), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3891
{"mfcsrr0",     XSPR(31,339, 58), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3892
{"mfcsrr1",     XSPR(31,339, 59), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3893
{"mfdear",      XSPR(31,339, 61), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3894
{"mfesr",       XSPR(31,339, 62), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3895
{"mfivpr",      XSPR(31,339, 63), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3896
{"mfcmpa",      XSPR(31,339,144), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3897
{"mfcmpb",      XSPR(31,339,145), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3898
{"mfcmpc",      XSPR(31,339,146), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3899
{"mfcmpd",      XSPR(31,339,147), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3900
{"mficr",       XSPR(31,339,148), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3901
{"mfder",       XSPR(31,339,149), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3902
{"mfcounta",    XSPR(31,339,150), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3903
{"mfcountb",    XSPR(31,339,151), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3904
{"mfcmpe",      XSPR(31,339,152), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3905
{"mfcmpf",      XSPR(31,339,153), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3906
{"mfcmpg",      XSPR(31,339,154), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3907
{"mfcmph",      XSPR(31,339,155), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3908
{"mflctrl1",    XSPR(31,339,156), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3909
{"mflctrl2",    XSPR(31,339,157), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3910
{"mfictrl",     XSPR(31,339,158), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3911
{"mfbar",       XSPR(31,339,159), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3912
{"mfvrsave",    XSPR(31,339,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RT}},
3913
{"mfusprg0",    XSPR(31,339,256), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3914
{"mfsprg",      XSPR(31,339,256), XSPRG_MASK, PPC,      PPCNONE,        {RT, SPRG}},
3915
{"mfsprg4",     XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3916
{"mfsprg5",     XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3917
{"mfsprg6",     XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3918
{"mfsprg7",     XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3919
{"mftb",        XSPR(31,339,268), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3920
{"mftbl",       XSPR(31,339,268), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3921
{"mftbu",       XSPR(31,339,269), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3922
{"mfsprg0",     XSPR(31,339,272), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3923
{"mfsprg1",     XSPR(31,339,273), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3924
{"mfsprg2",     XSPR(31,339,274), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3925
{"mfsprg3",     XSPR(31,339,275), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3926
{"mfasr",       XSPR(31,339,280), XSPR_MASK, PPC64,     PPCNONE,        {RT}},
3927
{"mfear",       XSPR(31,339,282), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3928
{"mfpir",       XSPR(31,339,286), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3929
{"mfpvr",       XSPR(31,339,287), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3930
{"mfdbsr",      XSPR(31,339,304), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3931
{"mfdbcr0",     XSPR(31,339,308), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3932
{"mfdbcr1",     XSPR(31,339,309), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3933
{"mfdbcr2",     XSPR(31,339,310), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3934
{"mfiac1",      XSPR(31,339,312), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3935
{"mfiac2",      XSPR(31,339,313), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3936
{"mfiac3",      XSPR(31,339,314), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3937
{"mfiac4",      XSPR(31,339,315), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3938
{"mfdac1",      XSPR(31,339,316), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3939
{"mfdac2",      XSPR(31,339,317), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3940
{"mfdvc1",      XSPR(31,339,318), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3941
{"mfdvc2",      XSPR(31,339,319), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3942
{"mftsr",       XSPR(31,339,336), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3943
{"mftcr",       XSPR(31,339,340), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3944
{"mfivor0",     XSPR(31,339,400), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3945
{"mfivor1",     XSPR(31,339,401), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3946
{"mfivor2",     XSPR(31,339,402), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3947
{"mfivor3",     XSPR(31,339,403), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3948
{"mfivor4",     XSPR(31,339,404), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3949
{"mfivor5",     XSPR(31,339,405), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3950
{"mfivor6",     XSPR(31,339,406), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3951
{"mfivor7",     XSPR(31,339,407), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3952
{"mfivor8",     XSPR(31,339,408), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3953
{"mfivor9",     XSPR(31,339,409), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3954
{"mfivor10",    XSPR(31,339,410), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3955
{"mfivor11",    XSPR(31,339,411), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3956
{"mfivor12",    XSPR(31,339,412), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3957
{"mfivor13",    XSPR(31,339,413), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3958
{"mfivor14",    XSPR(31,339,414), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3959
{"mfivor15",    XSPR(31,339,415), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3960
{"mfspefscr",   XSPR(31,339,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3961
{"mfbbear",     XSPR(31,339,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
3962
{"mfbbtar",     XSPR(31,339,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
3963
{"mfivor32",    XSPR(31,339,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3964
{"mfibatu",     XSPR(31,339,528), XSPRBAT_MASK, PPC,    PPCNONE,        {RT, SPRBAT}},
3965
{"mfivor33",    XSPR(31,339,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3966
{"mfibatl",     XSPR(31,339,529), XSPRBAT_MASK, PPC,    PPCNONE,        {RT, SPRBAT}},
3967
{"mfivor34",    XSPR(31,339,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3968
{"mfivor35",    XSPR(31,339,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RT}},
3969
{"mfdbatu",     XSPR(31,339,536), XSPRBAT_MASK, PPC,    PPCNONE,        {RT, SPRBAT}},
3970
{"mfdbatl",     XSPR(31,339,537), XSPRBAT_MASK, PPC,    PPCNONE,        {RT, SPRBAT}},
3971
{"mfic_cst",    XSPR(31,339,560), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3972
{"mfic_adr",    XSPR(31,339,561), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3973
{"mfic_dat",    XSPR(31,339,562), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3974
{"mfdc_cst",    XSPR(31,339,568), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3975
{"mfdc_adr",    XSPR(31,339,569), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3976
{"mfdc_dat",    XSPR(31,339,570), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3977
{"mfmcsrr0",    XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
3978
{"mfmcsrr1",    XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
3979
{"mfmcsr",      XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
3980
{"mfmcar",      XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
3981
{"mfdpdr",      XSPR(31,339,630), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3982
{"mfdpir",      XSPR(31,339,631), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3983
{"mfimmr",      XSPR(31,339,638), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3984
{"mfmi_ctr",    XSPR(31,339,784), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3985
{"mfmi_ap",     XSPR(31,339,786), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3986
{"mfmi_epn",    XSPR(31,339,787), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3987
{"mfmi_twc",    XSPR(31,339,789), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3988
{"mfmi_rpn",    XSPR(31,339,790), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3989
{"mfmd_ctr",    XSPR(31,339,792), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3990
{"mfm_casid",   XSPR(31,339,793), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3991
{"mfmd_ap",     XSPR(31,339,794), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3992
{"mfmd_epn",    XSPR(31,339,795), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3993
{"mfmd_twb",    XSPR(31,339,796), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3994
{"mfmd_twc",    XSPR(31,339,797), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3995
{"mfmd_rpn",    XSPR(31,339,798), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3996
{"mfm_tw",      XSPR(31,339,799), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3997
{"mfmi_dbcam",  XSPR(31,339,816), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3998
{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3999
{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4000
{"mfmd_dbcam",  XSPR(31,339,824), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4001
{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4002
{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4003
{"mfummcr0",    XSPR(31,339,936), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4004
{"mfupmc1",     XSPR(31,339,937), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4005
{"mfupmc2",     XSPR(31,339,938), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4006
{"mfusia",      XSPR(31,339,939), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4007
{"mfummcr1",    XSPR(31,339,940), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4008
{"mfupmc3",     XSPR(31,339,941), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4009
{"mfupmc4",     XSPR(31,339,942), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4010
{"mfzpr",       XSPR(31,339,944), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4011
{"mfpid",       XSPR(31,339,945), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4012
{"mfccr0",      XSPR(31,339,947), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4013
{"mfiac3",      XSPR(31,339,948), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4014
{"mfiac4",      XSPR(31,339,949), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4015
{"mfdvc1",      XSPR(31,339,950), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4016
{"mfdvc2",      XSPR(31,339,951), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4017
{"mfmmcr0",     XSPR(31,339,952), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4018
{"mfpmc1",      XSPR(31,339,953), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4019
{"mfsgr",       XSPR(31,339,953), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4020
{"mfdcwr",      XSPR(31,339,954), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4021
{"mfpmc2",      XSPR(31,339,954), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4022
{"mfsia",       XSPR(31,339,955), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4023
{"mfsler",      XSPR(31,339,955), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4024
{"mfmmcr1",     XSPR(31,339,956), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4025
{"mfsu0r",      XSPR(31,339,956), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4026
{"mfdbcr1",     XSPR(31,339,957), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4027
{"mfpmc3",      XSPR(31,339,957), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4028
{"mfpmc4",      XSPR(31,339,958), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4029
{"mficdbdr",    XSPR(31,339,979), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4030
{"mfesr",       XSPR(31,339,980), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4031
{"mfdear",      XSPR(31,339,981), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4032
{"mfevpr",      XSPR(31,339,982), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4033
{"mfcdbcr",     XSPR(31,339,983), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4034
{"mftsr",       XSPR(31,339,984), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4035
{"mftcr",       XSPR(31,339,986), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4036
{"mfpit",       XSPR(31,339,987), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4037
{"mftbhi",      XSPR(31,339,988), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4038
{"mftblo",      XSPR(31,339,989), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4039
{"mfsrr2",      XSPR(31,339,990), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4040
{"mfsrr3",      XSPR(31,339,991), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4041
{"mfdbsr",      XSPR(31,339,1008), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4042
{"mfdbcr0",     XSPR(31,339,1010), XSPR_MASK, PPC405,   PPCNONE,        {RT}},
4043
{"mfiac1",      XSPR(31,339,1012), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4044
{"mfiac2",      XSPR(31,339,1013), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4045
{"mfdac1",      XSPR(31,339,1014), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4046
{"mfdac2",      XSPR(31,339,1015), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4047
{"mfl2cr",      XSPR(31,339,1017), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4048
{"mfdccr",      XSPR(31,339,1018), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4049
{"mficcr",      XSPR(31,339,1019), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4050
{"mfictc",      XSPR(31,339,1019), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4051
{"mfpbl1",      XSPR(31,339,1020), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4052
{"mfthrm1",     XSPR(31,339,1020), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4053
{"mfpbu1",      XSPR(31,339,1021), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4054
{"mfthrm2",     XSPR(31,339,1021), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4055
{"mfpbl2",      XSPR(31,339,1022), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4056
{"mfthrm3",     XSPR(31,339,1022), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4057
{"mfpbu2",      XSPR(31,339,1023), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4058
{"mfspr",       X(31,339),      X_MASK,      COM,       PPCNONE,        {RT, SPR}},
4059
 
4060
{"lwax",        X(31,341),      X_MASK,      PPC64,     PPCNONE,        {RT, RA0, RB}},
4061
 
4062
{"dst",         XDSS(31,342,0),  XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4063
 
4064
{"lhax",        X(31,343),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
4065
 
4066
{"lvxl",        X(31,359),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
4067
 
4068
{"abs",         XO(31,360,0,0),   XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4069
{"abs.",        XO(31,360,0,1),  XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4070
 
4071
{"divs",        XO(31,363,0,0),   XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4072
{"divs.",       XO(31,363,0,1),  XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4073
 
4074
{"tlbia",       X(31,370),      0xffffffff,  PPC,       PPCNONE,        {0}},
4075
 
4076
{"mftbl",       XSPR(31,371,268), XSPR_MASK, CLASSIC,   PPCNONE,        {RT}},
4077
{"mftbu",       XSPR(31,371,269), XSPR_MASK, CLASSIC,   PPCNONE,        {RT}},
4078
{"mftb",        X(31,371),      X_MASK,  CLASSIC|PPCA2, POWER7,         {RT, TBR}},
4079
 
4080
{"lwaux",       X(31,373),      X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
4081
 
4082
{"dstst",       XDSS(31,374,0),  XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4083
 
4084
{"lhaux",       X(31,375),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
4085
 
4086
{"popcntw",     X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
4087
 
4088
{"mtdcrx",      X(31,387),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {RA, RS}},
4089
{"mtdcrx.",     XRC(31,387,1),  X_MASK,      PPCA2,     PPCNONE,        {RA, RS}},
4090
 
4091
{"dcblc",       X(31,390),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
4092
{"stdfcmx",     APU(31,391,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4093
 
4094
{"divdeu",      XO(31,393,0,0),   XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4095
{"divdeu.",     XO(31,393,0,1),  XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4096
{"divweu",      XO(31,395,0,0),   XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4097
{"divweu.",     XO(31,395,0,1),  XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4098
 
4099
{"dcblce",      X(31,398),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
4100
 
4101
{"slbmte",      X(31,402),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
4102
 
4103
{"icswx",       XRC(31,406,0),   X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
4104
{"icswx.",      XRC(31,406,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
4105
 
4106
{"sthx",        X(31,407),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
4107
 
4108
{"orc",         XRC(31,412,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4109
{"orc.",        XRC(31,412,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4110
 
4111
{"sthepx",      X(31,415),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
4112
 
4113
{"mtdcrux",     X(31,419),      X_MASK,      PPC464,    PPCNONE,        {RA, RS}},
4114
 
4115
{"divde",       XO(31,425,0,0),   XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4116
{"divde.",      XO(31,425,0,1),  XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4117
{"divwe",       XO(31,427,0,0),   XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4118
{"divwe.",      XO(31,427,0,1),  XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4119
 
4120
{"slbie",       X(31,434),      XRTRA_MASK,  PPC64,     PPCNONE,        {RB}},
4121
 
4122
{"ecowx",       X(31,438),      X_MASK,      PPC,       PPCNONE,        {RT, RA, RB}},
4123
 
4124
{"sthux",       X(31,439),      X_MASK,      COM,       PPCNONE,        {RS, RAS, RB}},
4125
 
4126
{"mdors",       0x7f9ce378,     0xffffffff,  E500MC,    PPCNONE,        {0}},
4127
 
4128
{"mr",          XRC(31,444,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4129
{"or",          XRC(31,444,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4130
{"mr.",         XRC(31,444,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4131
{"or.",         XRC(31,444,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4132
 
4133
{"mtexisr",     XSPR(31,451, 64), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4134
{"mtexier",     XSPR(31,451, 66), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4135
{"mtbr0",       XSPR(31,451,128), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4136
{"mtbr1",       XSPR(31,451,129), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4137
{"mtbr2",       XSPR(31,451,130), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4138
{"mtbr3",       XSPR(31,451,131), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4139
{"mtbr4",       XSPR(31,451,132), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4140
{"mtbr5",       XSPR(31,451,133), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4141
{"mtbr6",       XSPR(31,451,134), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4142
{"mtbr7",       XSPR(31,451,135), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4143
{"mtbear",      XSPR(31,451,144), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4144
{"mtbesr",      XSPR(31,451,145), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4145
{"mtiocr",      XSPR(31,451,160), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4146
{"mtdmacr0",    XSPR(31,451,192), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4147
{"mtdmact0",    XSPR(31,451,193), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4148
{"mtdmada0",    XSPR(31,451,194), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4149
{"mtdmasa0",    XSPR(31,451,195), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4150
{"mtdmacc0",    XSPR(31,451,196), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4151
{"mtdmacr1",    XSPR(31,451,200), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4152
{"mtdmact1",    XSPR(31,451,201), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4153
{"mtdmada1",    XSPR(31,451,202), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4154
{"mtdmasa1",    XSPR(31,451,203), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4155
{"mtdmacc1",    XSPR(31,451,204), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4156
{"mtdmacr2",    XSPR(31,451,208), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4157
{"mtdmact2",    XSPR(31,451,209), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4158
{"mtdmada2",    XSPR(31,451,210), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4159
{"mtdmasa2",    XSPR(31,451,211), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4160
{"mtdmacc2",    XSPR(31,451,212), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4161
{"mtdmacr3",    XSPR(31,451,216), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4162
{"mtdmact3",    XSPR(31,451,217), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4163
{"mtdmada3",    XSPR(31,451,218), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4164
{"mtdmasa3",    XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4165
{"mtdmacc3",    XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4166
{"mtdmasr",     XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4167
{"mtdcr",       X(31,451),     X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {SPR, RS}},
4168
{"mtdcr.",      XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
4169
 
4170
{"dccci",       X(31,454),     XRT_MASK, PPC403|PPC440, PPCA2|PPC476,   {RA, RB}},
4171
{"dci",         X(31,454),      XRARB_MASK, PPCA2|PPC476, PPCNONE,      {CT}},
4172
 
4173
{"divdu",       XO(31,457,0,0),   XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4174
{"divdu.",      XO(31,457,0,1),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4175
 
4176
{"divwu",       XO(31,459,0,0),   XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4177
{"divwu.",      XO(31,459,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4178
 
4179
{"mtpmr",       X(31,462),      X_MASK, PPCPMR|PPCE300, PPCNONE,        {PMR, RS}},
4180
 
4181
{"mtmq",        XSPR(31,467,  0), XSPR_MASK, M601,       PPCNONE,        {RS}},
4182
{"mtxer",       XSPR(31,467,  1), XSPR_MASK, COM,       PPCNONE,        {RS}},
4183
{"mtlr",        XSPR(31,467,  8), XSPR_MASK, COM,       PPCNONE,        {RS}},
4184
{"mtctr",       XSPR(31,467,  9), XSPR_MASK, COM,       PPCNONE,        {RS}},
4185
{"mttid",       XSPR(31,467, 17), XSPR_MASK, POWER,     PPCNONE,        {RS}},
4186
{"mtdsisr",     XSPR(31,467, 18), XSPR_MASK, COM,       PPCNONE,        {RS}},
4187
{"mtdar",       XSPR(31,467, 19), XSPR_MASK, COM,       PPCNONE,        {RS}},
4188
{"mtrtcu",      XSPR(31,467, 20), XSPR_MASK, COM,       PPCNONE,        {RS}},
4189
{"mtrtcl",      XSPR(31,467, 21), XSPR_MASK, COM,       PPCNONE,        {RS}},
4190
{"mtdec",       XSPR(31,467, 22), XSPR_MASK, COM,       PPCNONE,        {RS}},
4191
{"mtsdr0",      XSPR(31,467, 24), XSPR_MASK, POWER,     PPCNONE,        {RS}},
4192
{"mtsdr1",      XSPR(31,467, 25), XSPR_MASK, COM,       PPCNONE,        {RS}},
4193
{"mtsrr0",      XSPR(31,467, 26), XSPR_MASK, COM,       PPCNONE,        {RS}},
4194
{"mtsrr1",      XSPR(31,467, 27), XSPR_MASK, COM,       PPCNONE,        {RS}},
4195
{"mtcfar",      XSPR(31,467, 28), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
4196
{"mtpid",       XSPR(31,467, 48), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4197
{"mtdecar",     XSPR(31,467, 54), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4198
{"mtcsrr0",     XSPR(31,467, 58), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4199
{"mtcsrr1",     XSPR(31,467, 59), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4200
{"mtdear",      XSPR(31,467, 61), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4201
{"mtesr",       XSPR(31,467, 62), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4202
{"mtivpr",      XSPR(31,467, 63), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4203
{"mtcmpa",      XSPR(31,467,144), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4204
{"mtcmpb",      XSPR(31,467,145), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4205
{"mtcmpc",      XSPR(31,467,146), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4206
{"mtcmpd",      XSPR(31,467,147), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4207
{"mticr",       XSPR(31,467,148), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4208
{"mtder",       XSPR(31,467,149), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4209
{"mtcounta",    XSPR(31,467,150), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4210
{"mtcountb",    XSPR(31,467,151), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4211
{"mtcmpe",      XSPR(31,467,152), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4212
{"mtcmpf",      XSPR(31,467,153), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4213
{"mtcmpg",      XSPR(31,467,154), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4214
{"mtcmph",      XSPR(31,467,155), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4215
{"mtlctrl1",    XSPR(31,467,156), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4216
{"mtlctrl2",    XSPR(31,467,157), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4217
{"mtictrl",     XSPR(31,467,158), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4218
{"mtbar",       XSPR(31,467,159), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4219
{"mtvrsave",    XSPR(31,467,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RS}},
4220
{"mtusprg0",    XSPR(31,467,256), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4221
{"mtsprg",      XSPR(31,467,256), XSPRG_MASK,PPC,       PPCNONE,        {SPRG, RS}},
4222
{"mtsprg0",     XSPR(31,467,272), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4223
{"mtsprg1",     XSPR(31,467,273), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4224
{"mtsprg2",     XSPR(31,467,274), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4225
{"mtsprg3",     XSPR(31,467,275), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4226
{"mtsprg4",     XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4227
{"mtsprg5",     XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4228
{"mtsprg6",     XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4229
{"mtsprg7",     XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4230
{"mtasr",       XSPR(31,467,280), XSPR_MASK, PPC64,     PPCNONE,        {RS}},
4231
{"mtear",       XSPR(31,467,282), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4232
{"mttbl",       XSPR(31,467,284), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4233
{"mttbu",       XSPR(31,467,285), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4234
{"mtdbsr",      XSPR(31,467,304), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4235
{"mtdbcr0",     XSPR(31,467,308), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4236
{"mtdbcr1",     XSPR(31,467,309), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4237
{"mtdbcr2",     XSPR(31,467,310), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4238
{"mtiac1",      XSPR(31,467,312), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4239
{"mtiac2",      XSPR(31,467,313), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4240
{"mtiac3",      XSPR(31,467,314), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4241
{"mtiac4",      XSPR(31,467,315), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4242
{"mtdac1",      XSPR(31,467,316), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4243
{"mtdac2",      XSPR(31,467,317), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4244
{"mtdvc1",      XSPR(31,467,318), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4245
{"mtdvc2",      XSPR(31,467,319), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4246
{"mttsr",       XSPR(31,467,336), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4247
{"mttcr",       XSPR(31,467,340), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4248
{"mtivor0",     XSPR(31,467,400), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4249
{"mtivor1",     XSPR(31,467,401), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4250
{"mtivor2",     XSPR(31,467,402), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4251
{"mtivor3",     XSPR(31,467,403), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4252
{"mtivor4",     XSPR(31,467,404), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4253
{"mtivor5",     XSPR(31,467,405), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4254
{"mtivor6",     XSPR(31,467,406), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4255
{"mtivor7",     XSPR(31,467,407), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4256
{"mtivor8",     XSPR(31,467,408), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4257
{"mtivor9",     XSPR(31,467,409), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4258
{"mtivor10",    XSPR(31,467,410), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4259
{"mtivor11",    XSPR(31,467,411), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4260
{"mtivor12",    XSPR(31,467,412), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4261
{"mtivor13",    XSPR(31,467,413), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4262
{"mtivor14",    XSPR(31,467,414), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4263
{"mtivor15",    XSPR(31,467,415), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4264
{"mtspefscr",   XSPR(31,467,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4265
{"mtbbear",     XSPR(31,467,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
4266
{"mtbbtar",     XSPR(31,467,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
4267
{"mtivor32",    XSPR(31,467,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4268
{"mtibatu",     XSPR(31,467,528), XSPRBAT_MASK, PPC,    PPCNONE,        {SPRBAT, RS}},
4269
{"mtivor33",    XSPR(31,467,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4270
{"mtibatl",     XSPR(31,467,529), XSPRBAT_MASK, PPC,    PPCNONE,        {SPRBAT, RS}},
4271
{"mtivor34",    XSPR(31,467,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4272
{"mtivor35",    XSPR(31,467,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RS}},
4273
{"mtdbatu",     XSPR(31,467,536), XSPRBAT_MASK, PPC,    PPCNONE,        {SPRBAT, RS}},
4274
{"mtdbatl",     XSPR(31,467,537), XSPRBAT_MASK, PPC,    PPCNONE,        {SPRBAT, RS}},
4275
{"mtmcsrr0",    XSPR(31,467,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4276
{"mtmcsrr1",    XSPR(31,467,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4277
{"mtmcsr",      XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4278
{"mtummcr0",    XSPR(31,467,936), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4279
{"mtupmc1",     XSPR(31,467,937), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4280
{"mtupmc2",     XSPR(31,467,938), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4281
{"mtusia",      XSPR(31,467,939), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4282
{"mtummcr1",    XSPR(31,467,940), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4283
{"mtupmc3",     XSPR(31,467,941), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4284
{"mtupmc4",     XSPR(31,467,942), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4285
{"mtzpr",       XSPR(31,467,944), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4286
{"mtpid",       XSPR(31,467,945), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4287
{"mtccr0",      XSPR(31,467,947), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4288
{"mtiac3",      XSPR(31,467,948), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4289
{"mtiac4",      XSPR(31,467,949), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4290
{"mtdvc1",      XSPR(31,467,950), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4291
{"mtdvc2",      XSPR(31,467,951), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4292
{"mtmmcr0",     XSPR(31,467,952), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4293
{"mtpmc1",      XSPR(31,467,953), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4294
{"mtsgr",       XSPR(31,467,953), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4295
{"mtdcwr",      XSPR(31,467,954), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4296
{"mtpmc2",      XSPR(31,467,954), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4297
{"mtsia",       XSPR(31,467,955), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4298
{"mtsler",      XSPR(31,467,955), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4299
{"mtmmcr1",     XSPR(31,467,956), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4300
{"mtsu0r",      XSPR(31,467,956), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4301
{"mtdbcr1",     XSPR(31,467,957), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4302
{"mtpmc3",      XSPR(31,467,957), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4303
{"mtpmc4",      XSPR(31,467,958), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4304
{"mticdbdr",    XSPR(31,467,979), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4305
{"mtesr",       XSPR(31,467,980), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4306
{"mtdear",      XSPR(31,467,981), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4307
{"mtevpr",      XSPR(31,467,982), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4308
{"mtcdbcr",     XSPR(31,467,983), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4309
{"mttsr",       XSPR(31,467,984), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4310
{"mttcr",       XSPR(31,467,986), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4311
{"mtpit",       XSPR(31,467,987), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4312
{"mttbhi",      XSPR(31,467,988), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4313
{"mttblo",      XSPR(31,467,989), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4314
{"mtsrr2",      XSPR(31,467,990), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4315
{"mtsrr3",      XSPR(31,467,991), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4316
{"mtdbsr",      XSPR(31,467,1008), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4317
{"mtdbcr0",     XSPR(31,467,1010), XSPR_MASK, PPC405,   PPCNONE,        {RS}},
4318
{"mtiac1",      XSPR(31,467,1012), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4319
{"mtiac2",      XSPR(31,467,1013), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4320
{"mtdac1",      XSPR(31,467,1014), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4321
{"mtdac2",      XSPR(31,467,1015), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4322
{"mtl2cr",      XSPR(31,467,1017), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4323
{"mtdccr",      XSPR(31,467,1018), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4324
{"mticcr",      XSPR(31,467,1019), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4325
{"mtictc",      XSPR(31,467,1019), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4326
{"mtpbl1",      XSPR(31,467,1020), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4327
{"mtthrm1",     XSPR(31,467,1020), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4328
{"mtpbu1",      XSPR(31,467,1021), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4329
{"mtthrm2",     XSPR(31,467,1021), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4330
{"mtpbl2",      XSPR(31,467,1022), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4331
{"mtthrm3",     XSPR(31,467,1022), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4332
{"mtpbu2",      XSPR(31,467,1023), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4333
{"mtspr",       X(31,467),        X_MASK,    COM,       PPCNONE,        {SPR, RS}},
4334
 
4335
{"dcbi",        X(31,470),      XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4336
 
4337
{"nand",        XRC(31,476,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4338
{"nand.",       XRC(31,476,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4339
 
4340
{"dsn",         X(31,483),      XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
4341
 
4342
{"dcread",      X(31,486),      X_MASK,  PPC403|PPC440, PPCA2|PPC476,   {RT, RA, RB}},
4343
 
4344
{"icbtls",      X(31,486),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
4345
 
4346
{"stvxl",       X(31,487),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
4347
 
4348
{"nabs",        XO(31,488,0,0),   XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4349
{"nabs.",       XO(31,488,0,1),  XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4350
 
4351
{"divd",        XO(31,489,0,0),   XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4352
{"divd.",       XO(31,489,0,1),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4353
 
4354
{"divw",        XO(31,491,0,0),   XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4355
{"divw.",       XO(31,491,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4356
 
4357
{"icbtlse",     X(31,494),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
4358
 
4359
{"slbia",       X(31,498),      0xffffffff,  PPC64,     PPCNONE,        {0}},
4360
 
4361
{"cli",         X(31,502),      XRB_MASK,    POWER,     PPCNONE,        {RT, RA}},
4362
 
4363
{"popcntd",     X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
4364
 
4365
{"cmpb",        X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
4366
 
4367
{"mcrxr",       X(31,512), XRARB_MASK|(3<<21), COM,     POWER7,         {BF}},
4368
 
4369
{"lbdx",        X(31,515),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4370
 
4371
{"bblels",      X(31,518),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
4372
 
4373
{"lvlx",        X(31,519),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4374
{"lbfcmux",     APU(31,519,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4375
 
4376
{"subfco",      XO(31,8,1,0),    XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4377
{"sfo",         XO(31,8,1,0),    XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4378
{"subco",       XO(31,8,1,0),    XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4379
{"subfco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4380
{"sfo.",        XO(31,8,1,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4381
{"subco.",      XO(31,8,1,1),   XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4382
 
4383
{"addco",       XO(31,10,1,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4384
{"ao",          XO(31,10,1,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4385
{"addco.",      XO(31,10,1,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4386
{"ao.",         XO(31,10,1,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4387
 
4388
{"clcs",        X(31,531),      XRB_MASK,    M601,      PPCNONE,        {RT, RA}},
4389
 
4390
{"ldbrx",       X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
4391
 
4392
{"lswx",        X(31,533),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
4393
{"lsx",         X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4394
 
4395
{"lwbrx",       X(31,534),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
4396
{"lbrx",        X(31,534),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4397
 
4398
{"lfsx",        X(31,535),      X_MASK,      COM,       PPCNONE,        {FRT, RA0, RB}},
4399
 
4400
{"srw",         XRC(31,536,0),   X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4401
{"sr",          XRC(31,536,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4402
{"srw.",        XRC(31,536,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4403
{"sr.",         XRC(31,536,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4404
 
4405
{"rrib",        XRC(31,537,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4406
{"rrib.",       XRC(31,537,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4407
 
4408
{"srd",         XRC(31,539,0),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4409
{"srd.",        XRC(31,539,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4410
 
4411
{"maskir",      XRC(31,541,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4412
{"maskir.",     XRC(31,541,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4413
 
4414
{"lhdx",        X(31,547),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4415
 
4416
{"bbelr",       X(31,550),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
4417
 
4418
{"lvrx",        X(31,551),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4419
{"lhfcmux",     APU(31,551,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4420
 
4421
{"subfo",       XO(31,40,1,0),   XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4422
{"subo",        XO(31,40,1,0),   XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4423
{"subfo.",      XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4424
{"subo.",       XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4425
 
4426
{"tlbsync",     X(31,566),      0xffffffff,  PPC,       PPCNONE,        {0}},
4427
 
4428
{"lfsux",       X(31,567),      X_MASK,      COM,       PPCNONE,        {FRT, RAS, RB}},
4429
 
4430
{"lwdx",        X(31,579),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4431
 
4432
{"lwfcmux",     APU(31,583,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4433
 
4434
{"lxsdx",       X(31,588),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4435
 
4436
{"mfsr",        X(31,595), XRB_MASK|(1<<20), COM32,     PPCNONE,        {RT, SR}},
4437
 
4438
{"lswi",        X(31,597),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, NB}},
4439
{"lsi",         X(31,597),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA0, NB}},
4440
 
4441
{"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC,       PPCNONE,        {0}},
4442
{"ptesync",     XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
4443
{"sync",        X(31,598),      XSYNC_MASK,  PPCCOM,    BOOKE|PPC476,   {LS}},
4444
{"msync",       X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
4445
{"dcs",         X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
4446
 
4447
{"lfdx",        X(31,599),      X_MASK,      COM,       PPCNONE,        {FRT, RA0, RB}},
4448
 
4449
{"mffgpr",      XRC(31,607,0),   XRA_MASK,    POWER6,    POWER7,         {FRT, RB}},
4450
{"lfdepx",      X(31,607),      X_MASK,   E500MC|PPCA2, PPCNONE,        {FRT, RA, RB}},
4451
 
4452
{"lddx",        X(31,611),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4453
 
4454
{"lqfcmux",     APU(31,615,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4455
 
4456
{"nego",        XO(31,104,1,0),  XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
4457
{"nego.",       XO(31,104,1,1), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
4458
 
4459
{"mulo",        XO(31,107,1,0),  XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4460
{"mulo.",       XO(31,107,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4461
 
4462
{"mfsri",       X(31,627),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4463
 
4464
{"dclst",       X(31,630),      XRB_MASK,    PWRCOM,    PPCNONE,        {RS, RA}},
4465
 
4466
{"lfdux",       X(31,631),      X_MASK,      COM,       PPCNONE,        {FRT, RAS, RB}},
4467
 
4468
{"stbdx",       X(31,643),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4469
 
4470
{"stvlx",       X(31,647),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4471
{"stbfcmux",    APU(31,647,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4472
 
4473
{"subfeo",      XO(31,136,1,0),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4474
{"sfeo",        XO(31,136,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4475
{"subfeo.",     XO(31,136,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4476
{"sfeo.",       XO(31,136,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4477
 
4478
{"addeo",       XO(31,138,1,0),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4479
{"aeo",         XO(31,138,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4480
{"addeo.",      XO(31,138,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4481
{"aeo.",        XO(31,138,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4482
 
4483
{"mfsrin",      X(31,659),      XRA_MASK,    PPC32,     PPCNONE,        {RT, RB}},
4484
 
4485
{"stdbrx",      X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
4486
 
4487
{"stswx",       X(31,661),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
4488
{"stsx",        X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4489
 
4490
{"stwbrx",      X(31,662),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
4491
{"stbrx",       X(31,662),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4492
 
4493
{"stfsx",       X(31,663),      X_MASK,      COM,       PPCNONE,        {FRS, RA0, RB}},
4494
 
4495
{"srq",         XRC(31,664,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4496
{"srq.",        XRC(31,664,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4497
 
4498
{"sre",         XRC(31,665,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4499
{"sre.",        XRC(31,665,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4500
 
4501
{"sthdx",       X(31,675),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4502
 
4503
{"stvrx",       X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4504
{"sthfcmux",    APU(31,679,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4505
 
4506
{"wclrone",     XOPL2(31,694,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
4507
{"wclrall",     X(31,694),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
4508
{"wclr",        X(31,694),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
4509
 
4510
{"stbcx.",      XRC(31,694,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
4511
 
4512
{"stfsux",      X(31,695),      X_MASK,      COM,       PPCNONE,        {FRS, RAS, RB}},
4513
 
4514
{"sriq",        XRC(31,696,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4515
{"sriq.",       XRC(31,696,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4516
 
4517
{"stwdx",       X(31,707),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4518
 
4519
{"stwfcmux",    APU(31,711,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4520
 
4521
{"stxsdx",      X(31,716),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4522
 
4523
{"subfzeo",     XO(31,200,1,0),  XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4524
{"sfzeo",       XO(31,200,1,0),  XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4525
{"subfzeo.",    XO(31,200,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4526
{"sfzeo.",      XO(31,200,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4527
 
4528
{"addzeo",      XO(31,202,1,0),  XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4529
{"azeo",        XO(31,202,1,0),  XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4530
{"addzeo.",     XO(31,202,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4531
{"azeo.",       XO(31,202,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4532
 
4533
{"stswi",       X(31,725),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, NB}},
4534
{"stsi",        X(31,725),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, NB}},
4535
 
4536
{"sthcx.",      XRC(31,726,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
4537
 
4538
{"stfdx",       X(31,727),      X_MASK,      COM,       PPCNONE,        {FRS, RA0, RB}},
4539
 
4540
{"srlq",        XRC(31,728,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4541
{"srlq.",       XRC(31,728,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4542
 
4543
{"sreq",        XRC(31,729,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4544
{"sreq.",       XRC(31,729,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4545
 
4546
{"mftgpr",      XRC(31,735,0),   XRA_MASK,    POWER6,    POWER7,         {RT, FRB}},
4547
{"stfdepx",     X(31,735),      X_MASK,   E500MC|PPCA2, PPCNONE,        {FRS, RA, RB}},
4548
 
4549
{"stddx",       X(31,739),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4550
 
4551
{"stqfcmux",    APU(31,743,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4552
 
4553
{"subfmeo",     XO(31,232,1,0),  XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4554
{"sfmeo",       XO(31,232,1,0),  XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4555
{"subfmeo.",    XO(31,232,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4556
{"sfmeo.",      XO(31,232,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4557
 
4558
{"mulldo",      XO(31,233,1,0),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4559
{"mulldo.",     XO(31,233,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4560
 
4561
{"addmeo",      XO(31,234,1,0),  XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4562
{"ameo",        XO(31,234,1,0),  XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4563
{"addmeo.",     XO(31,234,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4564
{"ameo.",       XO(31,234,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4565
 
4566
{"mullwo",      XO(31,235,1,0),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4567
{"mulso",       XO(31,235,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4568
{"mullwo.",     XO(31,235,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4569
{"mulso.",      XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4570
 
4571
{"dcba",        X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
4572
{"dcbal",       XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
4573
 
4574
{"stfdux",      X(31,759),      X_MASK,      COM,       PPCNONE,        {FRS, RAS, RB}},
4575
 
4576
{"srliq",       XRC(31,760,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4577
{"srliq.",      XRC(31,760,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4578
 
4579
{"lvlxl",       X(31,775),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4580
{"ldfcmux",     APU(31,775,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4581
 
4582
{"dozo",        XO(31,264,1,0),  XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4583
{"dozo.",       XO(31,264,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4584
 
4585
{"addo",        XO(31,266,1,0),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4586
{"caxo",        XO(31,266,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4587
{"addo.",       XO(31,266,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4588
{"caxo.",       XO(31,266,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4589
 
4590
{"lxvw4x",      X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4591
 
4592
{"tlbivax",     X(31,786),      XRT_MASK,  BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
4593
 
4594
{"lwzcix",      X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4595
 
4596
{"lhbrx",       X(31,790),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
4597
 
4598
{"lfdpx",       X(31,791),      X_MASK,      POWER6,    POWER7,         {FRT, RA, RB}},
4599
{"lfqx",        X(31,791),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
4600
 
4601
{"sraw",        XRC(31,792,0),   X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4602
{"sra",         XRC(31,792,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4603
{"sraw.",       XRC(31,792,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4604
{"sra.",        XRC(31,792,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4605
 
4606
{"srad",        XRC(31,794,0),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4607
{"srad.",       XRC(31,794,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4608
 
4609
{"lfddx",       X(31,803),      X_MASK,      E500MC,    PPCNONE,        {FRT, RA, RB}},
4610
 
4611
{"lvrxl",       X(31,807),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4612
 
4613
{"rac",         X(31,818),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4614
 
4615
{"erativax",    X(31,819),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA0, RB}},
4616
 
4617
{"lhzcix",      X(31,821),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4618
 
4619
{"dss",         XDSS(31,822,0),  XDSS_MASK,   PPCVEC,    PPCNONE,        {STRM}},
4620
 
4621
{"lfqux",       X(31,823),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
4622
 
4623
{"srawi",       XRC(31,824,0),   X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH}},
4624
{"srai",        XRC(31,824,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
4625
{"srawi.",      XRC(31,824,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH}},
4626
{"srai.",       XRC(31,824,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
4627
 
4628
{"sradi",       XS(31,413,0),    XS_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6}},
4629
{"sradi.",      XS(31,413,1),   XS_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6}},
4630
 
4631
{"divo",        XO(31,331,1,0),  XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4632
{"divo.",       XO(31,331,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4633
 
4634
{"lxvd2x",      X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4635
 
4636
{"tlbsrx.",     XRC(31,850,1),  XRT_MASK,    PPCA2,     PPCNONE,        {RA, RB}},
4637
 
4638
{"slbmfev",     X(31,851),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
4639
 
4640
{"lbzcix",      X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4641
 
4642
{"eieio",       X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
4643
{"mbar",        X(31,854),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {MO}},
4644
{"eieio",       X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
4645
 
4646
{"lfiwax",      X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
4647
 
4648
{"abso",        XO(31,360,1,0),  XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4649
{"abso.",       XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4650
 
4651
{"divso",       XO(31,363,1,0),  XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4652
{"divso.",      XO(31,363,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4653
 
4654
{"ldcix",       X(31,885),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4655
 
4656
{"lfiwzx",      X(31,887),      X_MASK,   POWER7|PPCA2, PPCNONE,        {FRT, RA0, RB}},
4657
 
4658
{"stvlxl",      X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4659
{"stdfcmux",    APU(31,903,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4660
 
4661
{"divdeuo",     XO(31,393,1,0),  XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4662
{"divdeuo.",    XO(31,393,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4663
{"divweuo",     XO(31,395,1,0),  XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4664
{"divweuo.",    XO(31,395,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4665
 
4666
{"stxvw4x",     X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4667
 
4668
{"tlbsx",       XRC(31,914,0),   X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
4669
{"tlbsx.",      XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
4670
 
4671
{"slbmfee",     X(31,915),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
4672
 
4673
{"stwcix",      X(31,917),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4674
 
4675
{"sthbrx",      X(31,918),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
4676
 
4677
{"stfdpx",      X(31,919),      X_MASK,      POWER6,    PPCNONE,        {FRS, RA, RB}},
4678
{"stfqx",       X(31,919),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
4679
 
4680
{"sraq",        XRC(31,920,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4681
{"sraq.",       XRC(31,920,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4682
 
4683
{"srea",        XRC(31,921,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4684
{"srea.",       XRC(31,921,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4685
 
4686
{"extsh",       XRC(31,922,0),   XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
4687
{"exts",        XRC(31,922,0),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4688
{"extsh.",      XRC(31,922,1),  XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
4689
{"exts.",       XRC(31,922,1),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4690
 
4691
{"stfddx",      X(31,931),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
4692
 
4693
{"stvrxl",      X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4694
 
4695
{"divdeo",      XO(31,425,1,0),  XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4696
{"divdeo.",     XO(31,425,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4697
{"divweo",      XO(31,427,1,0),  XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4698
{"divweo.",     XO(31,427,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4699
 
4700
{"tlbrehi",     XTLB(31,946,0),  XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
4701
{"tlbrelo",     XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
4702
{"tlbre",       X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
4703
 
4704
{"sthcix",      X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4705
 
4706
{"stfqux",      X(31,951),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
4707
 
4708
{"sraiq",       XRC(31,952,0),   X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4709
{"sraiq.",      XRC(31,952,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4710
 
4711
{"extsb",       XRC(31,954,0),   XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
4712
{"extsb.",      XRC(31,954,1),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
4713
 
4714
{"iccci",       X(31,966),     XRT_MASK, PPC403|PPC440, PPC476,         {RA, RB}},
4715
{"ici",         X(31,966),      XRARB_MASK,  PPCA2|PPC476, PPCNONE,     {CT}},
4716
 
4717
{"divduo",      XO(31,457,1,0),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4718
{"divduo.",     XO(31,457,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4719
 
4720
{"divwuo",      XO(31,459,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4721
{"divwuo.",     XO(31,459,1,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4722
 
4723
{"stxvd2x",     X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4724
 
4725
{"tlbld",       X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
4726
{"tlbwehi",     XTLB(31,978,0),  XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
4727
{"tlbwelo",     XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
4728
{"tlbwe",       X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
4729
 
4730
{"stbcix",      X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4731
 
4732
{"icbi",        X(31,982),      XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4733
 
4734
{"stfiwx",      X(31,983),      X_MASK,      PPC,       PPCNONE,        {FRS, RA0, RB}},
4735
 
4736
{"extsw",       XRC(31,986,0),  XRB_MASK,    PPC64,      PPCNONE,        {RA, RS}},
4737
{"extsw.",      XRC(31,986,1),  XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
4738
 
4739
{"icbiep",      XRT(31,991,0),   XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
4740
 
4741
{"icread",      X(31,998),     XRT_MASK, PPC403|PPC440|PPC476, PPCNONE, {RA, RB}},
4742
 
4743
{"nabso",       XO(31,488,1,0),  XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4744
{"nabso.",      XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4745
 
4746
{"divdo",       XO(31,489,1,0),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4747
{"divdo.",      XO(31,489,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4748
 
4749
{"divwo",       XO(31,491,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4750
{"divwo.",      XO(31,491,1,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4751
 
4752
{"tlbli",       X(31,1010),     XRTRA_MASK,  PPC,       PPCNONE,        {RB}},
4753
 
4754
{"stdcix",      X(31,1013),     X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4755
 
4756
{"dcbz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4757
{"dclz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4758
 
4759
{"dcbzep",      XRT(31,1023,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
4760
 
4761
{"dcbzl",       XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA, RB}},
4762
 
4763
{"cctpl",       0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4764
{"cctpm",       0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4765
{"cctph",       0x7c631b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4766
 
4767
{"dstt",        XDSS(31,342,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4768
{"dststt",      XDSS(31,374,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4769
{"dssall",      XDSS(31,822,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {0}},
4770
 
4771
{"db8cyc",      0x7f9ce378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4772
{"db10cyc",     0x7fbdeb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4773
{"db12cyc",     0x7fdef378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4774
{"db16cyc",     0x7ffffb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4775
 
4776
{"lwz",         OP(32),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
4777
{"l",           OP(32),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4778
 
4779
{"lwzu",        OP(33),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAL}},
4780
{"lu",          OP(33),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4781
 
4782
{"lbz",         OP(34),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4783
 
4784
{"lbzu",        OP(35),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4785
 
4786
{"stw",         OP(36),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
4787
{"st",          OP(36),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4788
 
4789
{"stwu",        OP(37),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RAS}},
4790
{"stu",         OP(37),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4791
 
4792
{"stb",         OP(38),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
4793
 
4794
{"stbu",        OP(39),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
4795
 
4796
{"lhz",         OP(40),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4797
 
4798
{"lhzu",        OP(41),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4799
 
4800
{"lha",         OP(42),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4801
 
4802
{"lhau",        OP(43),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4803
 
4804
{"sth",         OP(44),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
4805
 
4806
{"sthu",        OP(45),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
4807
 
4808
{"lmw",         OP(46),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAM}},
4809
{"lm",          OP(46),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4810
 
4811
{"stmw",        OP(47),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
4812
{"stm",         OP(47),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4813
 
4814
{"lfs",         OP(48),         OP_MASK,     COM,       PPCNONE,        {FRT, D, RA0}},
4815
 
4816
{"lfsu",        OP(49),         OP_MASK,     COM,       PPCNONE,        {FRT, D, RAS}},
4817
 
4818
{"lfd",         OP(50),         OP_MASK,     COM,       PPCNONE,        {FRT, D, RA0}},
4819
 
4820
{"lfdu",        OP(51),         OP_MASK,     COM,       PPCNONE,        {FRT, D, RAS}},
4821
 
4822
{"stfs",        OP(52),         OP_MASK,     COM,       PPCNONE,        {FRS, D, RA0}},
4823
 
4824
{"stfsu",       OP(53),         OP_MASK,     COM,       PPCNONE,        {FRS, D, RAS}},
4825
 
4826
{"stfd",        OP(54),         OP_MASK,     COM,       PPCNONE,        {FRS, D, RA0}},
4827
 
4828
{"stfdu",       OP(55),         OP_MASK,     COM,       PPCNONE,        {FRS, D, RAS}},
4829
 
4830
{"lq",          OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
4831
{"psq_l",       OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
4832
{"lfq",         OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
4833
 
4834
{"lfdp",        OP(57),         OP_MASK,     POWER6,    POWER7,         {FRT, D, RA0}},
4835
{"psq_lu",      OP(57),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
4836
{"lfqu",        OP(57),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
4837
 
4838
{"ld",          DSO(58,0),       DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
4839
{"ldu",         DSO(58,1),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RAL}},
4840
{"lwa",         DSO(58,2),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
4841
 
4842
{"dadd",        XRC(59,2,0),     X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4843
{"dadd.",       XRC(59,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4844
 
4845
{"dqua",        ZRC(59,3,0),     Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
4846
{"dqua.",       ZRC(59,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
4847
 
4848
{"fdivs",       A(59,18,0),      AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4849
{"fdivs.",      A(59,18,1),     AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4850
 
4851
{"fsubs",       A(59,20,0),      AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4852
{"fsubs.",      A(59,20,1),     AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4853
 
4854
{"fadds",       A(59,21,0),      AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4855
{"fadds.",      A(59,21,1),     AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4856
 
4857
{"fsqrts",      A(59,22,0),    AFRAFRC_MASK, PPC,        PPCNONE,        {FRT, FRB}},
4858
{"fsqrts.",     A(59,22,1),    AFRAFRC_MASK, PPC,       PPCNONE,        {FRT, FRB}},
4859
 
4860
{"fres",        A(59,24,0),   AFRAFRC_MASK,  POWER7,     PPCNONE,        {FRT, FRB}},
4861
{"fres",        A(59,24,0),   AFRALFRC_MASK, PPC,        POWER7,         {FRT, FRB, A_L}},
4862
{"fres.",       A(59,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4863
{"fres.",       A(59,24,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
4864
 
4865
{"fmuls",       A(59,25,0),      AFRB_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRC}},
4866
{"fmuls.",      A(59,25,1),     AFRB_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRC}},
4867
 
4868
{"frsqrtes",    A(59,26,0),   AFRAFRC_MASK,  POWER7,     PPCNONE,        {FRT, FRB}},
4869
{"frsqrtes",    A(59,26,0),   AFRALFRC_MASK, POWER5,     POWER7,         {FRT, FRB, A_L}},
4870
{"frsqrtes.",   A(59,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4871
{"frsqrtes.",   A(59,26,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
4872
 
4873
{"fmsubs",      A(59,28,0),      A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4874
{"fmsubs.",     A(59,28,1),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4875
 
4876
{"fmadds",      A(59,29,0),      A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4877
{"fmadds.",     A(59,29,1),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4878
 
4879
{"fnmsubs",     A(59,30,0),      A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4880
{"fnmsubs.",    A(59,30,1),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4881
 
4882
{"fnmadds",     A(59,31,0),      A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4883
{"fnmadds.",    A(59,31,1),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4884
 
4885
{"dmul",        XRC(59,34,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4886
{"dmul.",       XRC(59,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4887
 
4888
{"drrnd",       ZRC(59,35,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
4889
{"drrnd.",      ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
4890
 
4891
{"dscli",       ZRC(59,66,0),    Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4892
{"dscli.",      ZRC(59,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4893
 
4894
{"dquai",       ZRC(59,67,0),    Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
4895
{"dquai.",      ZRC(59,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
4896
 
4897
{"dscri",       ZRC(59,98,0),    Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4898
{"dscri.",      ZRC(59,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4899
 
4900
{"drintx",      ZRC(59,99,0),    Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4901
{"drintx.",     ZRC(59,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4902
 
4903
{"dcmpo",       X(59,130),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4904
 
4905
{"dtstex",      X(59,162),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4906
{"dtstdc",      Z(59,194),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DCM}},
4907
{"dtstdg",      Z(59,226),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DGM}},
4908
 
4909
{"drintn",      ZRC(59,227,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4910
{"drintn.",     ZRC(59,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4911
 
4912
{"dctdp",       XRC(59,258,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4913
{"dctdp.",      XRC(59,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4914
 
4915
{"dctfix",      XRC(59,290,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4916
{"dctfix.",     XRC(59,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4917
 
4918
{"ddedpd",      XRC(59,322,0),   X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
4919
{"ddedpd.",     XRC(59,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
4920
 
4921
{"dxex",        XRC(59,354,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4922
{"dxex.",       XRC(59,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4923
 
4924
{"dsub",        XRC(59,514,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4925
{"dsub.",       XRC(59,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4926
 
4927
{"ddiv",        XRC(59,546,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4928
{"ddiv.",       XRC(59,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4929
 
4930
{"dcmpu",       X(59,642),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4931
 
4932
{"dtstsf",      X(59,674),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4933
 
4934
{"drsp",        XRC(59,770,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4935
{"drsp.",       XRC(59,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4936
 
4937
{"dcffix",      XRC(59,802,0), X_MASK|FRA_MASK, POWER7,  PPCNONE,        {FRT, FRB}},
4938
{"dcffix.",     XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
4939
 
4940
{"denbcd",      XRC(59,834,0),   X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
4941
{"denbcd.",     XRC(59,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
4942
 
4943
{"fcfids",      XRC(59,846,0),   XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4944
{"fcfids.",     XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4945
 
4946
{"diex",        XRC(59,866,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4947
{"diex.",       XRC(59,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4948
 
4949
{"fcfidus",     XRC(59,974,0),   XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4950
{"fcfidus.",    XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4951
 
4952
{"xxsldwi",     XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6, SHW}},
4953
{"xxsel",       XX4(60,3),      XX4_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6, XC6}},
4954
{"xxspltd",     XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6S, DMEX}},
4955
{"xxmrghd",     XX3(60,10),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4956
{"xxswapd",     XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
4957
{"xxmrgld",     XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4958
{"xxpermdi",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6, DM}},
4959
{"xxmrghw",     XX3(60,18),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4960
{"xsadddp",     XX3(60,32),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4961
{"xsmaddadp",   XX3(60,33),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4962
{"xscmpudp",    XX3(60,35),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
4963
{"xssubdp",     XX3(60,40),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4964
{"xsmaddmdp",   XX3(60,41),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4965
{"xscmpodp",    XX3(60,43),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
4966
{"xsmuldp",     XX3(60,48),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4967
{"xsmsubadp",   XX3(60,49),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4968
{"xxmrglw",     XX3(60,50),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4969
{"xsdivdp",     XX3(60,56),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4970
{"xsmsubmdp",   XX3(60,57),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4971
{"xstdivdp",    XX3(60,61),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
4972
{"xvaddsp",     XX3(60,64),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4973
{"xvmaddasp",   XX3(60,65),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4974
{"xvcmpeqsp",   XX3RC(60,67,0),  XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4975
{"xvcmpeqsp.",  XX3RC(60,67,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4976
{"xvsubsp",     XX3(60,72),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4977
{"xscvdpuxws",  XX2(60,72),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
4978
{"xvmaddmsp",   XX3(60,73),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4979
{"xsrdpi",      XX2(60,73),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
4980
{"xsrsqrtedp",  XX2(60,74),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
4981
{"xssqrtdp",    XX2(60,75),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
4982
{"xvcmpgtsp",   XX3RC(60,75,0),  XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4983
{"xvcmpgtsp.",  XX3RC(60,75,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4984
{"xvmulsp",     XX3(60,80),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4985
{"xvmsubasp",   XX3(60,81),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4986
{"xvcmpgesp",   XX3RC(60,83,0),  XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4987
{"xvcmpgesp.",  XX3RC(60,83,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4988
{"xvdivsp",     XX3(60,88),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4989
{"xscvdpsxws",  XX2(60,88),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
4990
{"xvmsubmsp",   XX3(60,89),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4991
{"xsrdpiz",     XX2(60,89),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
4992
{"xsredp",      XX2(60,90),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
4993
{"xvtdivsp",    XX3(60,93),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
4994
{"xvadddp",     XX3(60,96),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4995
{"xvmaddadp",   XX3(60,97),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4996
{"xvcmpeqdp",   XX3RC(60,99,0),  XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4997
{"xvcmpeqdp.",  XX3RC(60,99,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4998
{"xvsubdp",     XX3(60,104),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4999
{"xvmaddmdp",   XX3(60,105),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5000
{"xsrdpip",     XX2(60,105),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5001
{"xstsqrtdp",   XX2(60,106),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5002
{"xsrdpic",     XX2(60,107),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5003
{"xvcmpgtdp",   XX3RC(60,107,0), XX3_MASK,   PPCVSX,     PPCNONE,        {XT6, XA6, XB6}},
5004
{"xvcmpgtdp.",  XX3RC(60,107,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5005
{"xvmuldp",     XX3(60,112),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5006
{"xvmsubadp",   XX3(60,113),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5007
{"xvcmpgedp",   XX3RC(60,115,0), XX3_MASK,   PPCVSX,     PPCNONE,        {XT6, XA6, XB6}},
5008
{"xvcmpgedp.",  XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5009
{"xvdivdp",     XX3(60,120),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5010
{"xvmsubmdp",   XX3(60,121),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5011
{"xsrdpim",     XX2(60,121),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5012
{"xvtdivdp",    XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5013
{"xxland",      XX3(60,130),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5014
{"xvcvspuxws",  XX2(60,136),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5015
{"xvrspi",      XX2(60,137),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5016
{"xxlandc",     XX3(60,138),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5017
{"xvrsqrtesp",  XX2(60,138),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5018
{"xvsqrtsp",    XX2(60,139),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5019
{"xxlor",       XX3(60,146),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5020
{"xvcvspsxws",  XX2(60,152),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5021
{"xvrspiz",     XX2(60,153),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5022
{"xxlxor",      XX3(60,154),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5023
{"xvresp",      XX2(60,154),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5024
{"xsmaxdp",     XX3(60,160),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5025
{"xsnmaddadp",  XX3(60,161),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5026
{"xxlnor",      XX3(60,162),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5027
{"xxspltw",     XX2(60,164),    XX2UIM_MASK, PPCVSX,    PPCNONE,        {XT6, XB6, UIM}},
5028
{"xsmindp",     XX3(60,168),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5029
{"xvcvuxwsp",   XX2(60,168),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5030
{"xsnmaddmdp",  XX3(60,169),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5031
{"xvrspip",     XX2(60,169),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5032
{"xvtsqrtsp",   XX2(60,170),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5033
{"xvrspic",     XX2(60,171),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5034
{"xscpsgndp",   XX3(60,176),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5035
{"xsnmsubadp",  XX3(60,177),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5036
{"xvcvsxwsp",   XX2(60,184),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5037
{"xsnmsubmdp",  XX3(60,185),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5038
{"xvrspim",     XX2(60,185),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5039
{"xvmaxsp",     XX3(60,192),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5040
{"xvnmaddasp",  XX3(60,193),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5041
{"xvminsp",     XX3(60,200),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5042
{"xvcvdpuxws",  XX2(60,200),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5043
{"xvnmaddmsp",  XX3(60,201),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5044
{"xvrdpi",      XX2(60,201),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5045
{"xvrsqrtedp",  XX2(60,202),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5046
{"xvsqrtdp",    XX2(60,203),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5047
{"xvmovsp",     XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5048
{"xvcpsgnsp",   XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5049
{"xvnmsubasp",  XX3(60,209),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5050
{"xvcvdpsxws",  XX2(60,216),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5051
{"xvnmsubmsp",  XX3(60,217),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5052
{"xvrdpiz",     XX2(60,217),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5053
{"xvredp",      XX2(60,218),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5054
{"xvmaxdp",     XX3(60,224),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5055
{"xvnmaddadp",  XX3(60,225),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5056
{"xvmindp",     XX3(60,232),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5057
{"xvnmaddmdp",  XX3(60,233),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5058
{"xvcvuxwdp",   XX2(60,232),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5059
{"xvrdpip",     XX2(60,233),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5060
{"xvtsqrtdp",   XX2(60,234),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5061
{"xvrdpic",     XX2(60,235),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5062
{"xvmovdp",     XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5063
{"xvcpsgndp",   XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5064
{"xvnmsubadp",  XX3(60,241),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5065
{"xvcvsxwdp",   XX2(60,248),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5066
{"xvnmsubmdp",  XX3(60,249),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5067
{"xvrdpim",     XX2(60,249),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5068
{"xscvdpsp",    XX2(60,265),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5069
{"xscvdpuxds",  XX2(60,328),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5070
{"xscvspdp",    XX2(60,329),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5071
{"xscvdpsxds",  XX2(60,344),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5072
{"xsabsdp",     XX2(60,345),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5073
{"xscvuxddp",   XX2(60,360),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5074
{"xsnabsdp",    XX2(60,361),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5075
{"xscvsxddp",   XX2(60,376),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5076
{"xsnegdp",     XX2(60,377),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5077
{"xvcvspuxds",  XX2(60,392),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5078
{"xvcvdpsp",    XX2(60,393),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5079
{"xvcvspsxds",  XX2(60,408),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5080
{"xvabssp",     XX2(60,409),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5081
{"xvcvuxdsp",   XX2(60,424),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5082
{"xvnabssp",    XX2(60,425),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5083
{"xvcvsxdsp",   XX2(60,440),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5084
{"xvnegsp",     XX2(60,441),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5085
{"xvcvdpuxds",  XX2(60,456),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5086
{"xvcvspdp",    XX2(60,457),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5087
{"xvcvdpsxds",  XX2(60,472),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5088
{"xvabsdp",     XX2(60,473),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5089
{"xvcvuxddp",   XX2(60,488),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5090
{"xvnabsdp",    XX2(60,489),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5091
{"xvcvsxddp",   XX2(60,504),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5092
{"xvnegdp",     XX2(60,505),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5093
 
5094
{"psq_st",      OP(60),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5095
{"stfq",        OP(60),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5096
 
5097
{"stfdp",       OP(61),         OP_MASK,     POWER6,    PPCNONE,        {FRT, D, RA0}},
5098
{"psq_stu",     OP(61),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5099
{"stfqu",       OP(61),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5100
 
5101
{"std",         DSO(62,0),       DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
5102
{"stdu",        DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
5103
{"stq",         DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
5104
 
5105
{"fcmpu",       X(63,0),     X_MASK|(3<<21), COM,        PPCNONE,        {BF, FRA, FRB}},
5106
 
5107
{"daddq",       XRC(63,2,0),     X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5108
{"daddq.",      XRC(63,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5109
 
5110
{"dquaq",       ZRC(63,3,0),     Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5111
{"dquaq.",      ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5112
 
5113
{"fcpsgn",      XRC(63,8,0),     X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5114
{"fcpsgn.",     XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5115
 
5116
{"frsp",        XRC(63,12,0),    XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5117
{"frsp.",       XRC(63,12,1),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5118
 
5119
{"fctiw",       XRC(63,14,0),    XRA_MASK,    PPCCOM,    PPCNONE,        {FRT, FRB}},
5120
{"fcir",        XRC(63,14,0),    XRA_MASK,    POWER2,    PPCNONE,        {FRT, FRB}},
5121
{"fctiw.",      XRC(63,14,1),   XRA_MASK,    PPCCOM,    PPCNONE,        {FRT, FRB}},
5122
{"fcir.",       XRC(63,14,1),   XRA_MASK,    POWER2,    PPCNONE,        {FRT, FRB}},
5123
 
5124
{"fctiwz",      XRC(63,15,0),    XRA_MASK,    PPCCOM,    PPCNONE,        {FRT, FRB}},
5125
{"fcirz",       XRC(63,15,0),    XRA_MASK,    POWER2,    PPCNONE,        {FRT, FRB}},
5126
{"fctiwz.",     XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCNONE,        {FRT, FRB}},
5127
{"fcirz.",      XRC(63,15,1),   XRA_MASK,    POWER2,    PPCNONE,        {FRT, FRB}},
5128
 
5129
{"fdiv",        A(63,18,0),      AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5130
{"fd",          A(63,18,0),      AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5131
{"fdiv.",       A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5132
{"fd.",         A(63,18,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5133
 
5134
{"fsub",        A(63,20,0),      AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5135
{"fs",          A(63,20,0),      AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5136
{"fsub.",       A(63,20,1),     AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5137
{"fs.",         A(63,20,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5138
 
5139
{"fadd",        A(63,21,0),      AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5140
{"fa",          A(63,21,0),      AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5141
{"fadd.",       A(63,21,1),     AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5142
{"fa.",         A(63,21,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5143
 
5144
{"fsqrt",       A(63,22,0),    AFRAFRC_MASK, PPCPWR2,    PPCNONE,        {FRT, FRB}},
5145
{"fsqrt.",      A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   PPCNONE,        {FRT, FRB}},
5146
 
5147
{"fsel",        A(63,23,0),      A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
5148
{"fsel.",       A(63,23,1),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
5149
 
5150
{"fre",         A(63,24,0),   AFRAFRC_MASK,  POWER7,     PPCNONE,        {FRT, FRB}},
5151
{"fre",         A(63,24,0),   AFRALFRC_MASK, POWER5,     POWER7,         {FRT, FRB, A_L}},
5152
{"fre.",        A(63,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5153
{"fre.",        A(63,24,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5154
 
5155
{"fmul",        A(63,25,0),      AFRB_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRC}},
5156
{"fm",          A(63,25,0),      AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
5157
{"fmul.",       A(63,25,1),     AFRB_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRC}},
5158
{"fm.",         A(63,25,1),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
5159
 
5160
{"frsqrte",     A(63,26,0),   AFRAFRC_MASK,  POWER7,     PPCNONE,        {FRT, FRB}},
5161
{"frsqrte",     A(63,26,0),   AFRALFRC_MASK, PPC,        POWER7,         {FRT, FRB, A_L}},
5162
{"frsqrte.",    A(63,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5163
{"frsqrte.",    A(63,26,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5164
 
5165
{"fmsub",       A(63,28,0),      A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5166
{"fms",         A(63,28,0),      A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5167
{"fmsub.",      A(63,28,1),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5168
{"fms.",        A(63,28,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5169
 
5170
{"fmadd",       A(63,29,0),      A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5171
{"fma",         A(63,29,0),      A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5172
{"fmadd.",      A(63,29,1),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5173
{"fma.",        A(63,29,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5174
 
5175
{"fnmsub",      A(63,30,0),      A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5176
{"fnms",        A(63,30,0),      A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5177
{"fnmsub.",     A(63,30,1),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5178
{"fnms.",       A(63,30,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5179
 
5180
{"fnmadd",      A(63,31,0),      A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5181
{"fnma",        A(63,31,0),      A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5182
{"fnmadd.",     A(63,31,1),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5183
{"fnma.",       A(63,31,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5184
 
5185
{"fcmpo",       X(63,32),    X_MASK|(3<<21), COM,       PPCNONE,        {BF, FRA, FRB}},
5186
 
5187
{"dmulq",       XRC(63,34,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5188
{"dmulq.",      XRC(63,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5189
 
5190
{"drrndq",      ZRC(63,35,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5191
{"drrndq.",     ZRC(63,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5192
 
5193
{"mtfsb1",      XRC(63,38,0),    XRARB_MASK,  COM,       PPCNONE,        {BT}},
5194
{"mtfsb1.",     XRC(63,38,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5195
 
5196
{"fneg",        XRC(63,40,0),    XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5197
{"fneg.",       XRC(63,40,1),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5198
 
5199
{"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
5200
 
5201
{"dscliq",      ZRC(63,66,0),    Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5202
{"dscliq.",     ZRC(63,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5203
 
5204
{"dquaiq",      ZRC(63,67,0),    Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT, FRB, RMC}},
5205
{"dquaiq.",     ZRC(63,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT, FRB, RMC}},
5206
 
5207
{"mtfsb0",      XRC(63,70,0),    XRARB_MASK,  COM,       PPCNONE,        {BT}},
5208
{"mtfsb0.",     XRC(63,70,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5209
 
5210
{"fmr",         XRC(63,72,0),    XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5211
{"fmr.",        XRC(63,72,1),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5212
 
5213
{"dscriq",      ZRC(63,98,0),    Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5214
{"dscriq.",     ZRC(63,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5215
 
5216
{"drintxq",     ZRC(63,99,0),    Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5217
{"drintxq.",    ZRC(63,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5218
 
5219
{"ftdiv",       X(63,128),   X_MASK|(3<<21), POWER7,    PPCNONE,        {BF, FRA, FRB}},
5220
 
5221
{"dcmpoq",      X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5222
 
5223
{"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5224
{"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
5225
{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5226
{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
5227
 
5228
{"fnabs",       XRC(63,136,0),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5229
{"fnabs.",      XRC(63,136,1),  XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5230
 
5231
{"fctiwu",      XRC(63,142,0),   XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5232
{"fctiwu.",     XRC(63,142,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5233
{"fctiwuz",     XRC(63,143,0),   XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5234
{"fctiwuz.",    XRC(63,143,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5235
 
5236
{"ftsqrt",      X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE,    {BF, FRB}},
5237
 
5238
{"dtstexq",     X(63,162),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5239
{"dtstdcq",     Z(63,194),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRA, DCM}},
5240
{"dtstdgq",     Z(63,226),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRA, DGM}},
5241
 
5242
{"drintnq",     ZRC(63,227,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5243
{"drintnq.",    ZRC(63,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5244
 
5245
{"dctqpq",      XRC(63,258,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5246
{"dctqpq.",     XRC(63,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5247
 
5248
{"fabs",        XRC(63,264,0),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5249
{"fabs.",       XRC(63,264,1),  XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5250
 
5251
{"dctfixq",     XRC(63,290,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5252
{"dctfixq.",    XRC(63,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5253
 
5254
{"ddedpdq",     XRC(63,322,0),   X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5255
{"ddedpdq.",    XRC(63,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5256
 
5257
{"dxexq",       XRC(63,354,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5258
{"dxexq.",      XRC(63,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5259
 
5260
{"frin",        XRC(63,392,0),   XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5261
{"frin.",       XRC(63,392,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5262
{"friz",        XRC(63,424,0),   XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5263
{"friz.",       XRC(63,424,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5264
{"frip",        XRC(63,456,0),   XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5265
{"frip.",       XRC(63,456,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5266
{"frim",        XRC(63,488,0),   XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5267
{"frim.",       XRC(63,488,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5268
 
5269
{"dsubq",       XRC(63,514,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5270
{"dsubq.",      XRC(63,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5271
 
5272
{"ddivq",       XRC(63,546,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5273
{"ddivq.",      XRC(63,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5274
 
5275
{"mffs",        XRC(63,583,0),   XRARB_MASK,  COM,       PPCNONE,        {FRT}},
5276
{"mffs.",       XRC(63,583,1),  XRARB_MASK,  COM,       PPCNONE,        {FRT}},
5277
 
5278
{"dcmpuq",      X(63,642),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5279
 
5280
{"dtstsfq",     X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5281
 
5282
{"mtfsf",       XFL(63,711,0),   XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
5283
{"mtfsf",       XFL(63,711,0),   XFL_MASK,    COM, POWER6|PPCA2|PPC476,  {FLM, FRB}},
5284
{"mtfsf.",      XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
5285
{"mtfsf.",      XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476,  {FLM, FRB}},
5286
 
5287
{"drdpq",       XRC(63,770,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5288
{"drdpq.",      XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5289
 
5290
{"dcffixq",     XRC(63,802,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5291
{"dcffixq.",    XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5292
 
5293
{"fctid",       XRC(63,814,0),   XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5294
{"fctid",       XRC(63,814,0),   XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5295
{"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5296
{"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5297
 
5298
{"fctidz",      XRC(63,815,0),   XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5299
{"fctidz",      XRC(63,815,0),   XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5300
{"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5301
{"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5302
 
5303
{"denbcdq",     XRC(63,834,0),   X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5304
{"denbcdq.",    XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5305
 
5306
{"fcfid",       XRC(63,846,0),   XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5307
{"fcfid",       XRC(63,846,0),   XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5308
{"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5309
{"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5310
 
5311
{"diexq",       XRC(63,866,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5312
{"diexq.",      XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5313
 
5314
{"fctidu",      XRC(63,942,0),   XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5315
{"fctidu.",     XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5316
 
5317
{"fctiduz",     XRC(63,943,0),   XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5318
{"fctiduz.",    XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5319
 
5320
{"fcfidu",      XRC(63,974,0),   XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5321
{"fcfidu.",     XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5322
};
5323
 
5324
const int powerpc_num_opcodes =
5325
  sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5326
 
5327
/* The macro table.  This is only used by the assembler.  */
5328
 
5329
/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
5330
   when x=0; 32-x when x is between 1 and 31; are negative if x is
5331
   negative; and are 32 or more otherwise.  This is what you want
5332
   when, for instance, you are emulating a right shift by a
5333
   rotate-left-and-mask, because the underlying instructions support
5334
   shifts of size 0 but not shifts of size 32.  By comparison, when
5335
   extracting x bits from some word you want to use just 32-x, because
5336
   the underlying instructions don't support extracting 0 bits but do
5337
   support extracting the whole word (32 bits in this case).  */
5338
 
5339
const struct powerpc_macro powerpc_macros[] = {
5340
{"extldi",   4, PPC64,  "rldicr %0,%1,%3,(%2)-1"},
5341
{"extldi.",  4, PPC64,  "rldicr. %0,%1,%3,(%2)-1"},
5342
{"extrdi",   4, PPC64,  "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
5343
{"extrdi.",  4, PPC64,  "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
5344
{"insrdi",   4, PPC64,  "rldimi %0,%1,64-((%2)+(%3)),%3"},
5345
{"insrdi.",  4, PPC64,  "rldimi. %0,%1,64-((%2)+(%3)),%3"},
5346
{"rotrdi",   3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
5347
{"rotrdi.",  3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
5348
{"sldi",     3, PPC64,  "rldicr %0,%1,%2,63-(%2)"},
5349
{"sldi.",    3, PPC64,  "rldicr. %0,%1,%2,63-(%2)"},
5350
{"srdi",     3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
5351
{"srdi.",    3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
5352
{"clrrdi",   3, PPC64,  "rldicr %0,%1,0,63-(%2)"},
5353
{"clrrdi.",  3, PPC64,  "rldicr. %0,%1,0,63-(%2)"},
5354
{"clrlsldi", 4, PPC64,  "rldic %0,%1,%3,(%2)-(%3)"},
5355
{"clrlsldi.",4, PPC64,  "rldic. %0,%1,%3,(%2)-(%3)"},
5356
 
5357
{"extlwi",   4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
5358
{"extlwi.",  4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
5359
{"extrwi",   4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5360
{"extrwi.",  4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5361
{"inslwi",   4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5362
{"inslwi.",  4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5363
{"insrwi",   4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5364
{"insrwi.",  4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5365
{"rotrwi",   3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5366
{"rotrwi.",  3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5367
{"slwi",     3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
5368
{"sli",      3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
5369
{"slwi.",    3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
5370
{"sli.",     3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
5371
{"srwi",     3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5372
{"sri",      3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5373
{"srwi.",    3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5374
{"sri.",     3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5375
{"clrrwi",   3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
5376
{"clrrwi.",  3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
5377
{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
5378
{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
5379
};
5380
 
5381
const int powerpc_num_macros =
5382
  sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);

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