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/* Definitions for SH opcodes.

   Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2002, 2003, 2004,

   2005, 2007 Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with this file; see the file COPYING.  If not, write to the

   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

#include "bfd.h"

typedef enum

  {

    HEX_0,

    HEX_1,

    HEX_2,

    HEX_3,

    HEX_4,

    HEX_5,

    HEX_6,

    HEX_7,

    HEX_8,

    HEX_9,

    HEX_A,

    HEX_B,

    HEX_C,

    HEX_D,

    HEX_E,

    HEX_F,

    HEX_XX00,

    HEX_00YY,

    REG_N,

    REG_N_D,     /* nnn0 */

    REG_N_B01,   /* nn01 */

    REG_M,

    SDT_REG_N,

    REG_NM,

    REG_B,

    BRANCH_12,

    BRANCH_8,

    IMM0_4,

    IMM0_4BY2,

    IMM0_4BY4,

    IMM1_4,

    IMM1_4BY2,

    IMM1_4BY4,

    PCRELIMM_8BY2,

    PCRELIMM_8BY4,

    IMM0_8,

    IMM0_8BY2,

    IMM0_8BY4,

    IMM1_8,

    IMM1_8BY2,

    IMM1_8BY4,

    PPI,

    NOPX,

    NOPY,

    MOVX,

    MOVY,

    MOVX_NOPY,

    MOVY_NOPX,

    PSH,

    PMUL,

    PPI3,

    PPI3NC,

    PDC,

    PPIC,

    REPEAT,

    IMM0_3c,    /* xxxx 0iii */

    IMM0_3s,    /* xxxx 1iii */

    IMM0_3Uc,   /* 0iii xxxx */

    IMM0_3Us,   /* 1iii xxxx */

    IMM0_20_4,

    IMM0_20,    /* follows IMM0_20_4 */

    IMM0_20BY8, /* follows IMM0_20_4 */

    DISP0_12,

    DISP0_12BY2,

    DISP0_12BY4,

    DISP0_12BY8,

    DISP1_12,

    DISP1_12BY2,

    DISP1_12BY4,

    DISP1_12BY8

  }

sh_nibble_type;

typedef enum

  {

    A_END,

    A_BDISP12,

    A_BDISP8,

    A_DEC_M,

    A_DEC_N,

    A_DISP_GBR,

    A_PC,

    A_DISP_PC,

    A_DISP_PC_ABS,

    A_DISP_REG_M,

    A_DISP_REG_N,

    A_GBR,

    A_IMM,

    A_INC_M,

    A_INC_N,

    A_IND_M,

    A_IND_N,

    A_IND_R0_REG_M,

    A_IND_R0_REG_N,

    A_MACH,

    A_MACL,

    A_PR,

    A_R0,

    A_R0_GBR,

    A_REG_M,

    A_REG_N,

    A_REG_B,

    A_SR,

    A_VBR,

    A_TBR,

    A_DISP_TBR,

    A_DISP2_TBR,

    A_DEC_R15,

    A_INC_R15,

    A_MOD,

    A_RE,

    A_RS,

    A_DSR,

    DSP_REG_M,

    DSP_REG_N,

    DSP_REG_X,

    DSP_REG_Y,

    DSP_REG_E,

    DSP_REG_F,

    DSP_REG_G,

    DSP_REG_A_M,

    DSP_REG_AX,

    DSP_REG_XY,

    DSP_REG_AY,

    DSP_REG_YX,

    AX_INC_N,

    AY_INC_N,

    AXY_INC_N,

    AYX_INC_N,

    AX_IND_N,

    AY_IND_N,

    AXY_IND_N,

    AYX_IND_N,

    AX_PMOD_N,

    AXY_PMOD_N,

    AY_PMOD_N,

    AYX_PMOD_N,

    AS_DEC_N,

    AS_INC_N,

    AS_IND_N,

    AS_PMOD_N,

    A_A0,

    A_X0,

    A_X1,

    A_Y0,

    A_Y1,

    A_SSR,

    A_SPC,

    A_SGR,

    A_DBR,

    F_REG_N,

    F_REG_M,

    D_REG_N,

    D_REG_M,

    X_REG_N, /* Only used for argument parsing.  */

    X_REG_M, /* Only used for argument parsing.  */

    DX_REG_N,

    DX_REG_M,

    V_REG_N,

    V_REG_M,

    XMTRX_M4,

    F_FR0,

    FPUL_N,

    FPUL_M,

    FPSCR_N,

    FPSCR_M

  }

sh_arg_type;

typedef enum

  {

    A_A1_NUM =   5,

    A_A0_NUM =   7,

    A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM,

    A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM

  }

sh_dsp_reg_nums;

/* Return a mask with bits LO to HI (inclusive) set.  */

#define MASK(LO,HI)  (  LO < 1   ? ((1 << (HI + 1)) - 1) \

                      : HI > 30  ? (-1 << LO) \

                      : LO == HI ? (1 << LO) \

                      :            (((1 << (HI + 1)) - 1) & (-1 << LO)))

#define arch_sh1_base       (1 << 0)

#define arch_sh2_base       (1 << 1)

#define arch_sh2a_sh3_base  (1 << 2)

#define arch_sh3_base       (1 << 3)

#define arch_sh2a_sh4_base  (1 << 4)

#define arch_sh4_base       (1 << 5)

#define arch_sh4a_base      (1 << 6)

#define arch_sh2a_base      (1 << 7)

#define arch_sh_base_mask   MASK (0, 7)

/* Bits 8 ... 24 are currently free.  */

/* This is an annotation on instruction types, but we

   abuse the arch field in instructions to denote it.  */

#define arch_op32          (1 << 25)  /* This is a 32-bit opcode.  */

#define arch_opann_mask    MASK (25, 25)

#define arch_sh_no_mmu     (1 << 26)

#define arch_sh_has_mmu    (1 << 27)

#define arch_sh_mmu_mask   MASK (26, 27)

#define arch_sh_no_co      (1 << 28)  /* Neither FPU nor DSP co-processor.  */

#define arch_sh_sp_fpu     (1 << 29)  /* Single precision FPU.  */

#define arch_sh_dp_fpu     (1 << 30)  /* Double precision FPU.  */

#define arch_sh_has_dsp    (1 << 31)

#define arch_sh_co_mask    MASK (28, 31)

#define arch_sh1                           (arch_sh1_base     |arch_sh_no_mmu |arch_sh_no_co)

#define arch_sh2                           (arch_sh2_base     |arch_sh_no_mmu |arch_sh_no_co)

#define arch_sh2a                          (arch_sh2a_base    |arch_sh_no_mmu |arch_sh_dp_fpu)

#define arch_sh2a_nofpu                    (arch_sh2a_base    |arch_sh_no_mmu |arch_sh_no_co)

#define arch_sh2e                          (arch_sh2_base     |arch_sh_no_mmu |arch_sh_sp_fpu)

#define arch_sh_dsp                        (arch_sh2_base     |arch_sh_no_mmu |arch_sh_has_dsp)

#define arch_sh3_nommu                     (arch_sh3_base     |arch_sh_no_mmu |arch_sh_no_co)

#define arch_sh3                           (arch_sh3_base     |arch_sh_has_mmu|arch_sh_no_co)

#define arch_sh3e                          (arch_sh3_base     |arch_sh_has_mmu|arch_sh_sp_fpu)

#define arch_sh3_dsp                       (arch_sh3_base     |arch_sh_has_mmu|arch_sh_has_dsp)

#define arch_sh4                           (arch_sh4_base     |arch_sh_has_mmu|arch_sh_dp_fpu)

#define arch_sh4a                          (arch_sh4a_base    |arch_sh_has_mmu|arch_sh_dp_fpu)

#define arch_sh4al_dsp                     (arch_sh4a_base    |arch_sh_has_mmu|arch_sh_has_dsp)

#define arch_sh4_nofpu                     (arch_sh4_base     |arch_sh_has_mmu|arch_sh_no_co)

#define arch_sh4a_nofpu                    (arch_sh4a_base    |arch_sh_has_mmu|arch_sh_no_co)

#define arch_sh4_nommu_nofpu               (arch_sh4_base     |arch_sh_no_mmu |arch_sh_no_co)

#define arch_sh2a_nofpu_or_sh4_nommu_nofpu (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_no_co)

#define arch_sh2a_nofpu_or_sh3_nommu       (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)

#define arch_sh2a_or_sh3e                  (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)

#define arch_sh2a_or_sh4                   (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)

#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))

#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)

#define SH_VALID_MMU_ARCH_SET(SET)  (((SET) & arch_sh_mmu_mask) != 0)

#define SH_VALID_CO_ARCH_SET(SET)   (((SET) & arch_sh_co_mask) != 0)

#define SH_VALID_ARCH_SET(SET) \

  (SH_VALID_BASE_ARCH_SET (SET) \

   && SH_VALID_MMU_ARCH_SET (SET) \

   && SH_VALID_CO_ARCH_SET (SET))

#define SH_MERGE_ARCH_SET_VALID(SET1, SET2) \

  SH_VALID_ARCH_SET (SH_MERGE_ARCH_SET (SET1, SET2))

#define SH_ARCH_SET_HAS_FPU(SET) \

  (((SET) & (arch_sh_sp_fpu | arch_sh_dp_fpu)) != 0)

#define SH_ARCH_SET_HAS_DSP(SET) \

  (((SET) & arch_sh_has_dsp) != 0)

/* This is returned from the functions below when an error occurs

   (in addition to a call to BFD_FAIL). The value should allow

   the tools to continue to function in most cases - there may

   be some confusion between DSP and FPU etc.  */

#define SH_ARCH_UNKNOWN_ARCH 0xffffffff

/* These are defined in bfd/cpu-sh.c .  */

unsigned int sh_get_arch_from_bfd_mach (unsigned long mach);

unsigned int sh_get_arch_up_from_bfd_mach (unsigned long mach);

unsigned long sh_get_bfd_mach_from_arch_set (unsigned int arch_set);

bfd_boolean sh_merge_bfd_arch (bfd *ibfd, bfd *obfd);

/* Below are the 'architecture sets'.

   They describe the following inheritance graph:

                SH1

                 |

                SH2

   .------------'|`--------------------------------.

  /              |                                  \

SH-DSP          SH3-nommu/SH2A-nofpu               SH2E

 |               |          |`--------------------. |

 |               |          |                      \|

 |              SH3-nommu  SH4-nm-nf/SH2A-nofpu    SH3E/SH2A

 |               |\         |          |      \     |    |

 |               | `------. |     SH2A-nofpu   `----+---.|

 |               |         \|            \          |   SH4/SH2A

 |              SH3     SH4-nommu-nofpu   `---------+--. |   |

 |              /|\         |                       |   \|   |

 | .-----------' | `--------+---------------------. |  SH2A  |

 |/              |          /                      \|        |

 |               | .-------'                        |        |

 |               |/                                 |        |

SH3-dsp         SH4-nofpu                          SH3E      |

 |               |`-------------------------------. | .-----'

 |               |                                 \|/

 |              SH4A-nofpu                         SH4

 | .------------' `-------------------------------. |

 |/                                                \|

SH4AL-dsp                                          SH4A

*/

/* Central branches.  */

#define arch_sh_up                             (arch_sh1 \

                | arch_sh2_up)

#define arch_sh2_up                            (arch_sh2 \

                | arch_sh2e_up \

                | arch_sh2a_nofpu_or_sh3_nommu_up \

                | arch_sh_dsp_up)

#define arch_sh2a_nofpu_or_sh3_nommu_up        (arch_sh2a_nofpu_or_sh3_nommu \

                | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \

                | arch_sh2a_or_sh3e_up \

                | arch_sh3_nommu_up)

#define arch_sh2a_nofpu_or_sh4_nommu_nofpu_up  (arch_sh2a_nofpu_or_sh4_nommu_nofpu \

                | arch_sh2a_nofpu_up \

                | arch_sh2a_or_sh4_up \

                | arch_sh4_nommu_nofpu_up)

#define arch_sh2a_nofpu_up                     (arch_sh2a_nofpu \

                | arch_sh2a_up)

#define arch_sh3_nommu_up                      (arch_sh3_nommu \

                | arch_sh3_up \

                | arch_sh4_nommu_nofpu_up)

#define arch_sh3_up                            (arch_sh3 \

                | arch_sh3e_up \

                | arch_sh3_dsp_up \

                | arch_sh4_nofpu_up)

#define arch_sh4_nommu_nofpu_up                (arch_sh4_nommu_nofpu \

                | arch_sh4_nofpu_up)

#define arch_sh4_nofpu_up                      (arch_sh4_nofpu \

                | arch_sh4_up \

                | arch_sh4a_nofpu_up)

#define arch_sh4a_nofpu_up                     (arch_sh4a_nofpu \

                | arch_sh4a_up \

                | arch_sh4al_dsp_up)

/* Right branches.  */

#define arch_sh2e_up                           (arch_sh2e \

                | arch_sh2a_or_sh3e_up)

#define arch_sh2a_or_sh3e_up                   (arch_sh2a_or_sh3e \

                | arch_sh2a_or_sh4_up \

                | arch_sh3e_up)

#define arch_sh2a_or_sh4_up                    (arch_sh2a_or_sh4 \

                | arch_sh2a_up \

                | arch_sh4_up)

#define arch_sh2a_up                           (arch_sh2a)

#define arch_sh3e_up                           (arch_sh3e \

                | arch_sh4_up)

#define arch_sh4_up                            (arch_sh4 \

                | arch_sh4a_up)

#define arch_sh4a_up                           (arch_sh4a)

/* Left branch.  */

#define arch_sh_dsp_up                         (arch_sh_dsp  \

                | arch_sh3_dsp_up)

#define arch_sh3_dsp_up                        (arch_sh3_dsp \

                | arch_sh4al_dsp_up)

#define arch_sh4al_dsp_up                      (arch_sh4al_dsp)

typedef struct

{

  char *name;

  sh_arg_type arg[4];

  sh_nibble_type nibbles[9];

  unsigned int arch;

} sh_opcode_info;

#ifdef DEFINE_TABLE

const sh_opcode_info sh_table[] =

  {

/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up},

/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up},

/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up},

/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up},

/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up},

/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up},

/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up},

/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up},

/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up},

/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up},

/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up},

/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},

/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},

/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},

/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},

/* 0000000010001000 clrdmxy             */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up},

/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up},

/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up},

/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up},

/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up},

/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up},

/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up},

/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up},

/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up},

/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up},

/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up},

/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up},

/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up},

/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up},

/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up},

/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up},

/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up},

/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up},

/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up},

/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up},

/* 0000nnnn11100011 icbi @<REG_N>       */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up},

/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up},

/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up},

/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up},

/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up},

/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},

/* 0100mmmm01001010 ldc <REG_M>,TBR     */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up},

/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up},

/* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up},

/* 0100nnnn01111110 ldc <REG_N>,RE     */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up},

/* 0100nnnn01101110 ldc <REG_N>,RS     */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up},

/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up},

/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up},

/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},

/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up},

/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up},

/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up},

/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up},

/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up},

/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up},

/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up},

/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up},

/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up},

/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up},

/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up},

/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up},

/* 0100mmmm00110100 ldrc <REG_M>        */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up},

/* 10001010i8*1.... ldrc #<imm>         */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up},

/* 10001110i8p2.... ldre @(<disp>,PC)   */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},

/* 10001100i8p2.... ldrs @(<disp>,PC)   */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up},

/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up},

/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up},

/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up},

/* 0100nnnn01101010 lds <REG_N>,DSR     */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},

/* 0100nnnn01111010 lds <REG_N>,A0      */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},

/* 0100nnnn10001010 lds <REG_N>,X0      */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},

/* 0100nnnn10011010 lds <REG_N>,X1      */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},

/* 0100nnnn10101010 lds <REG_N>,Y0      */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},

/* 0100nnnn10111010 lds <REG_N>,Y1      */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},

/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up},

/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up},

/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up},

/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up},

/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up},

/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up},

/* 0100nnnn01110110 lds.l @<REG_N>+,A0  */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up},

/* 0100nnnn10000110 lds.l @<REG_N>+,X0  */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up},

/* 0100nnnn10010110 lds.l @<REG_N>+,X1  */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up},

/* 0100nnnn10100110 lds.l @<REG_N>+,Y0  */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up},

/* 0100nnnn10110110 lds.l @<REG_N>+,Y1  */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up},

/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up},

/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},

/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},

/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up},

/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up},

/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up},

/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up},

/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up},

/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up},

/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up},

/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up},

/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up},

/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up},

/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up},

/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up},

/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up},

/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up},

/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up},

/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */

{"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},

/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */

{"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},

/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up},

/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up},

/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up},

/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up},

/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up},

/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up},

/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up},

/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up},

/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up},

/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up},

/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up},

/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up},