OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [opcodes/] [sh64-opc.h] - Blame information for rev 277

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
/* Declarations for SH64 opcodes.
2
   Copyright (C) 2000, 2001, 2002, 2005, 2007 Free Software Foundation, Inc.
3
 
4
   This file is part of the GNU opcodes library.
5
 
6
   This library is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 3, or (at your option)
9
   any later version.
10
 
11
   It is distributed in the hope that it will be useful, but WITHOUT
12
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14
   License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this file; see the file COPYING.  If not, write to the
18
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19
   MA 02110-1301, USA.  */
20
 
21
#ifndef _SH64_OPC_INCLUDED_H
22
#define _SH64_OPC_INCLUDED_H
23
 
24
typedef enum
25
{
26
  /* A placeholder.  */
27
  OFFSET_NONE = 0,
28
 
29
  /* Bit number for where to insert operand.  */
30
  OFFSET_4  = 4,
31
  OFFSET_9  = 9,
32
  OFFSET_10 = 10,
33
  OFFSET_20 = 20
34
} shmedia_nibble_type;
35
 
36
typedef enum {
37
  /* First a placeholder.  */
38
  A_NONE = 0,
39
 
40
  /* Registers.  */
41
  A_GREG_M,
42
  A_GREG_N,
43
  A_GREG_D,
44
  A_FREG_G,
45
  A_FREG_H,
46
  A_FREG_F,
47
  A_DREG_G,
48
  A_DREG_H,
49
  A_DREG_F,
50
  A_FVREG_G,
51
  A_FVREG_H,
52
  A_FVREG_F,
53
  A_FMREG_G,
54
  A_FMREG_H,
55
  A_FMREG_F,
56
  A_FPREG_G,
57
  A_FPREG_H,
58
  A_FPREG_F,
59
  A_TREG_A,
60
  A_TREG_B,
61
  A_CREG_K,
62
  A_CREG_J,
63
 
64
  /* This one is only used in a shmedia_get_operand.  */
65
  A_IMMM,
66
 
67
  /* Copy of previous register.  */
68
  A_REUSE_PREV,
69
 
70
  /* Unsigned 5-bit operand.  */
71
  A_IMMU5,
72
 
73
  /* Signed 6-bit operand.  */
74
  A_IMMS6,
75
 
76
  /* Signed operand, 6 bits << 5.  */
77
  A_IMMS6BY32,
78
 
79
  /* Unsigned 6-bit operand.  */
80
  A_IMMU6,
81
 
82
  /* Signed 10-bit operand.  */
83
  A_IMMS10,
84
 
85
  /* Signed operand, 10 bits << 0.  */
86
  A_IMMS10BY1,
87
 
88
  /* Signed operand, 10 bits << 1.  */
89
  A_IMMS10BY2,
90
 
91
  /* Signed operand, 10 bits << 2.  */
92
  A_IMMS10BY4,
93
 
94
  /* Signed operand, 10 bits << 3.  */
95
  A_IMMS10BY8,
96
 
97
  /* Signed 16-bit operand.  */
98
  A_IMMS16,
99
 
100
  /* Unsigned 16-bit operand.  */
101
  A_IMMU16,
102
 
103
  /* PC-relative signed operand, 16 bits << 2, for PTA and PTB insns.  */
104
  A_PCIMMS16BY4,
105
 
106
  /* PC relative signed operand, 16 bits << 2, for PT insns.  Also adjusts
107
     the opcode to be PTA or PTB.  */
108
  A_PCIMMS16BY4_PT,
109
} shmedia_arg_type;
110
 
111
typedef struct {
112
  char *name;
113
  shmedia_arg_type arg[4];
114
  shmedia_nibble_type nibbles[4];
115
  unsigned long opcode_base;
116
} shmedia_opcode_info;
117
 
118
extern const shmedia_opcode_info shmedia_table[];
119
 
120
typedef struct {
121
  int cregno;
122
  char *name;
123
} shmedia_creg_info;
124
 
125
extern const shmedia_creg_info shmedia_creg_table[];
126
 
127
#define SHMEDIA_LIKELY_BIT    0x00000200
128
#define SHMEDIA_PT_OPC        0xe8000000
129
#define SHMEDIA_PTB_BIT       0x04000000
130
#define SHMEDIA_PTA_OPC       0xe8000000
131
#define SHMEDIA_PTB_OPC       0xec000000
132
 
133
/* Note that this is ptrel/u.  "Or" in SHMEDIA_LIKELY_BIT for ptrel/l.  */
134
#define SHMEDIA_PTREL_OPC     0x6bf50000
135
#define SHMEDIA_MOVI_OPC      0xcc000000
136
#define SHMEDIA_SHORI_OPC     0xc8000000
137
#define SHMEDIA_ADDI_OPC      0xd0000000
138
#define SHMEDIA_ADD_OPC       0x00090000
139
#define SHMEDIA_NOP_OPC       0x6ff0fff0
140
#define SHMEDIA_TEMP_REG      25
141
 
142
#endif /* _SH64_OPC_INCLUDED_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.