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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [opcodes/] [xc16x-desc.h] - Blame information for rev 205

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1 205 julius
/* CPU data header for xc16x.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996-2009 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
 
9
   This file is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program; if not, write to the Free Software Foundation, Inc.,
21
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
 
23
*/
24
 
25
#ifndef XC16X_CPU_H
26
#define XC16X_CPU_H
27
 
28
#include "opcode/cgen-bitset.h"
29
 
30
#define CGEN_ARCH xc16x
31
 
32
/* Given symbol S, return xc16x_cgen_<S>.  */
33
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
34
#define CGEN_SYM(s) xc16x##_cgen_##s
35
#else
36
#define CGEN_SYM(s) xc16x/**/_cgen_/**/s
37
#endif
38
 
39
 
40
/* Selected cpu families.  */
41
#define HAVE_CPU_XC16XBF
42
 
43
#define CGEN_INSN_LSB0_P 1
44
 
45
/* Minimum size of any insn (in bytes).  */
46
#define CGEN_MIN_INSN_SIZE 2
47
 
48
/* Maximum size of any insn (in bytes).  */
49
#define CGEN_MAX_INSN_SIZE 4
50
 
51
#define CGEN_INT_INSN_P 1
52
 
53
/* Maximum number of syntax elements in an instruction.  */
54
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
55
 
56
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
57
   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
58
   we can't hash on everything up to the space.  */
59
#define CGEN_MNEMONIC_OPERANDS
60
 
61
/* Maximum number of fields in an instruction.  */
62
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
63
 
64
/* Enums.  */
65
 
66
/* Enum declaration for insn format enums.  */
67
typedef enum insn_op1 {
68
  OP1_0, OP1_1, OP1_2, OP1_3
69
 , OP1_4, OP1_5, OP1_6, OP1_7
70
 , OP1_8, OP1_9, OP1_10, OP1_11
71
 , OP1_12, OP1_13, OP1_14, OP1_15
72
} INSN_OP1;
73
 
74
/* Enum declaration for op2 enums.  */
75
typedef enum insn_op2 {
76
  OP2_0, OP2_1, OP2_2, OP2_3
77
 , OP2_4, OP2_5, OP2_6, OP2_7
78
 , OP2_8, OP2_9, OP2_10, OP2_11
79
 , OP2_12, OP2_13, OP2_14, OP2_15
80
} INSN_OP2;
81
 
82
/* Enum declaration for bit set/clear enums.  */
83
typedef enum insn_qcond {
84
  QBIT_0, QBIT_1, QBIT_2, QBIT_3
85
 , QBIT_4, QBIT_5, QBIT_6, QBIT_7
86
 , QBIT_8, QBIT_9, QBIT_10, QBIT_11
87
 , QBIT_12, QBIT_13, QBIT_14, QBIT_15
88
} INSN_QCOND;
89
 
90
/* Enum declaration for relative jump condition code op2 enums.  */
91
typedef enum insn_rcond {
92
  COND_UC = 0, COND_NET = 1, COND_Z = 2, COND_NE_NZ = 3
93
 , COND_V = 4, COND_NV = 5, COND_N = 6, COND_NN = 7
94
 , COND_C = 8, COND_NC = 9, COND_SGT = 10, COND_SLE = 11
95
 , COND_SLT = 12, COND_SGE = 13, COND_UGT = 14, COND_ULE = 15
96
 , COND_EQ = 2, COND_NE = 3, COND_ULT = 8, COND_UGE = 9
97
} INSN_RCOND;
98
 
99
/* Enum declaration for .  */
100
typedef enum gr_names {
101
  H_GR_R0, H_GR_R1, H_GR_R2, H_GR_R3
102
 , H_GR_R4, H_GR_R5, H_GR_R6, H_GR_R7
103
 , H_GR_R8, H_GR_R9, H_GR_R10, H_GR_R11
104
 , H_GR_R12, H_GR_R13, H_GR_R14, H_GR_R15
105
} GR_NAMES;
106
 
107
/* Enum declaration for .  */
108
typedef enum ext_names {
109
  H_EXT_0X1 = 0, H_EXT_0X2 = 1, H_EXT_0X3 = 2, H_EXT_0X4 = 3
110
 , H_EXT_1 = 0, H_EXT_2 = 1, H_EXT_3 = 2, H_EXT_4 = 3
111
} EXT_NAMES;
112
 
113
/* Enum declaration for .  */
114
typedef enum psw_names {
115
  H_PSW_IEN = 136, H_PSW_R0_11 = 240, H_PSW_R1_11 = 241, H_PSW_R2_11 = 242
116
 , H_PSW_R3_11 = 243, H_PSW_R4_11 = 244, H_PSW_R5_11 = 245, H_PSW_R6_11 = 246
117
 , H_PSW_R7_11 = 247, H_PSW_R8_11 = 248, H_PSW_R9_11 = 249, H_PSW_R10_11 = 250
118
 , H_PSW_R11_11 = 251, H_PSW_R12_11 = 252, H_PSW_R13_11 = 253, H_PSW_R14_11 = 254
119
 , H_PSW_R15_11 = 255
120
} PSW_NAMES;
121
 
122
/* Enum declaration for .  */
123
typedef enum grb_names {
124
  H_GRB_RL0, H_GRB_RH0, H_GRB_RL1, H_GRB_RH1
125
 , H_GRB_RL2, H_GRB_RH2, H_GRB_RL3, H_GRB_RH3
126
 , H_GRB_RL4, H_GRB_RH4, H_GRB_RL5, H_GRB_RH5
127
 , H_GRB_RL6, H_GRB_RH6, H_GRB_RL7, H_GRB_RH7
128
} GRB_NAMES;
129
 
130
/* Enum declaration for .  */
131
typedef enum conditioncode_names {
132
  H_CC_CC_UC = 0, H_CC_CC_NET = 1, H_CC_CC_Z = 2, H_CC_CC_EQ = 2
133
 , H_CC_CC_NZ = 3, H_CC_CC_NE = 3, H_CC_CC_V = 4, H_CC_CC_NV = 5
134
 , H_CC_CC_N = 6, H_CC_CC_NN = 7, H_CC_CC_ULT = 8, H_CC_CC_UGE = 9
135
 , H_CC_CC_C = 8, H_CC_CC_NC = 9, H_CC_CC_SGT = 10, H_CC_CC_SLE = 11
136
 , H_CC_CC_SLT = 12, H_CC_CC_SGE = 13, H_CC_CC_UGT = 14, H_CC_CC_ULE = 15
137
} CONDITIONCODE_NAMES;
138
 
139
/* Enum declaration for .  */
140
typedef enum extconditioncode_names {
141
  H_ECC_CC_UC = 0, H_ECC_CC_NET = 2, H_ECC_CC_Z = 4, H_ECC_CC_EQ = 4
142
 , H_ECC_CC_NZ = 6, H_ECC_CC_NE = 6, H_ECC_CC_V = 8, H_ECC_CC_NV = 10
143
 , H_ECC_CC_N = 12, H_ECC_CC_NN = 14, H_ECC_CC_ULT = 16, H_ECC_CC_UGE = 18
144
 , H_ECC_CC_C = 16, H_ECC_CC_NC = 18, H_ECC_CC_SGT = 20, H_ECC_CC_SLE = 22
145
 , H_ECC_CC_SLT = 24, H_ECC_CC_SGE = 26, H_ECC_CC_UGT = 28, H_ECC_CC_ULE = 30
146
 , H_ECC_CC_NUSR0 = 1, H_ECC_CC_NUSR1 = 3, H_ECC_CC_USR0 = 5, H_ECC_CC_USR1 = 7
147
} EXTCONDITIONCODE_NAMES;
148
 
149
/* Enum declaration for .  */
150
typedef enum grb8_names {
151
  H_GRB8_DPP0 = 0, H_GRB8_DPP1 = 1, H_GRB8_DPP2 = 2, H_GRB8_DPP3 = 3
152
 , H_GRB8_PSW = 136, H_GRB8_CP = 8, H_GRB8_MDL = 7, H_GRB8_MDH = 6
153
 , H_GRB8_MDC = 135, H_GRB8_SP = 9, H_GRB8_CSP = 4, H_GRB8_VECSEG = 137
154
 , H_GRB8_STKOV = 10, H_GRB8_STKUN = 11, H_GRB8_CPUCON1 = 12, H_GRB8_CPUCON2 = 13
155
 , H_GRB8_ZEROS = 142, H_GRB8_ONES = 143, H_GRB8_SPSEG = 134, H_GRB8_TFR = 214
156
 , H_GRB8_RL0 = 240, H_GRB8_RH0 = 241, H_GRB8_RL1 = 242, H_GRB8_RH1 = 243
157
 , H_GRB8_RL2 = 244, H_GRB8_RH2 = 245, H_GRB8_RL3 = 246, H_GRB8_RH3 = 247
158
 , H_GRB8_RL4 = 248, H_GRB8_RH4 = 249, H_GRB8_RL5 = 250, H_GRB8_RH5 = 251
159
 , H_GRB8_RL6 = 252, H_GRB8_RH6 = 253, H_GRB8_RL7 = 254, H_GRB8_RH7 = 255
160
} GRB8_NAMES;
161
 
162
/* Enum declaration for .  */
163
typedef enum r8_names {
164
  H_R8_DPP0 = 0, H_R8_DPP1 = 1, H_R8_DPP2 = 2, H_R8_DPP3 = 3
165
 , H_R8_PSW = 136, H_R8_CP = 8, H_R8_MDL = 7, H_R8_MDH = 6
166
 , H_R8_MDC = 135, H_R8_SP = 9, H_R8_CSP = 4, H_R8_VECSEG = 137
167
 , H_R8_STKOV = 10, H_R8_STKUN = 11, H_R8_CPUCON1 = 12, H_R8_CPUCON2 = 13
168
 , H_R8_ZEROS = 142, H_R8_ONES = 143, H_R8_SPSEG = 134, H_R8_TFR = 214
169
 , H_R8_R0 = 240, H_R8_R1 = 241, H_R8_R2 = 242, H_R8_R3 = 243
170
 , H_R8_R4 = 244, H_R8_R5 = 245, H_R8_R6 = 246, H_R8_R7 = 247
171
 , H_R8_R8 = 248, H_R8_R9 = 249, H_R8_R10 = 250, H_R8_R11 = 251
172
 , H_R8_R12 = 252, H_R8_R13 = 253, H_R8_R14 = 254, H_R8_R15 = 255
173
} R8_NAMES;
174
 
175
/* Enum declaration for .  */
176
typedef enum regmem8_names {
177
  H_REGMEM8_DPP0 = 0, H_REGMEM8_DPP1 = 1, H_REGMEM8_DPP2 = 2, H_REGMEM8_DPP3 = 3
178
 , H_REGMEM8_PSW = 136, H_REGMEM8_CP = 8, H_REGMEM8_MDL = 7, H_REGMEM8_MDH = 6
179
 , H_REGMEM8_MDC = 135, H_REGMEM8_SP = 9, H_REGMEM8_CSP = 4, H_REGMEM8_VECSEG = 137
180
 , H_REGMEM8_STKOV = 10, H_REGMEM8_STKUN = 11, H_REGMEM8_CPUCON1 = 12, H_REGMEM8_CPUCON2 = 13
181
 , H_REGMEM8_ZEROS = 142, H_REGMEM8_ONES = 143, H_REGMEM8_SPSEG = 134, H_REGMEM8_TFR = 214
182
 , H_REGMEM8_R0 = 240, H_REGMEM8_R1 = 241, H_REGMEM8_R2 = 242, H_REGMEM8_R3 = 243
183
 , H_REGMEM8_R4 = 244, H_REGMEM8_R5 = 245, H_REGMEM8_R6 = 246, H_REGMEM8_R7 = 247
184
 , H_REGMEM8_R8 = 248, H_REGMEM8_R9 = 249, H_REGMEM8_R10 = 250, H_REGMEM8_R11 = 251
185
 , H_REGMEM8_R12 = 252, H_REGMEM8_R13 = 253, H_REGMEM8_R14 = 254, H_REGMEM8_R15 = 255
186
} REGMEM8_NAMES;
187
 
188
/* Enum declaration for .  */
189
typedef enum regdiv8_names {
190
  H_REGDIV8_R0 = 0, H_REGDIV8_R1 = 17, H_REGDIV8_R2 = 34, H_REGDIV8_R3 = 51
191
 , H_REGDIV8_R4 = 68, H_REGDIV8_R5 = 85, H_REGDIV8_R6 = 102, H_REGDIV8_R7 = 119
192
 , H_REGDIV8_R8 = 136, H_REGDIV8_R9 = 153, H_REGDIV8_R10 = 170, H_REGDIV8_R11 = 187
193
 , H_REGDIV8_R12 = 204, H_REGDIV8_R13 = 221, H_REGDIV8_R14 = 238, H_REGDIV8_R15 = 255
194
} REGDIV8_NAMES;
195
 
196
/* Enum declaration for .  */
197
typedef enum reg0_name {
198
  H_REG0_0X1 = 1, H_REG0_0X2 = 2, H_REG0_0X3 = 3, H_REG0_0X4 = 4
199
 , H_REG0_0X5 = 5, H_REG0_0X6 = 6, H_REG0_0X7 = 7, H_REG0_0X8 = 8
200
 , H_REG0_0X9 = 9, H_REG0_0XA = 10, H_REG0_0XB = 11, H_REG0_0XC = 12
201
 , H_REG0_0XD = 13, H_REG0_0XE = 14, H_REG0_0XF = 15, H_REG0_1 = 1
202
 , H_REG0_2 = 2, H_REG0_3 = 3, H_REG0_4 = 4, H_REG0_5 = 5
203
 , H_REG0_6 = 6, H_REG0_7 = 7, H_REG0_8 = 8, H_REG0_9 = 9
204
 , H_REG0_10 = 10, H_REG0_11 = 11, H_REG0_12 = 12, H_REG0_13 = 13
205
 , H_REG0_14 = 14, H_REG0_15 = 15
206
} REG0_NAME;
207
 
208
/* Enum declaration for .  */
209
typedef enum reg0_name1 {
210
  H_REG01_0X1 = 1, H_REG01_0X2 = 2, H_REG01_0X3 = 3, H_REG01_0X4 = 4
211
 , H_REG01_0X5 = 5, H_REG01_0X6 = 6, H_REG01_0X7 = 7, H_REG01_1 = 1
212
 , H_REG01_2 = 2, H_REG01_3 = 3, H_REG01_4 = 4, H_REG01_5 = 5
213
 , H_REG01_6 = 6, H_REG01_7 = 7
214
} REG0_NAME1;
215
 
216
/* Enum declaration for .  */
217
typedef enum regbmem8_names {
218
  H_REGBMEM8_DPP0 = 0, H_REGBMEM8_DPP1 = 1, H_REGBMEM8_DPP2 = 2, H_REGBMEM8_DPP3 = 3
219
 , H_REGBMEM8_PSW = 136, H_REGBMEM8_CP = 8, H_REGBMEM8_MDL = 7, H_REGBMEM8_MDH = 6
220
 , H_REGBMEM8_MDC = 135, H_REGBMEM8_SP = 9, H_REGBMEM8_CSP = 4, H_REGBMEM8_VECSEG = 137
221
 , H_REGBMEM8_STKOV = 10, H_REGBMEM8_STKUN = 11, H_REGBMEM8_CPUCON1 = 12, H_REGBMEM8_CPUCON2 = 13
222
 , H_REGBMEM8_ZEROS = 142, H_REGBMEM8_ONES = 143, H_REGBMEM8_SPSEG = 134, H_REGBMEM8_TFR = 214
223
 , H_REGBMEM8_RL0 = 240, H_REGBMEM8_RH0 = 241, H_REGBMEM8_RL1 = 242, H_REGBMEM8_RH1 = 243
224
 , H_REGBMEM8_RL2 = 244, H_REGBMEM8_RH2 = 245, H_REGBMEM8_RL3 = 246, H_REGBMEM8_RH3 = 247
225
 , H_REGBMEM8_RL4 = 248, H_REGBMEM8_RH4 = 249, H_REGBMEM8_RL5 = 250, H_REGBMEM8_RH5 = 251
226
 , H_REGBMEM8_RL6 = 252, H_REGBMEM8_RH6 = 253, H_REGBMEM8_RL7 = 254, H_REGBMEM8_RH7 = 255
227
} REGBMEM8_NAMES;
228
 
229
/* Enum declaration for .  */
230
typedef enum memgr8_names {
231
  H_MEMGR8_DPP0 = 65024, H_MEMGR8_DPP1 = 65026, H_MEMGR8_DPP2 = 65028, H_MEMGR8_DPP3 = 65030
232
 , H_MEMGR8_PSW = 65296, H_MEMGR8_CP = 65040, H_MEMGR8_MDL = 65038, H_MEMGR8_MDH = 65036
233
 , H_MEMGR8_MDC = 65294, H_MEMGR8_SP = 65042, H_MEMGR8_CSP = 65032, H_MEMGR8_VECSEG = 65298
234
 , H_MEMGR8_STKOV = 65044, H_MEMGR8_STKUN = 65046, H_MEMGR8_CPUCON1 = 65048, H_MEMGR8_CPUCON2 = 65050
235
 , H_MEMGR8_ZEROS = 65308, H_MEMGR8_ONES = 65310, H_MEMGR8_SPSEG = 65292, H_MEMGR8_TFR = 65452
236
} MEMGR8_NAMES;
237
 
238
/* Attributes.  */
239
 
240
/* Enum declaration for machine type selection.  */
241
typedef enum mach_attr {
242
  MACH_BASE, MACH_XC16X, MACH_MAX
243
} MACH_ATTR;
244
 
245
/* Enum declaration for instruction set selection.  */
246
typedef enum isa_attr {
247
  ISA_XC16X, ISA_MAX
248
} ISA_ATTR;
249
 
250
/* Enum declaration for parallel execution pipeline selection.  */
251
typedef enum pipe_attr {
252
  PIPE_NONE, PIPE_OS
253
} PIPE_ATTR;
254
 
255
/* Number of architecture variants.  */
256
#define MAX_ISAS  1
257
#define MAX_MACHS ((int) MACH_MAX)
258
 
259
/* Ifield support.  */
260
 
261
/* Ifield attribute indices.  */
262
 
263
/* Enum declaration for cgen_ifld attrs.  */
264
typedef enum cgen_ifld_attr {
265
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
266
 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
267
 , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
268
} CGEN_IFLD_ATTR;
269
 
270
/* Number of non-boolean elements in cgen_ifld_attr.  */
271
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
272
 
273
/* cgen_ifld attribute accessor macros.  */
274
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
275
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
276
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
277
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
278
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
279
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
280
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
281
#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RELOC)) != 0)
282
 
283
/* Enum declaration for xc16x ifield types.  */
284
typedef enum ifield_type {
285
  XC16X_F_NIL, XC16X_F_ANYOF, XC16X_F_OP1, XC16X_F_OP2
286
 , XC16X_F_CONDCODE, XC16X_F_ICONDCODE, XC16X_F_RCOND, XC16X_F_QCOND
287
 , XC16X_F_EXTCCODE, XC16X_F_R0, XC16X_F_R1, XC16X_F_R2
288
 , XC16X_F_R3, XC16X_F_R4, XC16X_F_UIMM2, XC16X_F_UIMM3
289
 , XC16X_F_UIMM4, XC16X_F_UIMM7, XC16X_F_UIMM8, XC16X_F_UIMM16
290
 , XC16X_F_MEMORY, XC16X_F_MEMGR8, XC16X_F_REL8, XC16X_F_RELHI8
291
 , XC16X_F_REG8, XC16X_F_REGMEM8, XC16X_F_REGOFF8, XC16X_F_REGHI8
292
 , XC16X_F_REGB8, XC16X_F_SEG8, XC16X_F_SEGNUM8, XC16X_F_MASK8
293
 , XC16X_F_PAGENUM, XC16X_F_DATAHI8, XC16X_F_DATA8, XC16X_F_OFFSET16
294
 , XC16X_F_OP_BIT1, XC16X_F_OP_BIT2, XC16X_F_OP_BIT4, XC16X_F_OP_BIT3
295
 , XC16X_F_OP_2BIT, XC16X_F_OP_BITONE, XC16X_F_OP_ONEBIT, XC16X_F_OP_1BIT
296
 , XC16X_F_OP_LBIT4, XC16X_F_OP_LBIT2, XC16X_F_OP_BIT8, XC16X_F_OP_BIT16
297
 , XC16X_F_QBIT, XC16X_F_QLOBIT, XC16X_F_QHIBIT, XC16X_F_QLOBIT2
298
 , XC16X_F_POF, XC16X_F_MAX
299
} IFIELD_TYPE;
300
 
301
#define MAX_IFLD ((int) XC16X_F_MAX)
302
 
303
/* Hardware attribute indices.  */
304
 
305
/* Enum declaration for cgen_hw attrs.  */
306
typedef enum cgen_hw_attr {
307
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
308
 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
309
} CGEN_HW_ATTR;
310
 
311
/* Number of non-boolean elements in cgen_hw_attr.  */
312
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
313
 
314
/* cgen_hw attribute accessor macros.  */
315
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
316
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
317
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
318
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
319
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
320
 
321
/* Enum declaration for xc16x hardware types.  */
322
typedef enum cgen_hw_type {
323
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
324
 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_EXT
325
 , HW_H_PSW, HW_H_GRB, HW_H_CC, HW_H_ECC
326
 , HW_H_GRB8, HW_H_R8, HW_H_REGMEM8, HW_H_REGDIV8
327
 , HW_H_R0, HW_H_R01, HW_H_REGBMEM8, HW_H_MEMGR8
328
 , HW_H_COND, HW_H_CBIT, HW_H_SGTDIS, HW_MAX
329
} CGEN_HW_TYPE;
330
 
331
#define MAX_HW ((int) HW_MAX)
332
 
333
/* Operand attribute indices.  */
334
 
335
/* Enum declaration for cgen_operand attrs.  */
336
typedef enum cgen_operand_attr {
337
  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
338
 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
339
 , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_DOT_PREFIX, CGEN_OPERAND_POF_PREFIX
340
 , CGEN_OPERAND_PAG_PREFIX, CGEN_OPERAND_SOF_PREFIX, CGEN_OPERAND_SEG_PREFIX, CGEN_OPERAND_END_BOOLS
341
 , CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
342
} CGEN_OPERAND_ATTR;
343
 
344
/* Number of non-boolean elements in cgen_operand_attr.  */
345
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
346
 
347
/* cgen_operand attribute accessor macros.  */
348
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
349
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
350
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
351
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
352
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
353
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
354
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
355
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
356
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
357
#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC)) != 0)
358
#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
359
#define CGEN_ATTR_CGEN_OPERAND_DOT_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_DOT_PREFIX)) != 0)
360
#define CGEN_ATTR_CGEN_OPERAND_POF_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_POF_PREFIX)) != 0)
361
#define CGEN_ATTR_CGEN_OPERAND_PAG_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PAG_PREFIX)) != 0)
362
#define CGEN_ATTR_CGEN_OPERAND_SOF_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SOF_PREFIX)) != 0)
363
#define CGEN_ATTR_CGEN_OPERAND_SEG_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEG_PREFIX)) != 0)
364
 
365
/* Enum declaration for xc16x operand types.  */
366
typedef enum cgen_operand_type {
367
  XC16X_OPERAND_PC, XC16X_OPERAND_SR, XC16X_OPERAND_DR, XC16X_OPERAND_DRI
368
 , XC16X_OPERAND_SRB, XC16X_OPERAND_DRB, XC16X_OPERAND_SR2, XC16X_OPERAND_SRC1
369
 , XC16X_OPERAND_SRC2, XC16X_OPERAND_SRDIV, XC16X_OPERAND_REGNAM, XC16X_OPERAND_UIMM2
370
 , XC16X_OPERAND_UIMM3, XC16X_OPERAND_UIMM4, XC16X_OPERAND_UIMM7, XC16X_OPERAND_UIMM8
371
 , XC16X_OPERAND_UIMM16, XC16X_OPERAND_UPOF16, XC16X_OPERAND_REG8, XC16X_OPERAND_REGMEM8
372
 , XC16X_OPERAND_REGBMEM8, XC16X_OPERAND_REGOFF8, XC16X_OPERAND_REGHI8, XC16X_OPERAND_REGB8
373
 , XC16X_OPERAND_GENREG, XC16X_OPERAND_SEG, XC16X_OPERAND_SEGHI8, XC16X_OPERAND_CADDR
374
 , XC16X_OPERAND_REL, XC16X_OPERAND_RELHI, XC16X_OPERAND_CONDBIT, XC16X_OPERAND_BIT1
375
 , XC16X_OPERAND_BIT2, XC16X_OPERAND_BIT4, XC16X_OPERAND_LBIT4, XC16X_OPERAND_LBIT2
376
 , XC16X_OPERAND_BIT8, XC16X_OPERAND_U4, XC16X_OPERAND_BITONE, XC16X_OPERAND_BIT01
377
 , XC16X_OPERAND_COND, XC16X_OPERAND_ICOND, XC16X_OPERAND_EXTCOND, XC16X_OPERAND_MEMORY
378
 , XC16X_OPERAND_MEMGR8, XC16X_OPERAND_CBIT, XC16X_OPERAND_QBIT, XC16X_OPERAND_QLOBIT
379
 , XC16X_OPERAND_QHIBIT, XC16X_OPERAND_MASK8, XC16X_OPERAND_MASKLO8, XC16X_OPERAND_PAGENUM
380
 , XC16X_OPERAND_DATA8, XC16X_OPERAND_DATAHI8, XC16X_OPERAND_SGTDISBIT, XC16X_OPERAND_UPAG16
381
 , XC16X_OPERAND_USEG8, XC16X_OPERAND_USEG16, XC16X_OPERAND_USOF16, XC16X_OPERAND_HASH
382
 , XC16X_OPERAND_DOT, XC16X_OPERAND_POF, XC16X_OPERAND_PAG, XC16X_OPERAND_SOF
383
 , XC16X_OPERAND_SEGM, XC16X_OPERAND_MAX
384
} CGEN_OPERAND_TYPE;
385
 
386
/* Number of operands types.  */
387
#define MAX_OPERANDS 65
388
 
389
/* Maximum number of operands referenced by any insn.  */
390
#define MAX_OPERAND_INSTANCES 8
391
 
392
/* Insn attribute indices.  */
393
 
394
/* Enum declaration for cgen_insn attrs.  */
395
typedef enum cgen_insn_attr {
396
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
397
 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
398
 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
399
 , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS
400
} CGEN_INSN_ATTR;
401
 
402
/* Number of non-boolean elements in cgen_insn_attr.  */
403
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
404
 
405
/* cgen_insn attribute accessor macros.  */
406
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
407
#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset)
408
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
409
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
410
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
411
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
412
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
413
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
414
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
415
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
416
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
417
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
418
 
419
/* cgen.h uses things we just defined.  */
420
#include "opcode/cgen.h"
421
 
422
extern const struct cgen_ifld xc16x_cgen_ifld_table[];
423
 
424
/* Attributes.  */
425
extern const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[];
426
extern const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[];
427
extern const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[];
428
extern const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[];
429
 
430
/* Hardware decls.  */
431
 
432
extern CGEN_KEYWORD xc16x_cgen_opval_gr_names;
433
extern CGEN_KEYWORD xc16x_cgen_opval_ext_names;
434
extern CGEN_KEYWORD xc16x_cgen_opval_psw_names;
435
extern CGEN_KEYWORD xc16x_cgen_opval_grb_names;
436
extern CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names;
437
extern CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names;
438
extern CGEN_KEYWORD xc16x_cgen_opval_grb8_names;
439
extern CGEN_KEYWORD xc16x_cgen_opval_r8_names;
440
extern CGEN_KEYWORD xc16x_cgen_opval_regmem8_names;
441
extern CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names;
442
extern CGEN_KEYWORD xc16x_cgen_opval_reg0_name;
443
extern CGEN_KEYWORD xc16x_cgen_opval_reg0_name1;
444
extern CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names;
445
extern CGEN_KEYWORD xc16x_cgen_opval_memgr8_names;
446
 
447
extern const CGEN_HW_ENTRY xc16x_cgen_hw_table[];
448
 
449
 
450
 
451
#endif /* XC16X_CPU_H */

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