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julius |
/* Definitions of target machine for GNU compiler, for ARM.
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Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
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Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
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and Martin Simmons (@harleqn.co.uk).
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More major hacks by Richard Earnshaw (rearnsha@arm.com)
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Minor hacks by Nick Clifton (nickc@cygnus.com)
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_ARM_H
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#define GCC_ARM_H
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/* The architecture define. */
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extern char arm_arch_name[];
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/* Target CPU builtins. */
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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{ \
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/* Define __arm__ even when in thumb mode, for \
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consistency with armcc. */ \
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builtin_define ("__arm__"); \
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builtin_define ("__APCS_32__"); \
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if (TARGET_THUMB) \
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builtin_define ("__thumb__"); \
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\
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if (TARGET_BIG_END) \
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{ \
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builtin_define ("__ARMEB__"); \
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if (TARGET_THUMB) \
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builtin_define ("__THUMBEB__"); \
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if (TARGET_LITTLE_WORDS) \
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builtin_define ("__ARMWEL__"); \
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} \
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else \
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{ \
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builtin_define ("__ARMEL__"); \
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if (TARGET_THUMB) \
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builtin_define ("__THUMBEL__"); \
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} \
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\
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if (TARGET_SOFT_FLOAT) \
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builtin_define ("__SOFTFP__"); \
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\
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if (TARGET_VFP) \
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builtin_define ("__VFP_FP__"); \
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\
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/* Add a define for interworking. \
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Needed when building libgcc.a. */ \
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if (arm_cpp_interwork) \
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builtin_define ("__THUMB_INTERWORK__"); \
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\
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builtin_assert ("cpu=arm"); \
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builtin_assert ("machine=arm"); \
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\
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builtin_define (arm_arch_name); \
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if (arm_arch_cirrus) \
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builtin_define ("__MAVERICK__"); \
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if (arm_arch_xscale) \
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builtin_define ("__XSCALE__"); \
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if (arm_arch_iwmmxt) \
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builtin_define ("__IWMMXT__"); \
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if (TARGET_AAPCS_BASED) \
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builtin_define ("__ARM_EABI__"); \
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} while (0)
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/* The various ARM cores. */
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enum processor_type
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{
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#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
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IDENT,
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#include "arm-cores.def"
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#undef ARM_CORE
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/* Used to indicate that no processor has been specified. */
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arm_none
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};
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enum target_cpus
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{
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#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
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TARGET_CPU_##IDENT,
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#include "arm-cores.def"
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#undef ARM_CORE
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TARGET_CPU_generic
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};
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/* The processor for which instructions should be scheduled. */
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extern enum processor_type arm_tune;
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typedef enum arm_cond_code
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{
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ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
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ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
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}
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arm_cc;
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extern arm_cc arm_current_cc;
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#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
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extern int arm_target_label;
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extern int arm_ccfsm_state;
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extern GTY(()) rtx arm_target_insn;
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/* Define the information needed to generate branch insns. This is
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stored from the compare operation. */
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extern GTY(()) rtx arm_compare_op0;
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extern GTY(()) rtx arm_compare_op1;
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/* The label of the current constant pool. */
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extern rtx pool_vector_label;
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/* Set to 1 when a return insn is output, this means that the epilogue
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is not needed. */
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extern int return_used_this_function;
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/* Used to produce AOF syntax assembler. */
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extern GTY(()) rtx aof_pic_label;
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/* Just in case configure has failed to define anything. */
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#ifndef TARGET_CPU_DEFAULT
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#define TARGET_CPU_DEFAULT TARGET_CPU_generic
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#endif
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#undef CPP_SPEC
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#define CPP_SPEC "%(subtarget_cpp_spec) \
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%{msoft-float:%{mhard-float: \
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%e-msoft-float and -mhard_float may not be used together}} \
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%{mbig-endian:%{mlittle-endian: \
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%e-mbig-endian and -mlittle-endian may not be used together}}"
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#ifndef CC1_SPEC
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#define CC1_SPEC ""
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#endif
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/* This macro defines names of additional specifications to put in the specs
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that can be used in various specifications like CC1_SPEC. Its definition
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is an initializer with a subgrouping for each command option.
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Each subgrouping contains a string constant, that defines the
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specification name, and a string constant that used by the GCC driver
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program.
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Do not define this macro if it does not need to do anything. */
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#define EXTRA_SPECS \
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{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
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SUBTARGET_EXTRA_SPECS
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#ifndef SUBTARGET_EXTRA_SPECS
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#define SUBTARGET_EXTRA_SPECS
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#endif
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#ifndef SUBTARGET_CPP_SPEC
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#define SUBTARGET_CPP_SPEC ""
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#endif
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/* Run-time Target Specification. */
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#ifndef TARGET_VERSION
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#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
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#endif
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#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
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/* Use hardware floating point instructions. */
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#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
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/* Use hardware floating point calling convention. */
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#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
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#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
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#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
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#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
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#define TARGET_IWMMXT (arm_arch_iwmmxt)
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#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
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#define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
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#define TARGET_ARM (! TARGET_THUMB)
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#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
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#define TARGET_BACKTRACE (leaf_function_p () \
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? TARGET_TPCS_LEAF_FRAME \
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: TARGET_TPCS_FRAME)
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#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
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#define TARGET_AAPCS_BASED \
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(arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
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#define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
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#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
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/* True iff the full BPABI is being used. If TARGET_BPABI is true,
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then TARGET_AAPCS_BASED must be true -- but the converse does not
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hold. TARGET_BPABI implies the use of the BPABI runtime library,
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etc., in addition to just the AAPCS calling conventions. */
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#ifndef TARGET_BPABI
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#define TARGET_BPABI false
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#endif
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/* Support for a compile-time default CPU, et cetera. The rules are:
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--with-arch is ignored if -march or -mcpu are specified.
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--with-cpu is ignored if -march or -mcpu are specified, and is overridden
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by --with-arch.
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--with-tune is ignored if -mtune or -mcpu are specified (but not affected
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by -march).
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--with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
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specified.
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--with-fpu is ignored if -mfpu is specified.
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--with-abi is ignored is -mabi is specified. */
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#define OPTION_DEFAULT_SPECS \
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{"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
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{"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
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{"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
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{"float", \
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"%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
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{"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
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{"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
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{"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
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| 225 |
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/* Which floating point model to use. */
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enum arm_fp_model
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{
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ARM_FP_MODEL_UNKNOWN,
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/* FPA model (Hardware or software). */
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ARM_FP_MODEL_FPA,
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/* Cirrus Maverick floating point model. */
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ARM_FP_MODEL_MAVERICK,
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/* VFP floating point model. */
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ARM_FP_MODEL_VFP
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};
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| 237 |
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extern enum arm_fp_model arm_fp_model;
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| 239 |
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/* Which floating point hardware is available. Also update
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fp_model_for_fpu in arm.c when adding entries to this list. */
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| 241 |
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enum fputype
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{
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/* No FP hardware. */
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FPUTYPE_NONE,
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/* Full FPA support. */
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FPUTYPE_FPA,
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/* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
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FPUTYPE_FPA_EMU2,
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/* Emulated FPA hardware, Issue 3 emulator. */
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FPUTYPE_FPA_EMU3,
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/* Cirrus Maverick floating point co-processor. */
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FPUTYPE_MAVERICK,
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/* VFP. */
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FPUTYPE_VFP
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};
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| 256 |
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| 257 |
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/* Recast the floating point class to be the floating point attribute. */
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| 258 |
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#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
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| 259 |
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| 260 |
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/* What type of floating point to tune for */
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| 261 |
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extern enum fputype arm_fpu_tune;
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| 262 |
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| 263 |
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/* What type of floating point instructions are available */
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| 264 |
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extern enum fputype arm_fpu_arch;
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| 265 |
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| 266 |
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enum float_abi_type
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| 267 |
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{
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| 268 |
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ARM_FLOAT_ABI_SOFT,
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| 269 |
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ARM_FLOAT_ABI_SOFTFP,
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| 270 |
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ARM_FLOAT_ABI_HARD
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| 271 |
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};
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| 272 |
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| 273 |
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extern enum float_abi_type arm_float_abi;
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| 274 |
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| 275 |
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#ifndef TARGET_DEFAULT_FLOAT_ABI
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| 276 |
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#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
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| 277 |
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#endif
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| 278 |
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| 279 |
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/* Which ABI to use. */
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| 280 |
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enum arm_abi_type
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| 281 |
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{
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| 282 |
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ARM_ABI_APCS,
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| 283 |
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ARM_ABI_ATPCS,
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| 284 |
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ARM_ABI_AAPCS,
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| 285 |
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ARM_ABI_IWMMXT,
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| 286 |
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ARM_ABI_AAPCS_LINUX
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| 287 |
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};
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| 288 |
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| 289 |
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extern enum arm_abi_type arm_abi;
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| 290 |
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| 291 |
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#ifndef ARM_DEFAULT_ABI
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| 292 |
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#define ARM_DEFAULT_ABI ARM_ABI_APCS
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| 293 |
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#endif
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| 294 |
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| 295 |
|
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/* Which thread pointer access sequence to use. */
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| 296 |
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enum arm_tp_type {
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| 297 |
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TP_AUTO,
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| 298 |
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TP_SOFT,
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| 299 |
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TP_CP15
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| 300 |
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};
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| 301 |
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| 302 |
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extern enum arm_tp_type target_thread_pointer;
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| 303 |
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| 304 |
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/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
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| 305 |
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extern int arm_arch3m;
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| 306 |
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| 307 |
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/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
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| 308 |
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extern int arm_arch4;
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| 309 |
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| 310 |
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/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
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| 311 |
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extern int arm_arch4t;
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| 312 |
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| 313 |
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/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
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| 314 |
|
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extern int arm_arch5;
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| 315 |
|
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|
| 316 |
|
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/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
|
| 317 |
|
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extern int arm_arch5e;
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| 318 |
|
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| 319 |
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/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
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| 320 |
|
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extern int arm_arch6;
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| 321 |
|
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| 322 |
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/* Nonzero if this chip can benefit from load scheduling. */
|
| 323 |
|
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extern int arm_ld_sched;
|
| 324 |
|
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| 325 |
|
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/* Nonzero if generating thumb code. */
|
| 326 |
|
|
extern int thumb_code;
|
| 327 |
|
|
|
| 328 |
|
|
/* Nonzero if this chip is a StrongARM. */
|
| 329 |
|
|
extern int arm_tune_strongarm;
|
| 330 |
|
|
|
| 331 |
|
|
/* Nonzero if this chip is a Cirrus variant. */
|
| 332 |
|
|
extern int arm_arch_cirrus;
|
| 333 |
|
|
|
| 334 |
|
|
/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
|
| 335 |
|
|
extern int arm_arch_iwmmxt;
|
| 336 |
|
|
|
| 337 |
|
|
/* Nonzero if this chip is an XScale. */
|
| 338 |
|
|
extern int arm_arch_xscale;
|
| 339 |
|
|
|
| 340 |
|
|
/* Nonzero if tuning for XScale. */
|
| 341 |
|
|
extern int arm_tune_xscale;
|
| 342 |
|
|
|
| 343 |
|
|
/* Nonzero if tuning for stores via the write buffer. */
|
| 344 |
|
|
extern int arm_tune_wbuf;
|
| 345 |
|
|
|
| 346 |
|
|
/* Nonzero if we should define __THUMB_INTERWORK__ in the
|
| 347 |
|
|
preprocessor.
|
| 348 |
|
|
XXX This is a bit of a hack, it's intended to help work around
|
| 349 |
|
|
problems in GLD which doesn't understand that armv5t code is
|
| 350 |
|
|
interworking clean. */
|
| 351 |
|
|
extern int arm_cpp_interwork;
|
| 352 |
|
|
|
| 353 |
|
|
#ifndef TARGET_DEFAULT
|
| 354 |
|
|
#define TARGET_DEFAULT (MASK_APCS_FRAME)
|
| 355 |
|
|
#endif
|
| 356 |
|
|
|
| 357 |
|
|
/* The frame pointer register used in gcc has nothing to do with debugging;
|
| 358 |
|
|
that is controlled by the APCS-FRAME option. */
|
| 359 |
|
|
#define CAN_DEBUG_WITHOUT_FP
|
| 360 |
|
|
|
| 361 |
|
|
#define OVERRIDE_OPTIONS arm_override_options ()
|
| 362 |
|
|
|
| 363 |
|
|
/* Nonzero if PIC code requires explicit qualifiers to generate
|
| 364 |
|
|
PLT and GOT relocs rather than the assembler doing so implicitly.
|
| 365 |
|
|
Subtargets can override these if required. */
|
| 366 |
|
|
#ifndef NEED_GOT_RELOC
|
| 367 |
|
|
#define NEED_GOT_RELOC 0
|
| 368 |
|
|
#endif
|
| 369 |
|
|
#ifndef NEED_PLT_RELOC
|
| 370 |
|
|
#define NEED_PLT_RELOC 0
|
| 371 |
|
|
#endif
|
| 372 |
|
|
|
| 373 |
|
|
/* Nonzero if we need to refer to the GOT with a PC-relative
|
| 374 |
|
|
offset. In other words, generate
|
| 375 |
|
|
|
| 376 |
|
|
.word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
|
| 377 |
|
|
|
| 378 |
|
|
rather than
|
| 379 |
|
|
|
| 380 |
|
|
.word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
|
| 381 |
|
|
|
| 382 |
|
|
The default is true, which matches NetBSD. Subtargets can
|
| 383 |
|
|
override this if required. */
|
| 384 |
|
|
#ifndef GOT_PCREL
|
| 385 |
|
|
#define GOT_PCREL 1
|
| 386 |
|
|
#endif
|
| 387 |
|
|
|
| 388 |
|
|
/* Target machine storage Layout. */
|
| 389 |
|
|
|
| 390 |
|
|
|
| 391 |
|
|
/* Define this macro if it is advisable to hold scalars in registers
|
| 392 |
|
|
in a wider mode than that declared by the program. In such cases,
|
| 393 |
|
|
the value is constrained to be within the bounds of the declared
|
| 394 |
|
|
type, but kept valid in the wider mode. The signedness of the
|
| 395 |
|
|
extension may differ from that of the type. */
|
| 396 |
|
|
|
| 397 |
|
|
/* It is far faster to zero extend chars than to sign extend them */
|
| 398 |
|
|
|
| 399 |
|
|
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
|
| 400 |
|
|
if (GET_MODE_CLASS (MODE) == MODE_INT \
|
| 401 |
|
|
&& GET_MODE_SIZE (MODE) < 4) \
|
| 402 |
|
|
{ \
|
| 403 |
|
|
if (MODE == QImode) \
|
| 404 |
|
|
UNSIGNEDP = 1; \
|
| 405 |
|
|
else if (MODE == HImode) \
|
| 406 |
|
|
UNSIGNEDP = 1; \
|
| 407 |
|
|
(MODE) = SImode; \
|
| 408 |
|
|
}
|
| 409 |
|
|
|
| 410 |
|
|
#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
|
| 411 |
|
|
if ((GET_MODE_CLASS (MODE) == MODE_INT \
|
| 412 |
|
|
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
|
| 413 |
|
|
&& GET_MODE_SIZE (MODE) < 4) \
|
| 414 |
|
|
(MODE) = SImode; \
|
| 415 |
|
|
|
| 416 |
|
|
/* Define this if most significant bit is lowest numbered
|
| 417 |
|
|
in instructions that operate on numbered bit-fields. */
|
| 418 |
|
|
#define BITS_BIG_ENDIAN 0
|
| 419 |
|
|
|
| 420 |
|
|
/* Define this if most significant byte of a word is the lowest numbered.
|
| 421 |
|
|
Most ARM processors are run in little endian mode, so that is the default.
|
| 422 |
|
|
If you want to have it run-time selectable, change the definition in a
|
| 423 |
|
|
cover file to be TARGET_BIG_ENDIAN. */
|
| 424 |
|
|
#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
|
| 425 |
|
|
|
| 426 |
|
|
/* Define this if most significant word of a multiword number is the lowest
|
| 427 |
|
|
numbered.
|
| 428 |
|
|
This is always false, even when in big-endian mode. */
|
| 429 |
|
|
#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
|
| 430 |
|
|
|
| 431 |
|
|
/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
|
| 432 |
|
|
on processor pre-defineds when compiling libgcc2.c. */
|
| 433 |
|
|
#if defined(__ARMEB__) && !defined(__ARMWEL__)
|
| 434 |
|
|
#define LIBGCC2_WORDS_BIG_ENDIAN 1
|
| 435 |
|
|
#else
|
| 436 |
|
|
#define LIBGCC2_WORDS_BIG_ENDIAN 0
|
| 437 |
|
|
#endif
|
| 438 |
|
|
|
| 439 |
|
|
/* Define this if most significant word of doubles is the lowest numbered.
|
| 440 |
|
|
The rules are different based on whether or not we use FPA-format,
|
| 441 |
|
|
VFP-format or some other floating point co-processor's format doubles. */
|
| 442 |
|
|
#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
|
| 443 |
|
|
|
| 444 |
|
|
#define UNITS_PER_WORD 4
|
| 445 |
|
|
|
| 446 |
|
|
/* True if natural alignment is used for doubleword types. */
|
| 447 |
|
|
#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
|
| 448 |
|
|
|
| 449 |
|
|
#define DOUBLEWORD_ALIGNMENT 64
|
| 450 |
|
|
|
| 451 |
|
|
#define PARM_BOUNDARY 32
|
| 452 |
|
|
|
| 453 |
|
|
#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
|
| 454 |
|
|
|
| 455 |
|
|
#define PREFERRED_STACK_BOUNDARY \
|
| 456 |
|
|
(arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
|
| 457 |
|
|
|
| 458 |
|
|
#define FUNCTION_BOUNDARY 32
|
| 459 |
|
|
|
| 460 |
|
|
/* The lowest bit is used to indicate Thumb-mode functions, so the
|
| 461 |
|
|
vbit must go into the delta field of pointers to member
|
| 462 |
|
|
functions. */
|
| 463 |
|
|
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
|
| 464 |
|
|
|
| 465 |
|
|
#define EMPTY_FIELD_BOUNDARY 32
|
| 466 |
|
|
|
| 467 |
|
|
#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
|
| 468 |
|
|
|
| 469 |
|
|
/* XXX Blah -- this macro is used directly by libobjc. Since it
|
| 470 |
|
|
supports no vector modes, cut out the complexity and fall back
|
| 471 |
|
|
on BIGGEST_FIELD_ALIGNMENT. */
|
| 472 |
|
|
#ifdef IN_TARGET_LIBS
|
| 473 |
|
|
#define BIGGEST_FIELD_ALIGNMENT 64
|
| 474 |
|
|
#endif
|
| 475 |
|
|
|
| 476 |
|
|
/* Make strings word-aligned so strcpy from constants will be faster. */
|
| 477 |
|
|
#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
|
| 478 |
|
|
|
| 479 |
|
|
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
|
| 480 |
|
|
((TREE_CODE (EXP) == STRING_CST \
|
| 481 |
|
|
&& (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
|
| 482 |
|
|
? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
|
| 483 |
|
|
|
| 484 |
|
|
/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
|
| 485 |
|
|
value set in previous versions of this toolchain was 8, which produces more
|
| 486 |
|
|
compact structures. The command line option -mstructure_size_boundary=<n>
|
| 487 |
|
|
can be used to change this value. For compatibility with the ARM SDK
|
| 488 |
|
|
however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
|
| 489 |
|
|
0020D) page 2-20 says "Structures are aligned on word boundaries".
|
| 490 |
|
|
The AAPCS specifies a value of 8. */
|
| 491 |
|
|
#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
|
| 492 |
|
|
extern int arm_structure_size_boundary;
|
| 493 |
|
|
|
| 494 |
|
|
/* This is the value used to initialize arm_structure_size_boundary. If a
|
| 495 |
|
|
particular arm target wants to change the default value it should change
|
| 496 |
|
|
the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
|
| 497 |
|
|
for an example of this. */
|
| 498 |
|
|
#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
|
| 499 |
|
|
#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
|
| 500 |
|
|
#endif
|
| 501 |
|
|
|
| 502 |
|
|
/* Nonzero if move instructions will actually fail to work
|
| 503 |
|
|
when given unaligned data. */
|
| 504 |
|
|
#define STRICT_ALIGNMENT 1
|
| 505 |
|
|
|
| 506 |
|
|
/* wchar_t is unsigned under the AAPCS. */
|
| 507 |
|
|
#ifndef WCHAR_TYPE
|
| 508 |
|
|
#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
|
| 509 |
|
|
|
| 510 |
|
|
#define WCHAR_TYPE_SIZE BITS_PER_WORD
|
| 511 |
|
|
#endif
|
| 512 |
|
|
|
| 513 |
|
|
#ifndef SIZE_TYPE
|
| 514 |
|
|
#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
|
| 515 |
|
|
#endif
|
| 516 |
|
|
|
| 517 |
|
|
#ifndef PTRDIFF_TYPE
|
| 518 |
|
|
#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
|
| 519 |
|
|
#endif
|
| 520 |
|
|
|
| 521 |
|
|
/* AAPCS requires that structure alignment is affected by bitfields. */
|
| 522 |
|
|
#ifndef PCC_BITFIELD_TYPE_MATTERS
|
| 523 |
|
|
#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
|
| 524 |
|
|
#endif
|
| 525 |
|
|
|
| 526 |
|
|
|
| 527 |
|
|
/* Standard register usage. */
|
| 528 |
|
|
|
| 529 |
|
|
/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
|
| 530 |
|
|
(S - saved over call).
|
| 531 |
|
|
|
| 532 |
|
|
r0 * argument word/integer result
|
| 533 |
|
|
r1-r3 argument word
|
| 534 |
|
|
|
| 535 |
|
|
r4-r8 S register variable
|
| 536 |
|
|
r9 S (rfp) register variable (real frame pointer)
|
| 537 |
|
|
|
| 538 |
|
|
r10 F S (sl) stack limit (used by -mapcs-stack-check)
|
| 539 |
|
|
r11 F S (fp) argument pointer
|
| 540 |
|
|
r12 (ip) temp workspace
|
| 541 |
|
|
r13 F S (sp) lower end of current stack frame
|
| 542 |
|
|
r14 (lr) link address/workspace
|
| 543 |
|
|
r15 F (pc) program counter
|
| 544 |
|
|
|
| 545 |
|
|
f0 floating point result
|
| 546 |
|
|
f1-f3 floating point scratch
|
| 547 |
|
|
|
| 548 |
|
|
f4-f7 S floating point variable
|
| 549 |
|
|
|
| 550 |
|
|
cc This is NOT a real register, but is used internally
|
| 551 |
|
|
to represent things that use or set the condition
|
| 552 |
|
|
codes.
|
| 553 |
|
|
sfp This isn't either. It is used during rtl generation
|
| 554 |
|
|
since the offset between the frame pointer and the
|
| 555 |
|
|
auto's isn't known until after register allocation.
|
| 556 |
|
|
afp Nor this, we only need this because of non-local
|
| 557 |
|
|
goto. Without it fp appears to be used and the
|
| 558 |
|
|
elimination code won't get rid of sfp. It tracks
|
| 559 |
|
|
fp exactly at all times.
|
| 560 |
|
|
|
| 561 |
|
|
*: See CONDITIONAL_REGISTER_USAGE */
|
| 562 |
|
|
|
| 563 |
|
|
/*
|
| 564 |
|
|
mvf0 Cirrus floating point result
|
| 565 |
|
|
mvf1-mvf3 Cirrus floating point scratch
|
| 566 |
|
|
mvf4-mvf15 S Cirrus floating point variable. */
|
| 567 |
|
|
|
| 568 |
|
|
/* s0-s15 VFP scratch (aka d0-d7).
|
| 569 |
|
|
s16-s31 S VFP variable (aka d8-d15).
|
| 570 |
|
|
vfpcc Not a real register. Represents the VFP condition
|
| 571 |
|
|
code flags. */
|
| 572 |
|
|
|
| 573 |
|
|
/* The stack backtrace structure is as follows:
|
| 574 |
|
|
fp points to here: | save code pointer | [fp]
|
| 575 |
|
|
| return link value | [fp, #-4]
|
| 576 |
|
|
| return sp value | [fp, #-8]
|
| 577 |
|
|
| return fp value | [fp, #-12]
|
| 578 |
|
|
[| saved r10 value |]
|
| 579 |
|
|
[| saved r9 value |]
|
| 580 |
|
|
[| saved r8 value |]
|
| 581 |
|
|
[| saved r7 value |]
|
| 582 |
|
|
[| saved r6 value |]
|
| 583 |
|
|
[| saved r5 value |]
|
| 584 |
|
|
[| saved r4 value |]
|
| 585 |
|
|
[| saved r3 value |]
|
| 586 |
|
|
[| saved r2 value |]
|
| 587 |
|
|
[| saved r1 value |]
|
| 588 |
|
|
[| saved r0 value |]
|
| 589 |
|
|
[| saved f7 value |] three words
|
| 590 |
|
|
[| saved f6 value |] three words
|
| 591 |
|
|
[| saved f5 value |] three words
|
| 592 |
|
|
[| saved f4 value |] three words
|
| 593 |
|
|
r0-r3 are not normally saved in a C function. */
|
| 594 |
|
|
|
| 595 |
|
|
/* 1 for registers that have pervasive standard uses
|
| 596 |
|
|
and are not available for the register allocator. */
|
| 597 |
|
|
#define FIXED_REGISTERS \
|
| 598 |
|
|
{ \
|
| 599 |
|
|
0,0,0,0,0,0,0,0, \
|
| 600 |
|
|
0,0,0,0,0,1,0,1, \
|
| 601 |
|
|
0,0,0,0,0,0,0,0, \
|
| 602 |
|
|
1,1,1, \
|
| 603 |
|
|
1,1,1,1,1,1,1,1, \
|
| 604 |
|
|
1,1,1,1,1,1,1,1, \
|
| 605 |
|
|
1,1,1,1,1,1,1,1, \
|
| 606 |
|
|
1,1,1,1,1,1,1,1, \
|
| 607 |
|
|
1,1,1,1, \
|
| 608 |
|
|
1,1,1,1,1,1,1,1, \
|
| 609 |
|
|
1,1,1,1,1,1,1,1, \
|
| 610 |
|
|
1,1,1,1,1,1,1,1, \
|
| 611 |
|
|
1,1,1,1,1,1,1,1, \
|
| 612 |
|
|
1 \
|
| 613 |
|
|
}
|
| 614 |
|
|
|
| 615 |
|
|
/* 1 for registers not available across function calls.
|
| 616 |
|
|
These must include the FIXED_REGISTERS and also any
|
| 617 |
|
|
registers that can be used without being saved.
|
| 618 |
|
|
The latter must include the registers where values are returned
|
| 619 |
|
|
and the register where structure-value addresses are passed.
|
| 620 |
|
|
Aside from that, you can include as many other registers as you like.
|
| 621 |
|
|
The CC is not preserved over function calls on the ARM 6, so it is
|
| 622 |
|
|
easier to assume this for all. SFP is preserved, since FP is. */
|
| 623 |
|
|
#define CALL_USED_REGISTERS \
|
| 624 |
|
|
{ \
|
| 625 |
|
|
1,1,1,1,0,0,0,0, \
|
| 626 |
|
|
0,0,0,0,1,1,1,1, \
|
| 627 |
|
|
1,1,1,1,0,0,0,0, \
|
| 628 |
|
|
1,1,1, \
|
| 629 |
|
|
1,1,1,1,1,1,1,1, \
|
| 630 |
|
|
1,1,1,1,1,1,1,1, \
|
| 631 |
|
|
1,1,1,1,1,1,1,1, \
|
| 632 |
|
|
1,1,1,1,1,1,1,1, \
|
| 633 |
|
|
1,1,1,1, \
|
| 634 |
|
|
1,1,1,1,1,1,1,1, \
|
| 635 |
|
|
1,1,1,1,1,1,1,1, \
|
| 636 |
|
|
1,1,1,1,1,1,1,1, \
|
| 637 |
|
|
1,1,1,1,1,1,1,1, \
|
| 638 |
|
|
1 \
|
| 639 |
|
|
}
|
| 640 |
|
|
|
| 641 |
|
|
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
|
| 642 |
|
|
#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
|
| 643 |
|
|
#endif
|
| 644 |
|
|
|
| 645 |
|
|
#define CONDITIONAL_REGISTER_USAGE \
|
| 646 |
|
|
{ \
|
| 647 |
|
|
int regno; \
|
| 648 |
|
|
\
|
| 649 |
|
|
if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
|
| 650 |
|
|
{ \
|
| 651 |
|
|
for (regno = FIRST_FPA_REGNUM; \
|
| 652 |
|
|
regno <= LAST_FPA_REGNUM; ++regno) \
|
| 653 |
|
|
fixed_regs[regno] = call_used_regs[regno] = 1; \
|
| 654 |
|
|
} \
|
| 655 |
|
|
\
|
| 656 |
|
|
if (TARGET_THUMB && optimize_size) \
|
| 657 |
|
|
{ \
|
| 658 |
|
|
/* When optimizing for size, it's better not to use \
|
| 659 |
|
|
the HI regs, because of the overhead of stacking \
|
| 660 |
|
|
them. */ \
|
| 661 |
|
|
for (regno = FIRST_HI_REGNUM; \
|
| 662 |
|
|
regno <= LAST_HI_REGNUM; ++regno) \
|
| 663 |
|
|
fixed_regs[regno] = call_used_regs[regno] = 1; \
|
| 664 |
|
|
} \
|
| 665 |
|
|
\
|
| 666 |
|
|
/* The link register can be clobbered by any branch insn, \
|
| 667 |
|
|
but we have no way to track that at present, so mark \
|
| 668 |
|
|
it as unavailable. */ \
|
| 669 |
|
|
if (TARGET_THUMB) \
|
| 670 |
|
|
fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
|
| 671 |
|
|
\
|
| 672 |
|
|
if (TARGET_ARM && TARGET_HARD_FLOAT) \
|
| 673 |
|
|
{ \
|
| 674 |
|
|
if (TARGET_MAVERICK) \
|
| 675 |
|
|
{ \
|
| 676 |
|
|
for (regno = FIRST_FPA_REGNUM; \
|
| 677 |
|
|
regno <= LAST_FPA_REGNUM; ++ regno) \
|
| 678 |
|
|
fixed_regs[regno] = call_used_regs[regno] = 1; \
|
| 679 |
|
|
for (regno = FIRST_CIRRUS_FP_REGNUM; \
|
| 680 |
|
|
regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
|
| 681 |
|
|
{ \
|
| 682 |
|
|
fixed_regs[regno] = 0; \
|
| 683 |
|
|
call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
|
| 684 |
|
|
} \
|
| 685 |
|
|
} \
|
| 686 |
|
|
if (TARGET_VFP) \
|
| 687 |
|
|
{ \
|
| 688 |
|
|
for (regno = FIRST_VFP_REGNUM; \
|
| 689 |
|
|
regno <= LAST_VFP_REGNUM; ++ regno) \
|
| 690 |
|
|
{ \
|
| 691 |
|
|
fixed_regs[regno] = 0; \
|
| 692 |
|
|
call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
|
| 693 |
|
|
} \
|
| 694 |
|
|
} \
|
| 695 |
|
|
} \
|
| 696 |
|
|
\
|
| 697 |
|
|
if (TARGET_REALLY_IWMMXT) \
|
| 698 |
|
|
{ \
|
| 699 |
|
|
regno = FIRST_IWMMXT_GR_REGNUM; \
|
| 700 |
|
|
/* The 2002/10/09 revision of the XScale ABI has wCG0 \
|
| 701 |
|
|
and wCG1 as call-preserved registers. The 2002/11/21 \
|
| 702 |
|
|
revision changed this so that all wCG registers are \
|
| 703 |
|
|
scratch registers. */ \
|
| 704 |
|
|
for (regno = FIRST_IWMMXT_GR_REGNUM; \
|
| 705 |
|
|
regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
|
| 706 |
|
|
fixed_regs[regno] = 0; \
|
| 707 |
|
|
/* The XScale ABI has wR0 - wR9 as scratch registers, \
|
| 708 |
|
|
the rest as call-preserved registers. */ \
|
| 709 |
|
|
for (regno = FIRST_IWMMXT_REGNUM; \
|
| 710 |
|
|
regno <= LAST_IWMMXT_REGNUM; ++ regno) \
|
| 711 |
|
|
{ \
|
| 712 |
|
|
fixed_regs[regno] = 0; \
|
| 713 |
|
|
call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
|
| 714 |
|
|
} \
|
| 715 |
|
|
} \
|
| 716 |
|
|
\
|
| 717 |
|
|
if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
|
| 718 |
|
|
{ \
|
| 719 |
|
|
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
|
| 720 |
|
|
call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
|
| 721 |
|
|
} \
|
| 722 |
|
|
else if (TARGET_APCS_STACK) \
|
| 723 |
|
|
{ \
|
| 724 |
|
|
fixed_regs[10] = 1; \
|
| 725 |
|
|
call_used_regs[10] = 1; \
|
| 726 |
|
|
} \
|
| 727 |
|
|
/* -mcaller-super-interworking reserves r11 for calls to \
|
| 728 |
|
|
_interwork_r11_call_via_rN(). Making the register global \
|
| 729 |
|
|
is an easy way of ensuring that it remains valid for all \
|
| 730 |
|
|
calls. */ \
|
| 731 |
|
|
if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
|
| 732 |
|
|
|| TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
|
| 733 |
|
|
{ \
|
| 734 |
|
|
fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
|
| 735 |
|
|
call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
|
| 736 |
|
|
if (TARGET_CALLER_INTERWORKING) \
|
| 737 |
|
|
global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
|
| 738 |
|
|
} \
|
| 739 |
|
|
SUBTARGET_CONDITIONAL_REGISTER_USAGE \
|
| 740 |
|
|
}
|
| 741 |
|
|
|
| 742 |
|
|
/* These are a couple of extensions to the formats accepted
|
| 743 |
|
|
by asm_fprintf:
|
| 744 |
|
|
%@ prints out ASM_COMMENT_START
|
| 745 |
|
|
%r prints out REGISTER_PREFIX reg_names[arg] */
|
| 746 |
|
|
#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
|
| 747 |
|
|
case '@': \
|
| 748 |
|
|
fputs (ASM_COMMENT_START, FILE); \
|
| 749 |
|
|
break; \
|
| 750 |
|
|
\
|
| 751 |
|
|
case 'r': \
|
| 752 |
|
|
fputs (REGISTER_PREFIX, FILE); \
|
| 753 |
|
|
fputs (reg_names [va_arg (ARGS, int)], FILE); \
|
| 754 |
|
|
break;
|
| 755 |
|
|
|
| 756 |
|
|
/* Round X up to the nearest word. */
|
| 757 |
|
|
#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
|
| 758 |
|
|
|
| 759 |
|
|
/* Convert fron bytes to ints. */
|
| 760 |
|
|
#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
| 761 |
|
|
|
| 762 |
|
|
/* The number of (integer) registers required to hold a quantity of type MODE.
|
| 763 |
|
|
Also used for VFP registers. */
|
| 764 |
|
|
#define ARM_NUM_REGS(MODE) \
|
| 765 |
|
|
ARM_NUM_INTS (GET_MODE_SIZE (MODE))
|
| 766 |
|
|
|
| 767 |
|
|
/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
|
| 768 |
|
|
#define ARM_NUM_REGS2(MODE, TYPE) \
|
| 769 |
|
|
ARM_NUM_INTS ((MODE) == BLKmode ? \
|
| 770 |
|
|
int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
|
| 771 |
|
|
|
| 772 |
|
|
/* The number of (integer) argument register available. */
|
| 773 |
|
|
#define NUM_ARG_REGS 4
|
| 774 |
|
|
|
| 775 |
|
|
/* Return the register number of the N'th (integer) argument. */
|
| 776 |
|
|
#define ARG_REGISTER(N) (N - 1)
|
| 777 |
|
|
|
| 778 |
|
|
/* Specify the registers used for certain standard purposes.
|
| 779 |
|
|
The values of these macros are register numbers. */
|
| 780 |
|
|
|
| 781 |
|
|
/* The number of the last argument register. */
|
| 782 |
|
|
#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
|
| 783 |
|
|
|
| 784 |
|
|
/* The numbers of the Thumb register ranges. */
|
| 785 |
|
|
#define FIRST_LO_REGNUM 0
|
| 786 |
|
|
#define LAST_LO_REGNUM 7
|
| 787 |
|
|
#define FIRST_HI_REGNUM 8
|
| 788 |
|
|
#define LAST_HI_REGNUM 11
|
| 789 |
|
|
|
| 790 |
|
|
#ifndef TARGET_UNWIND_INFO
|
| 791 |
|
|
/* We use sjlj exceptions for backwards compatibility. */
|
| 792 |
|
|
#define MUST_USE_SJLJ_EXCEPTIONS 1
|
| 793 |
|
|
#endif
|
| 794 |
|
|
|
| 795 |
|
|
/* We can generate DWARF2 Unwind info, even though we don't use it. */
|
| 796 |
|
|
#define DWARF2_UNWIND_INFO 1
|
| 797 |
|
|
|
| 798 |
|
|
/* Use r0 and r1 to pass exception handling information. */
|
| 799 |
|
|
#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
|
| 800 |
|
|
|
| 801 |
|
|
/* The register that holds the return address in exception handlers. */
|
| 802 |
|
|
#define ARM_EH_STACKADJ_REGNUM 2
|
| 803 |
|
|
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
|
| 804 |
|
|
|
| 805 |
|
|
/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
|
| 806 |
|
|
as an invisible last argument (possible since varargs don't exist in
|
| 807 |
|
|
Pascal), so the following is not true. */
|
| 808 |
|
|
#define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
|
| 809 |
|
|
|
| 810 |
|
|
/* Define this to be where the real frame pointer is if it is not possible to
|
| 811 |
|
|
work out the offset between the frame pointer and the automatic variables
|
| 812 |
|
|
until after register allocation has taken place. FRAME_POINTER_REGNUM
|
| 813 |
|
|
should point to a special register that we will make sure is eliminated.
|
| 814 |
|
|
|
| 815 |
|
|
For the Thumb we have another problem. The TPCS defines the frame pointer
|
| 816 |
|
|
as r11, and GCC believes that it is always possible to use the frame pointer
|
| 817 |
|
|
as base register for addressing purposes. (See comments in
|
| 818 |
|
|
find_reloads_address()). But - the Thumb does not allow high registers,
|
| 819 |
|
|
including r11, to be used as base address registers. Hence our problem.
|
| 820 |
|
|
|
| 821 |
|
|
The solution used here, and in the old thumb port is to use r7 instead of
|
| 822 |
|
|
r11 as the hard frame pointer and to have special code to generate
|
| 823 |
|
|
backtrace structures on the stack (if required to do so via a command line
|
| 824 |
|
|
option) using r11. This is the only 'user visible' use of r11 as a frame
|
| 825 |
|
|
pointer. */
|
| 826 |
|
|
#define ARM_HARD_FRAME_POINTER_REGNUM 11
|
| 827 |
|
|
#define THUMB_HARD_FRAME_POINTER_REGNUM 7
|
| 828 |
|
|
|
| 829 |
|
|
#define HARD_FRAME_POINTER_REGNUM \
|
| 830 |
|
|
(TARGET_ARM \
|
| 831 |
|
|
? ARM_HARD_FRAME_POINTER_REGNUM \
|
| 832 |
|
|
: THUMB_HARD_FRAME_POINTER_REGNUM)
|
| 833 |
|
|
|
| 834 |
|
|
#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
|
| 835 |
|
|
|
| 836 |
|
|
/* Register to use for pushing function arguments. */
|
| 837 |
|
|
#define STACK_POINTER_REGNUM SP_REGNUM
|
| 838 |
|
|
|
| 839 |
|
|
/* ARM floating pointer registers. */
|
| 840 |
|
|
#define FIRST_FPA_REGNUM 16
|
| 841 |
|
|
#define LAST_FPA_REGNUM 23
|
| 842 |
|
|
#define IS_FPA_REGNUM(REGNUM) \
|
| 843 |
|
|
(((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
|
| 844 |
|
|
|
| 845 |
|
|
#define FIRST_IWMMXT_GR_REGNUM 43
|
| 846 |
|
|
#define LAST_IWMMXT_GR_REGNUM 46
|
| 847 |
|
|
#define FIRST_IWMMXT_REGNUM 47
|
| 848 |
|
|
#define LAST_IWMMXT_REGNUM 62
|
| 849 |
|
|
#define IS_IWMMXT_REGNUM(REGNUM) \
|
| 850 |
|
|
(((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
|
| 851 |
|
|
#define IS_IWMMXT_GR_REGNUM(REGNUM) \
|
| 852 |
|
|
(((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
|
| 853 |
|
|
|
| 854 |
|
|
/* Base register for access to local variables of the function. */
|
| 855 |
|
|
#define FRAME_POINTER_REGNUM 25
|
| 856 |
|
|
|
| 857 |
|
|
/* Base register for access to arguments of the function. */
|
| 858 |
|
|
#define ARG_POINTER_REGNUM 26
|
| 859 |
|
|
|
| 860 |
|
|
#define FIRST_CIRRUS_FP_REGNUM 27
|
| 861 |
|
|
#define LAST_CIRRUS_FP_REGNUM 42
|
| 862 |
|
|
#define IS_CIRRUS_REGNUM(REGNUM) \
|
| 863 |
|
|
(((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
|
| 864 |
|
|
|
| 865 |
|
|
#define FIRST_VFP_REGNUM 63
|
| 866 |
|
|
#define LAST_VFP_REGNUM 94
|
| 867 |
|
|
#define IS_VFP_REGNUM(REGNUM) \
|
| 868 |
|
|
(((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
|
| 869 |
|
|
|
| 870 |
|
|
/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
|
| 871 |
|
|
/* + 16 Cirrus registers take us up to 43. */
|
| 872 |
|
|
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
|
| 873 |
|
|
/* VFP adds 32 + 1 more. */
|
| 874 |
|
|
#define FIRST_PSEUDO_REGISTER 96
|
| 875 |
|
|
|
| 876 |
|
|
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
|
| 877 |
|
|
|
| 878 |
|
|
/* Value should be nonzero if functions must have frame pointers.
|
| 879 |
|
|
Zero means the frame pointer need not be set up (and parms may be accessed
|
| 880 |
|
|
via the stack pointer) in functions that seem suitable.
|
| 881 |
|
|
If we have to have a frame pointer we might as well make use of it.
|
| 882 |
|
|
APCS says that the frame pointer does not need to be pushed in leaf
|
| 883 |
|
|
functions, or simple tail call functions. */
|
| 884 |
|
|
|
| 885 |
|
|
#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
|
| 886 |
|
|
#define SUBTARGET_FRAME_POINTER_REQUIRED 0
|
| 887 |
|
|
#endif
|
| 888 |
|
|
|
| 889 |
|
|
#define FRAME_POINTER_REQUIRED \
|
| 890 |
|
|
(current_function_has_nonlocal_label \
|
| 891 |
|
|
|| SUBTARGET_FRAME_POINTER_REQUIRED \
|
| 892 |
|
|
|| (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
|
| 893 |
|
|
|
| 894 |
|
|
/* Return number of consecutive hard regs needed starting at reg REGNO
|
| 895 |
|
|
to hold something of mode MODE.
|
| 896 |
|
|
This is ordinarily the length in words of a value of mode MODE
|
| 897 |
|
|
but can be less for certain modes in special long registers.
|
| 898 |
|
|
|
| 899 |
|
|
On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
|
| 900 |
|
|
mode. */
|
| 901 |
|
|
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
| 902 |
|
|
((TARGET_ARM \
|
| 903 |
|
|
&& REGNO >= FIRST_FPA_REGNUM \
|
| 904 |
|
|
&& REGNO != FRAME_POINTER_REGNUM \
|
| 905 |
|
|
&& REGNO != ARG_POINTER_REGNUM) \
|
| 906 |
|
|
&& !IS_VFP_REGNUM (REGNO) \
|
| 907 |
|
|
? 1 : ARM_NUM_REGS (MODE))
|
| 908 |
|
|
|
| 909 |
|
|
/* Return true if REGNO is suitable for holding a quantity of type MODE. */
|
| 910 |
|
|
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
|
| 911 |
|
|
arm_hard_regno_mode_ok ((REGNO), (MODE))
|
| 912 |
|
|
|
| 913 |
|
|
/* Value is 1 if it is a good idea to tie two pseudo registers
|
| 914 |
|
|
when one has mode MODE1 and one has mode MODE2.
|
| 915 |
|
|
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
|
| 916 |
|
|
for any hard reg, then this must be 0 for correct output. */
|
| 917 |
|
|
#define MODES_TIEABLE_P(MODE1, MODE2) \
|
| 918 |
|
|
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
|
| 919 |
|
|
|
| 920 |
|
|
#define VALID_IWMMXT_REG_MODE(MODE) \
|
| 921 |
|
|
(arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
|
| 922 |
|
|
|
| 923 |
|
|
/* The order in which register should be allocated. It is good to use ip
|
| 924 |
|
|
since no saving is required (though calls clobber it) and it never contains
|
| 925 |
|
|
function parameters. It is quite good to use lr since other calls may
|
| 926 |
|
|
clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
|
| 927 |
|
|
least likely to contain a function parameter; in addition results are
|
| 928 |
|
|
returned in r0. */
|
| 929 |
|
|
|
| 930 |
|
|
#define REG_ALLOC_ORDER \
|
| 931 |
|
|
{ \
|
| 932 |
|
|
3, 2, 1, 0, 12, 14, 4, 5, \
|
| 933 |
|
|
6, 7, 8, 10, 9, 11, 13, 15, \
|
| 934 |
|
|
16, 17, 18, 19, 20, 21, 22, 23, \
|
| 935 |
|
|
27, 28, 29, 30, 31, 32, 33, 34, \
|
| 936 |
|
|
35, 36, 37, 38, 39, 40, 41, 42, \
|
| 937 |
|
|
43, 44, 45, 46, 47, 48, 49, 50, \
|
| 938 |
|
|
51, 52, 53, 54, 55, 56, 57, 58, \
|
| 939 |
|
|
59, 60, 61, 62, \
|
| 940 |
|
|
24, 25, 26, \
|
| 941 |
|
|
78, 77, 76, 75, 74, 73, 72, 71, \
|
| 942 |
|
|
70, 69, 68, 67, 66, 65, 64, 63, \
|
| 943 |
|
|
79, 80, 81, 82, 83, 84, 85, 86, \
|
| 944 |
|
|
87, 88, 89, 90, 91, 92, 93, 94, \
|
| 945 |
|
|
95 \
|
| 946 |
|
|
}
|
| 947 |
|
|
|
| 948 |
|
|
/* Interrupt functions can only use registers that have already been
|
| 949 |
|
|
saved by the prologue, even if they would normally be
|
| 950 |
|
|
call-clobbered. */
|
| 951 |
|
|
#define HARD_REGNO_RENAME_OK(SRC, DST) \
|
| 952 |
|
|
(! IS_INTERRUPT (cfun->machine->func_type) || \
|
| 953 |
|
|
regs_ever_live[DST])
|
| 954 |
|
|
|
| 955 |
|
|
/* Register and constant classes. */
|
| 956 |
|
|
|
| 957 |
|
|
/* Register classes: used to be simple, just all ARM regs or all FPA regs
|
| 958 |
|
|
Now that the Thumb is involved it has become more complicated. */
|
| 959 |
|
|
enum reg_class
|
| 960 |
|
|
{
|
| 961 |
|
|
NO_REGS,
|
| 962 |
|
|
FPA_REGS,
|
| 963 |
|
|
CIRRUS_REGS,
|
| 964 |
|
|
VFP_REGS,
|
| 965 |
|
|
IWMMXT_GR_REGS,
|
| 966 |
|
|
IWMMXT_REGS,
|
| 967 |
|
|
LO_REGS,
|
| 968 |
|
|
STACK_REG,
|
| 969 |
|
|
BASE_REGS,
|
| 970 |
|
|
HI_REGS,
|
| 971 |
|
|
CC_REG,
|
| 972 |
|
|
VFPCC_REG,
|
| 973 |
|
|
GENERAL_REGS,
|
| 974 |
|
|
ALL_REGS,
|
| 975 |
|
|
LIM_REG_CLASSES
|
| 976 |
|
|
};
|
| 977 |
|
|
|
| 978 |
|
|
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
| 979 |
|
|
|
| 980 |
|
|
/* Give names of register classes as strings for dump file. */
|
| 981 |
|
|
#define REG_CLASS_NAMES \
|
| 982 |
|
|
{ \
|
| 983 |
|
|
"NO_REGS", \
|
| 984 |
|
|
"FPA_REGS", \
|
| 985 |
|
|
"CIRRUS_REGS", \
|
| 986 |
|
|
"VFP_REGS", \
|
| 987 |
|
|
"IWMMXT_GR_REGS", \
|
| 988 |
|
|
"IWMMXT_REGS", \
|
| 989 |
|
|
"LO_REGS", \
|
| 990 |
|
|
"STACK_REG", \
|
| 991 |
|
|
"BASE_REGS", \
|
| 992 |
|
|
"HI_REGS", \
|
| 993 |
|
|
"CC_REG", \
|
| 994 |
|
|
"VFPCC_REG", \
|
| 995 |
|
|
"GENERAL_REGS", \
|
| 996 |
|
|
"ALL_REGS", \
|
| 997 |
|
|
}
|
| 998 |
|
|
|
| 999 |
|
|
/* Define which registers fit in which classes.
|
| 1000 |
|
|
This is an initializer for a vector of HARD_REG_SET
|
| 1001 |
|
|
of length N_REG_CLASSES. */
|
| 1002 |
|
|
#define REG_CLASS_CONTENTS \
|
| 1003 |
|
|
{ \
|
| 1004 |
|
|
{ 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
|
| 1005 |
|
|
{ 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
|
| 1006 |
|
|
{ 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
|
| 1007 |
|
|
{ 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
|
| 1008 |
|
|
{ 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
|
| 1009 |
|
|
{ 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
|
| 1010 |
|
|
{ 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
|
| 1011 |
|
|
{ 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
|
| 1012 |
|
|
{ 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
|
| 1013 |
|
|
{ 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
|
| 1014 |
|
|
{ 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
|
| 1015 |
|
|
{ 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
|
| 1016 |
|
|
{ 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
|
| 1017 |
|
|
{ 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
|
| 1018 |
|
|
}
|
| 1019 |
|
|
|
| 1020 |
|
|
/* The same information, inverted:
|
| 1021 |
|
|
Return the class number of the smallest class containing
|
| 1022 |
|
|
reg number REGNO. This could be a conditional expression
|
| 1023 |
|
|
or could index an array. */
|
| 1024 |
|
|
#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
|
| 1025 |
|
|
|
| 1026 |
|
|
/* FPA registers can't do subreg as all values are reformatted to internal
|
| 1027 |
|
|
precision. VFP registers may only be accessed in the mode they
|
| 1028 |
|
|
were set. */
|
| 1029 |
|
|
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
|
| 1030 |
|
|
(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
|
| 1031 |
|
|
? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
|
| 1032 |
|
|
|| reg_classes_intersect_p (VFP_REGS, (CLASS)) \
|
| 1033 |
|
|
: 0)
|
| 1034 |
|
|
|
| 1035 |
|
|
/* We need to define this for LO_REGS on thumb. Otherwise we can end up
|
| 1036 |
|
|
using r0-r4 for function arguments, r7 for the stack frame and don't
|
| 1037 |
|
|
have enough left over to do doubleword arithmetic. */
|
| 1038 |
|
|
#define CLASS_LIKELY_SPILLED_P(CLASS) \
|
| 1039 |
|
|
((TARGET_THUMB && (CLASS) == LO_REGS) \
|
| 1040 |
|
|
|| (CLASS) == CC_REG)
|
| 1041 |
|
|
|
| 1042 |
|
|
/* The class value for index registers, and the one for base regs. */
|
| 1043 |
|
|
#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
|
| 1044 |
|
|
#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
|
| 1045 |
|
|
|
| 1046 |
|
|
/* For the Thumb the high registers cannot be used as base registers
|
| 1047 |
|
|
when addressing quantities in QI or HI mode; if we don't know the
|
| 1048 |
|
|
mode, then we must be conservative. */
|
| 1049 |
|
|
#define MODE_BASE_REG_CLASS(MODE) \
|
| 1050 |
|
|
(TARGET_ARM ? GENERAL_REGS : \
|
| 1051 |
|
|
(((MODE) == SImode) ? BASE_REGS : LO_REGS))
|
| 1052 |
|
|
|
| 1053 |
|
|
/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
|
| 1054 |
|
|
instead of BASE_REGS. */
|
| 1055 |
|
|
#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
|
| 1056 |
|
|
|
| 1057 |
|
|
/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
|
| 1058 |
|
|
registers explicitly used in the rtl to be used as spill registers
|
| 1059 |
|
|
but prevents the compiler from extending the lifetime of these
|
| 1060 |
|
|
registers. */
|
| 1061 |
|
|
#define SMALL_REGISTER_CLASSES TARGET_THUMB
|
| 1062 |
|
|
|
| 1063 |
|
|
/* Given an rtx X being reloaded into a reg required to be
|
| 1064 |
|
|
in class CLASS, return the class of reg to actually use.
|
| 1065 |
|
|
In general this is just CLASS, but for the Thumb we prefer
|
| 1066 |
|
|
a LO_REGS class or a subset. */
|
| 1067 |
|
|
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
|
| 1068 |
|
|
(TARGET_ARM ? (CLASS) : \
|
| 1069 |
|
|
((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
|
| 1070 |
|
|
|
| 1071 |
|
|
/* Must leave BASE_REGS reloads alone */
|
| 1072 |
|
|
#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
|
| 1073 |
|
|
((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
|
| 1074 |
|
|
? ((true_regnum (X) == -1 ? LO_REGS \
|
| 1075 |
|
|
: (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
|
| 1076 |
|
|
: NO_REGS)) \
|
| 1077 |
|
|
: NO_REGS)
|
| 1078 |
|
|
|
| 1079 |
|
|
#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
|
| 1080 |
|
|
((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
|
| 1081 |
|
|
? ((true_regnum (X) == -1 ? LO_REGS \
|
| 1082 |
|
|
: (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
|
| 1083 |
|
|
: NO_REGS)) \
|
| 1084 |
|
|
: NO_REGS)
|
| 1085 |
|
|
|
| 1086 |
|
|
/* Return the register class of a scratch register needed to copy IN into
|
| 1087 |
|
|
or out of a register in CLASS in MODE. If it can be done directly,
|
| 1088 |
|
|
NO_REGS is returned. */
|
| 1089 |
|
|
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
|
| 1090 |
|
|
/* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
|
| 1091 |
|
|
((TARGET_VFP && TARGET_HARD_FLOAT \
|
| 1092 |
|
|
&& (CLASS) == VFP_REGS) \
|
| 1093 |
|
|
? coproc_secondary_reload_class (MODE, X, FALSE) \
|
| 1094 |
|
|
: (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
|
| 1095 |
|
|
? coproc_secondary_reload_class (MODE, X, TRUE) \
|
| 1096 |
|
|
: TARGET_ARM \
|
| 1097 |
|
|
? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
|
| 1098 |
|
|
? GENERAL_REGS : NO_REGS) \
|
| 1099 |
|
|
: THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
|
| 1100 |
|
|
|
| 1101 |
|
|
/* If we need to load shorts byte-at-a-time, then we need a scratch. */
|
| 1102 |
|
|
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
|
| 1103 |
|
|
/* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
|
| 1104 |
|
|
((TARGET_VFP && TARGET_HARD_FLOAT \
|
| 1105 |
|
|
&& (CLASS) == VFP_REGS) \
|
| 1106 |
|
|
? coproc_secondary_reload_class (MODE, X, FALSE) : \
|
| 1107 |
|
|
(TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
|
| 1108 |
|
|
coproc_secondary_reload_class (MODE, X, TRUE) : \
|
| 1109 |
|
|
/* Cannot load constants into Cirrus registers. */ \
|
| 1110 |
|
|
(TARGET_MAVERICK && TARGET_HARD_FLOAT \
|
| 1111 |
|
|
&& (CLASS) == CIRRUS_REGS \
|
| 1112 |
|
|
&& (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
|
| 1113 |
|
|
? GENERAL_REGS : \
|
| 1114 |
|
|
(TARGET_ARM ? \
|
| 1115 |
|
|
(((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
|
| 1116 |
|
|
&& CONSTANT_P (X)) \
|
| 1117 |
|
|
? GENERAL_REGS : \
|
| 1118 |
|
|
(((MODE) == HImode && ! arm_arch4 \
|
| 1119 |
|
|
&& (GET_CODE (X) == MEM \
|
| 1120 |
|
|
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
|
| 1121 |
|
|
&& true_regnum (X) == -1))) \
|
| 1122 |
|
|
? GENERAL_REGS : NO_REGS) \
|
| 1123 |
|
|
: THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
|
| 1124 |
|
|
|
| 1125 |
|
|
/* Try a machine-dependent way of reloading an illegitimate address
|
| 1126 |
|
|
operand. If we find one, push the reload and jump to WIN. This
|
| 1127 |
|
|
macro is used in only one place: `find_reloads_address' in reload.c.
|
| 1128 |
|
|
|
| 1129 |
|
|
For the ARM, we wish to handle large displacements off a base
|
| 1130 |
|
|
register by splitting the addend across a MOV and the mem insn.
|
| 1131 |
|
|
This can cut the number of reloads needed. */
|
| 1132 |
|
|
#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
|
| 1133 |
|
|
do \
|
| 1134 |
|
|
{ \
|
| 1135 |
|
|
if (GET_CODE (X) == PLUS \
|
| 1136 |
|
|
&& GET_CODE (XEXP (X, 0)) == REG \
|
| 1137 |
|
|
&& REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
|
| 1138 |
|
|
&& REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
|
| 1139 |
|
|
&& GET_CODE (XEXP (X, 1)) == CONST_INT) \
|
| 1140 |
|
|
{ \
|
| 1141 |
|
|
HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
|
| 1142 |
|
|
HOST_WIDE_INT low, high; \
|
| 1143 |
|
|
\
|
| 1144 |
|
|
if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
|
| 1145 |
|
|
low = ((val & 0xf) ^ 0x8) - 0x8; \
|
| 1146 |
|
|
else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
|
| 1147 |
|
|
/* Need to be careful, -256 is not a valid offset. */ \
|
| 1148 |
|
|
low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
|
| 1149 |
|
|
else if (MODE == SImode \
|
| 1150 |
|
|
|| (MODE == SFmode && TARGET_SOFT_FLOAT) \
|
| 1151 |
|
|
|| ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
|
| 1152 |
|
|
/* Need to be careful, -4096 is not a valid offset. */ \
|
| 1153 |
|
|
low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
|
| 1154 |
|
|
else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
|
| 1155 |
|
|
/* Need to be careful, -256 is not a valid offset. */ \
|
| 1156 |
|
|
low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
|
| 1157 |
|
|
else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
| 1158 |
|
|
&& TARGET_HARD_FLOAT && TARGET_FPA) \
|
| 1159 |
|
|
/* Need to be careful, -1024 is not a valid offset. */ \
|
| 1160 |
|
|
low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
|
| 1161 |
|
|
else \
|
| 1162 |
|
|
break; \
|
| 1163 |
|
|
\
|
| 1164 |
|
|
high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
|
| 1165 |
|
|
^ (unsigned HOST_WIDE_INT) 0x80000000) \
|
| 1166 |
|
|
- (unsigned HOST_WIDE_INT) 0x80000000); \
|
| 1167 |
|
|
/* Check for overflow or zero */ \
|
| 1168 |
|
|
if (low == 0 || high == 0 || (high + low != val)) \
|
| 1169 |
|
|
break; \
|
| 1170 |
|
|
\
|
| 1171 |
|
|
/* Reload the high part into a base reg; leave the low part \
|
| 1172 |
|
|
in the mem. */ \
|
| 1173 |
|
|
X = gen_rtx_PLUS (GET_MODE (X), \
|
| 1174 |
|
|
gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
|
| 1175 |
|
|
GEN_INT (high)), \
|
| 1176 |
|
|
GEN_INT (low)); \
|
| 1177 |
|
|
push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
|
| 1178 |
|
|
MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
|
| 1179 |
|
|
VOIDmode, 0, 0, OPNUM, TYPE); \
|
| 1180 |
|
|
goto WIN; \
|
| 1181 |
|
|
} \
|
| 1182 |
|
|
} \
|
| 1183 |
|
|
while (0)
|
| 1184 |
|
|
|
| 1185 |
|
|
/* XXX If an HImode FP+large_offset address is converted to an HImode
|
| 1186 |
|
|
SP+large_offset address, then reload won't know how to fix it. It sees
|
| 1187 |
|
|
only that SP isn't valid for HImode, and so reloads the SP into an index
|
| 1188 |
|
|
register, but the resulting address is still invalid because the offset
|
| 1189 |
|
|
is too big. We fix it here instead by reloading the entire address. */
|
| 1190 |
|
|
/* We could probably achieve better results by defining PROMOTE_MODE to help
|
| 1191 |
|
|
cope with the variances between the Thumb's signed and unsigned byte and
|
| 1192 |
|
|
halfword load instructions. */
|
| 1193 |
|
|
#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
|
| 1194 |
|
|
do { \
|
| 1195 |
|
|
rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
|
| 1196 |
|
|
if (new_x) \
|
| 1197 |
|
|
{ \
|
| 1198 |
|
|
X = new_x; \
|
| 1199 |
|
|
goto WIN; \
|
| 1200 |
|
|
} \
|
| 1201 |
|
|
} while (0)
|
| 1202 |
|
|
|
| 1203 |
|
|
#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
|
| 1204 |
|
|
if (TARGET_ARM) \
|
| 1205 |
|
|
ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
|
| 1206 |
|
|
else \
|
| 1207 |
|
|
THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
|
| 1208 |
|
|
|
| 1209 |
|
|
/* Return the maximum number of consecutive registers
|
| 1210 |
|
|
needed to represent mode MODE in a register of class CLASS.
|
| 1211 |
|
|
ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
|
| 1212 |
|
|
#define CLASS_MAX_NREGS(CLASS, MODE) \
|
| 1213 |
|
|
(((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
|
| 1214 |
|
|
|
| 1215 |
|
|
/* If defined, gives a class of registers that cannot be used as the
|
| 1216 |
|
|
operand of a SUBREG that changes the mode of the object illegally. */
|
| 1217 |
|
|
|
| 1218 |
|
|
/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
|
| 1219 |
|
|
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
|
| 1220 |
|
|
(TARGET_ARM ? \
|
| 1221 |
|
|
((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
|
| 1222 |
|
|
(FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
|
| 1223 |
|
|
(FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
|
| 1224 |
|
|
(FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
|
| 1225 |
|
|
(FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
|
| 1226 |
|
|
(FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
|
| 1227 |
|
|
(FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
|
| 1228 |
|
|
(FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
|
| 1229 |
|
|
(FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
|
| 1230 |
|
|
2) \
|
| 1231 |
|
|
: \
|
| 1232 |
|
|
((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
|
| 1233 |
|
|
|
| 1234 |
|
|
/* Stack layout; function entry, exit and calling. */
|
| 1235 |
|
|
|
| 1236 |
|
|
/* Define this if pushing a word on the stack
|
| 1237 |
|
|
makes the stack pointer a smaller address. */
|
| 1238 |
|
|
#define STACK_GROWS_DOWNWARD 1
|
| 1239 |
|
|
|
| 1240 |
|
|
/* Define this to nonzero if the nominal address of the stack frame
|
| 1241 |
|
|
is at the high-address end of the local variables;
|
| 1242 |
|
|
that is, each additional local variable allocated
|
| 1243 |
|
|
goes at a more negative offset in the frame. */
|
| 1244 |
|
|
#define FRAME_GROWS_DOWNWARD 1
|
| 1245 |
|
|
|
| 1246 |
|
|
/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
|
| 1247 |
|
|
When present, it is one word in size, and sits at the top of the frame,
|
| 1248 |
|
|
between the soft frame pointer and either r7 or r11.
|
| 1249 |
|
|
|
| 1250 |
|
|
We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
|
| 1251 |
|
|
and only then if some outgoing arguments are passed on the stack. It would
|
| 1252 |
|
|
be tempting to also check whether the stack arguments are passed by indirect
|
| 1253 |
|
|
calls, but there seems to be no reason in principle why a post-reload pass
|
| 1254 |
|
|
couldn't convert a direct call into an indirect one. */
|
| 1255 |
|
|
#define CALLER_INTERWORKING_SLOT_SIZE \
|
| 1256 |
|
|
(TARGET_CALLER_INTERWORKING \
|
| 1257 |
|
|
&& current_function_outgoing_args_size != 0 \
|
| 1258 |
|
|
? UNITS_PER_WORD : 0)
|
| 1259 |
|
|
|
| 1260 |
|
|
/* Offset within stack frame to start allocating local variables at.
|
| 1261 |
|
|
If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
|
| 1262 |
|
|
first local allocated. Otherwise, it is the offset to the BEGINNING
|
| 1263 |
|
|
of the first local allocated. */
|
| 1264 |
|
|
#define STARTING_FRAME_OFFSET 0
|
| 1265 |
|
|
|
| 1266 |
|
|
/* If we generate an insn to push BYTES bytes,
|
| 1267 |
|
|
this says how many the stack pointer really advances by. */
|
| 1268 |
|
|
/* The push insns do not do this rounding implicitly.
|
| 1269 |
|
|
So don't define this. */
|
| 1270 |
|
|
/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
|
| 1271 |
|
|
|
| 1272 |
|
|
/* Define this if the maximum size of all the outgoing args is to be
|
| 1273 |
|
|
accumulated and pushed during the prologue. The amount can be
|
| 1274 |
|
|
found in the variable current_function_outgoing_args_size. */
|
| 1275 |
|
|
#define ACCUMULATE_OUTGOING_ARGS 1
|
| 1276 |
|
|
|
| 1277 |
|
|
/* Offset of first parameter from the argument pointer register value. */
|
| 1278 |
|
|
#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
|
| 1279 |
|
|
|
| 1280 |
|
|
/* Value is the number of byte of arguments automatically
|
| 1281 |
|
|
popped when returning from a subroutine call.
|
| 1282 |
|
|
FUNDECL is the declaration node of the function (as a tree),
|
| 1283 |
|
|
FUNTYPE is the data type of the function (as a tree),
|
| 1284 |
|
|
or for a library call it is an identifier node for the subroutine name.
|
| 1285 |
|
|
SIZE is the number of bytes of arguments passed on the stack.
|
| 1286 |
|
|
|
| 1287 |
|
|
On the ARM, the caller does not pop any of its arguments that were passed
|
| 1288 |
|
|
on the stack. */
|
| 1289 |
|
|
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
|
| 1290 |
|
|
|
| 1291 |
|
|
/* Define how to find the value returned by a library function
|
| 1292 |
|
|
assuming the value has mode MODE. */
|
| 1293 |
|
|
#define LIBCALL_VALUE(MODE) \
|
| 1294 |
|
|
(TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
|
| 1295 |
|
|
&& GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
| 1296 |
|
|
? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
|
| 1297 |
|
|
: TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
|
| 1298 |
|
|
&& GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
| 1299 |
|
|
? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
|
| 1300 |
|
|
: TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
|
| 1301 |
|
|
? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
|
| 1302 |
|
|
: gen_rtx_REG (MODE, ARG_REGISTER (1)))
|
| 1303 |
|
|
|
| 1304 |
|
|
/* Define how to find the value returned by a function.
|
| 1305 |
|
|
VALTYPE is the data type of the value (as a tree).
|
| 1306 |
|
|
If the precise function being called is known, FUNC is its FUNCTION_DECL;
|
| 1307 |
|
|
otherwise, FUNC is 0. */
|
| 1308 |
|
|
#define FUNCTION_VALUE(VALTYPE, FUNC) \
|
| 1309 |
|
|
arm_function_value (VALTYPE, FUNC);
|
| 1310 |
|
|
|
| 1311 |
|
|
/* 1 if N is a possible register number for a function value.
|
| 1312 |
|
|
On the ARM, only r0 and f0 can return results. */
|
| 1313 |
|
|
/* On a Cirrus chip, mvf0 can return results. */
|
| 1314 |
|
|
#define FUNCTION_VALUE_REGNO_P(REGNO) \
|
| 1315 |
|
|
((REGNO) == ARG_REGISTER (1) \
|
| 1316 |
|
|
|| (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
|
| 1317 |
|
|
&& TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
|
| 1318 |
|
|
|| ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
|
| 1319 |
|
|
|| (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
|
| 1320 |
|
|
&& TARGET_HARD_FLOAT_ABI && TARGET_FPA))
|
| 1321 |
|
|
|
| 1322 |
|
|
/* Amount of memory needed for an untyped call to save all possible return
|
| 1323 |
|
|
registers. */
|
| 1324 |
|
|
#define APPLY_RESULT_SIZE arm_apply_result_size()
|
| 1325 |
|
|
|
| 1326 |
|
|
/* How large values are returned */
|
| 1327 |
|
|
/* A C expression which can inhibit the returning of certain function values
|
| 1328 |
|
|
in registers, based on the type of value. */
|
| 1329 |
|
|
#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
|
| 1330 |
|
|
|
| 1331 |
|
|
/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
|
| 1332 |
|
|
values must be in memory. On the ARM, they need only do so if larger
|
| 1333 |
|
|
than a word, or if they contain elements offset from zero in the struct. */
|
| 1334 |
|
|
#define DEFAULT_PCC_STRUCT_RETURN 0
|
| 1335 |
|
|
|
| 1336 |
|
|
/* Flags for the call/call_value rtl operations set up by function_arg. */
|
| 1337 |
|
|
#define CALL_NORMAL 0x00000000 /* No special processing. */
|
| 1338 |
|
|
#define CALL_LONG 0x00000001 /* Always call indirect. */
|
| 1339 |
|
|
#define CALL_SHORT 0x00000002 /* Never call indirect. */
|
| 1340 |
|
|
|
| 1341 |
|
|
/* These bits describe the different types of function supported
|
| 1342 |
|
|
by the ARM backend. They are exclusive. i.e. a function cannot be both a
|
| 1343 |
|
|
normal function and an interworked function, for example. Knowing the
|
| 1344 |
|
|
type of a function is important for determining its prologue and
|
| 1345 |
|
|
epilogue sequences.
|
| 1346 |
|
|
Note value 7 is currently unassigned. Also note that the interrupt
|
| 1347 |
|
|
function types all have bit 2 set, so that they can be tested for easily.
|
| 1348 |
|
|
Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
|
| 1349 |
|
|
machine_function structure is initialized (to zero) func_type will
|
| 1350 |
|
|
default to unknown. This will force the first use of arm_current_func_type
|
| 1351 |
|
|
to call arm_compute_func_type. */
|
| 1352 |
|
|
#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
|
| 1353 |
|
|
#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
|
| 1354 |
|
|
#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
|
| 1355 |
|
|
#define ARM_FT_ISR 4 /* An interrupt service routine. */
|
| 1356 |
|
|
#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
|
| 1357 |
|
|
#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
|
| 1358 |
|
|
|
| 1359 |
|
|
#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
|
| 1360 |
|
|
|
| 1361 |
|
|
/* In addition functions can have several type modifiers,
|
| 1362 |
|
|
outlined by these bit masks: */
|
| 1363 |
|
|
#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
|
| 1364 |
|
|
#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
|
| 1365 |
|
|
#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
|
| 1366 |
|
|
#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
|
| 1367 |
|
|
|
| 1368 |
|
|
/* Some macros to test these flags. */
|
| 1369 |
|
|
#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
|
| 1370 |
|
|
#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
|
| 1371 |
|
|
#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
|
| 1372 |
|
|
#define IS_NAKED(t) (t & ARM_FT_NAKED)
|
| 1373 |
|
|
#define IS_NESTED(t) (t & ARM_FT_NESTED)
|
| 1374 |
|
|
|
| 1375 |
|
|
|
| 1376 |
|
|
/* Structure used to hold the function stack frame layout. Offsets are
|
| 1377 |
|
|
relative to the stack pointer on function entry. Positive offsets are
|
| 1378 |
|
|
in the direction of stack growth.
|
| 1379 |
|
|
Only soft_frame is used in thumb mode. */
|
| 1380 |
|
|
|
| 1381 |
|
|
typedef struct arm_stack_offsets GTY(())
|
| 1382 |
|
|
{
|
| 1383 |
|
|
int saved_args; /* ARG_POINTER_REGNUM. */
|
| 1384 |
|
|
int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
|
| 1385 |
|
|
int saved_regs;
|
| 1386 |
|
|
int soft_frame; /* FRAME_POINTER_REGNUM. */
|
| 1387 |
|
|
int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
|
| 1388 |
|
|
int outgoing_args; /* STACK_POINTER_REGNUM. */
|
| 1389 |
|
|
}
|
| 1390 |
|
|
arm_stack_offsets;
|
| 1391 |
|
|
|
| 1392 |
|
|
/* A C structure for machine-specific, per-function data.
|
| 1393 |
|
|
This is added to the cfun structure. */
|
| 1394 |
|
|
typedef struct machine_function GTY(())
|
| 1395 |
|
|
{
|
| 1396 |
|
|
/* Additional stack adjustment in __builtin_eh_throw. */
|
| 1397 |
|
|
rtx eh_epilogue_sp_ofs;
|
| 1398 |
|
|
/* Records if LR has to be saved for far jumps. */
|
| 1399 |
|
|
int far_jump_used;
|
| 1400 |
|
|
/* Records if ARG_POINTER was ever live. */
|
| 1401 |
|
|
int arg_pointer_live;
|
| 1402 |
|
|
/* Records if the save of LR has been eliminated. */
|
| 1403 |
|
|
int lr_save_eliminated;
|
| 1404 |
|
|
/* The size of the stack frame. Only valid after reload. */
|
| 1405 |
|
|
arm_stack_offsets stack_offsets;
|
| 1406 |
|
|
/* Records the type of the current function. */
|
| 1407 |
|
|
unsigned long func_type;
|
| 1408 |
|
|
/* Record if the function has a variable argument list. */
|
| 1409 |
|
|
int uses_anonymous_args;
|
| 1410 |
|
|
/* Records if sibcalls are blocked because an argument
|
| 1411 |
|
|
register is needed to preserve stack alignment. */
|
| 1412 |
|
|
int sibcall_blocked;
|
| 1413 |
|
|
/* The PIC register for this function. This might be a pseudo. */
|
| 1414 |
|
|
rtx pic_reg;
|
| 1415 |
|
|
/* Labels for per-function Thumb call-via stubs. One per potential calling
|
| 1416 |
|
|
register. We can never call via LR or PC. We can call via SP if a
|
| 1417 |
|
|
trampoline happens to be on the top of the stack. */
|
| 1418 |
|
|
rtx call_via[14];
|
| 1419 |
|
|
}
|
| 1420 |
|
|
machine_function;
|
| 1421 |
|
|
|
| 1422 |
|
|
/* As in the machine_function, a global set of call-via labels, for code
|
| 1423 |
|
|
that is in text_section. */
|
| 1424 |
|
|
extern GTY(()) rtx thumb_call_via_label[14];
|
| 1425 |
|
|
|
| 1426 |
|
|
/* A C type for declaring a variable that is used as the first argument of
|
| 1427 |
|
|
`FUNCTION_ARG' and other related values. For some target machines, the
|
| 1428 |
|
|
type `int' suffices and can hold the number of bytes of argument so far. */
|
| 1429 |
|
|
typedef struct
|
| 1430 |
|
|
{
|
| 1431 |
|
|
/* This is the number of registers of arguments scanned so far. */
|
| 1432 |
|
|
int nregs;
|
| 1433 |
|
|
/* This is the number of iWMMXt register arguments scanned so far. */
|
| 1434 |
|
|
int iwmmxt_nregs;
|
| 1435 |
|
|
int named_count;
|
| 1436 |
|
|
int nargs;
|
| 1437 |
|
|
/* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
|
| 1438 |
|
|
int call_cookie;
|
| 1439 |
|
|
int can_split;
|
| 1440 |
|
|
} CUMULATIVE_ARGS;
|
| 1441 |
|
|
|
| 1442 |
|
|
/* Define where to put the arguments to a function.
|
| 1443 |
|
|
Value is zero to push the argument on the stack,
|
| 1444 |
|
|
or a hard register in which to store the argument.
|
| 1445 |
|
|
|
| 1446 |
|
|
MODE is the argument's machine mode.
|
| 1447 |
|
|
TYPE is the data type of the argument (as a tree).
|
| 1448 |
|
|
This is null for libcalls where that information may
|
| 1449 |
|
|
not be available.
|
| 1450 |
|
|
CUM is a variable of type CUMULATIVE_ARGS which gives info about
|
| 1451 |
|
|
the preceding args and about the function being called.
|
| 1452 |
|
|
NAMED is nonzero if this argument is a named parameter
|
| 1453 |
|
|
(otherwise it is an extra parameter matching an ellipsis).
|
| 1454 |
|
|
|
| 1455 |
|
|
On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
|
| 1456 |
|
|
other arguments are passed on the stack. If (NAMED == 0) (which happens
|
| 1457 |
|
|
only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
|
| 1458 |
|
|
defined), say it is passed in the stack (function_prologue will
|
| 1459 |
|
|
indeed make it pass in the stack if necessary). */
|
| 1460 |
|
|
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
| 1461 |
|
|
arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
|
| 1462 |
|
|
|
| 1463 |
|
|
#define FUNCTION_ARG_PADDING(MODE, TYPE) \
|
| 1464 |
|
|
(arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
|
| 1465 |
|
|
|
| 1466 |
|
|
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
|
| 1467 |
|
|
(arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
|
| 1468 |
|
|
|
| 1469 |
|
|
/* For AAPCS, padding should never be below the argument. For other ABIs,
|
| 1470 |
|
|
* mimic the default. */
|
| 1471 |
|
|
#define PAD_VARARGS_DOWN \
|
| 1472 |
|
|
((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
|
| 1473 |
|
|
|
| 1474 |
|
|
/* Initialize a variable CUM of type CUMULATIVE_ARGS
|
| 1475 |
|
|
for a call to a function whose data type is FNTYPE.
|
| 1476 |
|
|
For a library call, FNTYPE is 0.
|
| 1477 |
|
|
On the ARM, the offset starts at 0. */
|
| 1478 |
|
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
|
| 1479 |
|
|
arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
|
| 1480 |
|
|
|
| 1481 |
|
|
/* Update the data in CUM to advance over an argument
|
| 1482 |
|
|
of mode MODE and data type TYPE.
|
| 1483 |
|
|
(TYPE is null for libcalls where that information may not be available.) */
|
| 1484 |
|
|
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
| 1485 |
|
|
(CUM).nargs += 1; \
|
| 1486 |
|
|
if (arm_vector_mode_supported_p (MODE) \
|
| 1487 |
|
|
&& (CUM).named_count > (CUM).nargs) \
|
| 1488 |
|
|
(CUM).iwmmxt_nregs += 1; \
|
| 1489 |
|
|
else \
|
| 1490 |
|
|
(CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
|
| 1491 |
|
|
|
| 1492 |
|
|
/* If defined, a C expression that gives the alignment boundary, in bits, of an
|
| 1493 |
|
|
argument with the specified mode and type. If it is not defined,
|
| 1494 |
|
|
`PARM_BOUNDARY' is used for all arguments. */
|
| 1495 |
|
|
#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
|
| 1496 |
|
|
((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
|
| 1497 |
|
|
? DOUBLEWORD_ALIGNMENT \
|
| 1498 |
|
|
: PARM_BOUNDARY )
|
| 1499 |
|
|
|
| 1500 |
|
|
/* 1 if N is a possible register number for function argument passing.
|
| 1501 |
|
|
On the ARM, r0-r3 are used to pass args. */
|
| 1502 |
|
|
#define FUNCTION_ARG_REGNO_P(REGNO) \
|
| 1503 |
|
|
(IN_RANGE ((REGNO), 0, 3) \
|
| 1504 |
|
|
|| (TARGET_IWMMXT_ABI \
|
| 1505 |
|
|
&& IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
|
| 1506 |
|
|
|
| 1507 |
|
|
|
| 1508 |
|
|
/* If your target environment doesn't prefix user functions with an
|
| 1509 |
|
|
underscore, you may wish to re-define this to prevent any conflicts.
|
| 1510 |
|
|
e.g. AOF may prefix mcount with an underscore. */
|
| 1511 |
|
|
#ifndef ARM_MCOUNT_NAME
|
| 1512 |
|
|
#define ARM_MCOUNT_NAME "*mcount"
|
| 1513 |
|
|
#endif
|
| 1514 |
|
|
|
| 1515 |
|
|
/* Call the function profiler with a given profile label. The Acorn
|
| 1516 |
|
|
compiler puts this BEFORE the prolog but gcc puts it afterwards.
|
| 1517 |
|
|
On the ARM the full profile code will look like:
|
| 1518 |
|
|
.data
|
| 1519 |
|
|
LP1
|
| 1520 |
|
|
.word 0
|
| 1521 |
|
|
.text
|
| 1522 |
|
|
mov ip, lr
|
| 1523 |
|
|
bl mcount
|
| 1524 |
|
|
.word LP1
|
| 1525 |
|
|
|
| 1526 |
|
|
profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
|
| 1527 |
|
|
will output the .text section.
|
| 1528 |
|
|
|
| 1529 |
|
|
The ``mov ip,lr'' seems like a good idea to stick with cc convention.
|
| 1530 |
|
|
``prof'' doesn't seem to mind about this!
|
| 1531 |
|
|
|
| 1532 |
|
|
Note - this version of the code is designed to work in both ARM and
|
| 1533 |
|
|
Thumb modes. */
|
| 1534 |
|
|
#ifndef ARM_FUNCTION_PROFILER
|
| 1535 |
|
|
#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
|
| 1536 |
|
|
{ \
|
| 1537 |
|
|
char temp[20]; \
|
| 1538 |
|
|
rtx sym; \
|
| 1539 |
|
|
\
|
| 1540 |
|
|
asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
|
| 1541 |
|
|
IP_REGNUM, LR_REGNUM); \
|
| 1542 |
|
|
assemble_name (STREAM, ARM_MCOUNT_NAME); \
|
| 1543 |
|
|
fputc ('\n', STREAM); \
|
| 1544 |
|
|
ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
|
| 1545 |
|
|
sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
|
| 1546 |
|
|
assemble_aligned_integer (UNITS_PER_WORD, sym); \
|
| 1547 |
|
|
}
|
| 1548 |
|
|
#endif
|
| 1549 |
|
|
|
| 1550 |
|
|
#ifdef THUMB_FUNCTION_PROFILER
|
| 1551 |
|
|
#define FUNCTION_PROFILER(STREAM, LABELNO) \
|
| 1552 |
|
|
if (TARGET_ARM) \
|
| 1553 |
|
|
ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
|
| 1554 |
|
|
else \
|
| 1555 |
|
|
THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
|
| 1556 |
|
|
#else
|
| 1557 |
|
|
#define FUNCTION_PROFILER(STREAM, LABELNO) \
|
| 1558 |
|
|
ARM_FUNCTION_PROFILER (STREAM, LABELNO)
|
| 1559 |
|
|
#endif
|
| 1560 |
|
|
|
| 1561 |
|
|
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
|
| 1562 |
|
|
the stack pointer does not matter. The value is tested only in
|
| 1563 |
|
|
functions that have frame pointers.
|
| 1564 |
|
|
No definition is equivalent to always zero.
|
| 1565 |
|
|
|
| 1566 |
|
|
On the ARM, the function epilogue recovers the stack pointer from the
|
| 1567 |
|
|
frame. */
|
| 1568 |
|
|
#define EXIT_IGNORE_STACK 1
|
| 1569 |
|
|
|
| 1570 |
|
|
#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
|
| 1571 |
|
|
|
| 1572 |
|
|
/* Determine if the epilogue should be output as RTL.
|
| 1573 |
|
|
You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
|
| 1574 |
|
|
#define USE_RETURN_INSN(ISCOND) \
|
| 1575 |
|
|
(TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
|
| 1576 |
|
|
|
| 1577 |
|
|
/* Definitions for register eliminations.
|
| 1578 |
|
|
|
| 1579 |
|
|
This is an array of structures. Each structure initializes one pair
|
| 1580 |
|
|
of eliminable registers. The "from" register number is given first,
|
| 1581 |
|
|
followed by "to". Eliminations of the same "from" register are listed
|
| 1582 |
|
|
in order of preference.
|
| 1583 |
|
|
|
| 1584 |
|
|
We have two registers that can be eliminated on the ARM. First, the
|
| 1585 |
|
|
arg pointer register can often be eliminated in favor of the stack
|
| 1586 |
|
|
pointer register. Secondly, the pseudo frame pointer register can always
|
| 1587 |
|
|
be eliminated; it is replaced with either the stack or the real frame
|
| 1588 |
|
|
pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
|
| 1589 |
|
|
because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
|
| 1590 |
|
|
|
| 1591 |
|
|
#define ELIMINABLE_REGS \
|
| 1592 |
|
|
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
|
| 1593 |
|
|
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
|
| 1594 |
|
|
{ ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
|
| 1595 |
|
|
{ ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
|
| 1596 |
|
|
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
|
| 1597 |
|
|
{ FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
|
| 1598 |
|
|
{ FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
|
| 1599 |
|
|
|
| 1600 |
|
|
/* Given FROM and TO register numbers, say whether this elimination is
|
| 1601 |
|
|
allowed. Frame pointer elimination is automatically handled.
|
| 1602 |
|
|
|
| 1603 |
|
|
All eliminations are permissible. Note that ARG_POINTER_REGNUM and
|
| 1604 |
|
|
HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
|
| 1605 |
|
|
pointer, we must eliminate FRAME_POINTER_REGNUM into
|
| 1606 |
|
|
HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
|
| 1607 |
|
|
ARG_POINTER_REGNUM. */
|
| 1608 |
|
|
#define CAN_ELIMINATE(FROM, TO) \
|
| 1609 |
|
|
(((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
|
| 1610 |
|
|
((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
|
| 1611 |
|
|
((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
|
| 1612 |
|
|
((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
|
| 1613 |
|
|
1)
|
| 1614 |
|
|
|
| 1615 |
|
|
/* Define the offset between two registers, one to be eliminated, and the
|
| 1616 |
|
|
other its replacement, at the start of a routine. */
|
| 1617 |
|
|
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
| 1618 |
|
|
if (TARGET_ARM) \
|
| 1619 |
|
|
(OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
|
| 1620 |
|
|
else \
|
| 1621 |
|
|
(OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
|
| 1622 |
|
|
|
| 1623 |
|
|
/* Special case handling of the location of arguments passed on the stack. */
|
| 1624 |
|
|
#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
|
| 1625 |
|
|
|
| 1626 |
|
|
/* Initialize data used by insn expanders. This is called from insn_emit,
|
| 1627 |
|
|
once for every function before code is generated. */
|
| 1628 |
|
|
#define INIT_EXPANDERS arm_init_expanders ()
|
| 1629 |
|
|
|
| 1630 |
|
|
/* Output assembler code for a block containing the constant parts
|
| 1631 |
|
|
of a trampoline, leaving space for the variable parts.
|
| 1632 |
|
|
|
| 1633 |
|
|
On the ARM, (if r8 is the static chain regnum, and remembering that
|
| 1634 |
|
|
referencing pc adds an offset of 8) the trampoline looks like:
|
| 1635 |
|
|
ldr r8, [pc, #0]
|
| 1636 |
|
|
ldr pc, [pc]
|
| 1637 |
|
|
.word static chain value
|
| 1638 |
|
|
.word function's address
|
| 1639 |
|
|
XXX FIXME: When the trampoline returns, r8 will be clobbered. */
|
| 1640 |
|
|
#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
|
| 1641 |
|
|
{ \
|
| 1642 |
|
|
asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
|
| 1643 |
|
|
STATIC_CHAIN_REGNUM, PC_REGNUM); \
|
| 1644 |
|
|
asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
|
| 1645 |
|
|
PC_REGNUM, PC_REGNUM); \
|
| 1646 |
|
|
assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
|
| 1647 |
|
|
assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
|
| 1648 |
|
|
}
|
| 1649 |
|
|
|
| 1650 |
|
|
/* On the Thumb we always switch into ARM mode to execute the trampoline.
|
| 1651 |
|
|
Why - because it is easier. This code will always be branched to via
|
| 1652 |
|
|
a BX instruction and since the compiler magically generates the address
|
| 1653 |
|
|
of the function the linker has no opportunity to ensure that the
|
| 1654 |
|
|
bottom bit is set. Thus the processor will be in ARM mode when it
|
| 1655 |
|
|
reaches this code. So we duplicate the ARM trampoline code and add
|
| 1656 |
|
|
a switch into Thumb mode as well. */
|
| 1657 |
|
|
#define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
|
| 1658 |
|
|
{ \
|
| 1659 |
|
|
fprintf (FILE, "\t.code 32\n"); \
|
| 1660 |
|
|
fprintf (FILE, ".Ltrampoline_start:\n"); \
|
| 1661 |
|
|
asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
|
| 1662 |
|
|
STATIC_CHAIN_REGNUM, PC_REGNUM); \
|
| 1663 |
|
|
asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
|
| 1664 |
|
|
IP_REGNUM, PC_REGNUM); \
|
| 1665 |
|
|
asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
|
| 1666 |
|
|
IP_REGNUM, IP_REGNUM); \
|
| 1667 |
|
|
asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
|
| 1668 |
|
|
fprintf (FILE, "\t.word\t0\n"); \
|
| 1669 |
|
|
fprintf (FILE, "\t.word\t0\n"); \
|
| 1670 |
|
|
fprintf (FILE, "\t.code 16\n"); \
|
| 1671 |
|
|
}
|
| 1672 |
|
|
|
| 1673 |
|
|
#define TRAMPOLINE_TEMPLATE(FILE) \
|
| 1674 |
|
|
if (TARGET_ARM) \
|
| 1675 |
|
|
ARM_TRAMPOLINE_TEMPLATE (FILE) \
|
| 1676 |
|
|
else \
|
| 1677 |
|
|
THUMB_TRAMPOLINE_TEMPLATE (FILE)
|
| 1678 |
|
|
|
| 1679 |
|
|
/* Length in units of the trampoline for entering a nested function. */
|
| 1680 |
|
|
#define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
|
| 1681 |
|
|
|
| 1682 |
|
|
/* Alignment required for a trampoline in bits. */
|
| 1683 |
|
|
#define TRAMPOLINE_ALIGNMENT 32
|
| 1684 |
|
|
|
| 1685 |
|
|
|
| 1686 |
|
|
/* Emit RTL insns to initialize the variable parts of a trampoline.
|
| 1687 |
|
|
FNADDR is an RTX for the address of the function's pure code.
|
| 1688 |
|
|
CXT is an RTX for the static chain value for the function. */
|
| 1689 |
|
|
#ifndef INITIALIZE_TRAMPOLINE
|
| 1690 |
|
|
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
|
| 1691 |
|
|
{ \
|
| 1692 |
|
|
emit_move_insn (gen_rtx_MEM (SImode, \
|
| 1693 |
|
|
plus_constant (TRAMP, \
|
| 1694 |
|
|
TARGET_ARM ? 8 : 16)), \
|
| 1695 |
|
|
CXT); \
|
| 1696 |
|
|
emit_move_insn (gen_rtx_MEM (SImode, \
|
| 1697 |
|
|
plus_constant (TRAMP, \
|
| 1698 |
|
|
TARGET_ARM ? 12 : 20)), \
|
| 1699 |
|
|
FNADDR); \
|
| 1700 |
|
|
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
|
| 1701 |
|
|
0, VOIDmode, 2, TRAMP, Pmode, \
|
| 1702 |
|
|
plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
|
| 1703 |
|
|
}
|
| 1704 |
|
|
#endif
|
| 1705 |
|
|
|
| 1706 |
|
|
|
| 1707 |
|
|
/* Addressing modes, and classification of registers for them. */
|
| 1708 |
|
|
#define HAVE_POST_INCREMENT 1
|
| 1709 |
|
|
#define HAVE_PRE_INCREMENT TARGET_ARM
|
| 1710 |
|
|
#define HAVE_POST_DECREMENT TARGET_ARM
|
| 1711 |
|
|
#define HAVE_PRE_DECREMENT TARGET_ARM
|
| 1712 |
|
|
#define HAVE_PRE_MODIFY_DISP TARGET_ARM
|
| 1713 |
|
|
#define HAVE_POST_MODIFY_DISP TARGET_ARM
|
| 1714 |
|
|
#define HAVE_PRE_MODIFY_REG TARGET_ARM
|
| 1715 |
|
|
#define HAVE_POST_MODIFY_REG TARGET_ARM
|
| 1716 |
|
|
|
| 1717 |
|
|
/* Macros to check register numbers against specific register classes. */
|
| 1718 |
|
|
|
| 1719 |
|
|
/* These assume that REGNO is a hard or pseudo reg number.
|
| 1720 |
|
|
They give nonzero only if REGNO is a hard reg of the suitable class
|
| 1721 |
|
|
or a pseudo reg currently allocated to a suitable hard reg.
|
| 1722 |
|
|
Since they use reg_renumber, they are safe only once reg_renumber
|
| 1723 |
|
|
has been allocated, which happens in local-alloc.c. */
|
| 1724 |
|
|
#define TEST_REGNO(R, TEST, VALUE) \
|
| 1725 |
|
|
((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
|
| 1726 |
|
|
|
| 1727 |
|
|
/* On the ARM, don't allow the pc to be used. */
|
| 1728 |
|
|
#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
|
| 1729 |
|
|
(TEST_REGNO (REGNO, <, PC_REGNUM) \
|
| 1730 |
|
|
|| TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
|
| 1731 |
|
|
|| TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
|
| 1732 |
|
|
|
| 1733 |
|
|
#define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
|
| 1734 |
|
|
(TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
|
| 1735 |
|
|
|| (GET_MODE_SIZE (MODE) >= 4 \
|
| 1736 |
|
|
&& TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
|
| 1737 |
|
|
|
| 1738 |
|
|
#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
|
| 1739 |
|
|
(TARGET_THUMB \
|
| 1740 |
|
|
? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
|
| 1741 |
|
|
: ARM_REGNO_OK_FOR_BASE_P (REGNO))
|
| 1742 |
|
|
|
| 1743 |
|
|
/* Nonzero if X can be the base register in a reg+reg addressing mode.
|
| 1744 |
|
|
For Thumb, we can not use SP + reg, so reject SP. */
|
| 1745 |
|
|
#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
|
| 1746 |
|
|
REGNO_OK_FOR_INDEX_P (X)
|
| 1747 |
|
|
|
| 1748 |
|
|
/* For ARM code, we don't care about the mode, but for Thumb, the index
|
| 1749 |
|
|
must be suitable for use in a QImode load. */
|
| 1750 |
|
|
#define REGNO_OK_FOR_INDEX_P(REGNO) \
|
| 1751 |
|
|
REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
|
| 1752 |
|
|
|
| 1753 |
|
|
/* Maximum number of registers that can appear in a valid memory address.
|
| 1754 |
|
|
Shifts in addresses can't be by a register. */
|
| 1755 |
|
|
#define MAX_REGS_PER_ADDRESS 2
|
| 1756 |
|
|
|
| 1757 |
|
|
/* Recognize any constant value that is a valid address. */
|
| 1758 |
|
|
/* XXX We can address any constant, eventually... */
|
| 1759 |
|
|
|
| 1760 |
|
|
#ifdef AOF_ASSEMBLER
|
| 1761 |
|
|
|
| 1762 |
|
|
#define CONSTANT_ADDRESS_P(X) \
|
| 1763 |
|
|
(GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
|
| 1764 |
|
|
|
| 1765 |
|
|
#else
|
| 1766 |
|
|
|
| 1767 |
|
|
#define CONSTANT_ADDRESS_P(X) \
|
| 1768 |
|
|
(GET_CODE (X) == SYMBOL_REF \
|
| 1769 |
|
|
&& (CONSTANT_POOL_ADDRESS_P (X) \
|
| 1770 |
|
|
|| (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
|
| 1771 |
|
|
|
| 1772 |
|
|
#endif /* AOF_ASSEMBLER */
|
| 1773 |
|
|
|
| 1774 |
|
|
/* Nonzero if the constant value X is a legitimate general operand.
|
| 1775 |
|
|
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
|
| 1776 |
|
|
|
| 1777 |
|
|
On the ARM, allow any integer (invalid ones are removed later by insn
|
| 1778 |
|
|
patterns), nice doubles and symbol_refs which refer to the function's
|
| 1779 |
|
|
constant pool XXX.
|
| 1780 |
|
|
|
| 1781 |
|
|
When generating pic allow anything. */
|
| 1782 |
|
|
#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
|
| 1783 |
|
|
|
| 1784 |
|
|
#define THUMB_LEGITIMATE_CONSTANT_P(X) \
|
| 1785 |
|
|
( GET_CODE (X) == CONST_INT \
|
| 1786 |
|
|
|| GET_CODE (X) == CONST_DOUBLE \
|
| 1787 |
|
|
|| CONSTANT_ADDRESS_P (X) \
|
| 1788 |
|
|
|| flag_pic)
|
| 1789 |
|
|
|
| 1790 |
|
|
#define LEGITIMATE_CONSTANT_P(X) \
|
| 1791 |
|
|
(!arm_tls_referenced_p (X) \
|
| 1792 |
|
|
&& (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) \
|
| 1793 |
|
|
: THUMB_LEGITIMATE_CONSTANT_P (X)))
|
| 1794 |
|
|
|
| 1795 |
|
|
/* Special characters prefixed to function names
|
| 1796 |
|
|
in order to encode attribute like information.
|
| 1797 |
|
|
Note, '@' and '*' have already been taken. */
|
| 1798 |
|
|
#define SHORT_CALL_FLAG_CHAR '^'
|
| 1799 |
|
|
#define LONG_CALL_FLAG_CHAR '#'
|
| 1800 |
|
|
|
| 1801 |
|
|
#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
|
| 1802 |
|
|
(*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
|
| 1803 |
|
|
|
| 1804 |
|
|
#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
|
| 1805 |
|
|
(*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
|
| 1806 |
|
|
|
| 1807 |
|
|
#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
|
| 1808 |
|
|
#define SUBTARGET_NAME_ENCODING_LENGTHS
|
| 1809 |
|
|
#endif
|
| 1810 |
|
|
|
| 1811 |
|
|
/* This is a C fragment for the inside of a switch statement.
|
| 1812 |
|
|
Each case label should return the number of characters to
|
| 1813 |
|
|
be stripped from the start of a function's name, if that
|
| 1814 |
|
|
name starts with the indicated character. */
|
| 1815 |
|
|
#define ARM_NAME_ENCODING_LENGTHS \
|
| 1816 |
|
|
case SHORT_CALL_FLAG_CHAR: return 1; \
|
| 1817 |
|
|
case LONG_CALL_FLAG_CHAR: return 1; \
|
| 1818 |
|
|
case '*': return 1; \
|
| 1819 |
|
|
SUBTARGET_NAME_ENCODING_LENGTHS
|
| 1820 |
|
|
|
| 1821 |
|
|
/* This is how to output a reference to a user-level label named NAME.
|
| 1822 |
|
|
`assemble_name' uses this. */
|
| 1823 |
|
|
#undef ASM_OUTPUT_LABELREF
|
| 1824 |
|
|
#define ASM_OUTPUT_LABELREF(FILE, NAME) \
|
| 1825 |
|
|
arm_asm_output_labelref (FILE, NAME)
|
| 1826 |
|
|
|
| 1827 |
|
|
/* The EABI specifies that constructors should go in .init_array.
|
| 1828 |
|
|
Other targets use .ctors for compatibility. */
|
| 1829 |
|
|
#ifndef ARM_EABI_CTORS_SECTION_OP
|
| 1830 |
|
|
#define ARM_EABI_CTORS_SECTION_OP \
|
| 1831 |
|
|
"\t.section\t.init_array,\"aw\",%init_array"
|
| 1832 |
|
|
#endif
|
| 1833 |
|
|
#ifndef ARM_EABI_DTORS_SECTION_OP
|
| 1834 |
|
|
#define ARM_EABI_DTORS_SECTION_OP \
|
| 1835 |
|
|
"\t.section\t.fini_array,\"aw\",%fini_array"
|
| 1836 |
|
|
#endif
|
| 1837 |
|
|
#define ARM_CTORS_SECTION_OP \
|
| 1838 |
|
|
"\t.section\t.ctors,\"aw\",%progbits"
|
| 1839 |
|
|
#define ARM_DTORS_SECTION_OP \
|
| 1840 |
|
|
"\t.section\t.dtors,\"aw\",%progbits"
|
| 1841 |
|
|
|
| 1842 |
|
|
/* Define CTORS_SECTION_ASM_OP. */
|
| 1843 |
|
|
#undef CTORS_SECTION_ASM_OP
|
| 1844 |
|
|
#undef DTORS_SECTION_ASM_OP
|
| 1845 |
|
|
#ifndef IN_LIBGCC2
|
| 1846 |
|
|
# define CTORS_SECTION_ASM_OP \
|
| 1847 |
|
|
(TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
|
| 1848 |
|
|
# define DTORS_SECTION_ASM_OP \
|
| 1849 |
|
|
(TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
|
| 1850 |
|
|
#else /* !defined (IN_LIBGCC2) */
|
| 1851 |
|
|
/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
|
| 1852 |
|
|
so we cannot use the definition above. */
|
| 1853 |
|
|
# ifdef __ARM_EABI__
|
| 1854 |
|
|
/* The .ctors section is not part of the EABI, so we do not define
|
| 1855 |
|
|
CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
|
| 1856 |
|
|
from trying to use it. We do define it when doing normal
|
| 1857 |
|
|
compilation, as .init_array can be used instead of .ctors. */
|
| 1858 |
|
|
/* There is no need to emit begin or end markers when using
|
| 1859 |
|
|
init_array; the dynamic linker will compute the size of the
|
| 1860 |
|
|
array itself based on special symbols created by the static
|
| 1861 |
|
|
linker. However, we do need to arrange to set up
|
| 1862 |
|
|
exception-handling here. */
|
| 1863 |
|
|
# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
|
| 1864 |
|
|
# define CTOR_LIST_END /* empty */
|
| 1865 |
|
|
# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
|
| 1866 |
|
|
# define DTOR_LIST_END /* empty */
|
| 1867 |
|
|
# else /* !defined (__ARM_EABI__) */
|
| 1868 |
|
|
# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
|
| 1869 |
|
|
# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
|
| 1870 |
|
|
# endif /* !defined (__ARM_EABI__) */
|
| 1871 |
|
|
#endif /* !defined (IN_LIBCC2) */
|
| 1872 |
|
|
|
| 1873 |
|
|
/* True if the operating system can merge entities with vague linkage
|
| 1874 |
|
|
(e.g., symbols in COMDAT group) during dynamic linking. */
|
| 1875 |
|
|
#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
|
| 1876 |
|
|
#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
|
| 1877 |
|
|
#endif
|
| 1878 |
|
|
|
| 1879 |
|
|
/* Set the short-call flag for any function compiled in the current
|
| 1880 |
|
|
compilation unit. We skip this for functions with the section
|
| 1881 |
|
|
attribute when long-calls are in effect as this tells the compiler
|
| 1882 |
|
|
that the section might be placed a long way from the caller.
|
| 1883 |
|
|
See arm_is_longcall_p() for more information. */
|
| 1884 |
|
|
#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
|
| 1885 |
|
|
if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
|
| 1886 |
|
|
arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
|
| 1887 |
|
|
|
| 1888 |
|
|
#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
|
| 1889 |
|
|
|
| 1890 |
|
|
#ifdef TARGET_UNWIND_INFO
|
| 1891 |
|
|
#define ARM_EABI_UNWIND_TABLES \
|
| 1892 |
|
|
((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
|
| 1893 |
|
|
#else
|
| 1894 |
|
|
#define ARM_EABI_UNWIND_TABLES 0
|
| 1895 |
|
|
#endif
|
| 1896 |
|
|
|
| 1897 |
|
|
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
|
| 1898 |
|
|
and check its validity for a certain class.
|
| 1899 |
|
|
We have two alternate definitions for each of them.
|
| 1900 |
|
|
The usual definition accepts all pseudo regs; the other rejects
|
| 1901 |
|
|
them unless they have been allocated suitable hard regs.
|
| 1902 |
|
|
The symbol REG_OK_STRICT causes the latter definition to be used. */
|
| 1903 |
|
|
#ifndef REG_OK_STRICT
|
| 1904 |
|
|
|
| 1905 |
|
|
#define ARM_REG_OK_FOR_BASE_P(X) \
|
| 1906 |
|
|
(REGNO (X) <= LAST_ARM_REGNUM \
|
| 1907 |
|
|
|| REGNO (X) >= FIRST_PSEUDO_REGISTER \
|
| 1908 |
|
|
|| REGNO (X) == FRAME_POINTER_REGNUM \
|
| 1909 |
|
|
|| REGNO (X) == ARG_POINTER_REGNUM)
|
| 1910 |
|
|
|
| 1911 |
|
|
#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
|
| 1912 |
|
|
(REGNO (X) <= LAST_LO_REGNUM \
|
| 1913 |
|
|
|| REGNO (X) >= FIRST_PSEUDO_REGISTER \
|
| 1914 |
|
|
|| (GET_MODE_SIZE (MODE) >= 4 \
|
| 1915 |
|
|
&& (REGNO (X) == STACK_POINTER_REGNUM \
|
| 1916 |
|
|
|| (X) == hard_frame_pointer_rtx \
|
| 1917 |
|
|
|| (X) == arg_pointer_rtx)))
|
| 1918 |
|
|
|
| 1919 |
|
|
#define REG_STRICT_P 0
|
| 1920 |
|
|
|
| 1921 |
|
|
#else /* REG_OK_STRICT */
|
| 1922 |
|
|
|
| 1923 |
|
|
#define ARM_REG_OK_FOR_BASE_P(X) \
|
| 1924 |
|
|
ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
|
| 1925 |
|
|
|
| 1926 |
|
|
#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
|
| 1927 |
|
|
THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
|
| 1928 |
|
|
|
| 1929 |
|
|
#define REG_STRICT_P 1
|
| 1930 |
|
|
|
| 1931 |
|
|
#endif /* REG_OK_STRICT */
|
| 1932 |
|
|
|
| 1933 |
|
|
/* Now define some helpers in terms of the above. */
|
| 1934 |
|
|
|
| 1935 |
|
|
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
|
| 1936 |
|
|
(TARGET_THUMB \
|
| 1937 |
|
|
? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
|
| 1938 |
|
|
: ARM_REG_OK_FOR_BASE_P (X))
|
| 1939 |
|
|
|
| 1940 |
|
|
#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
|
| 1941 |
|
|
|
| 1942 |
|
|
/* For Thumb, a valid index register is anything that can be used in
|
| 1943 |
|
|
a byte load instruction. */
|
| 1944 |
|
|
#define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
|
| 1945 |
|
|
|
| 1946 |
|
|
/* Nonzero if X is a hard reg that can be used as an index
|
| 1947 |
|
|
or if it is a pseudo reg. On the Thumb, the stack pointer
|
| 1948 |
|
|
is not suitable. */
|
| 1949 |
|
|
#define REG_OK_FOR_INDEX_P(X) \
|
| 1950 |
|
|
(TARGET_THUMB \
|
| 1951 |
|
|
? THUMB_REG_OK_FOR_INDEX_P (X) \
|
| 1952 |
|
|
: ARM_REG_OK_FOR_INDEX_P (X))
|
| 1953 |
|
|
|
| 1954 |
|
|
/* Nonzero if X can be the base register in a reg+reg addressing mode.
|
| 1955 |
|
|
For Thumb, we can not use SP + reg, so reject SP. */
|
| 1956 |
|
|
#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
|
| 1957 |
|
|
REG_OK_FOR_INDEX_P (X)
|
| 1958 |
|
|
|
| 1959 |
|
|
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
|
| 1960 |
|
|
that is a valid memory address for an instruction.
|
| 1961 |
|
|
The MODE argument is the machine mode for the MEM expression
|
| 1962 |
|
|
that wants to use this address. */
|
| 1963 |
|
|
|
| 1964 |
|
|
#define ARM_BASE_REGISTER_RTX_P(X) \
|
| 1965 |
|
|
(GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
|
| 1966 |
|
|
|
| 1967 |
|
|
#define ARM_INDEX_REGISTER_RTX_P(X) \
|
| 1968 |
|
|
(GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
|
| 1969 |
|
|
|
| 1970 |
|
|
#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
|
| 1971 |
|
|
{ \
|
| 1972 |
|
|
if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
|
| 1973 |
|
|
goto WIN; \
|
| 1974 |
|
|
}
|
| 1975 |
|
|
|
| 1976 |
|
|
#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
|
| 1977 |
|
|
{ \
|
| 1978 |
|
|
if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
|
| 1979 |
|
|
goto WIN; \
|
| 1980 |
|
|
}
|
| 1981 |
|
|
|
| 1982 |
|
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
|
| 1983 |
|
|
if (TARGET_ARM) \
|
| 1984 |
|
|
ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
|
| 1985 |
|
|
else /* if (TARGET_THUMB) */ \
|
| 1986 |
|
|
THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
|
| 1987 |
|
|
|
| 1988 |
|
|
|
| 1989 |
|
|
/* Try machine-dependent ways of modifying an illegitimate address
|
| 1990 |
|
|
to be legitimate. If we find one, return the new, valid address. */
|
| 1991 |
|
|
#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
|
| 1992 |
|
|
do { \
|
| 1993 |
|
|
X = arm_legitimize_address (X, OLDX, MODE); \
|
| 1994 |
|
|
} while (0)
|
| 1995 |
|
|
|
| 1996 |
|
|
#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
|
| 1997 |
|
|
do { \
|
| 1998 |
|
|
X = thumb_legitimize_address (X, OLDX, MODE); \
|
| 1999 |
|
|
} while (0)
|
| 2000 |
|
|
|
| 2001 |
|
|
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
|
| 2002 |
|
|
do { \
|
| 2003 |
|
|
if (TARGET_ARM) \
|
| 2004 |
|
|
ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
|
| 2005 |
|
|
else \
|
| 2006 |
|
|
THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
|
| 2007 |
|
|
\
|
| 2008 |
|
|
if (memory_address_p (MODE, X)) \
|
| 2009 |
|
|
goto WIN; \
|
| 2010 |
|
|
} while (0)
|
| 2011 |
|
|
|
| 2012 |
|
|
/* Go to LABEL if ADDR (a legitimate address expression)
|
| 2013 |
|
|
has an effect that depends on the machine mode it is used for. */
|
| 2014 |
|
|
#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
|
| 2015 |
|
|
{ \
|
| 2016 |
|
|
if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
|
| 2017 |
|
|
|| GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
|
| 2018 |
|
|
goto LABEL; \
|
| 2019 |
|
|
}
|
| 2020 |
|
|
|
| 2021 |
|
|
/* Nothing helpful to do for the Thumb */
|
| 2022 |
|
|
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
|
| 2023 |
|
|
if (TARGET_ARM) \
|
| 2024 |
|
|
ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
|
| 2025 |
|
|
|
| 2026 |
|
|
|
| 2027 |
|
|
/* Specify the machine mode that this machine uses
|
| 2028 |
|
|
for the index in the tablejump instruction. */
|
| 2029 |
|
|
#define CASE_VECTOR_MODE Pmode
|
| 2030 |
|
|
|
| 2031 |
|
|
/* signed 'char' is most compatible, but RISC OS wants it unsigned.
|
| 2032 |
|
|
unsigned is probably best, but may break some code. */
|
| 2033 |
|
|
#ifndef DEFAULT_SIGNED_CHAR
|
| 2034 |
|
|
#define DEFAULT_SIGNED_CHAR 0
|
| 2035 |
|
|
#endif
|
| 2036 |
|
|
|
| 2037 |
|
|
/* Max number of bytes we can move from memory to memory
|
| 2038 |
|
|
in one reasonably fast instruction. */
|
| 2039 |
|
|
#define MOVE_MAX 4
|
| 2040 |
|
|
|
| 2041 |
|
|
#undef MOVE_RATIO
|
| 2042 |
|
|
#define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
|
| 2043 |
|
|
|
| 2044 |
|
|
/* Define if operations between registers always perform the operation
|
| 2045 |
|
|
on the full register even if a narrower mode is specified. */
|
| 2046 |
|
|
#define WORD_REGISTER_OPERATIONS
|
| 2047 |
|
|
|
| 2048 |
|
|
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
|
| 2049 |
|
|
will either zero-extend or sign-extend. The value of this macro should
|
| 2050 |
|
|
be the code that says which one of the two operations is implicitly
|
| 2051 |
|
|
done, UNKNOWN if none. */
|
| 2052 |
|
|
#define LOAD_EXTEND_OP(MODE) \
|
| 2053 |
|
|
(TARGET_THUMB ? ZERO_EXTEND : \
|
| 2054 |
|
|
((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
|
| 2055 |
|
|
: ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
|
| 2056 |
|
|
|
| 2057 |
|
|
/* Nonzero if access to memory by bytes is slow and undesirable. */
|
| 2058 |
|
|
#define SLOW_BYTE_ACCESS 0
|
| 2059 |
|
|
|
| 2060 |
|
|
#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
|
| 2061 |
|
|
|
| 2062 |
|
|
/* Immediate shift counts are truncated by the output routines (or was it
|
| 2063 |
|
|
the assembler?). Shift counts in a register are truncated by ARM. Note
|
| 2064 |
|
|
that the native compiler puts too large (> 32) immediate shift counts
|
| 2065 |
|
|
into a register and shifts by the register, letting the ARM decide what
|
| 2066 |
|
|
to do instead of doing that itself. */
|
| 2067 |
|
|
/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
|
| 2068 |
|
|
code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
|
| 2069 |
|
|
On the arm, Y in a register is used modulo 256 for the shift. Only for
|
| 2070 |
|
|
rotates is modulo 32 used. */
|
| 2071 |
|
|
/* #define SHIFT_COUNT_TRUNCATED 1 */
|
| 2072 |
|
|
|
| 2073 |
|
|
/* All integers have the same format so truncation is easy. */
|
| 2074 |
|
|
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
| 2075 |
|
|
|
| 2076 |
|
|
/* Calling from registers is a massive pain. */
|
| 2077 |
|
|
#define NO_FUNCTION_CSE 1
|
| 2078 |
|
|
|
| 2079 |
|
|
/* The machine modes of pointers and functions */
|
| 2080 |
|
|
#define Pmode SImode
|
| 2081 |
|
|
#define FUNCTION_MODE Pmode
|
| 2082 |
|
|
|
| 2083 |
|
|
#define ARM_FRAME_RTX(X) \
|
| 2084 |
|
|
( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
|
| 2085 |
|
|
|| (X) == arg_pointer_rtx)
|
| 2086 |
|
|
|
| 2087 |
|
|
/* Moves to and from memory are quite expensive */
|
| 2088 |
|
|
#define MEMORY_MOVE_COST(M, CLASS, IN) \
|
| 2089 |
|
|
(TARGET_ARM ? 10 : \
|
| 2090 |
|
|
((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
|
| 2091 |
|
|
* (CLASS == LO_REGS ? 1 : 2)))
|
| 2092 |
|
|
|
| 2093 |
|
|
/* Try to generate sequences that don't involve branches, we can then use
|
| 2094 |
|
|
conditional instructions */
|
| 2095 |
|
|
#define BRANCH_COST \
|
| 2096 |
|
|
(TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
|
| 2097 |
|
|
|
| 2098 |
|
|
/* Position Independent Code. */
|
| 2099 |
|
|
/* We decide which register to use based on the compilation options and
|
| 2100 |
|
|
the assembler in use; this is more general than the APCS restriction of
|
| 2101 |
|
|
using sb (r9) all the time. */
|
| 2102 |
|
|
extern unsigned arm_pic_register;
|
| 2103 |
|
|
|
| 2104 |
|
|
/* The register number of the register used to address a table of static
|
| 2105 |
|
|
data addresses in memory. */
|
| 2106 |
|
|
#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
|
| 2107 |
|
|
|
| 2108 |
|
|
/* We can't directly access anything that contains a symbol,
|
| 2109 |
|
|
nor can we indirect via the constant pool. One exception is
|
| 2110 |
|
|
UNSPEC_TLS, which is always PIC. */
|
| 2111 |
|
|
#define LEGITIMATE_PIC_OPERAND_P(X) \
|
| 2112 |
|
|
(!(symbol_mentioned_p (X) \
|
| 2113 |
|
|
|| label_mentioned_p (X) \
|
| 2114 |
|
|
|| (GET_CODE (X) == SYMBOL_REF \
|
| 2115 |
|
|
&& CONSTANT_POOL_ADDRESS_P (X) \
|
| 2116 |
|
|
&& (symbol_mentioned_p (get_pool_constant (X)) \
|
| 2117 |
|
|
|| label_mentioned_p (get_pool_constant (X))))) \
|
| 2118 |
|
|
|| tls_mentioned_p (X))
|
| 2119 |
|
|
|
| 2120 |
|
|
/* We need to know when we are making a constant pool; this determines
|
| 2121 |
|
|
whether data needs to be in the GOT or can be referenced via a GOT
|
| 2122 |
|
|
offset. */
|
| 2123 |
|
|
extern int making_const_table;
|
| 2124 |
|
|
|
| 2125 |
|
|
/* Handle pragmas for compatibility with Intel's compilers. */
|
| 2126 |
|
|
#define REGISTER_TARGET_PRAGMAS() do { \
|
| 2127 |
|
|
c_register_pragma (0, "long_calls", arm_pr_long_calls); \
|
| 2128 |
|
|
c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
|
| 2129 |
|
|
c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
|
| 2130 |
|
|
} while (0)
|
| 2131 |
|
|
|
| 2132 |
|
|
/* Condition code information. */
|
| 2133 |
|
|
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
|
| 2134 |
|
|
return the mode to be used for the comparison. */
|
| 2135 |
|
|
|
| 2136 |
|
|
#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
|
| 2137 |
|
|
|
| 2138 |
|
|
#define REVERSIBLE_CC_MODE(MODE) 1
|
| 2139 |
|
|
|
| 2140 |
|
|
#define REVERSE_CONDITION(CODE,MODE) \
|
| 2141 |
|
|
(((MODE) == CCFPmode || (MODE) == CCFPEmode) \
|
| 2142 |
|
|
? reverse_condition_maybe_unordered (code) \
|
| 2143 |
|
|
: reverse_condition (code))
|
| 2144 |
|
|
|
| 2145 |
|
|
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
|
| 2146 |
|
|
do \
|
| 2147 |
|
|
{ \
|
| 2148 |
|
|
if (GET_CODE (OP1) == CONST_INT \
|
| 2149 |
|
|
&& ! (const_ok_for_arm (INTVAL (OP1)) \
|
| 2150 |
|
|
|| (const_ok_for_arm (- INTVAL (OP1))))) \
|
| 2151 |
|
|
{ \
|
| 2152 |
|
|
rtx const_op = OP1; \
|
| 2153 |
|
|
CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
|
| 2154 |
|
|
&const_op); \
|
| 2155 |
|
|
OP1 = const_op; \
|
| 2156 |
|
|
} \
|
| 2157 |
|
|
} \
|
| 2158 |
|
|
while (0)
|
| 2159 |
|
|
|
| 2160 |
|
|
/* The arm5 clz instruction returns 32. */
|
| 2161 |
|
|
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
|
| 2162 |
|
|
|
| 2163 |
|
|
#undef ASM_APP_OFF
|
| 2164 |
|
|
#define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
|
| 2165 |
|
|
|
| 2166 |
|
|
/* Output a push or a pop instruction (only used when profiling). */
|
| 2167 |
|
|
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
|
| 2168 |
|
|
do \
|
| 2169 |
|
|
{ \
|
| 2170 |
|
|
if (TARGET_ARM) \
|
| 2171 |
|
|
asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
|
| 2172 |
|
|
STACK_POINTER_REGNUM, REGNO); \
|
| 2173 |
|
|
else \
|
| 2174 |
|
|
asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
|
| 2175 |
|
|
} while (0)
|
| 2176 |
|
|
|
| 2177 |
|
|
|
| 2178 |
|
|
#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
|
| 2179 |
|
|
do \
|
| 2180 |
|
|
{ \
|
| 2181 |
|
|
if (TARGET_ARM) \
|
| 2182 |
|
|
asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
|
| 2183 |
|
|
STACK_POINTER_REGNUM, REGNO); \
|
| 2184 |
|
|
else \
|
| 2185 |
|
|
asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
|
| 2186 |
|
|
} while (0)
|
| 2187 |
|
|
|
| 2188 |
|
|
/* This is how to output a label which precedes a jumptable. Since
|
| 2189 |
|
|
Thumb instructions are 2 bytes, we may need explicit alignment here. */
|
| 2190 |
|
|
#undef ASM_OUTPUT_CASE_LABEL
|
| 2191 |
|
|
#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
|
| 2192 |
|
|
do \
|
| 2193 |
|
|
{ \
|
| 2194 |
|
|
if (TARGET_THUMB) \
|
| 2195 |
|
|
ASM_OUTPUT_ALIGN (FILE, 2); \
|
| 2196 |
|
|
(*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
|
| 2197 |
|
|
} \
|
| 2198 |
|
|
while (0)
|
| 2199 |
|
|
|
| 2200 |
|
|
#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
|
| 2201 |
|
|
do \
|
| 2202 |
|
|
{ \
|
| 2203 |
|
|
if (TARGET_THUMB) \
|
| 2204 |
|
|
{ \
|
| 2205 |
|
|
if (is_called_in_ARM_mode (DECL) \
|
| 2206 |
|
|
|| current_function_is_thunk) \
|
| 2207 |
|
|
fprintf (STREAM, "\t.code 32\n") ; \
|
| 2208 |
|
|
else \
|
| 2209 |
|
|
fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
|
| 2210 |
|
|
} \
|
| 2211 |
|
|
if (TARGET_POKE_FUNCTION_NAME) \
|
| 2212 |
|
|
arm_poke_function_name (STREAM, (char *) NAME); \
|
| 2213 |
|
|
} \
|
| 2214 |
|
|
while (0)
|
| 2215 |
|
|
|
| 2216 |
|
|
/* For aliases of functions we use .thumb_set instead. */
|
| 2217 |
|
|
#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
|
| 2218 |
|
|
do \
|
| 2219 |
|
|
{ \
|
| 2220 |
|
|
const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
|
| 2221 |
|
|
const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
|
| 2222 |
|
|
\
|
| 2223 |
|
|
if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
|
| 2224 |
|
|
{ \
|
| 2225 |
|
|
fprintf (FILE, "\t.thumb_set "); \
|
| 2226 |
|
|
assemble_name (FILE, LABEL1); \
|
| 2227 |
|
|
fprintf (FILE, ","); \
|
| 2228 |
|
|
assemble_name (FILE, LABEL2); \
|
| 2229 |
|
|
fprintf (FILE, "\n"); \
|
| 2230 |
|
|
} \
|
| 2231 |
|
|
else \
|
| 2232 |
|
|
ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
|
| 2233 |
|
|
} \
|
| 2234 |
|
|
while (0)
|
| 2235 |
|
|
|
| 2236 |
|
|
#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
|
| 2237 |
|
|
/* To support -falign-* switches we need to use .p2align so
|
| 2238 |
|
|
that alignment directives in code sections will be padded
|
| 2239 |
|
|
with no-op instructions, rather than zeroes. */
|
| 2240 |
|
|
#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
|
| 2241 |
|
|
if ((LOG) != 0) \
|
| 2242 |
|
|
{ \
|
| 2243 |
|
|
if ((MAX_SKIP) == 0) \
|
| 2244 |
|
|
fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
|
| 2245 |
|
|
else \
|
| 2246 |
|
|
fprintf ((FILE), "\t.p2align %d,,%d\n", \
|
| 2247 |
|
|
(int) (LOG), (int) (MAX_SKIP)); \
|
| 2248 |
|
|
}
|
| 2249 |
|
|
#endif
|
| 2250 |
|
|
|
| 2251 |
|
|
/* Only perform branch elimination (by making instructions conditional) if
|
| 2252 |
|
|
we're optimizing. Otherwise it's of no use anyway. */
|
| 2253 |
|
|
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
|
| 2254 |
|
|
if (TARGET_ARM && optimize) \
|
| 2255 |
|
|
arm_final_prescan_insn (INSN); \
|
| 2256 |
|
|
else if (TARGET_THUMB) \
|
| 2257 |
|
|
thumb_final_prescan_insn (INSN)
|
| 2258 |
|
|
|
| 2259 |
|
|
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
|
| 2260 |
|
|
(CODE == '@' || CODE == '|' \
|
| 2261 |
|
|
|| (TARGET_ARM && (CODE == '?')) \
|
| 2262 |
|
|
|| (TARGET_THUMB && (CODE == '_')))
|
| 2263 |
|
|
|
| 2264 |
|
|
/* Output an operand of an instruction. */
|
| 2265 |
|
|
#define PRINT_OPERAND(STREAM, X, CODE) \
|
| 2266 |
|
|
arm_print_operand (STREAM, X, CODE)
|
| 2267 |
|
|
|
| 2268 |
|
|
#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
|
| 2269 |
|
|
(HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
|
| 2270 |
|
|
: ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
|
| 2271 |
|
|
((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
|
| 2272 |
|
|
? ((~ (unsigned HOST_WIDE_INT) 0) \
|
| 2273 |
|
|
& ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
|
| 2274 |
|
|
: 0))))
|
| 2275 |
|
|
|
| 2276 |
|
|
/* Output the address of an operand. */
|
| 2277 |
|
|
#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
|
| 2278 |
|
|
{ \
|
| 2279 |
|
|
int is_minus = GET_CODE (X) == MINUS; \
|
| 2280 |
|
|
\
|
| 2281 |
|
|
if (GET_CODE (X) == REG) \
|
| 2282 |
|
|
asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
|
| 2283 |
|
|
else if (GET_CODE (X) == PLUS || is_minus) \
|
| 2284 |
|
|
{ \
|
| 2285 |
|
|
rtx base = XEXP (X, 0); \
|
| 2286 |
|
|
rtx index = XEXP (X, 1); \
|
| 2287 |
|
|
HOST_WIDE_INT offset = 0; \
|
| 2288 |
|
|
if (GET_CODE (base) != REG) \
|
| 2289 |
|
|
{ \
|
| 2290 |
|
|
/* Ensure that BASE is a register. */ \
|
| 2291 |
|
|
/* (one of them must be). */ \
|
| 2292 |
|
|
rtx temp = base; \
|
| 2293 |
|
|
base = index; \
|
| 2294 |
|
|
index = temp; \
|
| 2295 |
|
|
} \
|
| 2296 |
|
|
switch (GET_CODE (index)) \
|
| 2297 |
|
|
{ \
|
| 2298 |
|
|
case CONST_INT: \
|
| 2299 |
|
|
offset = INTVAL (index); \
|
| 2300 |
|
|
if (is_minus) \
|
| 2301 |
|
|
offset = -offset; \
|
| 2302 |
|
|
asm_fprintf (STREAM, "[%r, #%wd]", \
|
| 2303 |
|
|
REGNO (base), offset); \
|
| 2304 |
|
|
break; \
|
| 2305 |
|
|
\
|
| 2306 |
|
|
case REG: \
|
| 2307 |
|
|
asm_fprintf (STREAM, "[%r, %s%r]", \
|
| 2308 |
|
|
REGNO (base), is_minus ? "-" : "", \
|
| 2309 |
|
|
REGNO (index)); \
|
| 2310 |
|
|
break; \
|
| 2311 |
|
|
\
|
| 2312 |
|
|
case MULT: \
|
| 2313 |
|
|
case ASHIFTRT: \
|
| 2314 |
|
|
case LSHIFTRT: \
|
| 2315 |
|
|
case ASHIFT: \
|
| 2316 |
|
|
case ROTATERT: \
|
| 2317 |
|
|
{ \
|
| 2318 |
|
|
asm_fprintf (STREAM, "[%r, %s%r", \
|
| 2319 |
|
|
REGNO (base), is_minus ? "-" : "", \
|
| 2320 |
|
|
REGNO (XEXP (index, 0))); \
|
| 2321 |
|
|
arm_print_operand (STREAM, index, 'S'); \
|
| 2322 |
|
|
fputs ("]", STREAM); \
|
| 2323 |
|
|
break; \
|
| 2324 |
|
|
} \
|
| 2325 |
|
|
\
|
| 2326 |
|
|
default: \
|
| 2327 |
|
|
gcc_unreachable (); \
|
| 2328 |
|
|
} \
|
| 2329 |
|
|
} \
|
| 2330 |
|
|
else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
|
| 2331 |
|
|
|| GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
|
| 2332 |
|
|
{ \
|
| 2333 |
|
|
extern enum machine_mode output_memory_reference_mode; \
|
| 2334 |
|
|
\
|
| 2335 |
|
|
gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
|
| 2336 |
|
|
\
|
| 2337 |
|
|
if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
|
| 2338 |
|
|
asm_fprintf (STREAM, "[%r, #%s%d]!", \
|
| 2339 |
|
|
REGNO (XEXP (X, 0)), \
|
| 2340 |
|
|
GET_CODE (X) == PRE_DEC ? "-" : "", \
|
| 2341 |
|
|
GET_MODE_SIZE (output_memory_reference_mode)); \
|
| 2342 |
|
|
else \
|
| 2343 |
|
|
asm_fprintf (STREAM, "[%r], #%s%d", \
|
| 2344 |
|
|
REGNO (XEXP (X, 0)), \
|
| 2345 |
|
|
GET_CODE (X) == POST_DEC ? "-" : "", \
|
| 2346 |
|
|
GET_MODE_SIZE (output_memory_reference_mode)); \
|
| 2347 |
|
|
} \
|
| 2348 |
|
|
else if (GET_CODE (X) == PRE_MODIFY) \
|
| 2349 |
|
|
{ \
|
| 2350 |
|
|
asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
|
| 2351 |
|
|
if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
|
| 2352 |
|
|
asm_fprintf (STREAM, "#%wd]!", \
|
| 2353 |
|
|
INTVAL (XEXP (XEXP (X, 1), 1))); \
|
| 2354 |
|
|
else \
|
| 2355 |
|
|
asm_fprintf (STREAM, "%r]!", \
|
| 2356 |
|
|
REGNO (XEXP (XEXP (X, 1), 1))); \
|
| 2357 |
|
|
} \
|
| 2358 |
|
|
else if (GET_CODE (X) == POST_MODIFY) \
|
| 2359 |
|
|
{ \
|
| 2360 |
|
|
asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
|
| 2361 |
|
|
if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
|
| 2362 |
|
|
asm_fprintf (STREAM, "#%wd", \
|
| 2363 |
|
|
INTVAL (XEXP (XEXP (X, 1), 1))); \
|
| 2364 |
|
|
else \
|
| 2365 |
|
|
asm_fprintf (STREAM, "%r", \
|
| 2366 |
|
|
REGNO (XEXP (XEXP (X, 1), 1))); \
|
| 2367 |
|
|
} \
|
| 2368 |
|
|
else output_addr_const (STREAM, X); \
|
| 2369 |
|
|
}
|
| 2370 |
|
|
|
| 2371 |
|
|
#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
|
| 2372 |
|
|
{ \
|
| 2373 |
|
|
if (GET_CODE (X) == REG) \
|
| 2374 |
|
|
asm_fprintf (STREAM, "[%r]", REGNO (X)); \
|
| 2375 |
|
|
else if (GET_CODE (X) == POST_INC) \
|
| 2376 |
|
|
asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
|
| 2377 |
|
|
else if (GET_CODE (X) == PLUS) \
|
| 2378 |
|
|
{ \
|
| 2379 |
|
|
gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
|
| 2380 |
|
|
if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
|
| 2381 |
|
|
asm_fprintf (STREAM, "[%r, #%wd]", \
|
| 2382 |
|
|
REGNO (XEXP (X, 0)), \
|
| 2383 |
|
|
INTVAL (XEXP (X, 1))); \
|
| 2384 |
|
|
else \
|
| 2385 |
|
|
asm_fprintf (STREAM, "[%r, %r]", \
|
| 2386 |
|
|
REGNO (XEXP (X, 0)), \
|
| 2387 |
|
|
REGNO (XEXP (X, 1))); \
|
| 2388 |
|
|
} \
|
| 2389 |
|
|
else \
|
| 2390 |
|
|
output_addr_const (STREAM, X); \
|
| 2391 |
|
|
}
|
| 2392 |
|
|
|
| 2393 |
|
|
#define PRINT_OPERAND_ADDRESS(STREAM, X) \
|
| 2394 |
|
|
if (TARGET_ARM) \
|
| 2395 |
|
|
ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
|
| 2396 |
|
|
else \
|
| 2397 |
|
|
THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
|
| 2398 |
|
|
|
| 2399 |
|
|
#define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
|
| 2400 |
|
|
if (arm_output_addr_const_extra (file, x) == FALSE) \
|
| 2401 |
|
|
goto fail
|
| 2402 |
|
|
|
| 2403 |
|
|
/* A C expression whose value is RTL representing the value of the return
|
| 2404 |
|
|
address for the frame COUNT steps up from the current frame. */
|
| 2405 |
|
|
|
| 2406 |
|
|
#define RETURN_ADDR_RTX(COUNT, FRAME) \
|
| 2407 |
|
|
arm_return_addr (COUNT, FRAME)
|
| 2408 |
|
|
|
| 2409 |
|
|
/* Mask of the bits in the PC that contain the real return address
|
| 2410 |
|
|
when running in 26-bit mode. */
|
| 2411 |
|
|
#define RETURN_ADDR_MASK26 (0x03fffffc)
|
| 2412 |
|
|
|
| 2413 |
|
|
/* Pick up the return address upon entry to a procedure. Used for
|
| 2414 |
|
|
dwarf2 unwind information. This also enables the table driven
|
| 2415 |
|
|
mechanism. */
|
| 2416 |
|
|
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
|
| 2417 |
|
|
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
|
| 2418 |
|
|
|
| 2419 |
|
|
/* Used to mask out junk bits from the return address, such as
|
| 2420 |
|
|
processor state, interrupt status, condition codes and the like. */
|
| 2421 |
|
|
#define MASK_RETURN_ADDR \
|
| 2422 |
|
|
/* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
|
| 2423 |
|
|
in 26 bit mode, the condition codes must be masked out of the \
|
| 2424 |
|
|
return address. This does not apply to ARM6 and later processors \
|
| 2425 |
|
|
when running in 32 bit mode. */ \
|
| 2426 |
|
|
((arm_arch4 || TARGET_THUMB) \
|
| 2427 |
|
|
? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
|
| 2428 |
|
|
: arm_gen_return_addr_mask ())
|
| 2429 |
|
|
|
| 2430 |
|
|
|
| 2431 |
|
|
enum arm_builtins
|
| 2432 |
|
|
{
|
| 2433 |
|
|
ARM_BUILTIN_GETWCX,
|
| 2434 |
|
|
ARM_BUILTIN_SETWCX,
|
| 2435 |
|
|
|
| 2436 |
|
|
ARM_BUILTIN_WZERO,
|
| 2437 |
|
|
|
| 2438 |
|
|
ARM_BUILTIN_WAVG2BR,
|
| 2439 |
|
|
ARM_BUILTIN_WAVG2HR,
|
| 2440 |
|
|
ARM_BUILTIN_WAVG2B,
|
| 2441 |
|
|
ARM_BUILTIN_WAVG2H,
|
| 2442 |
|
|
|
| 2443 |
|
|
ARM_BUILTIN_WACCB,
|
| 2444 |
|
|
ARM_BUILTIN_WACCH,
|
| 2445 |
|
|
ARM_BUILTIN_WACCW,
|
| 2446 |
|
|
|
| 2447 |
|
|
ARM_BUILTIN_WMACS,
|
| 2448 |
|
|
ARM_BUILTIN_WMACSZ,
|
| 2449 |
|
|
ARM_BUILTIN_WMACU,
|
| 2450 |
|
|
ARM_BUILTIN_WMACUZ,
|
| 2451 |
|
|
|
| 2452 |
|
|
ARM_BUILTIN_WSADB,
|
| 2453 |
|
|
ARM_BUILTIN_WSADBZ,
|
| 2454 |
|
|
ARM_BUILTIN_WSADH,
|
| 2455 |
|
|
ARM_BUILTIN_WSADHZ,
|
| 2456 |
|
|
|
| 2457 |
|
|
ARM_BUILTIN_WALIGN,
|
| 2458 |
|
|
|
| 2459 |
|
|
ARM_BUILTIN_TMIA,
|
| 2460 |
|
|
ARM_BUILTIN_TMIAPH,
|
| 2461 |
|
|
ARM_BUILTIN_TMIABB,
|
| 2462 |
|
|
ARM_BUILTIN_TMIABT,
|
| 2463 |
|
|
ARM_BUILTIN_TMIATB,
|
| 2464 |
|
|
ARM_BUILTIN_TMIATT,
|
| 2465 |
|
|
|
| 2466 |
|
|
ARM_BUILTIN_TMOVMSKB,
|
| 2467 |
|
|
ARM_BUILTIN_TMOVMSKH,
|
| 2468 |
|
|
ARM_BUILTIN_TMOVMSKW,
|
| 2469 |
|
|
|
| 2470 |
|
|
ARM_BUILTIN_TBCSTB,
|
| 2471 |
|
|
ARM_BUILTIN_TBCSTH,
|
| 2472 |
|
|
ARM_BUILTIN_TBCSTW,
|
| 2473 |
|
|
|
| 2474 |
|
|
ARM_BUILTIN_WMADDS,
|
| 2475 |
|
|
ARM_BUILTIN_WMADDU,
|
| 2476 |
|
|
|
| 2477 |
|
|
ARM_BUILTIN_WPACKHSS,
|
| 2478 |
|
|
ARM_BUILTIN_WPACKWSS,
|
| 2479 |
|
|
ARM_BUILTIN_WPACKDSS,
|
| 2480 |
|
|
ARM_BUILTIN_WPACKHUS,
|
| 2481 |
|
|
ARM_BUILTIN_WPACKWUS,
|
| 2482 |
|
|
ARM_BUILTIN_WPACKDUS,
|
| 2483 |
|
|
|
| 2484 |
|
|
ARM_BUILTIN_WADDB,
|
| 2485 |
|
|
ARM_BUILTIN_WADDH,
|
| 2486 |
|
|
ARM_BUILTIN_WADDW,
|
| 2487 |
|
|
ARM_BUILTIN_WADDSSB,
|
| 2488 |
|
|
ARM_BUILTIN_WADDSSH,
|
| 2489 |
|
|
ARM_BUILTIN_WADDSSW,
|
| 2490 |
|
|
ARM_BUILTIN_WADDUSB,
|
| 2491 |
|
|
ARM_BUILTIN_WADDUSH,
|
| 2492 |
|
|
ARM_BUILTIN_WADDUSW,
|
| 2493 |
|
|
ARM_BUILTIN_WSUBB,
|
| 2494 |
|
|
ARM_BUILTIN_WSUBH,
|
| 2495 |
|
|
ARM_BUILTIN_WSUBW,
|
| 2496 |
|
|
ARM_BUILTIN_WSUBSSB,
|
| 2497 |
|
|
ARM_BUILTIN_WSUBSSH,
|
| 2498 |
|
|
ARM_BUILTIN_WSUBSSW,
|
| 2499 |
|
|
ARM_BUILTIN_WSUBUSB,
|
| 2500 |
|
|
ARM_BUILTIN_WSUBUSH,
|
| 2501 |
|
|
ARM_BUILTIN_WSUBUSW,
|
| 2502 |
|
|
|
| 2503 |
|
|
ARM_BUILTIN_WAND,
|
| 2504 |
|
|
ARM_BUILTIN_WANDN,
|
| 2505 |
|
|
ARM_BUILTIN_WOR,
|
| 2506 |
|
|
ARM_BUILTIN_WXOR,
|
| 2507 |
|
|
|
| 2508 |
|
|
ARM_BUILTIN_WCMPEQB,
|
| 2509 |
|
|
ARM_BUILTIN_WCMPEQH,
|
| 2510 |
|
|
ARM_BUILTIN_WCMPEQW,
|
| 2511 |
|
|
ARM_BUILTIN_WCMPGTUB,
|
| 2512 |
|
|
ARM_BUILTIN_WCMPGTUH,
|
| 2513 |
|
|
ARM_BUILTIN_WCMPGTUW,
|
| 2514 |
|
|
ARM_BUILTIN_WCMPGTSB,
|
| 2515 |
|
|
ARM_BUILTIN_WCMPGTSH,
|
| 2516 |
|
|
ARM_BUILTIN_WCMPGTSW,
|
| 2517 |
|
|
|
| 2518 |
|
|
ARM_BUILTIN_TEXTRMSB,
|
| 2519 |
|
|
ARM_BUILTIN_TEXTRMSH,
|
| 2520 |
|
|
ARM_BUILTIN_TEXTRMSW,
|
| 2521 |
|
|
ARM_BUILTIN_TEXTRMUB,
|
| 2522 |
|
|
ARM_BUILTIN_TEXTRMUH,
|
| 2523 |
|
|
ARM_BUILTIN_TEXTRMUW,
|
| 2524 |
|
|
ARM_BUILTIN_TINSRB,
|
| 2525 |
|
|
ARM_BUILTIN_TINSRH,
|
| 2526 |
|
|
ARM_BUILTIN_TINSRW,
|
| 2527 |
|
|
|
| 2528 |
|
|
ARM_BUILTIN_WMAXSW,
|
| 2529 |
|
|
ARM_BUILTIN_WMAXSH,
|
| 2530 |
|
|
ARM_BUILTIN_WMAXSB,
|
| 2531 |
|
|
ARM_BUILTIN_WMAXUW,
|
| 2532 |
|
|
ARM_BUILTIN_WMAXUH,
|
| 2533 |
|
|
ARM_BUILTIN_WMAXUB,
|
| 2534 |
|
|
ARM_BUILTIN_WMINSW,
|
| 2535 |
|
|
ARM_BUILTIN_WMINSH,
|
| 2536 |
|
|
ARM_BUILTIN_WMINSB,
|
| 2537 |
|
|
ARM_BUILTIN_WMINUW,
|
| 2538 |
|
|
ARM_BUILTIN_WMINUH,
|
| 2539 |
|
|
ARM_BUILTIN_WMINUB,
|
| 2540 |
|
|
|
| 2541 |
|
|
ARM_BUILTIN_WMULUM,
|
| 2542 |
|
|
ARM_BUILTIN_WMULSM,
|
| 2543 |
|
|
ARM_BUILTIN_WMULUL,
|
| 2544 |
|
|
|
| 2545 |
|
|
ARM_BUILTIN_PSADBH,
|
| 2546 |
|
|
ARM_BUILTIN_WSHUFH,
|
| 2547 |
|
|
|
| 2548 |
|
|
ARM_BUILTIN_WSLLH,
|
| 2549 |
|
|
ARM_BUILTIN_WSLLW,
|
| 2550 |
|
|
ARM_BUILTIN_WSLLD,
|
| 2551 |
|
|
ARM_BUILTIN_WSRAH,
|
| 2552 |
|
|
ARM_BUILTIN_WSRAW,
|
| 2553 |
|
|
ARM_BUILTIN_WSRAD,
|
| 2554 |
|
|
ARM_BUILTIN_WSRLH,
|
| 2555 |
|
|
ARM_BUILTIN_WSRLW,
|
| 2556 |
|
|
ARM_BUILTIN_WSRLD,
|
| 2557 |
|
|
ARM_BUILTIN_WRORH,
|
| 2558 |
|
|
ARM_BUILTIN_WRORW,
|
| 2559 |
|
|
ARM_BUILTIN_WRORD,
|
| 2560 |
|
|
ARM_BUILTIN_WSLLHI,
|
| 2561 |
|
|
ARM_BUILTIN_WSLLWI,
|
| 2562 |
|
|
ARM_BUILTIN_WSLLDI,
|
| 2563 |
|
|
ARM_BUILTIN_WSRAHI,
|
| 2564 |
|
|
ARM_BUILTIN_WSRAWI,
|
| 2565 |
|
|
ARM_BUILTIN_WSRADI,
|
| 2566 |
|
|
ARM_BUILTIN_WSRLHI,
|
| 2567 |
|
|
ARM_BUILTIN_WSRLWI,
|
| 2568 |
|
|
ARM_BUILTIN_WSRLDI,
|
| 2569 |
|
|
ARM_BUILTIN_WRORHI,
|
| 2570 |
|
|
ARM_BUILTIN_WRORWI,
|
| 2571 |
|
|
ARM_BUILTIN_WRORDI,
|
| 2572 |
|
|
|
| 2573 |
|
|
ARM_BUILTIN_WUNPCKIHB,
|
| 2574 |
|
|
ARM_BUILTIN_WUNPCKIHH,
|
| 2575 |
|
|
ARM_BUILTIN_WUNPCKIHW,
|
| 2576 |
|
|
ARM_BUILTIN_WUNPCKILB,
|
| 2577 |
|
|
ARM_BUILTIN_WUNPCKILH,
|
| 2578 |
|
|
ARM_BUILTIN_WUNPCKILW,
|
| 2579 |
|
|
|
| 2580 |
|
|
ARM_BUILTIN_WUNPCKEHSB,
|
| 2581 |
|
|
ARM_BUILTIN_WUNPCKEHSH,
|
| 2582 |
|
|
ARM_BUILTIN_WUNPCKEHSW,
|
| 2583 |
|
|
ARM_BUILTIN_WUNPCKEHUB,
|
| 2584 |
|
|
ARM_BUILTIN_WUNPCKEHUH,
|
| 2585 |
|
|
ARM_BUILTIN_WUNPCKEHUW,
|
| 2586 |
|
|
ARM_BUILTIN_WUNPCKELSB,
|
| 2587 |
|
|
ARM_BUILTIN_WUNPCKELSH,
|
| 2588 |
|
|
ARM_BUILTIN_WUNPCKELSW,
|
| 2589 |
|
|
ARM_BUILTIN_WUNPCKELUB,
|
| 2590 |
|
|
ARM_BUILTIN_WUNPCKELUH,
|
| 2591 |
|
|
ARM_BUILTIN_WUNPCKELUW,
|
| 2592 |
|
|
|
| 2593 |
|
|
ARM_BUILTIN_THREAD_POINTER,
|
| 2594 |
|
|
|
| 2595 |
|
|
ARM_BUILTIN_MAX
|
| 2596 |
|
|
};
|
| 2597 |
|
|
#endif /* ! GCC_ARM_H */
|
