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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [cris/] [cris.c] - Blame information for rev 154

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1 38 julius
/* Definitions for GCC.  Part of the machine description for CRIS.
2
   Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3
   2007 Free Software Foundation, Inc.
4
   Contributed by Axis Communications.  Written by Hans-Peter Nilsson.
5
 
6
This file is part of GCC.
7
 
8
GCC is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 3, or (at your option)
11
any later version.
12
 
13
GCC is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with GCC; see the file COPYING3.  If not see
20
<http://www.gnu.org/licenses/>.  */
21
 
22
#include "config.h"
23
#include "system.h"
24
#include "coretypes.h"
25
#include "tm.h"
26
#include "rtl.h"
27
#include "regs.h"
28
#include "hard-reg-set.h"
29
#include "real.h"
30
#include "insn-config.h"
31
#include "conditions.h"
32
#include "insn-attr.h"
33
#include "flags.h"
34
#include "tree.h"
35
#include "expr.h"
36
#include "except.h"
37
#include "function.h"
38
#include "toplev.h"
39
#include "recog.h"
40
#include "reload.h"
41
#include "tm_p.h"
42
#include "debug.h"
43
#include "output.h"
44
#include "target.h"
45
#include "target-def.h"
46
#include "ggc.h"
47
#include "optabs.h"
48
 
49
/* Usable when we have an amount to add or subtract, and want the
50
   optimal size of the insn.  */
51
#define ADDITIVE_SIZE_MODIFIER(size) \
52
 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
53
 
54
#define ASSERT_PLT_UNSPEC(x)                                            \
55
  CRIS_ASSERT (XINT (x, 1) == CRIS_UNSPEC_PLT                           \
56
               && ((GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF)           \
57
                   || GET_CODE (XVECEXP (x, 0, 0)) == LABEL_REF))
58
 
59
#define LOSE_AND_RETURN(msgid, x)                       \
60
  do                                            \
61
    {                                           \
62
      cris_operand_lossage (msgid, x);          \
63
      return;                                   \
64
    } while (0)
65
 
66
enum cris_retinsn_type
67
 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP };
68
 
69
/* Per-function machine data.  */
70
struct machine_function GTY(())
71
 {
72
   int needs_return_address_on_stack;
73
 
74
   /* This is the number of registers we save in the prologue due to
75
      stdarg.  */
76
   int stdarg_regs;
77
 
78
   enum cris_retinsn_type return_type;
79
 };
80
 
81
/* This little fix suppresses the 'u' or 's' when '%e' in assembly
82
   pattern.  */
83
static char cris_output_insn_is_bound = 0;
84
 
85
/* In code for output macros, this is how we know whether e.g. constant
86
   goes in code or in a static initializer.  */
87
static int in_code = 0;
88
 
89
/* Fix for reg_overlap_mentioned_p.  */
90
static int cris_reg_overlap_mentioned_p (rtx, rtx);
91
 
92
static void cris_print_base (rtx, FILE *);
93
 
94
static void cris_print_index (rtx, FILE *);
95
 
96
static void cris_output_addr_const (FILE *, rtx);
97
 
98
static struct machine_function * cris_init_machine_status (void);
99
 
100
static rtx cris_struct_value_rtx (tree, int);
101
 
102
static void cris_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
103
                                         tree type, int *, int);
104
 
105
static int cris_initial_frame_pointer_offset (void);
106
 
107
static int saved_regs_mentioned (rtx);
108
 
109
static void cris_operand_lossage (const char *, rtx);
110
 
111
static int cris_reg_saved_in_regsave_area  (unsigned int, bool);
112
 
113
static void cris_asm_output_mi_thunk
114
  (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
115
 
116
static void cris_file_start (void);
117
static void cris_init_libfuncs (void);
118
 
119
static bool cris_rtx_costs (rtx, int, int, int *);
120
static int cris_address_cost (rtx);
121
static bool cris_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
122
                                    tree, bool);
123
static int cris_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
124
                                   tree, bool);
125
static tree cris_md_asm_clobbers (tree, tree, tree);
126
 
127
static bool cris_handle_option (size_t, const char *, int);
128
 
129
/* This is the parsed result of the "-max-stack-stackframe=" option.  If
130
   it (still) is zero, then there was no such option given.  */
131
int cris_max_stackframe = 0;
132
 
133
/* This is the parsed result of the "-march=" option, if given.  */
134
int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION;
135
 
136
#undef TARGET_ASM_ALIGNED_HI_OP
137
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
138
#undef TARGET_ASM_ALIGNED_SI_OP
139
#define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
140
#undef TARGET_ASM_ALIGNED_DI_OP
141
#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
142
 
143
/* We need to define these, since the 2byte, 4byte, 8byte op:s are only
144
   available in ELF.  These "normal" pseudos do not have any alignment
145
   constraints or side-effects.  */
146
#undef TARGET_ASM_UNALIGNED_HI_OP
147
#define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
148
 
149
#undef TARGET_ASM_UNALIGNED_SI_OP
150
#define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
151
 
152
#undef TARGET_ASM_UNALIGNED_DI_OP
153
#define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
154
 
155
#undef TARGET_ASM_OUTPUT_MI_THUNK
156
#define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
157
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
158
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
159
 
160
#undef TARGET_ASM_FILE_START
161
#define TARGET_ASM_FILE_START cris_file_start
162
 
163
#undef TARGET_INIT_LIBFUNCS
164
#define TARGET_INIT_LIBFUNCS cris_init_libfuncs
165
 
166
#undef TARGET_RTX_COSTS
167
#define TARGET_RTX_COSTS cris_rtx_costs
168
#undef TARGET_ADDRESS_COST
169
#define TARGET_ADDRESS_COST cris_address_cost
170
 
171
#undef TARGET_PROMOTE_FUNCTION_ARGS
172
#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
173
#undef TARGET_STRUCT_VALUE_RTX
174
#define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
175
#undef TARGET_SETUP_INCOMING_VARARGS
176
#define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
177
#undef TARGET_PASS_BY_REFERENCE
178
#define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
179
#undef TARGET_ARG_PARTIAL_BYTES
180
#define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
181
#undef TARGET_MD_ASM_CLOBBERS
182
#define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
183
#undef TARGET_DEFAULT_TARGET_FLAGS
184
#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | CRIS_SUBTARGET_DEFAULT)
185
#undef TARGET_HANDLE_OPTION
186
#define TARGET_HANDLE_OPTION cris_handle_option
187
 
188
struct gcc_target targetm = TARGET_INITIALIZER;
189
 
190
/* Helper for cris_load_multiple_op and cris_ret_movem_op.  */
191
 
192
bool
193
cris_movem_load_rest_p (rtx op, int offs)
194
{
195
  unsigned int reg_count = XVECLEN (op, 0) - offs;
196
  rtx src_addr;
197
  int i;
198
  rtx elt;
199
  int setno;
200
  int regno_dir = 1;
201
  unsigned int regno = 0;
202
 
203
  /* Perform a quick check so we don't blow up below.  FIXME: Adjust for
204
     other than (MEM reg).  */
205
  if (reg_count <= 1
206
      || GET_CODE (XVECEXP (op, 0, offs)) != SET
207
      || GET_CODE (SET_DEST (XVECEXP (op, 0, offs))) != REG
208
      || GET_CODE (SET_SRC (XVECEXP (op, 0, offs))) != MEM)
209
    return false;
210
 
211
  /* Check a possible post-inc indicator.  */
212
  if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS)
213
    {
214
      rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0);
215
      rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1);
216
 
217
      reg_count--;
218
 
219
      if (reg_count == 1
220
          || !REG_P (reg)
221
          || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1)))
222
          || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1)))
223
          || GET_CODE (inc) != CONST_INT
224
          || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4)
225
        return false;
226
      i = offs + 2;
227
    }
228
  else
229
    i = offs + 1;
230
 
231
  /* FIXME: These two only for pre-v32.  */
232
  regno_dir = -1;
233
  regno = reg_count - 1;
234
 
235
  elt = XVECEXP (op, 0, offs);
236
  src_addr = XEXP (SET_SRC (elt), 0);
237
 
238
  if (GET_CODE (elt) != SET
239
      || GET_CODE (SET_DEST (elt)) != REG
240
      || GET_MODE (SET_DEST (elt)) != SImode
241
      || REGNO (SET_DEST (elt)) != regno
242
      || GET_CODE (SET_SRC (elt)) != MEM
243
      || GET_MODE (SET_SRC (elt)) != SImode
244
      || !memory_address_p (SImode, src_addr))
245
    return false;
246
 
247
  for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
248
    {
249
      rtx elt = XVECEXP (op, 0, i);
250
      regno += regno_dir;
251
 
252
      if (GET_CODE (elt) != SET
253
          || GET_CODE (SET_DEST (elt)) != REG
254
          || GET_MODE (SET_DEST (elt)) != SImode
255
          || REGNO (SET_DEST (elt)) != regno
256
          || GET_CODE (SET_SRC (elt)) != MEM
257
          || GET_MODE (SET_SRC (elt)) != SImode
258
          || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
259
          || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
260
          || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
261
          || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4)
262
        return false;
263
    }
264
 
265
  return true;
266
}
267
 
268
/* Worker function for predicate for the parallel contents in a movem
269
   to-memory.  */
270
 
271
bool
272
cris_store_multiple_op_p (rtx op)
273
{
274
  int reg_count = XVECLEN (op, 0);
275
  rtx dest;
276
  rtx dest_addr;
277
  rtx dest_base;
278
  int i;
279
  rtx elt;
280
  int setno;
281
  int regno_dir = 1;
282
  int regno = 0;
283
  int offset = 0;
284
 
285
  /* Perform a quick check so we don't blow up below.  FIXME: Adjust for
286
     other than (MEM reg) and (MEM (PLUS reg const)).  */
287
  if (reg_count <= 1)
288
    return false;
289
 
290
  elt = XVECEXP (op, 0, 0);
291
 
292
  if (GET_CODE (elt) != SET)
293
    return  false;
294
 
295
  dest = SET_DEST (elt);
296
 
297
  if (GET_CODE (SET_SRC (elt)) != REG
298
      || GET_CODE (dest) != MEM)
299
    return false;
300
 
301
  dest_addr = XEXP (dest, 0);
302
 
303
  /* Check a possible post-inc indicator.  */
304
  if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS)
305
    {
306
      rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0);
307
      rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1);
308
 
309
      reg_count--;
310
 
311
      if (reg_count == 1
312
          || !REG_P (reg)
313
          || !REG_P (SET_DEST (XVECEXP (op, 0, 1)))
314
          || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1)))
315
          || GET_CODE (inc) != CONST_INT
316
          /* Support increment by number of registers, and by the offset
317
             of the destination, if it has the form (MEM (PLUS reg
318
             offset)).  */
319
          || !((REG_P (dest_addr)
320
                && REGNO (dest_addr) == REGNO (reg)
321
                && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4)
322
               || (GET_CODE (dest_addr) == PLUS
323
                   && REG_P (XEXP (dest_addr, 0))
324
                   && REGNO (XEXP (dest_addr, 0)) == REGNO (reg)
325
                   && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT
326
                   && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc))))
327
        return false;
328
 
329
      i = 2;
330
    }
331
  else
332
    i = 1;
333
 
334
  /* FIXME: These two only for pre-v32.  */
335
  regno_dir = -1;
336
  regno = reg_count - 1;
337
 
338
  if (GET_CODE (elt) != SET
339
      || GET_CODE (SET_SRC (elt)) != REG
340
      || GET_MODE (SET_SRC (elt)) != SImode
341
      || REGNO (SET_SRC (elt)) != (unsigned int) regno
342
      || GET_CODE (SET_DEST (elt)) != MEM
343
      || GET_MODE (SET_DEST (elt)) != SImode)
344
    return false;
345
 
346
  if (REG_P (dest_addr))
347
    {
348
      dest_base = dest_addr;
349
      offset = 0;
350
    }
351
  else if (GET_CODE (dest_addr) == PLUS
352
           && REG_P (XEXP (dest_addr, 0))
353
           && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
354
    {
355
      dest_base = XEXP (dest_addr, 0);
356
      offset = INTVAL (XEXP (dest_addr, 1));
357
    }
358
  else
359
    return false;
360
 
361
  for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
362
    {
363
      rtx elt = XVECEXP (op, 0, i);
364
      regno += regno_dir;
365
 
366
      if (GET_CODE (elt) != SET
367
          || GET_CODE (SET_SRC (elt)) != REG
368
          || GET_MODE (SET_SRC (elt)) != SImode
369
          || REGNO (SET_SRC (elt)) != (unsigned int) regno
370
          || GET_CODE (SET_DEST (elt)) != MEM
371
          || GET_MODE (SET_DEST (elt)) != SImode
372
          || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
373
          || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base)
374
          || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
375
          || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset)
376
        return false;
377
    }
378
 
379
  return true;
380
}
381
 
382
/* The CONDITIONAL_REGISTER_USAGE worker.  */
383
 
384
void
385
cris_conditional_register_usage (void)
386
{
387
  /* FIXME: This isn't nice.  We should be able to use that register for
388
     something else if the PIC table isn't needed.  */
389
  if (flag_pic)
390
    fixed_regs[PIC_OFFSET_TABLE_REGNUM]
391
      = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
392
 
393
  if (TARGET_HAS_MUL_INSNS)
394
    fixed_regs[CRIS_MOF_REGNUM] = 0;
395
 
396
  /* On early versions, we must use the 16-bit condition-code register,
397
     which has another name.  */
398
  if (cris_cpu_version < 8)
399
    reg_names[CRIS_CC0_REGNUM] = "ccr";
400
}
401
 
402
/* Return current_function_uses_pic_offset_table.  For use in cris.md,
403
   since some generated files do not include function.h.  */
404
 
405
int
406
cris_cfun_uses_pic_table (void)
407
{
408
  return current_function_uses_pic_offset_table;
409
}
410
 
411
/* Given an rtx, return the text string corresponding to the CODE of X.
412
   Intended for use in the assembly language output section of a
413
   define_insn.  */
414
 
415
const char *
416
cris_op_str (rtx x)
417
{
418
  cris_output_insn_is_bound = 0;
419
  switch (GET_CODE (x))
420
    {
421
    case PLUS:
422
      return "add";
423
      break;
424
 
425
    case MINUS:
426
      return "sub";
427
      break;
428
 
429
    case MULT:
430
      /* This function is for retrieving a part of an instruction name for
431
         an operator, for immediate output.  If that ever happens for
432
         MULT, we need to apply TARGET_MUL_BUG in the caller.  Make sure
433
         we notice.  */
434
      internal_error ("MULT case in cris_op_str");
435
      break;
436
 
437
    case DIV:
438
      return "div";
439
      break;
440
 
441
    case AND:
442
      return "and";
443
      break;
444
 
445
    case IOR:
446
      return "or";
447
      break;
448
 
449
    case XOR:
450
      return "xor";
451
      break;
452
 
453
    case NOT:
454
      return "not";
455
      break;
456
 
457
    case ASHIFT:
458
      return "lsl";
459
      break;
460
 
461
    case LSHIFTRT:
462
      return "lsr";
463
      break;
464
 
465
    case ASHIFTRT:
466
      return "asr";
467
      break;
468
 
469
    case UMIN:
470
      /* Used to control the sign/zero-extend character for the 'E' modifier.
471
         BOUND has none.  */
472
      cris_output_insn_is_bound = 1;
473
      return "bound";
474
      break;
475
 
476
    default:
477
      return "Unknown operator";
478
      break;
479
  }
480
}
481
 
482
/* Emit an error message when we're in an asm, and a fatal error for
483
   "normal" insns.  Formatted output isn't easily implemented, since we
484
   use output_operand_lossage to output the actual message and handle the
485
   categorization of the error.  */
486
 
487
static void
488
cris_operand_lossage (const char *msgid, rtx op)
489
{
490
  debug_rtx (op);
491
  output_operand_lossage ("%s", msgid);
492
}
493
 
494
/* Print an index part of an address to file.  */
495
 
496
static void
497
cris_print_index (rtx index, FILE *file)
498
{
499
  rtx inner = XEXP (index, 0);
500
 
501
  /* Make the index "additive" unless we'll output a negative number, in
502
     which case the sign character is free (as in free beer).  */
503
  if (GET_CODE (index) != CONST_INT || INTVAL (index) >= 0)
504
    putc ('+', file);
505
 
506
  if (REG_P (index))
507
    fprintf (file, "$%s.b", reg_names[REGNO (index)]);
508
  else if (CONSTANT_P (index))
509
    cris_output_addr_const (file, index);
510
  else if (GET_CODE (index) == MULT)
511
    {
512
      fprintf (file, "$%s.",
513
               reg_names[REGNO (XEXP (index, 0))]);
514
 
515
      putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file);
516
    }
517
  else if (GET_CODE (index) == SIGN_EXTEND &&
518
           GET_CODE (inner) == MEM)
519
    {
520
      rtx inner_inner = XEXP (inner, 0);
521
 
522
      if (GET_CODE (inner_inner) == POST_INC)
523
        {
524
          fprintf (file, "[$%s+].",
525
                   reg_names[REGNO (XEXP (inner_inner, 0))]);
526
          putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
527
        }
528
      else
529
        {
530
          fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]);
531
 
532
          putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
533
        }
534
    }
535
  else if (GET_CODE (index) == MEM)
536
    {
537
      if (GET_CODE (inner) == POST_INC)
538
        fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]);
539
      else
540
        fprintf (file, "[$%s].d", reg_names[REGNO (inner)]);
541
    }
542
  else
543
    cris_operand_lossage ("unexpected index-type in cris_print_index",
544
                          index);
545
}
546
 
547
/* Print a base rtx of an address to file.  */
548
 
549
static void
550
cris_print_base (rtx base, FILE *file)
551
{
552
  if (REG_P (base))
553
    fprintf (file, "$%s", reg_names[REGNO (base)]);
554
  else if (GET_CODE (base) == POST_INC)
555
    fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]);
556
  else
557
    cris_operand_lossage ("unexpected base-type in cris_print_base",
558
                          base);
559
}
560
 
561
/* Usable as a guard in expressions.  */
562
 
563
int
564
cris_fatal (char *arg)
565
{
566
  internal_error (arg);
567
 
568
  /* We'll never get here; this is just to appease compilers.  */
569
  return 0;
570
}
571
 
572
/* Return nonzero if REGNO is an ordinary register that *needs* to be
573
   saved together with other registers, possibly by a MOVEM instruction,
574
   or is saved for target-independent reasons.  There may be
575
   target-dependent reasons to save the register anyway; this is just a
576
   wrapper for a complicated conditional.  */
577
 
578
static int
579
cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used)
580
{
581
  return
582
    (((regs_ever_live[regno]
583
       && !call_used_regs[regno])
584
      || (regno == PIC_OFFSET_TABLE_REGNUM
585
          && (got_really_used
586
              /* It is saved anyway, if there would be a gap.  */
587
              || (flag_pic
588
                  && regs_ever_live[regno + 1]
589
                  && !call_used_regs[regno + 1]))))
590
     && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed)
591
     && regno != CRIS_SRP_REGNUM)
592
    || (current_function_calls_eh_return
593
        && (regno == EH_RETURN_DATA_REGNO (0)
594
            || regno == EH_RETURN_DATA_REGNO (1)
595
            || regno == EH_RETURN_DATA_REGNO (2)
596
            || regno == EH_RETURN_DATA_REGNO (3)));
597
}
598
 
599
/* Return nonzero if there are regs mentioned in the insn that are not all
600
   in the call_used regs.  This is part of the decision whether an insn
601
   can be put in the epilogue.  */
602
 
603
static int
604
saved_regs_mentioned (rtx x)
605
{
606
  int i;
607
  const char *fmt;
608
  RTX_CODE code;
609
 
610
  /* Mainly stolen from refers_to_regno_p in rtlanal.c.  */
611
 
612
  code = GET_CODE (x);
613
 
614
  switch (code)
615
    {
616
    case REG:
617
      i = REGNO (x);
618
      return !call_used_regs[i];
619
 
620
    case SUBREG:
621
      /* If this is a SUBREG of a hard reg, we can see exactly which
622
         registers are being modified.  Otherwise, handle normally.  */
623
      i = REGNO (SUBREG_REG (x));
624
      return !call_used_regs[i];
625
 
626
    default:
627
      ;
628
    }
629
 
630
  fmt = GET_RTX_FORMAT (code);
631
  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
632
    {
633
      if (fmt[i] == 'e')
634
        {
635
          if (saved_regs_mentioned (XEXP (x, i)))
636
            return 1;
637
        }
638
      else if (fmt[i] == 'E')
639
        {
640
          int j;
641
          for (j = XVECLEN (x, i) - 1; j >=0; j--)
642
            if (saved_regs_mentioned (XEXP (x, i)))
643
              return 1;
644
        }
645
    }
646
 
647
  return 0;
648
}
649
 
650
/* The PRINT_OPERAND worker.  */
651
 
652
void
653
cris_print_operand (FILE *file, rtx x, int code)
654
{
655
  rtx operand = x;
656
 
657
  /* Size-strings corresponding to MULT expressions.  */
658
  static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
659
 
660
  /* New code entries should just be added to the switch below.  If
661
     handling is finished, just return.  If handling was just a
662
     modification of the operand, the modified operand should be put in
663
     "operand", and then do a break to let default handling
664
     (zero-modifier) output the operand.  */
665
 
666
  switch (code)
667
    {
668
    case 'b':
669
      /* Print the unsigned supplied integer as if it were signed
670
         and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc.  */
671
      if (GET_CODE (x) != CONST_INT
672
          || ! CONST_OK_FOR_LETTER_P (INTVAL (x), 'O'))
673
        LOSE_AND_RETURN ("invalid operand for 'b' modifier", x);
674
      fprintf (file, HOST_WIDE_INT_PRINT_DEC,
675
               INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535));
676
      return;
677
 
678
    case 'x':
679
      /* Print assembler code for operator.  */
680
      fprintf (file, "%s", cris_op_str (operand));
681
      return;
682
 
683
    case 'o':
684
      {
685
        /* A movem modifier working on a parallel; output the register
686
           name.  */
687
        int regno;
688
 
689
        if (GET_CODE (x) != PARALLEL)
690
          LOSE_AND_RETURN ("invalid operand for 'o' modifier", x);
691
 
692
        /* The second item can be (set reg (plus reg const)) to denote a
693
           postincrement.  */
694
        regno
695
          = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS
696
             ? XVECLEN (x, 0) - 2
697
             : XVECLEN (x, 0) - 1);
698
 
699
        fprintf (file, "$%s", reg_names [regno]);
700
      }
701
      return;
702
 
703
    case 'O':
704
      {
705
        /* A similar movem modifier; output the memory operand.  */
706
        rtx addr;
707
 
708
        if (GET_CODE (x) != PARALLEL)
709
          LOSE_AND_RETURN ("invalid operand for 'O' modifier", x);
710
 
711
        /* The lowest mem operand is in the first item, but perhaps it
712
           needs to be output as postincremented.  */
713
        addr = GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == MEM
714
          ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0)
715
          : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0);
716
 
717
        /* The second item can be a (set reg (plus reg const)) to denote
718
           a modification.  */
719
        if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS)
720
          {
721
            /* It's a post-increment, if the address is a naked (reg).  */
722
            if (REG_P (addr))
723
              addr = gen_rtx_POST_INC (SImode, addr);
724
            else
725
              {
726
                /* Otherwise, it's a side-effect; RN=RN+M.  */
727
                fprintf (file, "[$%s=$%s%s%d]",
728
                         reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))],
729
                         reg_names [REGNO (XEXP (addr, 0))],
730
                         INTVAL (XEXP (addr, 1)) < 0 ? "" : "+",
731
                         (int) INTVAL (XEXP (addr, 1)));
732
                return;
733
              }
734
          }
735
        output_address (addr);
736
      }
737
      return;
738
 
739
    case 'p':
740
      /* Adjust a power of two to its log2.  */
741
      if (GET_CODE (x) != CONST_INT || exact_log2 (INTVAL (x)) < 0 )
742
        LOSE_AND_RETURN ("invalid operand for 'p' modifier", x);
743
      fprintf (file, "%d", exact_log2 (INTVAL (x)));
744
      return;
745
 
746
    case 's':
747
      /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
748
         respectively.  This modifier also terminates the inhibiting
749
         effects of the 'x' modifier.  */
750
      cris_output_insn_is_bound = 0;
751
      if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
752
        {
753
          if (INTVAL (x) >= 0)
754
            {
755
              if (INTVAL (x) <= 255)
756
                putc ('b', file);
757
              else if (INTVAL (x) <= 65535)
758
                putc ('w', file);
759
              else
760
                putc ('d', file);
761
            }
762
          else
763
            putc ('d', file);
764
          return;
765
        }
766
 
767
      /* For a non-integer, print the size of the operand.  */
768
      putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode)
769
            ? 'd' : GET_MODE (x) == HImode ? 'w'
770
            : GET_MODE (x) == QImode ? 'b'
771
            /* If none of the above, emit an erroneous size letter.  */
772
            : 'X',
773
            file);
774
      return;
775
 
776
    case 'z':
777
      /* Const_int: print b for -127 <= x <= 255,
778
         w for -32768 <= x <= 65535, else die.  */
779
      if (GET_CODE (x) != CONST_INT
780
          || INTVAL (x) < -32768 || INTVAL (x) > 65535)
781
        LOSE_AND_RETURN ("invalid operand for 'z' modifier", x);
782
      putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file);
783
      return;
784
 
785
    case '#':
786
      /* Output a 'nop' if there's nothing for the delay slot.
787
         This method stolen from the sparc files.  */
788
      if (dbr_sequence_length () == 0)
789
        fputs ("\n\tnop", file);
790
      return;
791
 
792
    case '!':
793
      /* Output directive for alignment padded with "nop" insns.
794
         Optimizing for size, it's plain 4-byte alignment, otherwise we
795
         align the section to a cache-line (32 bytes) and skip at max 2
796
         bytes, i.e. we skip if it's the last insn on a cache-line.  The
797
         latter is faster by a small amount (for two test-programs 99.6%
798
         and 99.9%) and larger by a small amount (ditto 100.1% and
799
         100.2%).  This is supposed to be the simplest yet performance-
800
         wise least intrusive way to make sure the immediately following
801
         (supposed) muls/mulu insn isn't located at the end of a
802
         cache-line.  */
803
      if (TARGET_MUL_BUG)
804
        fputs (optimize_size
805
               ? ".p2alignw 2,0x050f\n\t"
806
               : ".p2alignw 5,0x050f,2\n\t", file);
807
      return;
808
 
809
    case ':':
810
      /* The PIC register.  */
811
      if (! flag_pic)
812
        internal_error ("invalid use of ':' modifier");
813
      fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]);
814
      return;
815
 
816
    case 'H':
817
      /* Print high (most significant) part of something.  */
818
      switch (GET_CODE (operand))
819
        {
820
        case CONST_INT:
821
          /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
822
             value is kept here, and so may be other than 0 or -1.  */
823
          fprintf (file, HOST_WIDE_INT_PRINT_DEC,
824
                   INTVAL (operand_subword (operand, 1, 0, DImode)));
825
          return;
826
 
827
        case CONST_DOUBLE:
828
          /* High part of a long long constant.  */
829
          if (GET_MODE (operand) == VOIDmode)
830
            {
831
              fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x));
832
              return;
833
            }
834
          else
835
            LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
836
 
837
        case REG:
838
          /* Print reg + 1.  Check that there's not an attempt to print
839
             high-parts of registers like stack-pointer or higher.  */
840
          if (REGNO (operand) > STACK_POINTER_REGNUM - 2)
841
            LOSE_AND_RETURN ("bad register", operand);
842
          fprintf (file, "$%s", reg_names[REGNO (operand) + 1]);
843
          return;
844
 
845
        case MEM:
846
          /* Adjust memory address to high part.  */
847
          {
848
            rtx adj_mem = operand;
849
            int size
850
              = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT;
851
 
852
            /* Adjust so we can use two SImode in DImode.
853
               Calling adj_offsettable_operand will make sure it is an
854
               offsettable address.  Don't do this for a postincrement
855
               though; it should remain as it was.  */
856
            if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC)
857
              adj_mem
858
                = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2);
859
 
860
            output_address (XEXP (adj_mem, 0));
861
            return;
862
          }
863
 
864
        default:
865
          LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
866
        }
867
 
868
    case 'L':
869
      /* Strip the MEM expression.  */
870
      operand = XEXP (operand, 0);
871
      break;
872
 
873
    case 'e':
874
      /* Like 'E', but ignore state set by 'x'.  FIXME: Use code
875
         iterators ("code macros") and attributes in cris.md to avoid
876
         the need for %x and %E (and %e) and state passed between
877
         those modifiers.  */
878
      cris_output_insn_is_bound = 0;
879
      /* FALL THROUGH.  */
880
    case 'E':
881
      /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
882
         cris_output_insn_is_bound is nonzero.  */
883
      if (GET_CODE (operand) != SIGN_EXTEND
884
          && GET_CODE (operand) != ZERO_EXTEND
885
          && GET_CODE (operand) != CONST_INT)
886
        LOSE_AND_RETURN ("invalid operand for 'e' modifier", x);
887
 
888
      if (cris_output_insn_is_bound)
889
        {
890
          cris_output_insn_is_bound = 0;
891
          return;
892
        }
893
 
894
      putc (GET_CODE (operand) == SIGN_EXTEND
895
            || (GET_CODE (operand) == CONST_INT && INTVAL (operand) < 0)
896
            ? 's' : 'u', file);
897
      return;
898
 
899
    case 'm':
900
      /* Print the size letter of the inner element.  We can do it by
901
         calling ourselves with the 's' modifier.  */
902
      if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
903
        LOSE_AND_RETURN ("invalid operand for 'm' modifier", x);
904
      cris_print_operand (file, XEXP (operand, 0), 's');
905
      return;
906
 
907
    case 'M':
908
      /* Print the least significant part of operand.  */
909
      if (GET_CODE (operand) == CONST_DOUBLE)
910
        {
911
          fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
912
          return;
913
        }
914
      else if (HOST_BITS_PER_WIDE_INT > 32 && GET_CODE (operand) == CONST_INT)
915
        {
916
          fprintf (file, HOST_WIDE_INT_PRINT_HEX,
917
                   INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1));
918
          return;
919
        }
920
      /* Otherwise the least significant part equals the normal part,
921
         so handle it normally.  */
922
      break;
923
 
924
    case 'A':
925
      /* When emitting an add for the high part of a DImode constant, we
926
         want to use addq for 0 and adds.w for -1.  */
927
      if (GET_CODE (operand) != CONST_INT)
928
        LOSE_AND_RETURN ("invalid operand for 'A' modifier", x);
929
      fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq");
930
      return;
931
 
932
    case 'd':
933
      /* If this is a GOT symbol, force it to be emitted as :GOT and
934
         :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
935
         Avoid making this too much of a special case.  */
936
      if (flag_pic == 1 && CONSTANT_P (operand))
937
        {
938
          int flag_pic_save = flag_pic;
939
 
940
          flag_pic = 2;
941
          cris_output_addr_const (file, operand);
942
          flag_pic = flag_pic_save;
943
          return;
944
        }
945
      break;
946
 
947
    case 'D':
948
      /* When emitting an sub for the high part of a DImode constant, we
949
         want to use subq for 0 and subs.w for -1.  */
950
      if (GET_CODE (operand) != CONST_INT)
951
        LOSE_AND_RETURN ("invalid operand for 'D' modifier", x);
952
      fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq");
953
      return;
954
 
955
    case 'S':
956
      /* Print the operand as the index-part of an address.
957
         Easiest way out is to use cris_print_index.  */
958
      cris_print_index (operand, file);
959
      return;
960
 
961
    case 'T':
962
      /* Print the size letter for an operand to a MULT, which must be a
963
         const_int with a suitable value.  */
964
      if (GET_CODE (operand) != CONST_INT || INTVAL (operand) > 4)
965
        LOSE_AND_RETURN ("invalid operand for 'T' modifier", x);
966
      fprintf (file, "%s", mults[INTVAL (operand)]);
967
      return;
968
 
969
    case 0:
970
      /* No code, print as usual.  */
971
      break;
972
 
973
    default:
974
      LOSE_AND_RETURN ("invalid operand modifier letter", x);
975
    }
976
 
977
  /* Print an operand as without a modifier letter.  */
978
  switch (GET_CODE (operand))
979
    {
980
    case REG:
981
      if (REGNO (operand) > 15
982
          && REGNO (operand) != CRIS_MOF_REGNUM
983
          && REGNO (operand) != CRIS_SRP_REGNUM
984
          && REGNO (operand) != CRIS_CC0_REGNUM)
985
        internal_error ("internal error: bad register: %d", REGNO (operand));
986
      fprintf (file, "$%s", reg_names[REGNO (operand)]);
987
      return;
988
 
989
    case MEM:
990
      output_address (XEXP (operand, 0));
991
      return;
992
 
993
    case CONST_DOUBLE:
994
      if (GET_MODE (operand) == VOIDmode)
995
        /* A long long constant.  */
996
        output_addr_const (file, operand);
997
      else
998
        {
999
          /* Only single precision is allowed as plain operands the
1000
             moment.  FIXME:  REAL_VALUE_FROM_CONST_DOUBLE isn't
1001
             documented.  */
1002
          REAL_VALUE_TYPE r;
1003
          long l;
1004
 
1005
          /* FIXME:  Perhaps check overflow of the "single".  */
1006
          REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
1007
          REAL_VALUE_TO_TARGET_SINGLE (r, l);
1008
 
1009
          fprintf (file, "0x%lx", l);
1010
        }
1011
      return;
1012
 
1013
    case UNSPEC:
1014
      /* Fall through.  */
1015
    case CONST:
1016
      cris_output_addr_const (file, operand);
1017
      return;
1018
 
1019
    case MULT:
1020
    case ASHIFT:
1021
      {
1022
        /* For a (MULT (reg X) const_int) we output "rX.S".  */
1023
        int i = GET_CODE (XEXP (operand, 1)) == CONST_INT
1024
          ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0));
1025
        rtx reg = GET_CODE (XEXP (operand, 1)) == CONST_INT
1026
          ? XEXP (operand, 0) : XEXP (operand, 1);
1027
 
1028
        if (GET_CODE (reg) != REG
1029
            || (GET_CODE (XEXP (operand, 0)) != CONST_INT
1030
                && GET_CODE (XEXP (operand, 1)) != CONST_INT))
1031
          LOSE_AND_RETURN ("unexpected multiplicative operand", x);
1032
 
1033
        cris_print_base (reg, file);
1034
        fprintf (file, ".%c",
1035
                 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b'
1036
                 : i == 4 ? 'd'
1037
                 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w'
1038
                 : 'd');
1039
        return;
1040
      }
1041
 
1042
    default:
1043
      /* No need to handle all strange variants, let output_addr_const
1044
         do it for us.  */
1045
      if (CONSTANT_P (operand))
1046
        {
1047
          cris_output_addr_const (file, operand);
1048
          return;
1049
        }
1050
 
1051
      LOSE_AND_RETURN ("unexpected operand", x);
1052
    }
1053
}
1054
 
1055
/* The PRINT_OPERAND_ADDRESS worker.  */
1056
 
1057
void
1058
cris_print_operand_address (FILE *file, rtx x)
1059
{
1060
  /* All these were inside MEM:s so output indirection characters.  */
1061
  putc ('[', file);
1062
 
1063
  if (CONSTANT_ADDRESS_P (x))
1064
    cris_output_addr_const (file, x);
1065
  else if (BASE_OR_AUTOINCR_P (x))
1066
    cris_print_base (x, file);
1067
  else if (GET_CODE (x) == PLUS)
1068
    {
1069
      rtx x1, x2;
1070
 
1071
      x1 = XEXP (x, 0);
1072
      x2 = XEXP (x, 1);
1073
      if (BASE_P (x1))
1074
        {
1075
          cris_print_base (x1, file);
1076
          cris_print_index (x2, file);
1077
        }
1078
      else if (BASE_P (x2))
1079
        {
1080
          cris_print_base (x2, file);
1081
          cris_print_index (x1, file);
1082
        }
1083
      else
1084
        LOSE_AND_RETURN ("unrecognized address", x);
1085
    }
1086
  else if (GET_CODE (x) == MEM)
1087
    {
1088
      /* A DIP.  Output more indirection characters.  */
1089
      putc ('[', file);
1090
      cris_print_base (XEXP (x, 0), file);
1091
      putc (']', file);
1092
    }
1093
  else
1094
    LOSE_AND_RETURN ("unrecognized address", x);
1095
 
1096
  putc (']', file);
1097
}
1098
 
1099
/* The RETURN_ADDR_RTX worker.
1100
   We mark that the return address is used, either by EH or
1101
   __builtin_return_address, for use by the function prologue and
1102
   epilogue.  FIXME: This isn't optimal; we just use the mark in the
1103
   prologue and epilogue to say that the return address is to be stored
1104
   in the stack frame.  We could return SRP for leaf-functions and use the
1105
   initial-value machinery.  */
1106
 
1107
rtx
1108
cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED)
1109
{
1110
  cfun->machine->needs_return_address_on_stack = 1;
1111
 
1112
  /* The return-address is stored just above the saved frame-pointer (if
1113
     present).  Apparently we can't eliminate from the frame-pointer in
1114
     that direction, so use the incoming args (maybe pretended) pointer.  */
1115
  return count == 0
1116
    ? gen_rtx_MEM (Pmode, plus_constant (virtual_incoming_args_rtx, -4))
1117
    : NULL_RTX;
1118
}
1119
 
1120
/* Accessor used in cris.md:return because cfun->machine isn't available
1121
   there.  */
1122
 
1123
bool
1124
cris_return_address_on_stack (void)
1125
{
1126
  return regs_ever_live[CRIS_SRP_REGNUM]
1127
    || cfun->machine->needs_return_address_on_stack;
1128
}
1129
 
1130
/* Accessor used in cris.md:return because cfun->machine isn't available
1131
   there.  */
1132
 
1133
bool
1134
cris_return_address_on_stack_for_return (void)
1135
{
1136
  return cfun->machine->return_type == CRIS_RETINSN_RET ? false
1137
    : cris_return_address_on_stack ();
1138
}
1139
 
1140
/* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1141
   handles FP -> SP elimination offset.  */
1142
 
1143
static int
1144
cris_initial_frame_pointer_offset (void)
1145
{
1146
  int regno;
1147
 
1148
  /* Initial offset is 0 if we don't have a frame pointer.  */
1149
  int offs = 0;
1150
  bool got_really_used = false;
1151
 
1152
  if (current_function_uses_pic_offset_table)
1153
    {
1154
      push_topmost_sequence ();
1155
      got_really_used
1156
        = reg_used_between_p (pic_offset_table_rtx, get_insns (),
1157
                              NULL_RTX);
1158
      pop_topmost_sequence ();
1159
    }
1160
 
1161
  /* And 4 for each register pushed.  */
1162
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1163
    if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1164
      offs += 4;
1165
 
1166
  /* And then, last, we add the locals allocated.  */
1167
  offs += get_frame_size ();
1168
 
1169
  /* And more; the accumulated args size.  */
1170
  offs += current_function_outgoing_args_size;
1171
 
1172
  /* Then round it off, in case we use aligned stack.  */
1173
  if (TARGET_STACK_ALIGN)
1174
    offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1;
1175
 
1176
  return offs;
1177
}
1178
 
1179
/* The INITIAL_ELIMINATION_OFFSET worker.
1180
   Calculate the difference between imaginary registers such as frame
1181
   pointer and the stack pointer.  Used to eliminate the frame pointer
1182
   and imaginary arg pointer.  */
1183
 
1184
int
1185
cris_initial_elimination_offset (int fromreg, int toreg)
1186
{
1187
  int fp_sp_offset
1188
    = cris_initial_frame_pointer_offset ();
1189
 
1190
  /* We should be able to use regs_ever_live and related prologue
1191
     information here, or alpha should not as well.  */
1192
  bool return_address_on_stack = cris_return_address_on_stack ();
1193
 
1194
  /* Here we act as if the frame-pointer were needed.  */
1195
  int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0);
1196
 
1197
  if (fromreg == ARG_POINTER_REGNUM
1198
      && toreg == FRAME_POINTER_REGNUM)
1199
    return ap_fp_offset;
1200
 
1201
  /* Between the frame pointer and the stack are only "normal" stack
1202
     variables and saved registers.  */
1203
  if (fromreg == FRAME_POINTER_REGNUM
1204
      && toreg == STACK_POINTER_REGNUM)
1205
    return fp_sp_offset;
1206
 
1207
  /* We need to balance out the frame pointer here.  */
1208
  if (fromreg == ARG_POINTER_REGNUM
1209
      && toreg == STACK_POINTER_REGNUM)
1210
    return ap_fp_offset + fp_sp_offset - 4;
1211
 
1212
  gcc_unreachable ();
1213
}
1214
 
1215
/* Worker function for LEGITIMIZE_RELOAD_ADDRESS.  */
1216
 
1217
bool
1218
cris_reload_address_legitimized (rtx x,
1219
                                 enum machine_mode mode ATTRIBUTE_UNUSED,
1220
                                 int opnum ATTRIBUTE_UNUSED,
1221
                                 int itype,
1222
                                 int ind_levels ATTRIBUTE_UNUSED)
1223
{
1224
  enum reload_type type = itype;
1225
  rtx op0, op1;
1226
  rtx *op0p;
1227
  rtx *op1p;
1228
 
1229
  if (GET_CODE (x) != PLUS)
1230
    return false;
1231
 
1232
  op0 = XEXP (x, 0);
1233
  op0p = &XEXP (x, 0);
1234
  op1 = XEXP (x, 1);
1235
  op1p = &XEXP (x, 1);
1236
 
1237
  if (!REG_P (op1))
1238
    return false;
1239
 
1240
  if (GET_CODE (op0) == SIGN_EXTEND
1241
      && GET_CODE (XEXP (op0, 0)) == MEM)
1242
    {
1243
      rtx op00 = XEXP (op0, 0);
1244
      rtx op000 = XEXP (op00, 0);
1245
      rtx *op000p = &XEXP (op00, 0);
1246
 
1247
      if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode)
1248
          && (REG_P (op000)
1249
              || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0)))))
1250
        {
1251
          bool something_reloaded = false;
1252
 
1253
          if (GET_CODE (op000) == POST_INC
1254
              && REG_P (XEXP (op000, 0))
1255
              && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER)
1256
            /* No, this gets too complicated and is too rare to care
1257
               about trying to improve on the general code Here.
1258
               As the return-value is an all-or-nothing indicator, we
1259
               punt on the other register too.  */
1260
            return false;
1261
 
1262
          if ((REG_P (op000)
1263
               && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER))
1264
            {
1265
              /* The address of the inner mem is a pseudo or wrong
1266
                 reg: reload that.  */
1267
              push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS,
1268
                           GET_MODE (x), VOIDmode, 0, 0, opnum, type);
1269
              something_reloaded = true;
1270
            }
1271
 
1272
          if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER)
1273
            {
1274
              /* Base register is a pseudo or wrong reg: reload it.  */
1275
              push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS,
1276
                           GET_MODE (x), VOIDmode, 0, 0,
1277
                           opnum, type);
1278
              something_reloaded = true;
1279
            }
1280
 
1281
          gcc_assert (something_reloaded);
1282
 
1283
          return true;
1284
        }
1285
    }
1286
 
1287
  return false;
1288
}
1289
 
1290
/*  This function looks into the pattern to see how this insn affects
1291
    condition codes.
1292
 
1293
    Used when to eliminate test insns before a condition-code user,
1294
    such as a "scc" insn or a conditional branch.  This includes
1295
    checking if the entities that cc was updated by, are changed by the
1296
    operation.
1297
 
1298
    Currently a jumble of the old peek-inside-the-insn and the newer
1299
    check-cc-attribute methods.  */
1300
 
1301
void
1302
cris_notice_update_cc (rtx exp, rtx insn)
1303
{
1304
  /* Check if user specified "-mcc-init" as a bug-workaround.  FIXME:
1305
     TARGET_CCINIT does not work; we must set CC_REVERSED as below.
1306
     Several testcases will otherwise fail, for example
1307
     gcc.c-torture/execute/20000217-1.c -O0 and -O1.  */
1308
  if (TARGET_CCINIT)
1309
    {
1310
      CC_STATUS_INIT;
1311
      return;
1312
    }
1313
 
1314
  /* Slowly, we're converting to using attributes to control the setting
1315
     of condition-code status.  */
1316
  switch (get_attr_cc (insn))
1317
    {
1318
    case CC_NONE:
1319
      /* Even if it is "none", a setting may clobber a previous
1320
         cc-value, so check.  */
1321
      if (GET_CODE (exp) == SET)
1322
        {
1323
          if (cc_status.value1
1324
              && modified_in_p (cc_status.value1, insn))
1325
            cc_status.value1 = 0;
1326
 
1327
          if (cc_status.value2
1328
              && modified_in_p (cc_status.value2, insn))
1329
            cc_status.value2 = 0;
1330
        }
1331
      return;
1332
 
1333
    case CC_CLOBBER:
1334
      CC_STATUS_INIT;
1335
      break;
1336
 
1337
    case CC_NORMAL:
1338
      /* Which means, for:
1339
         (set (cc0) (...)):
1340
         CC is (...).
1341
 
1342
         (set (reg) (...)):
1343
         CC is (reg) and (...) - unless (...) is 0, then CC does not change.
1344
         CC_NO_OVERFLOW unless (...) is reg or mem.
1345
 
1346
         (set (mem) (...)):
1347
         CC does not change.
1348
 
1349
         (set (pc) (...)):
1350
         CC does not change.
1351
 
1352
         (parallel
1353
          (set (reg1) (mem (bdap/biap)))
1354
          (set (reg2) (bdap/biap))):
1355
         CC is (reg1) and (mem (reg2))
1356
 
1357
         (parallel
1358
          (set (mem (bdap/biap)) (reg1)) [or 0]
1359
          (set (reg2) (bdap/biap))):
1360
         CC does not change.
1361
 
1362
         (where reg and mem includes strict_low_parts variants thereof)
1363
 
1364
         For all others, assume CC is clobbered.
1365
         Note that we do not have to care about setting CC_NO_OVERFLOW,
1366
         since the overflow flag is set to 0 (i.e. right) for
1367
         instructions where it does not have any sane sense, but where
1368
         other flags have meanings.  (This includes shifts; the carry is
1369
         not set by them).
1370
 
1371
         Note that there are other parallel constructs we could match,
1372
         but we don't do that yet.  */
1373
 
1374
      if (GET_CODE (exp) == SET)
1375
        {
1376
          /* FIXME: Check when this happens.  It looks like we should
1377
             actually do a CC_STATUS_INIT here to be safe.  */
1378
          if (SET_DEST (exp) == pc_rtx)
1379
            return;
1380
 
1381
          /* Record CC0 changes, so we do not have to output multiple
1382
             test insns.  */
1383
          if (SET_DEST (exp) == cc0_rtx)
1384
            {
1385
              cc_status.value1 = SET_SRC (exp);
1386
              cc_status.value2 = 0;
1387
 
1388
              /* Handle flags for the special btstq on one bit.  */
1389
              if (GET_CODE (SET_SRC (exp)) == ZERO_EXTRACT
1390
                  && XEXP (SET_SRC (exp), 1) == const1_rtx)
1391
                {
1392
                  if (GET_CODE (XEXP (SET_SRC (exp), 0)) == CONST_INT)
1393
                    /* Using cmpq.  */
1394
                    cc_status.flags = CC_INVERTED;
1395
                  else
1396
                    /* A one-bit btstq.  */
1397
                    cc_status.flags = CC_Z_IN_NOT_N;
1398
                }
1399
              else
1400
                cc_status.flags = 0;
1401
 
1402
              if (GET_CODE (SET_SRC (exp)) == COMPARE)
1403
                {
1404
                  if (!REG_P (XEXP (SET_SRC (exp), 0))
1405
                      && XEXP (SET_SRC (exp), 1) != const0_rtx)
1406
                    /* For some reason gcc will not canonicalize compare
1407
                       operations, reversing the sign by itself if
1408
                       operands are in wrong order.  */
1409
                    /* (But NOT inverted; eq is still eq.) */
1410
                    cc_status.flags = CC_REVERSED;
1411
 
1412
                  /* This seems to be overlooked by gcc.  FIXME: Check again.
1413
                     FIXME:  Is it really safe?  */
1414
                  cc_status.value2
1415
                    = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)),
1416
                                     XEXP (SET_SRC (exp), 0),
1417
                                     XEXP (SET_SRC (exp), 1));
1418
                }
1419
              return;
1420
            }
1421
          else if (REG_P (SET_DEST (exp))
1422
                   || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1423
                       && REG_P (XEXP (SET_DEST (exp), 0))))
1424
            {
1425
              /* A register is set; normally CC is set to show that no
1426
                 test insn is needed.  Catch the exceptions.  */
1427
 
1428
              /* If not to cc0, then no "set"s in non-natural mode give
1429
                 ok cc0...  */
1430
              if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
1431
                  || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
1432
                {
1433
                  /* ... except add:s and sub:s in DImode.  */
1434
                  if (GET_MODE (SET_DEST (exp)) == DImode
1435
                      && (GET_CODE (SET_SRC (exp)) == PLUS
1436
                          || GET_CODE (SET_SRC (exp)) == MINUS))
1437
                    {
1438
                      cc_status.flags = 0;
1439
                      cc_status.value1 = SET_DEST (exp);
1440
                      cc_status.value2 = SET_SRC (exp);
1441
 
1442
                      if (cris_reg_overlap_mentioned_p (cc_status.value1,
1443
                                                        cc_status.value2))
1444
                        cc_status.value2 = 0;
1445
 
1446
                      /* Add and sub may set V, which gets us
1447
                         unoptimizable results in "gt" and "le" condition
1448
                         codes.  */
1449
                      cc_status.flags |= CC_NO_OVERFLOW;
1450
 
1451
                      return;
1452
                    }
1453
                }
1454
              else if (SET_SRC (exp) == const0_rtx)
1455
                {
1456
                  /* There's no CC0 change when clearing a register or
1457
                     memory.  Just check for overlap.  */
1458
                  if (cc_status.value1
1459
                      && modified_in_p (cc_status.value1, insn))
1460
                    cc_status.value1 = 0;
1461
 
1462
                  if (cc_status.value2
1463
                      && modified_in_p (cc_status.value2, insn))
1464
                    cc_status.value2 = 0;
1465
 
1466
                  return;
1467
                }
1468
              else
1469
                {
1470
                  cc_status.flags = 0;
1471
                  cc_status.value1 = SET_DEST (exp);
1472
                  cc_status.value2 = SET_SRC (exp);
1473
 
1474
                  if (cris_reg_overlap_mentioned_p (cc_status.value1,
1475
                                                    cc_status.value2))
1476
                    cc_status.value2 = 0;
1477
 
1478
                  /* Some operations may set V, which gets us
1479
                     unoptimizable results in "gt" and "le" condition
1480
                     codes.  */
1481
                  if (GET_CODE (SET_SRC (exp)) == PLUS
1482
                      || GET_CODE (SET_SRC (exp)) == MINUS
1483
                      || GET_CODE (SET_SRC (exp)) == NEG)
1484
                    cc_status.flags |= CC_NO_OVERFLOW;
1485
 
1486
                  return;
1487
                }
1488
            }
1489
          else if (GET_CODE (SET_DEST (exp)) == MEM
1490
                   || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1491
                       && GET_CODE (XEXP (SET_DEST (exp), 0)) == MEM))
1492
            {
1493
              /* When SET to MEM, then CC is not changed (except for
1494
                 overlap).  */
1495
              if (cc_status.value1
1496
                  && modified_in_p (cc_status.value1, insn))
1497
                cc_status.value1 = 0;
1498
 
1499
              if (cc_status.value2
1500
                  && modified_in_p (cc_status.value2, insn))
1501
                cc_status.value2 = 0;
1502
 
1503
              return;
1504
            }
1505
        }
1506
      else if (GET_CODE (exp) == PARALLEL)
1507
        {
1508
          if (GET_CODE (XVECEXP (exp, 0, 0)) == SET
1509
              && GET_CODE (XVECEXP (exp, 0, 1)) == SET
1510
              && REG_P (XEXP (XVECEXP (exp, 0, 1), 0)))
1511
            {
1512
              if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0))
1513
                  && GET_CODE (XEXP (XVECEXP (exp, 0, 0), 1)) == MEM)
1514
                {
1515
                  /* For "move.S [rx=ry+o],rz", say CC reflects
1516
                     value1=rz and value2=[rx] */
1517
                  cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
1518
                  cc_status.value2
1519
                    = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1),
1520
                                             XEXP (XVECEXP (exp, 0, 1), 0));
1521
                  cc_status.flags = 0;
1522
 
1523
                  /* Huh?  A side-effect cannot change the destination
1524
                     register.  */
1525
                  if (cris_reg_overlap_mentioned_p (cc_status.value1,
1526
                                                    cc_status.value2))
1527
                    internal_error ("internal error: sideeffect-insn affecting main effect");
1528
                  return;
1529
                }
1530
              else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1))
1531
                        || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx)
1532
                       && GET_CODE (XEXP (XVECEXP (exp, 0, 0), 0)) == MEM)
1533
                {
1534
                  /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1535
                     say flags are not changed, except for overlap.  */
1536
                  if (cc_status.value1
1537
                      && modified_in_p (cc_status.value1, insn))
1538
                    cc_status.value1 = 0;
1539
 
1540
                  if (cc_status.value2
1541
                      && modified_in_p (cc_status.value2, insn))
1542
                    cc_status.value2 = 0;
1543
 
1544
                  return;
1545
                }
1546
            }
1547
        }
1548
      break;
1549
 
1550
    default:
1551
      internal_error ("unknown cc_attr value");
1552
    }
1553
 
1554
  CC_STATUS_INIT;
1555
}
1556
 
1557
/* Return != 0 if the return sequence for the current function is short,
1558
   like "ret" or "jump [sp+]".  Prior to reloading, we can't tell if
1559
   registers must be saved, so return 0 then.  */
1560
 
1561
bool
1562
cris_simple_epilogue (void)
1563
{
1564
  unsigned int regno;
1565
  unsigned int reglimit = STACK_POINTER_REGNUM;
1566
  bool got_really_used = false;
1567
 
1568
  if (! reload_completed
1569
      || frame_pointer_needed
1570
      || get_frame_size () != 0
1571
      || current_function_pretend_args_size
1572
      || current_function_args_size
1573
      || current_function_outgoing_args_size
1574
      || current_function_calls_eh_return
1575
 
1576
      /* If we're not supposed to emit prologue and epilogue, we must
1577
         not emit return-type instructions.  */
1578
      || !TARGET_PROLOGUE_EPILOGUE)
1579
    return false;
1580
 
1581
  if (current_function_uses_pic_offset_table)
1582
    {
1583
      push_topmost_sequence ();
1584
      got_really_used
1585
        = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
1586
      pop_topmost_sequence ();
1587
    }
1588
 
1589
  /* No simple epilogue if there are saved registers.  */
1590
  for (regno = 0; regno < reglimit; regno++)
1591
    if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1592
      return false;
1593
 
1594
  return true;
1595
}
1596
 
1597
/* Expand a return insn (just one insn) marked as using SRP or stack
1598
   slot depending on parameter ON_STACK.  */
1599
 
1600
void
1601
cris_expand_return (bool on_stack)
1602
{
1603
  /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1604
     tell "ret" from "jump [sp+]".  Some, but not all, other parts of
1605
     GCC expect just (return) to do the right thing when optimizing, so
1606
     we do that until they're fixed.  Currently, all return insns in a
1607
     function must be the same (not really a limiting factor) so we need
1608
     to check that it doesn't change half-way through.  */
1609
  emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1610
 
1611
  CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
1612
  CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
1613
 
1614
  cfun->machine->return_type
1615
    = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET;
1616
}
1617
 
1618
/* Compute a (partial) cost for rtx X.  Return true if the complete
1619
   cost has been computed, and false if subexpressions should be
1620
   scanned.  In either case, *TOTAL contains the cost result.  */
1621
 
1622
static bool
1623
cris_rtx_costs (rtx x, int code, int outer_code, int *total)
1624
{
1625
  switch (code)
1626
    {
1627
    case CONST_INT:
1628
      {
1629
        HOST_WIDE_INT val = INTVAL (x);
1630
        if (val == 0)
1631
          *total = 0;
1632
        else if (val < 32 && val >= -32)
1633
          *total = 1;
1634
        /* Eight or 16 bits are a word and cycle more expensive.  */
1635
        else if (val <= 32767 && val >= -32768)
1636
          *total = 2;
1637
        /* A 32 bit constant (or very seldom, unsigned 16 bits) costs
1638
           another word.  FIXME: This isn't linear to 16 bits.  */
1639
        else
1640
          *total = 4;
1641
        return true;
1642
      }
1643
 
1644
    case LABEL_REF:
1645
      *total = 6;
1646
      return true;
1647
 
1648
    case CONST:
1649
    case SYMBOL_REF:
1650
      *total = 6;
1651
      return true;
1652
 
1653
    case CONST_DOUBLE:
1654
      if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x)))
1655
        *total = 12;
1656
      else
1657
        /* Make 0.0 cheap, else test-insns will not be used.  */
1658
        *total = 0;
1659
      return true;
1660
 
1661
    case MULT:
1662
      /* Identify values that are no powers of two.  Powers of 2 are
1663
         taken care of already and those values should not be changed.  */
1664
      if (GET_CODE (XEXP (x, 1)) != CONST_INT
1665
          || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1666
        {
1667
          /* If we have a multiply insn, then the cost is between
1668
             1 and 2 "fast" instructions.  */
1669
          if (TARGET_HAS_MUL_INSNS)
1670
            {
1671
              *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
1672
              return true;
1673
            }
1674
 
1675
          /* Estimate as 4 + 4 * #ofbits.  */
1676
          *total = COSTS_N_INSNS (132);
1677
          return true;
1678
        }
1679
      return false;
1680
 
1681
    case UDIV:
1682
    case MOD:
1683
    case UMOD:
1684
    case DIV:
1685
      if (GET_CODE (XEXP (x, 1)) != CONST_INT
1686
          || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1687
        {
1688
          /* Estimate this as 4 + 8 * #of bits.  */
1689
          *total = COSTS_N_INSNS (260);
1690
          return true;
1691
        }
1692
      return false;
1693
 
1694
    case AND:
1695
      if (GET_CODE (XEXP (x, 1)) == CONST_INT
1696
          /* Two constants may actually happen before optimization.  */
1697
          && GET_CODE (XEXP (x, 0)) != CONST_INT
1698
          && !CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
1699
        {
1700
          *total = (rtx_cost (XEXP (x, 0), outer_code) + 2
1701
                    + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0))));
1702
          return true;
1703
        }
1704
      return false;
1705
 
1706
    case ZERO_EXTEND: case SIGN_EXTEND:
1707
      *total = rtx_cost (XEXP (x, 0), outer_code);
1708
      return true;
1709
 
1710
    default:
1711
      return false;
1712
    }
1713
}
1714
 
1715
/* The ADDRESS_COST worker.  */
1716
 
1717
static int
1718
cris_address_cost (rtx x)
1719
{
1720
  /* The metric to use for the cost-macros is unclear.
1721
     The metric used here is (the number of cycles needed) / 2,
1722
     where we consider equal a cycle for a word of code and a cycle to
1723
     read memory.  */
1724
 
1725
  /* The cheapest addressing modes get 0, since nothing extra is needed.  */
1726
  if (BASE_OR_AUTOINCR_P (x))
1727
    return 0;
1728
 
1729
  /* An indirect mem must be a DIP.  This means two bytes extra for code,
1730
     and 4 bytes extra for memory read, i.e.  (2 + 4) / 2.  */
1731
  if (GET_CODE (x) == MEM)
1732
    return (2 + 4) / 2;
1733
 
1734
  /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
1735
     an extra DIP prefix and 4 bytes of constant in most cases.  */
1736
  if (CONSTANT_P (x))
1737
    return (2 + 4) / 2;
1738
 
1739
  /* Handle BIAP and BDAP prefixes.  */
1740
  if (GET_CODE (x) == PLUS)
1741
    {
1742
      rtx tem1 = XEXP (x, 0);
1743
      rtx tem2 = XEXP (x, 1);
1744
 
1745
    /* A BIAP is 2 extra bytes for the prefix insn, nothing more.  We
1746
       recognize the typical MULT which is always in tem1 because of
1747
       insn canonicalization.  */
1748
    if ((GET_CODE (tem1) == MULT && BIAP_INDEX_P (tem1))
1749
        || REG_P (tem1))
1750
      return 2 / 2;
1751
 
1752
    /* A BDAP (quick) is 2 extra bytes.  Any constant operand to the
1753
       PLUS is always found in tem2.  */
1754
    if (GET_CODE (tem2) == CONST_INT
1755
        && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128)
1756
      return 2 / 2;
1757
 
1758
    /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
1759
       bytes.  */
1760
    if (GET_CODE (tem2) == CONST_INT
1761
        && CONST_OK_FOR_LETTER_P (INTVAL (tem2), 'L'))
1762
      return (2 + 2) / 2;
1763
 
1764
    /* A BDAP with some other constant is 2 bytes extra.  */
1765
    if (CONSTANT_P (tem2))
1766
      return (2 + 2 + 2) / 2;
1767
 
1768
    /* BDAP with something indirect should have a higher cost than
1769
       BIAP with register.   FIXME: Should it cost like a MEM or more?  */
1770
    /* Don't need to check it, it's the only one left.
1771
       FIXME:  There was a REG test missing, perhaps there are others.
1772
       Think more.  */
1773
    return (2 + 2 + 2) / 2;
1774
  }
1775
 
1776
  /* What else?  Return a high cost.  It matters only for valid
1777
     addressing modes.  */
1778
  return 10;
1779
}
1780
 
1781
/* Check various objections to the side-effect.  Used in the test-part
1782
   of an anonymous insn describing an insn with a possible side-effect.
1783
   Returns nonzero if the implied side-effect is ok.
1784
 
1785
   code     : PLUS or MULT
1786
   ops      : An array of rtx:es. lreg, rreg, rval,
1787
              The variables multop and other_op are indexes into this,
1788
              or -1 if they are not applicable.
1789
   lreg     : The register that gets assigned in the side-effect.
1790
   rreg     : One register in the side-effect expression
1791
   rval     : The other register, or an int.
1792
   multop   : An integer to multiply rval with.
1793
   other_op : One of the entities of the main effect,
1794
              whose mode we must consider.  */
1795
 
1796
int
1797
cris_side_effect_mode_ok (enum rtx_code code, rtx *ops,
1798
                          int lreg, int rreg, int rval,
1799
                          int multop, int other_op)
1800
{
1801
  /* Find what value to multiply with, for rx =ry + rz * n.  */
1802
  int mult = multop < 0 ? 1 : INTVAL (ops[multop]);
1803
 
1804
  rtx reg_rtx = ops[rreg];
1805
  rtx val_rtx = ops[rval];
1806
 
1807
  /* The operands may be swapped.  Canonicalize them in reg_rtx and
1808
     val_rtx, where reg_rtx always is a reg (for this constraint to
1809
     match).  */
1810
  if (! BASE_P (reg_rtx))
1811
    reg_rtx = val_rtx, val_rtx = ops[rreg];
1812
 
1813
  /* Don't forget to check that reg_rtx really is a reg.  If it isn't,
1814
     we have no business.  */
1815
  if (! BASE_P (reg_rtx))
1816
    return 0;
1817
 
1818
  /* Don't do this when -mno-split.  */
1819
  if (!TARGET_SIDE_EFFECT_PREFIXES)
1820
    return 0;
1821
 
1822
  /* The mult expression may be hidden in lreg.  FIXME:  Add more
1823
     commentary about that.  */
1824
  if (GET_CODE (val_rtx) == MULT)
1825
    {
1826
      mult = INTVAL (XEXP (val_rtx, 1));
1827
      val_rtx = XEXP (val_rtx, 0);
1828
      code = MULT;
1829
    }
1830
 
1831
  /* First check the "other operand".  */
1832
  if (other_op >= 0)
1833
    {
1834
      if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD)
1835
        return 0;
1836
 
1837
      /* Check if the lvalue register is the same as the "other
1838
         operand".  If so, the result is undefined and we shouldn't do
1839
         this.  FIXME:  Check again.  */
1840
      if ((BASE_P (ops[lreg])
1841
           && BASE_P (ops[other_op])
1842
           && REGNO (ops[lreg]) == REGNO (ops[other_op]))
1843
          || rtx_equal_p (ops[other_op], ops[lreg]))
1844
      return 0;
1845
    }
1846
 
1847
  /* Do not accept frame_pointer_rtx as any operand.  */
1848
  if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx
1849
      || ops[rval] == frame_pointer_rtx
1850
      || (other_op >= 0 && ops[other_op] == frame_pointer_rtx))
1851
    return 0;
1852
 
1853
  if (code == PLUS
1854
      && ! BASE_P (val_rtx))
1855
    {
1856
 
1857
      /* Do not allow rx = rx + n if a normal add or sub with same size
1858
         would do.  */
1859
      if (rtx_equal_p (ops[lreg], reg_rtx)
1860
          && GET_CODE (val_rtx) == CONST_INT
1861
          && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63))
1862
        return 0;
1863
 
1864
      /* Check allowed cases, like [r(+)?].[bwd] and const.  */
1865
      if (CONSTANT_P (val_rtx))
1866
        return 1;
1867
 
1868
      if (GET_CODE (val_rtx) == MEM
1869
          && BASE_OR_AUTOINCR_P (XEXP (val_rtx, 0)))
1870
        return 1;
1871
 
1872
      if (GET_CODE (val_rtx) == SIGN_EXTEND
1873
          && GET_CODE (XEXP (val_rtx, 0)) == MEM
1874
          && BASE_OR_AUTOINCR_P (XEXP (XEXP (val_rtx, 0), 0)))
1875
        return 1;
1876
 
1877
      /* If we got here, it's not a valid addressing mode.  */
1878
      return 0;
1879
    }
1880
  else if (code == MULT
1881
           || (code == PLUS && BASE_P (val_rtx)))
1882
    {
1883
      /* Do not allow rx = rx + ry.S, since it doesn't give better code.  */
1884
      if (rtx_equal_p (ops[lreg], reg_rtx)
1885
          || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx)))
1886
        return 0;
1887
 
1888
      /* Do not allow bad multiply-values.  */
1889
      if (mult != 1 && mult != 2 && mult != 4)
1890
        return 0;
1891
 
1892
      /* Only allow  r + ...  */
1893
      if (! BASE_P (reg_rtx))
1894
        return 0;
1895
 
1896
      /* If we got here, all seems ok.
1897
         (All checks need to be done above).  */
1898
      return 1;
1899
    }
1900
 
1901
  /* If we get here, the caller got its initial tests wrong.  */
1902
  internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
1903
}
1904
 
1905
/* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
1906
   does not handle the case where the IN operand is strict_low_part; it
1907
   does handle it for X.  Test-case in Axis-20010516.  This function takes
1908
   care of that for THIS port.  FIXME: strict_low_part is going away
1909
   anyway.  */
1910
 
1911
static int
1912
cris_reg_overlap_mentioned_p (rtx x, rtx in)
1913
{
1914
  /* The function reg_overlap_mentioned now handles when X is
1915
     strict_low_part, but not when IN is a STRICT_LOW_PART.  */
1916
  if (GET_CODE (in) == STRICT_LOW_PART)
1917
    in = XEXP (in, 0);
1918
 
1919
  return reg_overlap_mentioned_p (x, in);
1920
}
1921
 
1922
/* The TARGET_ASM_NAMED_SECTION worker.
1923
   We just dispatch to the functions for ELF and a.out.  */
1924
 
1925
void
1926
cris_target_asm_named_section (const char *name, unsigned int flags,
1927
                               tree decl)
1928
{
1929
  if (! TARGET_ELF)
1930
    default_no_named_section (name, flags, decl);
1931
  else
1932
    default_elf_asm_named_section (name, flags, decl);
1933
}
1934
 
1935
/* Return TRUE iff X is a CONST valid for e.g. indexing.  */
1936
 
1937
bool
1938
cris_valid_pic_const (rtx x)
1939
{
1940
  gcc_assert (flag_pic);
1941
 
1942
  switch (GET_CODE (x))
1943
    {
1944
    case CONST_INT:
1945
    case CONST_DOUBLE:
1946
      return true;
1947
    default:
1948
      ;
1949
    }
1950
 
1951
  if (GET_CODE (x) != CONST)
1952
    return false;
1953
 
1954
  x = XEXP (x, 0);
1955
 
1956
  /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))).  */
1957
  if (GET_CODE (x) == PLUS
1958
      && GET_CODE (XEXP (x, 0)) == UNSPEC
1959
      && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL
1960
      && GET_CODE (XEXP (x, 1)) == CONST_INT)
1961
    x = XEXP (x, 0);
1962
 
1963
  if (GET_CODE (x) == UNSPEC)
1964
    switch (XINT (x, 1))
1965
      {
1966
      case CRIS_UNSPEC_PLT:
1967
      case CRIS_UNSPEC_PLTGOTREAD:
1968
      case CRIS_UNSPEC_GOTREAD:
1969
      case CRIS_UNSPEC_GOTREL:
1970
        return true;
1971
      default:
1972
        gcc_unreachable ();
1973
      }
1974
 
1975
  return cris_pic_symbol_type_of (x) == cris_no_symbol;
1976
}
1977
 
1978
/* Helper function to find the right PIC-type symbol to generate,
1979
   given the original (non-PIC) representation.  */
1980
 
1981
enum cris_pic_symbol_type
1982
cris_pic_symbol_type_of (rtx x)
1983
{
1984
  switch (GET_CODE (x))
1985
    {
1986
    case SYMBOL_REF:
1987
      return SYMBOL_REF_LOCAL_P (x)
1988
        ? cris_gotrel_symbol : cris_got_symbol;
1989
 
1990
    case LABEL_REF:
1991
      return cris_gotrel_symbol;
1992
 
1993
    case CONST:
1994
      return cris_pic_symbol_type_of (XEXP (x, 0));
1995
 
1996
    case PLUS:
1997
    case MINUS:
1998
      {
1999
        enum cris_pic_symbol_type t1 = cris_pic_symbol_type_of (XEXP (x, 0));
2000
        enum cris_pic_symbol_type t2 = cris_pic_symbol_type_of (XEXP (x, 1));
2001
 
2002
        gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol);
2003
 
2004
        if (t1 == cris_got_symbol || t1 == cris_got_symbol)
2005
          return cris_got_symbol_needing_fixup;
2006
 
2007
        return t1 != cris_no_symbol ? t1 : t2;
2008
      }
2009
 
2010
    case CONST_INT:
2011
    case CONST_DOUBLE:
2012
      return cris_no_symbol;
2013
 
2014
    case UNSPEC:
2015
      /* Likely an offsettability-test attempting to add a constant to
2016
         a GOTREAD symbol, which can't be handled.  */
2017
      return cris_invalid_pic_symbol;
2018
 
2019
    default:
2020
      fatal_insn ("unrecognized supposed constant", x);
2021
    }
2022
 
2023
  gcc_unreachable ();
2024
}
2025
 
2026
/* The LEGITIMATE_PIC_OPERAND_P worker.  */
2027
 
2028
int
2029
cris_legitimate_pic_operand (rtx x)
2030
{
2031
  /* Symbols are not valid PIC operands as-is; just constants.  */
2032
  return cris_valid_pic_const (x);
2033
}
2034
 
2035
/* TARGET_HANDLE_OPTION worker.  We just store the values into local
2036
   variables here.  Checks for correct semantics are in
2037
   cris_override_options.  */
2038
 
2039
static bool
2040
cris_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
2041
                    int value ATTRIBUTE_UNUSED)
2042
{
2043
  switch (code)
2044
    {
2045
    case OPT_metrax100:
2046
      target_flags
2047
        |= (MASK_SVINTO
2048
            + MASK_ETRAX4_ADD
2049
            + MASK_ALIGN_BY_32);
2050
      break;
2051
 
2052
    case OPT_mno_etrax100:
2053
      target_flags
2054
        &= ~(MASK_SVINTO
2055
             + MASK_ETRAX4_ADD
2056
             + MASK_ALIGN_BY_32);
2057
      break;
2058
 
2059
    case OPT_m32_bit:
2060
    case OPT_m32bit:
2061
      target_flags
2062
        |= (MASK_STACK_ALIGN
2063
            + MASK_CONST_ALIGN
2064
            + MASK_DATA_ALIGN
2065
            + MASK_ALIGN_BY_32);
2066
      break;
2067
 
2068
    case OPT_m16_bit:
2069
    case OPT_m16bit:
2070
      target_flags
2071
        |= (MASK_STACK_ALIGN
2072
            + MASK_CONST_ALIGN
2073
            + MASK_DATA_ALIGN);
2074
      break;
2075
 
2076
    case OPT_m8_bit:
2077
    case OPT_m8bit:
2078
      target_flags
2079
        &= ~(MASK_STACK_ALIGN
2080
             + MASK_CONST_ALIGN
2081
             + MASK_DATA_ALIGN);
2082
      break;
2083
 
2084
    default:
2085
      break;
2086
    }
2087
 
2088
  CRIS_SUBTARGET_HANDLE_OPTION(code, arg, value);
2089
 
2090
  return true;
2091
}
2092
 
2093
/* The OVERRIDE_OPTIONS worker.
2094
   As is the norm, this also parses -mfoo=bar type parameters.  */
2095
 
2096
void
2097
cris_override_options (void)
2098
{
2099
  if (cris_max_stackframe_str)
2100
    {
2101
      cris_max_stackframe = atoi (cris_max_stackframe_str);
2102
 
2103
      /* Do some sanity checking.  */
2104
      if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000)
2105
        internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2106
                        cris_max_stackframe, 0x20000000);
2107
    }
2108
 
2109
  /* Let "-metrax4" and "-metrax100" change the cpu version.  */
2110
  if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO)
2111
    cris_cpu_version = CRIS_CPU_SVINTO;
2112
  else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4)
2113
    cris_cpu_version = CRIS_CPU_ETRAX4;
2114
 
2115
  /* Parse -march=... and its synonym, the deprecated -mcpu=...  */
2116
  if (cris_cpu_str)
2117
    {
2118
      cris_cpu_version
2119
        = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1);
2120
 
2121
      if (strcmp ("etrax4", cris_cpu_str) == 0)
2122
        cris_cpu_version = 3;
2123
 
2124
      if (strcmp ("svinto", cris_cpu_str) == 0
2125
          || strcmp ("etrax100", cris_cpu_str) == 0)
2126
        cris_cpu_version = 8;
2127
 
2128
      if (strcmp ("ng", cris_cpu_str) == 0
2129
          || strcmp ("etrax100lx", cris_cpu_str) == 0)
2130
        cris_cpu_version = 10;
2131
 
2132
      if (cris_cpu_version < 0 || cris_cpu_version > 10)
2133
        error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2134
               cris_cpu_str);
2135
 
2136
      /* Set the target flags.  */
2137
      if (cris_cpu_version >= CRIS_CPU_ETRAX4)
2138
        target_flags |= MASK_ETRAX4_ADD;
2139
 
2140
      /* If this is Svinto or higher, align for 32 bit accesses.  */
2141
      if (cris_cpu_version >= CRIS_CPU_SVINTO)
2142
        target_flags
2143
          |= (MASK_SVINTO | MASK_ALIGN_BY_32
2144
              | MASK_STACK_ALIGN | MASK_CONST_ALIGN
2145
              | MASK_DATA_ALIGN);
2146
 
2147
      /* Note that we do not add new flags when it can be completely
2148
         described with a macro that uses -mcpu=X.  So
2149
         TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG).  */
2150
    }
2151
 
2152
  if (cris_tune_str)
2153
    {
2154
      int cris_tune
2155
        = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1);
2156
 
2157
      if (strcmp ("etrax4", cris_tune_str) == 0)
2158
        cris_tune = 3;
2159
 
2160
      if (strcmp ("svinto", cris_tune_str) == 0
2161
          || strcmp ("etrax100", cris_tune_str) == 0)
2162
        cris_tune = 8;
2163
 
2164
      if (strcmp ("ng", cris_tune_str) == 0
2165
          || strcmp ("etrax100lx", cris_tune_str) == 0)
2166
        cris_tune = 10;
2167
 
2168
      if (cris_tune < 0 || cris_tune > 10)
2169
        error ("unknown CRIS cpu version specification in -mtune= : %s",
2170
               cris_tune_str);
2171
 
2172
      if (cris_tune >= CRIS_CPU_SVINTO)
2173
        /* We have currently nothing more to tune than alignment for
2174
           memory accesses.  */
2175
        target_flags
2176
          |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN
2177
              | MASK_DATA_ALIGN | MASK_ALIGN_BY_32);
2178
    }
2179
 
2180
  if (flag_pic)
2181
    {
2182
      /* Use error rather than warning, so invalid use is easily
2183
         detectable.  Still change to the values we expect, to avoid
2184
         further errors.  */
2185
      if (! TARGET_LINUX)
2186
        {
2187
          error ("-fPIC and -fpic are not supported in this configuration");
2188
          flag_pic = 0;
2189
        }
2190
 
2191
      /* Turn off function CSE.  We need to have the addresses reach the
2192
         call expanders to get PLT-marked, as they could otherwise be
2193
         compared against zero directly or indirectly.  After visiting the
2194
         call expanders they will then be cse:ed, as the call expanders
2195
         force_reg the addresses, effectively forcing flag_no_function_cse
2196
         to 0.  */
2197
      flag_no_function_cse = 1;
2198
    }
2199
 
2200
  if (write_symbols == DWARF2_DEBUG && ! TARGET_ELF)
2201
    {
2202
      warning (0, "that particular -g option is invalid with -maout and -melinux");
2203
      write_symbols = DBX_DEBUG;
2204
    }
2205
 
2206
  /* Set the per-function-data initializer.  */
2207
  init_machine_status = cris_init_machine_status;
2208
}
2209
 
2210
/* The TARGET_ASM_OUTPUT_MI_THUNK worker.  */
2211
 
2212
static void
2213
cris_asm_output_mi_thunk (FILE *stream,
2214
                          tree thunkdecl ATTRIBUTE_UNUSED,
2215
                          HOST_WIDE_INT delta,
2216
                          HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2217
                          tree funcdecl)
2218
{
2219
  if (delta > 0)
2220
    fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2221
             ADDITIVE_SIZE_MODIFIER (delta), delta,
2222
             reg_names[CRIS_FIRST_ARG_REG]);
2223
  else if (delta < 0)
2224
    fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2225
             ADDITIVE_SIZE_MODIFIER (-delta), -delta,
2226
             reg_names[CRIS_FIRST_ARG_REG]);
2227
 
2228
  if (flag_pic)
2229
    {
2230
      const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0);
2231
 
2232
      name = (* targetm.strip_name_encoding) (name);
2233
      fprintf (stream, "add.d ");
2234
      assemble_name (stream, name);
2235
      fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX);
2236
    }
2237
  else
2238
    {
2239
      fprintf (stream, "jump ");
2240
      assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0));
2241
      fprintf (stream, "\n");
2242
    }
2243
}
2244
 
2245
/* Boilerplate emitted at start of file.
2246
 
2247
   NO_APP *only at file start* means faster assembly.  It also means
2248
   comments are not allowed.  In some cases comments will be output
2249
   for debugging purposes.  Make sure they are allowed then.
2250
 
2251
   We want a .file directive only if TARGET_ELF.  */
2252
static void
2253
cris_file_start (void)
2254
{
2255
  /* These expressions can vary at run time, so we cannot put
2256
     them into TARGET_INITIALIZER.  */
2257
  targetm.file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name);
2258
  targetm.file_start_file_directive = TARGET_ELF;
2259
 
2260
  default_file_start ();
2261
}
2262
 
2263
/* Rename the function calls for integer multiply and divide.  */
2264
static void
2265
cris_init_libfuncs (void)
2266
{
2267
  set_optab_libfunc (smul_optab, SImode, "__Mul");
2268
  set_optab_libfunc (sdiv_optab, SImode, "__Div");
2269
  set_optab_libfunc (udiv_optab, SImode, "__Udiv");
2270
  set_optab_libfunc (smod_optab, SImode, "__Mod");
2271
  set_optab_libfunc (umod_optab, SImode, "__Umod");
2272
}
2273
 
2274
/* The INIT_EXPANDERS worker sets the per-function-data initializer and
2275
   mark functions.  */
2276
 
2277
void
2278
cris_init_expanders (void)
2279
{
2280
  /* Nothing here at the moment.  */
2281
}
2282
 
2283
/* Zero initialization is OK for all current fields.  */
2284
 
2285
static struct machine_function *
2286
cris_init_machine_status (void)
2287
{
2288
  return ggc_alloc_cleared (sizeof (struct machine_function));
2289
}
2290
 
2291
/* Split a 2 word move (DI or presumably DF) into component parts.
2292
   Originally a copy of gen_split_move_double in m32r.c.  */
2293
 
2294
rtx
2295
cris_split_movdx (rtx *operands)
2296
{
2297
  enum machine_mode mode = GET_MODE (operands[0]);
2298
  rtx dest = operands[0];
2299
  rtx src  = operands[1];
2300
  rtx val;
2301
 
2302
  /* We used to have to handle (SUBREG (MEM)) here, but that should no
2303
     longer happen; after reload there are no SUBREGs any more, and we're
2304
     only called after reload.  */
2305
  CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
2306
 
2307
  start_sequence ();
2308
  if (GET_CODE (dest) == REG)
2309
    {
2310
      int dregno = REGNO (dest);
2311
 
2312
      /* Reg-to-reg copy.  */
2313
      if (GET_CODE (src) == REG)
2314
        {
2315
          int sregno = REGNO (src);
2316
 
2317
          int reverse = (dregno == sregno + 1);
2318
 
2319
          /* We normally copy the low-numbered register first.  However, if
2320
             the first register operand 0 is the same as the second register of
2321
             operand 1, we must copy in the opposite order.  */
2322
          emit_insn (gen_rtx_SET (VOIDmode,
2323
                                  operand_subword (dest, reverse, TRUE, mode),
2324
                                  operand_subword (src, reverse, TRUE, mode)));
2325
 
2326
          emit_insn (gen_rtx_SET (VOIDmode,
2327
                                  operand_subword (dest, !reverse, TRUE, mode),
2328
                                  operand_subword (src, !reverse, TRUE, mode)));
2329
        }
2330
      /* Constant-to-reg copy.  */
2331
      else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
2332
        {
2333
          rtx words[2];
2334
          split_double (src, &words[0], &words[1]);
2335
          emit_insn (gen_rtx_SET (VOIDmode,
2336
                                  operand_subword (dest, 0, TRUE, mode),
2337
                                  words[0]));
2338
 
2339
          emit_insn (gen_rtx_SET (VOIDmode,
2340
                                  operand_subword (dest, 1, TRUE, mode),
2341
                                  words[1]));
2342
        }
2343
      /* Mem-to-reg copy.  */
2344
      else if (GET_CODE (src) == MEM)
2345
        {
2346
          /* If the high-address word is used in the address, we must load it
2347
             last.  Otherwise, load it first.  */
2348
          rtx addr = XEXP (src, 0);
2349
          int reverse
2350
            = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0);
2351
 
2352
          /* The original code implies that we can't do
2353
             move.x [rN+],rM  move.x [rN],rM+1
2354
             when rN is dead, because of REG_NOTES damage.  That is
2355
             consistent with what I've seen, so don't try it.
2356
 
2357
             We have two different cases here; if the addr is POST_INC,
2358
             just pass it through, otherwise add constants.  */
2359
 
2360
          if (GET_CODE (addr) == POST_INC)
2361
            {
2362
              rtx mem;
2363
              rtx insn;
2364
 
2365
              /* Whenever we emit insns with post-incremented
2366
                 addresses ourselves, we must add a post-inc note
2367
                 manually.  */
2368
              mem = change_address (src, SImode, addr);
2369
              insn
2370
                = gen_rtx_SET (VOIDmode,
2371
                               operand_subword (dest, 0, TRUE, mode), mem);
2372
              insn = emit_insn (insn);
2373
              if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2374
                REG_NOTES (insn)
2375
                  = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2376
                                     REG_NOTES (insn));
2377
 
2378
              mem = change_address (src, SImode, addr);
2379
              insn
2380
                = gen_rtx_SET (VOIDmode,
2381
                               operand_subword (dest, 1, TRUE, mode), mem);
2382
              insn = emit_insn (insn);
2383
              if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2384
                REG_NOTES (insn)
2385
                  = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2386
                                     REG_NOTES (insn));
2387
            }
2388
          else
2389
            {
2390
              /* Make sure we don't get any other addresses with
2391
                 embedded postincrements.  They should be stopped in
2392
                 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2393
                 safety.  */
2394
              if (side_effects_p (addr))
2395
                fatal_insn ("unexpected side-effects in address", addr);
2396
 
2397
              emit_insn (gen_rtx_SET
2398
                         (VOIDmode,
2399
                          operand_subword (dest, reverse, TRUE, mode),
2400
                          change_address
2401
                          (src, SImode,
2402
                           plus_constant (addr,
2403
                                          reverse * UNITS_PER_WORD))));
2404
              emit_insn (gen_rtx_SET
2405
                         (VOIDmode,
2406
                          operand_subword (dest, ! reverse, TRUE, mode),
2407
                          change_address
2408
                          (src, SImode,
2409
                           plus_constant (addr,
2410
                                          (! reverse) *
2411
                                          UNITS_PER_WORD))));
2412
            }
2413
        }
2414
      else
2415
        internal_error ("Unknown src");
2416
    }
2417
  /* Reg-to-mem copy or clear mem.  */
2418
  else if (GET_CODE (dest) == MEM
2419
           && (GET_CODE (src) == REG
2420
               || src == const0_rtx
2421
               || src == CONST0_RTX (DFmode)))
2422
    {
2423
      rtx addr = XEXP (dest, 0);
2424
 
2425
      if (GET_CODE (addr) == POST_INC)
2426
        {
2427
          rtx mem;
2428
          rtx insn;
2429
 
2430
          /* Whenever we emit insns with post-incremented addresses
2431
             ourselves, we must add a post-inc note manually.  */
2432
          mem = change_address (dest, SImode, addr);
2433
          insn
2434
            = gen_rtx_SET (VOIDmode,
2435
                           mem, operand_subword (src, 0, TRUE, mode));
2436
          insn = emit_insn (insn);
2437
          if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2438
            REG_NOTES (insn)
2439
              = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2440
                                 REG_NOTES (insn));
2441
 
2442
          mem = change_address (dest, SImode, addr);
2443
          insn
2444
            = gen_rtx_SET (VOIDmode,
2445
                           mem,
2446
                           operand_subword (src, 1, TRUE, mode));
2447
          insn = emit_insn (insn);
2448
          if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2449
            REG_NOTES (insn)
2450
              = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2451
                                 REG_NOTES (insn));
2452
        }
2453
      else
2454
        {
2455
          /* Make sure we don't get any other addresses with embedded
2456
             postincrements.  They should be stopped in
2457
             GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety.  */
2458
          if (side_effects_p (addr))
2459
            fatal_insn ("unexpected side-effects in address", addr);
2460
 
2461
          emit_insn (gen_rtx_SET
2462
                     (VOIDmode,
2463
                      change_address (dest, SImode, addr),
2464
                      operand_subword (src, 0, TRUE, mode)));
2465
 
2466
          emit_insn (gen_rtx_SET
2467
                     (VOIDmode,
2468
                      change_address (dest, SImode,
2469
                                      plus_constant (addr,
2470
                                                     UNITS_PER_WORD)),
2471
                      operand_subword (src, 1, TRUE, mode)));
2472
        }
2473
    }
2474
 
2475
  else
2476
    internal_error ("Unknown dest");
2477
 
2478
  val = get_insns ();
2479
  end_sequence ();
2480
  return val;
2481
}
2482
 
2483
/* The expander for the prologue pattern name.  */
2484
 
2485
void
2486
cris_expand_prologue (void)
2487
{
2488
  int regno;
2489
  int size = get_frame_size ();
2490
  /* Shorten the used name for readability.  */
2491
  int cfoa_size = current_function_outgoing_args_size;
2492
  int last_movem_reg = -1;
2493
  int framesize = 0;
2494
  rtx mem, insn;
2495
  int return_address_on_stack = cris_return_address_on_stack ();
2496
  int got_really_used = false;
2497
  int n_movem_regs = 0;
2498
  int pretend = current_function_pretend_args_size;
2499
 
2500
  /* Don't do anything if no prologues or epilogues are wanted.  */
2501
  if (!TARGET_PROLOGUE_EPILOGUE)
2502
    return;
2503
 
2504
  CRIS_ASSERT (size >= 0);
2505
 
2506
  if (current_function_uses_pic_offset_table)
2507
    {
2508
      /* A reference may have been optimized out (like the abort () in
2509
         fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2510
         it's still used.  */
2511
      push_topmost_sequence ();
2512
      got_really_used
2513
        = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
2514
      pop_topmost_sequence ();
2515
    }
2516
 
2517
  /* Align the size to what's best for the CPU model.  */
2518
  if (TARGET_STACK_ALIGN)
2519
    size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
2520
 
2521
  if (pretend)
2522
    {
2523
      /* See also cris_setup_incoming_varargs where
2524
         cfun->machine->stdarg_regs is set.  There are other setters of
2525
         current_function_pretend_args_size than stdarg handling, like
2526
         for an argument passed with parts in R13 and stack.  We must
2527
         not store R13 into the pretend-area for that case, as GCC does
2528
         that itself.  "Our" store would be marked as redundant and GCC
2529
         will attempt to remove it, which will then be flagged as an
2530
         internal error; trying to remove a frame-related insn.  */
2531
      int stdarg_regs = cfun->machine->stdarg_regs;
2532
 
2533
      framesize += pretend;
2534
 
2535
      for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1;
2536
           stdarg_regs > 0;
2537
           regno--, pretend -= 4, stdarg_regs--)
2538
        {
2539
          insn = emit_insn (gen_rtx_SET (VOIDmode,
2540
                                         stack_pointer_rtx,
2541
                                         plus_constant (stack_pointer_rtx,
2542
                                                        -4)));
2543
          /* FIXME: When dwarf2 frame output and unless asynchronous
2544
             exceptions, make dwarf2 bundle together all stack
2545
             adjustments like it does for registers between stack
2546
             adjustments.  */
2547
          RTX_FRAME_RELATED_P (insn) = 1;
2548
 
2549
          mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2550
          set_mem_alias_set (mem, get_varargs_alias_set ());
2551
          insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2552
 
2553
          /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2554
             the value isn't restored, so we don't want to tell dwarf2
2555
             that it's been stored to stack, else EH handling info would
2556
             get confused.  */
2557
        }
2558
 
2559
      /* For other setters of current_function_pretend_args_size, we
2560
         just adjust the stack by leaving the remaining size in
2561
         "pretend", handled below.  */
2562
    }
2563
 
2564
  /* Save SRP if not a leaf function.  */
2565
  if (return_address_on_stack)
2566
    {
2567
      insn = emit_insn (gen_rtx_SET (VOIDmode,
2568
                                     stack_pointer_rtx,
2569
                                     plus_constant (stack_pointer_rtx,
2570
                                                    -4 - pretend)));
2571
      pretend = 0;
2572
      RTX_FRAME_RELATED_P (insn) = 1;
2573
 
2574
      mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2575
      set_mem_alias_set (mem, get_frame_alias_set ());
2576
      insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM));
2577
      RTX_FRAME_RELATED_P (insn) = 1;
2578
      framesize += 4;
2579
    }
2580
 
2581
  /* Set up the frame pointer, if needed.  */
2582
  if (frame_pointer_needed)
2583
    {
2584
      insn = emit_insn (gen_rtx_SET (VOIDmode,
2585
                                     stack_pointer_rtx,
2586
                                     plus_constant (stack_pointer_rtx,
2587
                                                    -4 - pretend)));
2588
      pretend = 0;
2589
      RTX_FRAME_RELATED_P (insn) = 1;
2590
 
2591
      mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2592
      set_mem_alias_set (mem, get_frame_alias_set ());
2593
      insn = emit_move_insn (mem, frame_pointer_rtx);
2594
      RTX_FRAME_RELATED_P (insn) = 1;
2595
 
2596
      insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2597
      RTX_FRAME_RELATED_P (insn) = 1;
2598
 
2599
      framesize += 4;
2600
    }
2601
 
2602
  /* Between frame-pointer and saved registers lie the area for local
2603
     variables.  If we get here with "pretended" size remaining, count
2604
     it into the general stack size.  */
2605
  size += pretend;
2606
 
2607
  /* Get a contiguous sequence of registers, starting with R0, that need
2608
     to be saved.  */
2609
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2610
    {
2611
      if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2612
        {
2613
          n_movem_regs++;
2614
 
2615
          /* Check if movem may be used for registers so far.  */
2616
          if (regno == last_movem_reg + 1)
2617
            /* Yes, update next expected register.  */
2618
            last_movem_reg = regno;
2619
          else
2620
            {
2621
              /* We cannot use movem for all registers.  We have to flush
2622
                 any movem:ed registers we got so far.  */
2623
              if (last_movem_reg != -1)
2624
                {
2625
                  int n_saved
2626
                    = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2627
 
2628
                  /* It is a win to use a side-effect assignment for
2629
                     64 <= size <= 128.  But side-effect on movem was
2630
                     not usable for CRIS v0..3.  Also only do it if
2631
                     side-effects insns are allowed.  */
2632
                  if ((last_movem_reg + 1) * 4 + size >= 64
2633
                      && (last_movem_reg + 1) * 4 + size <= 128
2634
                      && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2635
                      && TARGET_SIDE_EFFECT_PREFIXES)
2636
                    {
2637
                      mem
2638
                        = gen_rtx_MEM (SImode,
2639
                                       plus_constant (stack_pointer_rtx,
2640
                                                      -(n_saved * 4 + size)));
2641
                      set_mem_alias_set (mem, get_frame_alias_set ());
2642
                      insn
2643
                        = cris_emit_movem_store (mem, GEN_INT (n_saved),
2644
                                                 -(n_saved * 4 + size),
2645
                                                 true);
2646
                    }
2647
                  else
2648
                    {
2649
                      insn
2650
                        = gen_rtx_SET (VOIDmode,
2651
                                       stack_pointer_rtx,
2652
                                       plus_constant (stack_pointer_rtx,
2653
                                                      -(n_saved * 4 + size)));
2654
                      insn = emit_insn (insn);
2655
                      RTX_FRAME_RELATED_P (insn) = 1;
2656
 
2657
                      mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2658
                      set_mem_alias_set (mem, get_frame_alias_set ());
2659
                      insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
2660
                                                    0, true);
2661
                    }
2662
 
2663
                  framesize += n_saved * 4 + size;
2664
                  last_movem_reg = -1;
2665
                  size = 0;
2666
                }
2667
 
2668
              insn = emit_insn (gen_rtx_SET (VOIDmode,
2669
                                             stack_pointer_rtx,
2670
                                             plus_constant (stack_pointer_rtx,
2671
                                                            -4 - size)));
2672
              RTX_FRAME_RELATED_P (insn) = 1;
2673
 
2674
              mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2675
              set_mem_alias_set (mem, get_frame_alias_set ());
2676
              insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2677
              RTX_FRAME_RELATED_P (insn) = 1;
2678
 
2679
              framesize += 4 + size;
2680
              size = 0;
2681
            }
2682
        }
2683
    }
2684
 
2685
  /* Check after, if we could movem all registers.  This is the normal case.  */
2686
  if (last_movem_reg != -1)
2687
    {
2688
      int n_saved
2689
        = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2690
 
2691
      /* Side-effect on movem was not usable for CRIS v0..3.  Also only
2692
         do it if side-effects insns are allowed.  */
2693
      if ((last_movem_reg + 1) * 4 + size >= 64
2694
          && (last_movem_reg + 1) * 4 + size <= 128
2695
          && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2696
          && TARGET_SIDE_EFFECT_PREFIXES)
2697
        {
2698
          mem
2699
            = gen_rtx_MEM (SImode,
2700
                           plus_constant (stack_pointer_rtx,
2701
                                          -(n_saved * 4 + size)));
2702
          set_mem_alias_set (mem, get_frame_alias_set ());
2703
          insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
2704
                                        -(n_saved * 4 + size), true);
2705
        }
2706
      else
2707
        {
2708
          insn
2709
            = gen_rtx_SET (VOIDmode,
2710
                           stack_pointer_rtx,
2711
                           plus_constant (stack_pointer_rtx,
2712
                                          -(n_saved * 4 + size)));
2713
          insn = emit_insn (insn);
2714
          RTX_FRAME_RELATED_P (insn) = 1;
2715
 
2716
          mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2717
          set_mem_alias_set (mem, get_frame_alias_set ());
2718
          insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true);
2719
        }
2720
 
2721
      framesize += n_saved * 4 + size;
2722
      /* We have to put outgoing argument space after regs.  */
2723
      if (cfoa_size)
2724
        {
2725
          insn = emit_insn (gen_rtx_SET (VOIDmode,
2726
                                         stack_pointer_rtx,
2727
                                         plus_constant (stack_pointer_rtx,
2728
                                                        -cfoa_size)));
2729
          RTX_FRAME_RELATED_P (insn) = 1;
2730
          framesize += cfoa_size;
2731
        }
2732
    }
2733
  else if ((size + cfoa_size) > 0)
2734
    {
2735
      insn = emit_insn (gen_rtx_SET (VOIDmode,
2736
                                     stack_pointer_rtx,
2737
                                     plus_constant (stack_pointer_rtx,
2738
                                                    -(cfoa_size + size))));
2739
      RTX_FRAME_RELATED_P (insn) = 1;
2740
      framesize += size + cfoa_size;
2741
    }
2742
 
2743
  /* Set up the PIC register, if it is used.  */
2744
  if (got_really_used)
2745
    {
2746
      rtx got
2747
        = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT);
2748
      emit_move_insn (pic_offset_table_rtx, got);
2749
 
2750
      /* FIXME: This is a cover-up for flow2 messing up; it doesn't
2751
         follow exceptional paths and tries to delete the GOT load as
2752
         unused, if it isn't used on the non-exceptional paths.  Other
2753
         ports have similar or other cover-ups, or plain bugs marking
2754
         the GOT register load as maybe-dead.  To see this, remove the
2755
         line below and try libsupc++/vec.cc or a trivial
2756
         "static void y (); void x () {try {y ();} catch (...) {}}".  */
2757
      emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2758
    }
2759
 
2760
  if (cris_max_stackframe && framesize > cris_max_stackframe)
2761
    warning (0, "stackframe too big: %d bytes", framesize);
2762
}
2763
 
2764
/* The expander for the epilogue pattern.  */
2765
 
2766
void
2767
cris_expand_epilogue (void)
2768
{
2769
  int regno;
2770
  int size = get_frame_size ();
2771
  int last_movem_reg = -1;
2772
  int argspace_offset = current_function_outgoing_args_size;
2773
  int pretend =  current_function_pretend_args_size;
2774
  rtx mem;
2775
  bool return_address_on_stack = cris_return_address_on_stack ();
2776
  /* A reference may have been optimized out
2777
     (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
2778
     so check that it's still used.  */
2779
  int got_really_used = false;
2780
  int n_movem_regs = 0;
2781
 
2782
  if (!TARGET_PROLOGUE_EPILOGUE)
2783
    return;
2784
 
2785
  if (current_function_uses_pic_offset_table)
2786
    {
2787
      /* A reference may have been optimized out (like the abort () in
2788
         fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2789
         it's still used.  */
2790
      push_topmost_sequence ();
2791
      got_really_used
2792
        = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
2793
      pop_topmost_sequence ();
2794
    }
2795
 
2796
  /* Align byte count of stack frame.  */
2797
  if (TARGET_STACK_ALIGN)
2798
    size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
2799
 
2800
  /* Check how many saved regs we can movem.  They start at r0 and must
2801
     be contiguous.  */
2802
  for (regno = 0;
2803
       regno < FIRST_PSEUDO_REGISTER;
2804
       regno++)
2805
    if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2806
      {
2807
        n_movem_regs++;
2808
 
2809
        if (regno == last_movem_reg + 1)
2810
          last_movem_reg = regno;
2811
        else
2812
          break;
2813
      }
2814
 
2815
  /* If there was only one register that really needed to be saved
2816
     through movem, don't use movem.  */
2817
  if (n_movem_regs == 1)
2818
    last_movem_reg = -1;
2819
 
2820
  /* Now emit "normal" move insns for all regs higher than the movem
2821
     regs.  */
2822
  for (regno = FIRST_PSEUDO_REGISTER - 1;
2823
       regno > last_movem_reg;
2824
       regno--)
2825
    if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2826
      {
2827
        rtx insn;
2828
 
2829
        if (argspace_offset)
2830
          {
2831
            /* There is an area for outgoing parameters located before
2832
               the saved registers.  We have to adjust for that.  */
2833
            emit_insn (gen_rtx_SET (VOIDmode,
2834
                                    stack_pointer_rtx,
2835
                                    plus_constant (stack_pointer_rtx,
2836
                                                   argspace_offset)));
2837
            /* Make sure we only do this once.  */
2838
            argspace_offset = 0;
2839
          }
2840
 
2841
        mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
2842
                                                     stack_pointer_rtx));
2843
        set_mem_alias_set (mem, get_frame_alias_set ());
2844
        insn = emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem);
2845
 
2846
        /* Whenever we emit insns with post-incremented addresses
2847
           ourselves, we must add a post-inc note manually.  */
2848
        REG_NOTES (insn)
2849
          = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2850
      }
2851
 
2852
  /* If we have any movem-restore, do it now.  */
2853
  if (last_movem_reg != -1)
2854
    {
2855
      rtx insn;
2856
 
2857
      if (argspace_offset)
2858
        {
2859
          emit_insn (gen_rtx_SET (VOIDmode,
2860
                                  stack_pointer_rtx,
2861
                                  plus_constant (stack_pointer_rtx,
2862
                                                 argspace_offset)));
2863
          argspace_offset = 0;
2864
        }
2865
 
2866
      mem = gen_rtx_MEM (SImode,
2867
                         gen_rtx_POST_INC (SImode, stack_pointer_rtx));
2868
      set_mem_alias_set (mem, get_frame_alias_set ());
2869
      insn
2870
        = emit_insn (cris_gen_movem_load (mem,
2871
                                          GEN_INT (last_movem_reg + 1), 0));
2872
      /* Whenever we emit insns with post-incremented addresses
2873
         ourselves, we must add a post-inc note manually.  */
2874
      if (side_effects_p (PATTERN (insn)))
2875
        REG_NOTES (insn)
2876
          = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2877
    }
2878
 
2879
  /* If we don't clobber all of the allocated stack area (we've already
2880
     deallocated saved registers), GCC might want to schedule loads from
2881
     the stack to *after* the stack-pointer restore, which introduces an
2882
     interrupt race condition.  This happened for the initial-value
2883
     SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
2884
     other failure for that test).  It also happened for the stack slot
2885
     for the return value in (one version of)
2886
     linux/fs/dcache.c:__d_lookup, at least with "-O2
2887
     -fno-omit-frame-pointer".  */
2888
 
2889
  /* Restore frame pointer if necessary.  */
2890
  if (frame_pointer_needed)
2891
    {
2892
      rtx insn;
2893
 
2894
      emit_insn (gen_cris_frame_deallocated_barrier ());
2895
 
2896
      emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
2897
      mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
2898
                                                   stack_pointer_rtx));
2899
      set_mem_alias_set (mem, get_frame_alias_set ());
2900
      insn = emit_move_insn (frame_pointer_rtx, mem);
2901
 
2902
      /* Whenever we emit insns with post-incremented addresses
2903
         ourselves, we must add a post-inc note manually.  */
2904
      REG_NOTES (insn)
2905
        = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2906
    }
2907
  else if ((size + argspace_offset) != 0)
2908
    {
2909
      emit_insn (gen_cris_frame_deallocated_barrier ());
2910
 
2911
      /* If there was no frame-pointer to restore sp from, we must
2912
         explicitly deallocate local variables.  */
2913
 
2914
      /* Handle space for outgoing parameters that hasn't been handled
2915
         yet.  */
2916
      size += argspace_offset;
2917
 
2918
      emit_insn (gen_rtx_SET (VOIDmode,
2919
                              stack_pointer_rtx,
2920
                              plus_constant (stack_pointer_rtx, size)));
2921
    }
2922
 
2923
  /* If this function has no pushed register parameters
2924
     (stdargs/varargs), and if it is not a leaf function, then we have
2925
     the return address on the stack.  */
2926
  if (return_address_on_stack && pretend == 0)
2927
    {
2928
      if (current_function_calls_eh_return)
2929
        {
2930
          rtx mem;
2931
          rtx insn;
2932
          rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
2933
          mem = gen_rtx_MEM (SImode,
2934
                             gen_rtx_POST_INC (SImode,
2935
                                               stack_pointer_rtx));
2936
          set_mem_alias_set (mem, get_frame_alias_set ());
2937
          insn = emit_move_insn (srpreg, mem);
2938
 
2939
          /* Whenever we emit insns with post-incremented addresses
2940
             ourselves, we must add a post-inc note manually.  */
2941
          REG_NOTES (insn)
2942
            = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2943
 
2944
          emit_insn (gen_addsi3 (stack_pointer_rtx,
2945
                                 stack_pointer_rtx,
2946
                                 gen_rtx_raw_REG (SImode,
2947
                                                  CRIS_STACKADJ_REG)));
2948
          cris_expand_return (false);
2949
        }
2950
      else
2951
        cris_expand_return (true);
2952
 
2953
      return;
2954
    }
2955
 
2956
  /* If we pushed some register parameters, then adjust the stack for
2957
     them.  */
2958
  if (pretend != 0)
2959
    {
2960
      /* If SRP is stored on the way, we need to restore it first.  */
2961
      if (return_address_on_stack)
2962
        {
2963
          rtx mem;
2964
          rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
2965
          rtx insn;
2966
 
2967
          mem = gen_rtx_MEM (SImode,
2968
                             gen_rtx_POST_INC (SImode,
2969
                                               stack_pointer_rtx));
2970
          set_mem_alias_set (mem, get_frame_alias_set ());
2971
          insn = emit_move_insn (srpreg, mem);
2972
 
2973
          /* Whenever we emit insns with post-incremented addresses
2974
             ourselves, we must add a post-inc note manually.  */
2975
          REG_NOTES (insn)
2976
            = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2977
        }
2978
 
2979
      emit_insn (gen_rtx_SET (VOIDmode,
2980
                              stack_pointer_rtx,
2981
                              plus_constant (stack_pointer_rtx, pretend)));
2982
    }
2983
 
2984
  /* Perform the "physical" unwinding that the EH machinery calculated.  */
2985
  if (current_function_calls_eh_return)
2986
    emit_insn (gen_addsi3 (stack_pointer_rtx,
2987
                           stack_pointer_rtx,
2988
                           gen_rtx_raw_REG (SImode,
2989
                                            CRIS_STACKADJ_REG)));
2990
  cris_expand_return (false);
2991
}
2992
 
2993
/* Worker function for generating movem from mem for load_multiple.  */
2994
 
2995
rtx
2996
cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix)
2997
{
2998
  int nregs = INTVAL (nregs_rtx);
2999
  rtvec vec;
3000
  int eltno = 1;
3001
  int i;
3002
  rtx srcreg = XEXP (src, 0);
3003
  unsigned int regno = nregs - 1;
3004
  int regno_inc = -1;
3005
 
3006
  if (GET_CODE (srcreg) == POST_INC)
3007
    srcreg = XEXP (srcreg, 0);
3008
 
3009
  CRIS_ASSERT (REG_P (srcreg));
3010
 
3011
  /* Don't use movem for just one insn.  The insns are equivalent except
3012
     for the pipeline hazard (on v32); movem does not forward the loaded
3013
     registers so there's a three cycles penalty for their use.  */
3014
  if (nregs == 1)
3015
    return gen_movsi (gen_rtx_REG (SImode, 0), src);
3016
 
3017
  vec = rtvec_alloc (nprefix + nregs
3018
                     + (GET_CODE (XEXP (src, 0)) == POST_INC));
3019
 
3020
  if (GET_CODE (XEXP (src, 0)) == POST_INC)
3021
    {
3022
      RTVEC_ELT (vec, nprefix + 1)
3023
        = gen_rtx_SET (VOIDmode, srcreg, plus_constant (srcreg, nregs * 4));
3024
      eltno++;
3025
    }
3026
 
3027
  src = replace_equiv_address (src, srcreg);
3028
  RTVEC_ELT (vec, nprefix)
3029
    = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src);
3030
  regno += regno_inc;
3031
 
3032
  for (i = 1; i < nregs; i++, eltno++)
3033
    {
3034
      RTVEC_ELT (vec, nprefix + eltno)
3035
        = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno),
3036
                       adjust_address_nv (src, SImode, i * 4));
3037
      regno += regno_inc;
3038
    }
3039
 
3040
  return gen_rtx_PARALLEL (VOIDmode, vec);
3041
}
3042
 
3043
/* Worker function for generating movem to mem.  If FRAME_RELATED, notes
3044
   are added that the dwarf2 machinery understands.  */
3045
 
3046
rtx
3047
cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment,
3048
                       bool frame_related)
3049
{
3050
  int nregs = INTVAL (nregs_rtx);
3051
  rtvec vec;
3052
  int eltno = 1;
3053
  int i;
3054
  rtx insn;
3055
  rtx destreg = XEXP (dest, 0);
3056
  unsigned int regno = nregs - 1;
3057
  int regno_inc = -1;
3058
 
3059
  if (GET_CODE (destreg) == POST_INC)
3060
    increment += nregs * 4;
3061
 
3062
  if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS)
3063
    destreg = XEXP (destreg, 0);
3064
 
3065
  CRIS_ASSERT (REG_P (destreg));
3066
 
3067
  /* Don't use movem for just one insn.  The insns are equivalent except
3068
     for the pipeline hazard (on v32); movem does not forward the loaded
3069
     registers so there's a three cycles penalty for use.  */
3070
  if (nregs == 1)
3071
    {
3072
      rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0));
3073
 
3074
      if (increment == 0)
3075
        {
3076
          insn = emit_insn (mov);
3077
          if (frame_related)
3078
            RTX_FRAME_RELATED_P (insn) = 1;
3079
          return insn;
3080
        }
3081
 
3082
      /* If there was a request for a side-effect, create the ordinary
3083
         parallel.  */
3084
      vec = rtvec_alloc (2);
3085
 
3086
      RTVEC_ELT (vec, 0) = mov;
3087
      RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg,
3088
                                        plus_constant (destreg, increment));
3089
      if (frame_related)
3090
        {
3091
          RTX_FRAME_RELATED_P (mov) = 1;
3092
          RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3093
        }
3094
    }
3095
  else
3096
    {
3097
      vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0));
3098
      RTVEC_ELT (vec, 0)
3099
        = gen_rtx_SET (VOIDmode,
3100
                       replace_equiv_address (dest,
3101
                                              plus_constant (destreg,
3102
                                                             increment)),
3103
                       gen_rtx_REG (SImode, regno));
3104
      regno += regno_inc;
3105
 
3106
      /* The dwarf2 info wants this mark on each component in a parallel
3107
         that's part of the prologue (though it's optional on the first
3108
         component).  */
3109
      if (frame_related)
3110
        RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1;
3111
 
3112
      if (increment != 0)
3113
        {
3114
          RTVEC_ELT (vec, 1)
3115
            = gen_rtx_SET (VOIDmode, destreg,
3116
                           plus_constant (destreg,
3117
                                          increment != 0
3118
                                          ? increment : nregs * 4));
3119
          eltno++;
3120
 
3121
          if (frame_related)
3122
            RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3123
 
3124
          /* Don't call adjust_address_nv on a post-incremented address if
3125
             we can help it.  */
3126
          if (GET_CODE (XEXP (dest, 0)) == POST_INC)
3127
            dest = replace_equiv_address (dest, destreg);
3128
        }
3129
 
3130
      for (i = 1; i < nregs; i++, eltno++)
3131
        {
3132
          RTVEC_ELT (vec, eltno)
3133
            = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4),
3134
                           gen_rtx_REG (SImode, regno));
3135
          if (frame_related)
3136
            RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1;
3137
          regno += regno_inc;
3138
        }
3139
    }
3140
 
3141
  insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
3142
 
3143
  /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3144
     we need to keep the stack adjustment separate, after the
3145
     MEM-setters.  Else the stack-adjustment in the second component of
3146
     the parallel would be mishandled; the offsets for the SETs that
3147
     follow it would be wrong.  We prepare for this by adding a
3148
     REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3149
     followed by the increment.  Note that we have FRAME_RELATED_P on
3150
     all the SETs, including the original stack adjustment SET in the
3151
     parallel.  */
3152
  if (frame_related)
3153
    {
3154
      if (increment != 0)
3155
        {
3156
          rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1));
3157
          XVECEXP (seq, 0, 0) = XVECEXP (PATTERN (insn), 0, 0);
3158
          for (i = 1; i < nregs; i++)
3159
            XVECEXP (seq, 0, i) = XVECEXP (PATTERN (insn), 0, i + 1);
3160
          XVECEXP (seq, 0, nregs) = XVECEXP (PATTERN (insn), 0, 1);
3161
          REG_NOTES (insn)
3162
            = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, seq,
3163
                                 REG_NOTES (insn));
3164
        }
3165
 
3166
      RTX_FRAME_RELATED_P (insn) = 1;
3167
    }
3168
 
3169
  return insn;
3170
}
3171
 
3172
/* Worker function for expanding the address for PIC function calls.  */
3173
 
3174
void
3175
cris_expand_pic_call_address (rtx *opp)
3176
{
3177
  rtx op = *opp;
3178
 
3179
  gcc_assert (MEM_P (op));
3180
  op = XEXP (op, 0);
3181
 
3182
  /* It might be that code can be generated that jumps to 0 (or to a
3183
     specific address).  Don't die on that.  (There is a
3184
     testcase.)  */
3185
  if (CONSTANT_ADDRESS_P (op) && GET_CODE (op) != CONST_INT)
3186
    {
3187
      enum cris_pic_symbol_type t = cris_pic_symbol_type_of (op);
3188
 
3189
      CRIS_ASSERT (!no_new_pseudos);
3190
 
3191
      /* For local symbols (non-PLT), just get the plain symbol
3192
         reference into a register.  For symbols that can be PLT, make
3193
         them PLT.  */
3194
      if (t == cris_gotrel_symbol)
3195
        op = force_reg (Pmode, op);
3196
      else if (t == cris_got_symbol)
3197
        {
3198
          if (TARGET_AVOID_GOTPLT)
3199
            {
3200
              /* Change a "jsr sym" into (allocate register rM, rO)
3201
                 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT)),rM"
3202
                 "add.d rPIC,rM,rO", "jsr rO".  */
3203
              rtx tem, rm, ro;
3204
              gcc_assert (! no_new_pseudos);
3205
              current_function_uses_pic_offset_table = 1;
3206
              tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), CRIS_UNSPEC_PLT);
3207
              rm = gen_reg_rtx (Pmode);
3208
              emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3209
              ro = gen_reg_rtx (Pmode);
3210
              if (expand_binop (Pmode, add_optab, rm,
3211
                                pic_offset_table_rtx,
3212
                                ro, 0, OPTAB_LIB_WIDEN) != ro)
3213
                internal_error ("expand_binop failed in movsi got");
3214
              op = ro;
3215
            }
3216
          else
3217
            {
3218
              /* Change a "jsr sym" into (allocate register rM, rO)
3219
                 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOT)),rM"
3220
                 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3221
                 marked as not trapping and not aliasing.  No "move.d
3222
                 [rO],rP" as that would invite to re-use of a value
3223
                 that should not be reused.  FIXME: Need a peephole2
3224
                 for cases when this is cse:d from the call, to change
3225
                 back to just get the PLT entry address, so we don't
3226
                 resolve the same symbol over and over (the memory
3227
                 access of the PLTGOT isn't constant).  */
3228
              rtx tem, mem, rm, ro;
3229
 
3230
              gcc_assert (! no_new_pseudos);
3231
              current_function_uses_pic_offset_table = 1;
3232
              tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3233
                                    CRIS_UNSPEC_PLTGOTREAD);
3234
              rm = gen_reg_rtx (Pmode);
3235
              emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3236
              ro = gen_reg_rtx (Pmode);
3237
              if (expand_binop (Pmode, add_optab, rm,
3238
                                pic_offset_table_rtx,
3239
                                ro, 0, OPTAB_LIB_WIDEN) != ro)
3240
                internal_error ("expand_binop failed in movsi got");
3241
              mem = gen_rtx_MEM (Pmode, ro);
3242
 
3243
              /* This MEM doesn't alias anything.  Whether it aliases
3244
                 other same symbols is unimportant.  */
3245
              set_mem_alias_set (mem, new_alias_set ());
3246
              MEM_NOTRAP_P (mem) = 1;
3247
              op = mem;
3248
            }
3249
        }
3250
      else
3251
        /* Can't possibly get a GOT-needing-fixup for a function-call,
3252
           right?  */
3253
        fatal_insn ("Unidentifiable call op", op);
3254
 
3255
      *opp = replace_equiv_address (*opp, op);
3256
    }
3257
}
3258
 
3259
/* Make sure operands are in the right order for an addsi3 insn as
3260
   generated by a define_split.  A MEM as the first operand isn't
3261
   recognized by addsi3 after reload.  OPERANDS contains the operands,
3262
   with the first at OPERANDS[N] and the second at OPERANDS[N+1].  */
3263
 
3264
void
3265
cris_order_for_addsi3 (rtx *operands, int n)
3266
{
3267
  if (MEM_P (operands[n]))
3268
    {
3269
      rtx tem = operands[n];
3270
      operands[n] = operands[n + 1];
3271
      operands[n + 1] = tem;
3272
    }
3273
}
3274
 
3275
/* Use from within code, from e.g. PRINT_OPERAND and
3276
   PRINT_OPERAND_ADDRESS.  Macros used in output_addr_const need to emit
3277
   different things depending on whether code operand or constant is
3278
   emitted.  */
3279
 
3280
static void
3281
cris_output_addr_const (FILE *file, rtx x)
3282
{
3283
  in_code++;
3284
  output_addr_const (file, x);
3285
  in_code--;
3286
}
3287
 
3288
/* Worker function for ASM_OUTPUT_SYMBOL_REF.  */
3289
 
3290
void
3291
cris_asm_output_symbol_ref (FILE *file, rtx x)
3292
{
3293
  gcc_assert (GET_CODE (x) == SYMBOL_REF);
3294
 
3295
  if (flag_pic && in_code > 0)
3296
    {
3297
     const char *origstr = XSTR (x, 0);
3298
     const char *str;
3299
     str = (* targetm.strip_name_encoding) (origstr);
3300
     assemble_name (file, str);
3301
 
3302
     /* Sanity check.  */
3303
     if (! current_function_uses_pic_offset_table)
3304
       output_operand_lossage ("PIC register isn't set up");
3305
    }
3306
  else
3307
    assemble_name (file, XSTR (x, 0));
3308
}
3309
 
3310
/* Worker function for ASM_OUTPUT_LABEL_REF.  */
3311
 
3312
void
3313
cris_asm_output_label_ref (FILE *file, char *buf)
3314
{
3315
  if (flag_pic && in_code > 0)
3316
    {
3317
      assemble_name (file, buf);
3318
 
3319
      /* Sanity check.  */
3320
      if (! current_function_uses_pic_offset_table)
3321
        internal_error ("emitting PIC operand, but PIC register isn't set up");
3322
    }
3323
  else
3324
    assemble_name (file, buf);
3325
}
3326
 
3327
/* Worker function for OUTPUT_ADDR_CONST_EXTRA.  */
3328
 
3329
bool
3330
cris_output_addr_const_extra (FILE *file, rtx xconst)
3331
{
3332
  switch (GET_CODE (xconst))
3333
    {
3334
      rtx x;
3335
 
3336
    case UNSPEC:
3337
      x = XVECEXP (xconst, 0, 0);
3338
      CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
3339
                   || GET_CODE (x) == LABEL_REF
3340
                   || GET_CODE (x) == CONST);
3341
      output_addr_const (file, x);
3342
      switch (XINT (xconst, 1))
3343
        {
3344
        case CRIS_UNSPEC_PLT:
3345
          fprintf (file, ":PLTG");
3346
          break;
3347
 
3348
        case CRIS_UNSPEC_GOTREL:
3349
          fprintf (file, ":GOTOFF");
3350
          break;
3351
 
3352
        case CRIS_UNSPEC_GOTREAD:
3353
          if (flag_pic == 1)
3354
            fprintf (file, ":GOT16");
3355
          else
3356
            fprintf (file, ":GOT");
3357
          break;
3358
 
3359
        case CRIS_UNSPEC_PLTGOTREAD:
3360
          if (flag_pic == 1)
3361
            fprintf (file, CRIS_GOTPLT_SUFFIX "16");
3362
          else
3363
            fprintf (file, CRIS_GOTPLT_SUFFIX);
3364
          break;
3365
 
3366
        default:
3367
          gcc_unreachable ();
3368
        }
3369
      return true;
3370
 
3371
    default:
3372
      return false;
3373
    }
3374
}
3375
 
3376
/* Worker function for TARGET_STRUCT_VALUE_RTX.  */
3377
 
3378
static rtx
3379
cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
3380
                       int incoming ATTRIBUTE_UNUSED)
3381
{
3382
  return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM);
3383
}
3384
 
3385
/* Worker function for TARGET_SETUP_INCOMING_VARARGS.  */
3386
 
3387
static void
3388
cris_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
3389
                             enum machine_mode mode ATTRIBUTE_UNUSED,
3390
                             tree type ATTRIBUTE_UNUSED,
3391
                             int *pretend_arg_size,
3392
                             int second_time)
3393
{
3394
  if (ca->regs < CRIS_MAX_ARGS_IN_REGS)
3395
    {
3396
      int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs;
3397
      cfun->machine->stdarg_regs = stdarg_regs;
3398
      *pretend_arg_size = stdarg_regs * 4;
3399
    }
3400
 
3401
  if (TARGET_PDEBUG)
3402
    fprintf (asm_out_file,
3403
             "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3404
             ca->regs, *pretend_arg_size, second_time);
3405
}
3406
 
3407
/* Return true if TYPE must be passed by invisible reference.
3408
   For cris, we pass <= 8 bytes by value, others by reference.  */
3409
 
3410
static bool
3411
cris_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
3412
                        enum machine_mode mode, tree type,
3413
                        bool named ATTRIBUTE_UNUSED)
3414
{
3415
  return (targetm.calls.must_pass_in_stack (mode, type)
3416
          || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8);
3417
}
3418
 
3419
 
3420
static int
3421
cris_arg_partial_bytes (CUMULATIVE_ARGS *ca, enum machine_mode mode,
3422
                        tree type, bool named ATTRIBUTE_UNUSED)
3423
{
3424
  if (ca->regs == CRIS_MAX_ARGS_IN_REGS - 1
3425
      && !targetm.calls.must_pass_in_stack (mode, type)
3426
      && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4
3427
      && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8)
3428
    return UNITS_PER_WORD;
3429
  else
3430
    return 0;
3431
}
3432
 
3433
/* Worker function for TARGET_MD_ASM_CLOBBERS.  */
3434
 
3435
static tree
3436
cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers)
3437
{
3438
  HARD_REG_SET mof_set;
3439
  tree clobbers;
3440
  tree t;
3441
 
3442
  CLEAR_HARD_REG_SET (mof_set);
3443
  SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM);
3444
 
3445
  /* For the time being, all asms clobber condition codes.  Revisit when
3446
     there's a reasonable use for inputs/outputs that mention condition
3447
     codes.  */
3448
  clobbers
3449
    = tree_cons (NULL_TREE,
3450
                 build_string (strlen (reg_names[CRIS_CC0_REGNUM]),
3451
                               reg_names[CRIS_CC0_REGNUM]),
3452
                 in_clobbers);
3453
 
3454
  for (t = outputs; t != NULL; t = TREE_CHAIN (t))
3455
    {
3456
      tree val = TREE_VALUE (t);
3457
 
3458
      /* The constraint letter for the singleton register class of MOF
3459
         is 'h'.  If it's mentioned in the constraints, the asm is
3460
         MOF-aware and adding it to the clobbers would cause it to have
3461
         impossible constraints.  */
3462
      if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3463
                  'h') != NULL
3464
          || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
3465
        return clobbers;
3466
    }
3467
 
3468
  for (t = inputs; t != NULL; t = TREE_CHAIN (t))
3469
    {
3470
      tree val = TREE_VALUE (t);
3471
 
3472
      if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3473
                  'h') != NULL
3474
          || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
3475
        return clobbers;
3476
    }
3477
 
3478
  return tree_cons (NULL_TREE,
3479
                    build_string (strlen (reg_names[CRIS_MOF_REGNUM]),
3480
                                  reg_names[CRIS_MOF_REGNUM]),
3481
                    clobbers);
3482
}
3483
 
3484
#if 0
3485
/* Various small functions to replace macros.  Only called from a
3486
   debugger.  They might collide with gcc functions or system functions,
3487
   so only emit them when '#if 1' above.  */
3488
 
3489
enum rtx_code Get_code (rtx);
3490
 
3491
enum rtx_code
3492
Get_code (rtx x)
3493
{
3494
  return GET_CODE (x);
3495
}
3496
 
3497
const char *Get_mode (rtx);
3498
 
3499
const char *
3500
Get_mode (rtx x)
3501
{
3502
  return GET_MODE_NAME (GET_MODE (x));
3503
}
3504
 
3505
rtx Xexp (rtx, int);
3506
 
3507
rtx
3508
Xexp (rtx x, int n)
3509
{
3510
  return XEXP (x, n);
3511
}
3512
 
3513
rtx Xvecexp (rtx, int, int);
3514
 
3515
rtx
3516
Xvecexp (rtx x, int n, int m)
3517
{
3518
  return XVECEXP (x, n, m);
3519
}
3520
 
3521
int Get_rtx_len (rtx);
3522
 
3523
int
3524
Get_rtx_len (rtx x)
3525
{
3526
  return GET_RTX_LENGTH (GET_CODE (x));
3527
}
3528
 
3529
/* Use upper-case to distinguish from local variables that are sometimes
3530
   called next_insn and prev_insn.  */
3531
 
3532
rtx Next_insn (rtx);
3533
 
3534
rtx
3535
Next_insn (rtx insn)
3536
{
3537
  return NEXT_INSN (insn);
3538
}
3539
 
3540
rtx Prev_insn (rtx);
3541
 
3542
rtx
3543
Prev_insn (rtx insn)
3544
{
3545
  return PREV_INSN (insn);
3546
}
3547
#endif
3548
 
3549
#include "gt-cris.h"
3550
 
3551
/*
3552
 * Local variables:
3553
 * eval: (c-set-style "gnu")
3554
 * indent-tabs-mode: t
3555
 * End:
3556
 */

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