Subversion Repositories openrisc_me

;; GCC machine description for CRIS cpu cores.

;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,

;; 2007 Free Software Foundation, Inc.

;; Contributed by Axis Communications.

;; This file is part of GCC.

;;

;; GCC is free software; you can redistribute it and/or modify

;; it under the terms of the GNU General Public License as published by

;; the Free Software Foundation; either version 3, or (at your option)

;; any later version.

;;

;; GCC is distributed in the hope that it will be useful,

;; but WITHOUT ANY WARRANTY; without even the implied warranty of

;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

;; GNU General Public License for more details.

;;

;; You should have received a copy of the GNU General Public License

;; along with GCC; see the file COPYING3.  If not see

;; .

;; The original PO technology requires these to be ordered by speed,

;; so that assigner will pick the fastest.

;; See files "md.texi" and "rtl.def" for documentation on define_insn,

;; match_*, et. al.

;;

;; The function cris_notice_update_cc in cris.c handles condition code

;; updates for most instructions, helped by the "cc" attribute.

;; There are several instructions that are orthogonal in size, and seems

;; they could be matched by a single pattern without a specified size

;; for the operand that is orthogonal.  However, this did not work on

;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a

;; constant is substituted into an operand, the actual mode must be

;; deduced from the pattern.  There is reasonable hope that that has been

;; fixed, so FIXME: try again.

;; You will notice that three-operand alternatives ("=r", "r", "!To")

;; are marked with a "!" constraint modifier to avoid being reloaded

;; into.  This is because gcc would otherwise prefer to use the constant

;; pool and its offsettable address instead of reloading to an

;; ("=r", "0", "i") alternative.  Also, the constant-pool support was not

;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.

;; All insns that look like (set (...) (plus (...) (reg:SI 8)))

;; get problems when reloading r8 (frame pointer) to r14 + offs (stack

;; pointer).  Thus the instructions that get into trouble have specific

;; checks against matching frame_pointer_rtx.

;; ??? But it should be re-checked for gcc > 2.7.2

;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.

;; FIXME: When PIC, all [rX=rY+S] could be enabled to match

;; [rX=gotless_symbol].

;; The movsi for a gotless symbol could be split (post reload).

;; UNSPEC Usage:

;; 0 PLT reference from call expansion: operand 0 is the address,

;;   the mode is VOIDmode.  Always wrapped in CONST.

;; 1 Stack frame deallocation barrier.

;; 2 The address of the global offset table as a source operand.

;; 3 The address of a global-offset-table-relative symbol + offset.

;; 4 The offset within GOT of a symbol.

;; 5 The offset within GOT of a symbol that has a PLT.

(define_constants ; FIXME: reorder sanely.

  [(CRIS_UNSPEC_PLT 0)

   (CRIS_UNSPEC_FRAME_DEALLOC 1)

   (CRIS_UNSPEC_GOT 2)

   (CRIS_UNSPEC_GOTREL 3)

   (CRIS_UNSPEC_GOTREAD 4)

   (CRIS_UNSPEC_PLTGOTREAD 5)])

;; Register numbers.

(define_constants

  [(CRIS_GOT_REGNUM 0)

   (CRIS_STATIC_CHAIN_REGNUM 7)

   (CRIS_FP_REGNUM 8)

   (CRIS_SP_REGNUM 14)

   (CRIS_SRP_REGNUM 16)

   (CRIS_MOF_REGNUM 17)

   (CRIS_AP_REGNUM 18)

   (CRIS_CC0_REGNUM 19)]

)

;; We need an attribute to define whether an instruction can be put in

;; a branch-delay slot or not, and whether it has a delay slot.

;;

;; Branches and return instructions have a delay slot, and cannot

;; themselves be put in a delay slot.  This has changed *for short

;; branches only* between architecture variants, but the possible win

;; is presumed negligible compared to the added complexity of the machine

;; description: one would have to add always-correct infrastructure to

;; distinguish short branches.

;;

;; Whether an instruction can be put in a delay slot depends on the

;; instruction (all short instructions except jumps and branches)

;; and the addressing mode (must not be prefixed or referring to pc).

;; In short, any "slottable" instruction must be 16 bit and not refer

;; to pc, or alter it.

;;

;; The possible values are "yes", "no" and "has_slot".  Yes/no means if

;; the insn is slottable or not.  Has_slot means that the insn is a

;; return insn or branch insn (which are not considered slottable since

;; that is generally true).  Having the seemingly illogical value

;; "has_slot" means we do not have to add another attribute just to say

;; that an insn has a delay-slot, since it also infers that it is not

;; slottable.  Better names for the attribute were found to be longer and

;; not add readability to the machine description.

;;

;; The default that is defined here for this attribute is "no", not

;; slottable, not having a delay-slot, so there's no need to worry about

;; it being wrong for non-branch and return instructions.

;;  The default could depend on the kind of insn and the addressing

;; mode, but that would need more attributes and hairier, more error

;; prone code.

;;

;;  There is an extra memory constraint, 'Q', which recognizes an indirect

;; register.  The constraints 'Q' and '>' together match all possible

;; memory operands that are slottable.

;;  For other operands, you need to check if it has a valid "slottable"

;; quick-immediate operand, where the particular signedness-variation

;; may match the constraints 'I' or 'J'.), and include it in the

;; constraint pattern for the slottable pattern.  An alternative using

;; only "r" constraints is most often slottable.

(define_attr "slottable" "no,yes,has_slot" (const_string "no"))

;; We also need attributes to sanely determine the condition code

;; state.  See cris_notice_update_cc for how this is used.

(define_attr "cc" "none,clobber,normal" (const_string "normal"))

;; At the moment, this attribute is just used to help bb-reorder do its

;; work; the default 0 doesn't help it.  Many insns have other lengths,

;; though none are shorter.

(define_attr "length" "" (const_int 2))

;; A branch or return has one delay-slot.  The instruction in the

;; delay-slot is always executed, independent of whether the branch is

;; taken or not.  Note that besides setting "slottable" to "has_slot",

;; there also has to be a "%#" at the end of a "delayed" instruction

;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can

;; catch it and print a "nop" if necessary.  This method was stolen from

;; sparc.md.

(define_delay (eq_attr "slottable" "has_slot")

  [(eq_attr "slottable" "yes") (nil) (nil)])

;; Iterator definitions.

;; For the "usual" pattern size alternatives.

(define_mode_macro BWD [SI HI QI])

(define_mode_macro WD [SI HI])

(define_mode_macro BW [HI QI])

(define_mode_attr S [(SI "HI") (HI "QI")])

(define_mode_attr s [(SI "hi") (HI "qi")])

(define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])

(define_mode_attr mm [(SI ".w") (HI ".b")])

(define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")])

;; For the sign_extend+zero_extend variants.

(define_code_macro szext [sign_extend zero_extend])

(define_code_attr u [(sign_extend "") (zero_extend "u")])

(define_code_attr su [(sign_extend "s") (zero_extend "u")])

;; For the shift variants.

(define_code_macro shift [ashiftrt lshiftrt ashift])

(define_code_macro shiftrt [ashiftrt lshiftrt])

(define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])

(define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])

(define_code_macro ncond [eq ne gtu ltu geu leu])

(define_code_macro ocond [gt le])

(define_code_macro rcond [lt ge])

(define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")

                      (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])

(define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")

                       (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")])

(define_code_attr oCC [(lt "mi") (ge "pl")])

(define_code_attr roCC [(lt "pl") (ge "mi")])

;; Operand and operator predicates.

(include "predicates.md")

;; Test insns.

;; DImode

;;

;; Allow register and offsettable mem operands only; post-increment is

;; not worth the trouble.

(define_insn "tstdi"

  [(set (cc0)

        (match_operand:DI 0 "nonimmediate_operand" "r,o"))]

  ""

  "test.d %M0\;ax\;test.d %H0")

;; No test insns with side-effect on the mem addressing.

;;

;; See note on cmp-insns with side-effects (or lack of them)

;; Normal named test patterns from SI on.

;; FIXME: Seems they should change to be in order smallest..largest.

(define_insn "tst"

  [(set (cc0)

        (match_operand:BWD 0 "nonimmediate_operand" "r,Q>,m"))]

  ""

  "test %0"

  [(set_attr "slottable" "yes,yes,no")])

;; It seems that the position of the sign-bit and the fact that 0.0 is

;; all 0-bits would make "tstsf" a straight-forward implementation;

;; either "test.d" it for positive/negative or "btstq 30,r" it for

;; zeroness.

;;

;; FIXME: Do that some time; check next_cc0_user to determine if

;; zero or negative is tested for.

;; Compare insns.

;; We could optimize the sizes of the immediate operands for various

;; cases, but that is not worth it because of the very little usage of

;; DImode for anything else but a structure/block-mode.  Just do the

;; obvious stuff for the straight-forward constraint letters.

(define_insn "cmpdi"

  [(set (cc0)

        (compare (match_operand:DI 0 "nonimmediate_operand" "r,r,r,r,r,r,o")

                 (match_operand:DI 1 "general_operand" "K,I,P,n,r,o,r")))]

  ""

  "@

   cmpq %1,%M0\;ax\;cmpq 0,%H0

   cmpq %1,%M0\;ax\;cmpq -1,%H0

   cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0

   cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0

   cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0

   cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0

   cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")

;; Note that compare insns with side effect addressing mode (e.g.):

;;

;; cmp.S [rx=ry+i],rz;

;; cmp.S [%3=%1+%2],%0

;;

;; are *not* usable for gcc since the reloader *does not accept*

;; cc0-changing insns with side-effects other than setting the condition

;; codes.  The reason is that the reload stage *may* cause another insn to

;; be output after the main instruction, in turn invalidating cc0 for the

;; insn using the test.  (This does not apply to the CRIS case, since a

;; reload for output -- move to memory -- does not change the condition

;; code.  Unfortunately we have no way to describe that at the moment.  I

;; think code would improve being in the order of one percent faster.

;; We have cmps and cmpu (compare reg w. sign/zero extended mem).

;; These are mostly useful for compares in SImode, using 8 or 16-bit

;; constants, but sometimes gcc will find its way to use it for other

;; (memory) operands.  Avoid side-effect patterns, though (see above).

(define_insn "*cmp_ext"

  [(set (cc0)

        (compare

         (match_operand:SI 0 "register_operand" "r,r")

         (match_operator:SI 2 "cris_extend_operator"

                         [(match_operand:BW 1 "memory_operand" "Q>,m")])))]

  ""

  "cmp%e2 %1,%0"

  [(set_attr "slottable" "yes,no")])

;; Swap operands; it seems the canonical look (if any) is not enforced.

;;

;; FIXME: Investigate that.

(define_insn "*cmp_swapext"

  [(set (cc0)

        (compare

         (match_operator:SI 2 "cris_extend_operator"

                            [(match_operand:BW 0 "memory_operand" "Q>,m")])

         (match_operand:SI 1 "register_operand" "r,r")))]

  ""

  "cmp%e2 %0,%1" ; The function cris_notice_update_cc knows about

                     ; swapped operands to compares.

  [(set_attr "slottable" "yes,no")])

;; The "normal" compare patterns, from SI on.

(define_insn "cmpsi"

  [(set (cc0)

        (compare

         (match_operand:SI 0 "nonimmediate_operand" "r,r,r, r,Q>,Q>,r,r,m,m")

         (match_operand:SI 1 "general_operand"      "I,r,Q>,M,M, r, P,g,M,r")))]

  ""

  "@

   cmpq %1,%0

   cmp.d %1,%0

   cmp.d %1,%0

   test.d %0

   test.d %0

   cmp.d %0,%1

   cmp%e1.%z1 %1,%0

   cmp.d %1,%0

   test.d %0

   cmp.d %0,%1"

  [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no")])

(define_insn "cmp"

  [(set (cc0)

        (compare

         (match_operand:BW 0 "nonimmediate_operand" "r,r, r,Q>,Q>,r,m,m")

         (match_operand:BW 1 "general_operand"      "r,Q>,M,M, r, g,M,r")))]

  ""

  "@

   cmp %1,%0

   cmp %1,%0

   test %0

   test %0

   cmp %0,%1

   cmp %1,%0

   test %0

   cmp %0,%1"

  [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])

;; Pattern matching the BTST insn.

;; It is useful for "if (i & val)" constructs, where val is an exact

;; power of 2, or if val + 1 is a power of two, where we check for a bunch

;; of zeros starting at bit 0).

;; SImode.  This mode is the only one needed, since gcc automatically

;; extends subregs for lower-size modes.  FIXME: Add testcase.

(define_insn "*btst"

  [(set (cc0)

        (zero_extract

         (match_operand:SI 0 "nonmemory_operand" "r,r,r,r,r,r,n")

         (match_operand:SI 1 "const_int_operand" "K,n,K,n,K,n,n")

         (match_operand:SI 2 "nonmemory_operand" "M,M,K,n,r,r,r")))]

  ;; Either it is a single bit, or consecutive ones starting at 0.

  "GET_CODE (operands[1]) == CONST_INT

   && (operands[1] == const1_rtx || operands[2] == const0_rtx)

   && (REG_S_P (operands[0])

       || (operands[1] == const1_rtx

           && REG_S_P (operands[2])

           && GET_CODE (operands[0]) == CONST_INT

           && exact_log2 (INTVAL (operands[0])) >= 0))"

;; The last "&&" condition above should be caught by some kind of

;; canonicalization in gcc, but we can easily help with it here.

;;  It results from expressions of the type

;; "power_of_2_value & (1 << y)".

;;

;; Since there may be codes with tests in on bits (in constant position)

;; beyond the size of a word, handle that by assuming those bits are 0.

;; GCC should handle that, but it's a matter of easily-added belts while

;; having suspenders.

  "@

   btstq (%1-1),%0

   test.d %0

   btstq %2,%0

   clearf nz

   btst %2,%0

   clearf nz

   cmpq %p0,%2"

 [(set_attr "slottable" "yes")])

;; Move insns.

;; The whole mandatory movdi family is here; expander, "anonymous"

;; recognizer and splitter.  We're forced to have a movdi pattern,

;; although GCC should be able to split it up itself.  Normally it can,

;; but if other insns have DI operands (as is the case here), reload

;; must be able to generate or match a movdi.  many testcases fail at

;; -O3 or -fssa if we don't have this.  FIXME: Fix GCC...  See

;; .

;; However, a patch from Richard Kenner (similar to the cause of

;; discussion at the URL above), indicates otherwise.  See

;; .

;; The truth has IMO is not been decided yet, so check from time to

;; time by disabling the movdi patterns.

;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at

;; -O0, we need a movdi as a temporary measure.  Here's how things fail:

;;  A cmpdi RTX needs reloading (global):

;;    (insn 185 326 186 (set (cc0)

;;          (compare (mem/f:DI (reg/v:SI 22) 0)

;;              (const_int 1 [0x1]))) 4 {cmpdi} (nil)

;;      (nil))

;; Now, reg 22 is reloaded for input address, and the mem is also moved

;; out of the instruction (into a register), since one of the operands

;; must be a register.  Reg 22 is reloaded (into reg 10), and the mem is

;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok

;; wrt. overlap).  The bad things happen with the synthesis in

;; emit_move_insn_1; the location where to substitute reg 10 is lost into

;; two new RTX:es, both still having reg 22.  Later on, the left-over reg

;; 22 is recognized to have an equivalent in memory which is substituted

;; straight in, and we end up with an unrecognizable insn:

;;    (insn 325 324 326 (set (reg:SI 9 r9)

;;            (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)

;;                        (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)

;;        (nil))

;; which is the first part of the reloaded synthesized "movdi".

;;  The right thing would be to add equivalent replacement locations for

;; insn with pseudos that need more reloading.  The question is where.

(define_expand "movdi"

  [(set (match_operand:DI 0 "nonimmediate_operand" "")

        (match_operand:DI 1 "general_operand" ""))]

  ""

{

  if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)

    operands[1] = copy_to_mode_reg (DImode, operands[1]);

  /* Some other ports (as of 2001-09-10 for example mcore and romp) also

     prefer to split up constants early, like this.  The testcase in

     gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the

     resulting subreg sets when using the construct from mcore (as of FSF

     CVS, version -r 1.5), and it believes that the high part (the last one

     emitted) is the final value.  This construct from romp seems more

     robust, especially considering the head comments from

     emit_no_conflict_block.  */

  if ((GET_CODE (operands[1]) == CONST_INT

       || GET_CODE (operands[1]) == CONST_DOUBLE)

      && ! reload_completed

      && ! reload_in_progress)

    {

      rtx insns;

      rtx op0 = operands[0];

      rtx op1 = operands[1];

      start_sequence ();

      emit_move_insn (operand_subword (op0, 0, 1, DImode),

                      operand_subword (op1, 0, 1, DImode));

      emit_move_insn (operand_subword (op0, 1, 1, DImode),

                      operand_subword (op1, 1, 1, DImode));

      insns = get_insns ();

      end_sequence ();

      emit_no_conflict_block (insns, op0, op1, 0, op1);

      DONE;

    }

})

(define_insn "*movdi_insn"

  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m")

        (match_operand:DI 1 "general_operand" "rx,g,rxM"))]

  "register_operand (operands[0], DImode)

   || register_operand (operands[1], DImode)

   || operands[1] == const0_rtx"

  "#")

(define_split

  [(set (match_operand:DI 0 "nonimmediate_operand" "")

        (match_operand:DI 1 "general_operand" ""))]

  "reload_completed"

  [(match_dup 2)]

  "operands[2] = cris_split_movdx (operands);")

;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw

;; and move.S1 [rx=ry+i],rz

;;  Then movs.S1 and movu.S1 for both modes.

;;

;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx

;; FIXME: These could have anonymous mode for operand 0.

(define_insn "*mov_side_biap"

  [(set (match_operand:BW 0 "register_operand" "=r,r")

        (mem:BW (plus:SI

                 (mult:SI (match_operand:SI 1 "register_operand" "r,r")

                          (match_operand:SI 2 "const_int_operand" "n,n"))

                 (match_operand:SI 3 "register_operand" "r,r"))))

   (set (match_operand:SI 4 "register_operand" "=*3,r")

        (plus:SI (mult:SI (match_dup 1)

                          (match_dup 2))

                 (match_dup 3)))]

  "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"

  "@

   #

   move [%4=%3+%1%T2],%0")

(define_insn "*mov_sidesisf_biap"

  [(set (match_operand 0 "register_operand" "=r,r,x,x")

        (mem (plus:SI

              (mult:SI (match_operand:SI 1 "register_operand" "r,r,r,r")

                       (match_operand:SI 2 "const_int_operand" "n,n,n,n"))

              (match_operand:SI 3 "register_operand" "r,r,r,r"))))

   (set (match_operand:SI 4 "register_operand" "=*3,r,*3,r")

        (plus:SI (mult:SI (match_dup 1)

                          (match_dup 2))

                 (match_dup 3)))]

  "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD

   && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"

  "@

   #

   move.%s0 [%4=%3+%1%T2],%0

   #

   move [%4=%3+%1%T2],%0")

;; move.S1 [rx=ry+i],rz

;; avoiding move.S1 [ry=ry+i],rz

;; and      move.S1 [rz=ry+i],rz

;; Note that "i" is allowed to be a register.

(define_insn "*mov_side"

  [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")

        (mem:BW

         (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")

                  (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))))

   (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")

        (plus:SI (match_dup 1)

                 (match_dup 2)))]

  "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"

{

  if ((which_alternative == 0 || which_alternative == 3)

      && (GET_CODE (operands[2]) != CONST_INT

          || INTVAL (operands[2]) > 127

          || INTVAL (operands[2]) < -128

          || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')

          || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))

    return "#";

  if (which_alternative == 4)

    return "move [%3=%2%S1],%0";

  return "move [%3=%1%S2],%0";

})

(define_insn "*mov_sidesisf"

  [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x,r,r,x,x")

        (mem

         (plus:SI

          (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,r,r,r,R,R,R,R")

          (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,r,r"))))

   (set (match_operand:SI 3 "register_operand" "=*1,r,r,*1,r,r,*2,r,*2,r")

        (plus:SI (match_dup 1)

                 (match_dup 2)))]

  "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD

   && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"

{

  if ((which_alternative == 0

       || which_alternative == 3

       || which_alternative == 6

       || which_alternative == 8)

      && (GET_CODE (operands[2]) != CONST_INT

          || INTVAL (operands[2]) > 127

          || INTVAL (operands[2]) < -128

          || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')

          || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))

    return "#";

  if (which_alternative < 3)

    return "move.%s0 [%3=%1%S2],%0";

  if (which_alternative == 7)

    return "move.%s0 [%3=%2%S1],%0";

  if (which_alternative == 9)

    return "move [%3=%2%S1],%0";

  return "move [%3=%1%S2],%0";

})

;; Other way around; move to memory.

;; Note that the condition (which for side-effect patterns is usually a

;; call to cris_side_effect_mode_ok), isn't consulted for register

;; allocation preferences -- constraints is the method for that.  The

;; drawback is that we can't exclude register allocation to cause

;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or

;; rx==rz if we use an earlyclobber modifier for the constraint for rx.

;; Instead of that, we recognize and split the cases where dangerous

;; register combinations are spotted: where a register is set in the

;; side-effect, and used in the main insn.  We don't handle the case where

;; the set in the main insn overlaps the set in the side-effect; that case

;; must be handled in gcc.  We handle just the case where the set in the

;; side-effect overlaps the input operand of the main insn (i.e. just

;; moves to memory).

;;

;; move.s rz,[ry=rx+rw.S]

(define_insn "*mov_side_biap_mem"

  [(set (mem:BW (plus:SI

                 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")

                          (match_operand:SI 1 "const_int_operand" "n,n,n"))

                 (match_operand:SI 2 "register_operand" "r,r,r")))

        (match_operand:BW 3 "register_operand" "r,r,r"))

   (set (match_operand:SI 4 "register_operand" "=*2,!3,r")

        (plus:SI (mult:SI (match_dup 0)

                          (match_dup 1))

                 (match_dup 2)))]

  "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"

  "@

   #

   #

   move %3,[%4=%2+%0%T1]")

(define_insn "*mov_sidesisf_biap_mem"

  [(set (mem (plus:SI

              (mult:SI (match_operand:SI 0 "register_operand" "r,r,r,r,r,r")

                       (match_operand:SI 1 "const_int_operand" "n,n,n,n,n,n"))

              (match_operand:SI 2 "register_operand" "r,r,r,r,r,r")))

        (match_operand 3 "register_operand" "r,r,r,x,x,x"))

   (set (match_operand:SI 4 "register_operand" "=*2,!3,r,*2,!3,r")

        (plus:SI (mult:SI (match_dup 0)

                          (match_dup 1))

                 (match_dup 2)))]

  "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD

   && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"

  "@

   #

   #

   move.%s3 %3,[%4=%2+%0%T1]

   #

   #

   move %3,[%4=%2+%0%T1]")

;; Split for the case above where we're out of luck with register

;; allocation (again, the condition isn't checked for that), and we end up

;; with the set in the side-effect getting the same register as the input

;; register.

(define_split

  [(parallel

    [(set (match_operator

           6 "cris_mem_op"

           [(plus:SI

             (mult:SI (match_operand:SI 0 "register_operand" "")

                      (match_operand:SI 1 "const_int_operand" ""))

             (match_operand:SI 2 "register_operand" ""))])

          (match_operand 3 "register_operand" ""))

     (set (match_operand:SI 4 "register_operand" "")

          (plus:SI (mult:SI (match_dup 0)

                            (match_dup 1))

                   (match_dup 2)))])]

  "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"

  [(set (match_dup 5) (match_dup 3))

   (set (match_dup 4) (match_dup 2))

   (set (match_dup 4)

        (plus:SI (mult:SI (match_dup 0)

                          (match_dup 1))

                 (match_dup 4)))]

  "operands[5]

     = replace_equiv_address (operands[6],

                              gen_rtx_PLUS (SImode,

                                            gen_rtx_MULT (SImode,

                                                          operands[0],

                                                          operands[1]),

                                            operands[2]));")

;; move.s rx,[ry=rz+i]

;; FIXME: These could have anonymous mode for operand 2.

;; QImode

(define_insn "*mov_side_mem"

  [(set (mem:BW

         (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r,R,R,R")

                  (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r,r,r")))

        (match_operand:BW 2 "register_operand" "r,r,r,r,r,r,r"))

   (set (match_operand:SI 3 "register_operand" "=*0,!*2,r,r,*1,!*2,r")

        (plus:SI (match_dup 0)

                 (match_dup 1)))]

  "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"

{

  if ((which_alternative == 0 || which_alternative == 4)

      && (GET_CODE (operands[1]) != CONST_INT

          || INTVAL (operands[1]) > 127

          || INTVAL (operands[1]) < -128

          || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')

          || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))

    return "#";

  if (which_alternative == 1 || which_alternative == 5)

    return "#";

  if (which_alternative == 6)

    return "move.%s2 %2,[%3=%1%S0]";

  return "move %2,[%3=%0%S1]";

})

;; SImode

(define_insn "*mov_sidesisf_mem"

  [(set (mem

         (plus:SI

          (match_operand:SI

                                "%r,  r,   r,r,  r,   r,r,  R,R,  R,R, R")

          (match_operand:SI

           1 "cris_bdap_operand"

                                "r>Rn,r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,  r,r, r")))

        (match_operand 2 "register_operand"

                                "r,   r,   r,r,  x,   x,x,  r,r,  r,x, x"))

   (set (match_operand:SI 3 "register_operand"

                                "=*0,!2,   r,r,  *0,  r,r, *1,!*2,r,*1,r")

        (plus:SI (match_dup 0)

                 (match_dup 1)))]

  "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD

   && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"

{

  if ((which_alternative == 0 || which_alternative == 4)

      && (GET_CODE (operands[1]) != CONST_INT

          || INTVAL (operands[1]) > 127

          || INTVAL (operands[1]) < -128

          || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')

          || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))

    return "#";

  if (which_alternative == 1

      || which_alternative == 7

      || which_alternative == 8

      || which_alternative == 10)

    return "#";

  if (which_alternative < 4)

    return "move.%s2 %2,[%3=%0%S1]";

  if (which_alternative == 9)

    return "move.%s2 %2,[%3=%1%S0]";

  if (which_alternative == 11)

    return "move %2,[%3=%1%S0]";

  return "move %2,[%3=%0%S1]";

})

;; Like the biap case, a split where the set in the side-effect gets the

;; same register as the input register to the main insn, since the

;; condition isn't checked at register allocation.

(define_split

  [(parallel

    [(set (match_operator

           4 "cris_mem_op"

           [(plus:SI

             (match_operand:SI 0 "cris_bdap_operand" "")

             (match_operand:SI 1 "cris_bdap_operand" ""))])

          (match_operand 2 "register_operand" ""))

     (set (match_operand:SI 3 "register_operand" "")

          (plus:SI (match_dup 0) (match_dup 1)))])]

  "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"

  [(set (match_dup 4) (match_dup 2))

   (set (match_dup 3) (match_dup 0))

   (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]

  "")

;; Clear memory side-effect patterns.  It is hard to get to the mode if

;; the MEM was anonymous, so there will be one for each mode.

;;  clear.[bwd] [ry=rx+rw.s2]

(define_insn "*clear_side_biap"

  [(set (mem:BWD (plus:SI

                  (mult:SI (match_operand:SI 0 "register_operand" "r,r")

                           (match_operand:SI 1 "const_int_operand" "n,n"))

                  (match_operand:SI 2 "register_operand" "r,r")))

        (const_int 0))

   (set (match_operand:SI 3 "register_operand" "=*2,r")

        (plus:SI (mult:SI (match_dup 0)

                          (match_dup 1))

                 (match_dup 2)))]

  "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"

  "@

   #

   clear [%3=%2+%0%T1]")

;; clear.[bwd] [ry=rz+i]

(define_insn "*clear_side"

  [(set (mem:BWD

         (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,R,R")

                  (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))

        (const_int 0))

   (set (match_operand:SI 2 "register_operand" "=*0,r,r,*1,r")

        (plus:SI (match_dup 0)

                 (match_dup 1)))]

  "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"

{

  if ((which_alternative == 0 || which_alternative == 3)

      && (GET_CODE (operands[1]) != CONST_INT

          || INTVAL (operands[1]) > 127

          || INTVAL (operands[1]) < -128

          || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')

          || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))

    return "#";

  if (which_alternative == 4)

    return "clear [%2=%1%S0]";

  return "clear [%2=%0%S1]";

})

;; Normal move patterns from SI on.

(define_expand "movsi"

  [(set

    (match_operand:SI 0 "nonimmediate_operand" "")

    (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]

  ""

{

  /* If the output goes to a MEM, make sure we have zero or a register as

     input.  */

  if (GET_CODE (operands[0]) == MEM

      && ! REG_S_P (operands[1])

      && operands[1] != const0_rtx

      && ! no_new_pseudos)

    operands[1] = force_reg (SImode, operands[1]);

  /* If we're generating PIC and have an incoming symbol, validize it to a

     general operand or something that will match a special pattern.

     FIXME: Do we *have* to recognize anything that would normally be a

     valid symbol?  Can we exclude global PIC addresses with an added

     offset?  */

    if (flag_pic

        && CONSTANT_ADDRESS_P (operands[1])

        && !cris_valid_pic_const (operands[1]))

      {

        enum cris_pic_symbol_type t = cris_pic_symbol_type_of (operands[1]);

        gcc_assert (t != cris_no_symbol);

        if (! REG_S_P (operands[0]))

          {

            /* We must have a register as destination for what we're about to

               do, and for the patterns we generate.  */

            CRIS_ASSERT (!no_new_pseudos);

            operands[1] = force_reg (SImode, operands[1]);

          }

        else

          {

            /* FIXME: add a REG_EQUAL (or is it REG_EQUIV) note to the

               destination register for the symbol.  It might not be

               worth it.  Measure.  */

            current_function_uses_pic_offset_table = 1;

            if (t == cris_gotrel_symbol)

              {

                /* Change a "move.d sym(+offs),rN" into (allocate register rM)

                   "move.d (const (plus (unspec [sym]

                    CRIS_UNSPEC_GOTREL) offs)),rM" "add.d rPIC,rM,rN"  */

                rtx tem, rm, rn = operands[0];

                rtx sym = GET_CODE (operands[1]) != CONST

                  ? operands[1] : get_related_value (operands[1]);

                HOST_WIDE_INT offs = get_integer_term (operands[1]);

                gcc_assert (! no_new_pseudos);

                tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),

                                      CRIS_UNSPEC_GOTREL);

                if (offs != 0)

                  tem = plus_constant (tem, offs);

                rm = gen_reg_rtx (Pmode);

                emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));

                if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,

                                  rn, 0, OPTAB_LIB_WIDEN) != rn)

                  internal_error ("expand_binop failed in movsi gotrel");

                DONE;

              }

            else if (t == cris_got_symbol)

              {

                /* Change a "move.d sym,rN" into (allocate register rM, rO)

                   "move.d (const (unspec [sym] CRIS_UNSPEC_GOTREAD)),rM"

                   "add.d rPIC,rM,rO", "move.d [rO],rN" with

                   the memory access marked as read-only.  */

                rtx tem, mem, rm, ro, rn = operands[0];

                gcc_assert (! no_new_pseudos);

                tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),

                                      CRIS_UNSPEC_GOTREAD);

                rm = gen_reg_rtx (Pmode);

                emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));

                ro = gen_reg_rtx (Pmode);

                if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,

                                  ro, 0, OPTAB_LIB_WIDEN) != ro)

                  internal_error ("expand_binop failed in movsi got");

                mem = gen_rtx_MEM (Pmode, ro);

                /* This MEM doesn't alias anything.  Whether it

                   aliases other same symbols is unimportant.  */

                set_mem_alias_set (mem, new_alias_set ());

                MEM_NOTRAP_P (mem) = 1;

                MEM_READONLY_P (mem) = 1;

                emit_move_insn (rn, mem);

                DONE;

              }

            else

              {

                /* We get here when we have to change something that would

                   be recognizable if it wasn't PIC.  A ``sym'' is ok for

                   PIC symbols both with and without a GOT entry.  And ``sym

                   + offset'' is ok for local symbols, so the only thing it

                   could be, is a global symbol with an offset.  Check and

                   abort if not.  */

                rtx reg = gen_reg_rtx (Pmode);

                rtx sym = get_related_value (operands[1]);

                HOST_WIDE_INT offs = get_integer_term (operands[1]);

                gcc_assert (! no_new_pseudos

                            && t == cris_got_symbol_needing_fixup

                            && sym != NULL_RTX && offs != 0);

                emit_move_insn (reg, sym);

                if (expand_binop (SImode, add_optab, reg,

                                  GEN_INT (offs), operands[0], 0,

                                  OPTAB_LIB_WIDEN) != operands[0])

                  internal_error ("expand_binop failed in movsi got+offs");

                DONE;

              }

          }

      }

})

(define_insn "*movsi_got_load"

  [(set (reg:SI CRIS_GOT_REGNUM) (unspec:SI [(const_int 0)] CRIS_UNSPEC_GOT))]

  "flag_pic"

  "move.d $pc,%:\;sub.d .:GOTOFF,%:"

  [(set_attr "cc" "clobber")])

(define_insn "*movsi_internal"

  [(set

    (match_operand:SI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x,  m,x")

    ;; Note that we prefer not to use the S alternative (if for some reason

    ;; it competes with others), but g matches S.

    (match_operand:SI 1 "general_operand"       "r,Q>,M,M, I,r, M,n,!S,g,r,x,  rQ>,x,gi"))]

  ""

{

  /* Better to have c-switch here; it is worth it to optimize the size of

     move insns.  The alternative would be to try to find more constraint

     letters.  FIXME: Check again.  It seems this could shrink a bit.  */

  switch (which_alternative)

    {

    case 0:

    case 1:

    case 5:

    case 9:

    case 10:

      return "move.d %1,%0";

    case 11:

    case 12:

    case 13:

    case 14:

      return "move %d1,%0";

    case 2:

    case 3:

    case 6:

      return "clear.d %0";

      /* Constants -32..31 except 0.  */

    case 4: