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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [h8300/] [h8300.c] - Blame information for rev 154

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1 38 julius
/* Subroutines for insn-output.c for Renesas H8/300.
2
   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3
   2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
4
   Contributed by Steve Chamberlain (sac@cygnus.com),
5
   Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6
 
7
This file is part of GCC.
8
 
9
GCC is free software; you can redistribute it and/or modify
10
it under the terms of the GNU General Public License as published by
11
the Free Software Foundation; either version 3, or (at your option)
12
any later version.
13
 
14
GCC is distributed in the hope that it will be useful,
15
but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with GCC; see the file COPYING3.  If not see
21
<http://www.gnu.org/licenses/>.  */
22
 
23
#include "config.h"
24
#include "system.h"
25
#include "coretypes.h"
26
#include "tm.h"
27
#include "rtl.h"
28
#include "tree.h"
29
#include "regs.h"
30
#include "hard-reg-set.h"
31
#include "real.h"
32
#include "insn-config.h"
33
#include "conditions.h"
34
#include "output.h"
35
#include "insn-attr.h"
36
#include "flags.h"
37
#include "recog.h"
38
#include "expr.h"
39
#include "function.h"
40
#include "optabs.h"
41
#include "toplev.h"
42
#include "c-pragma.h"
43
#include "tm_p.h"
44
#include "ggc.h"
45
#include "target.h"
46
#include "target-def.h"
47
 
48
/* Classifies a h8300_src_operand or h8300_dst_operand.
49
 
50
   H8OP_IMMEDIATE
51
        A constant operand of some sort.
52
 
53
   H8OP_REGISTER
54
        An ordinary register.
55
 
56
   H8OP_MEM_ABSOLUTE
57
        A memory reference with a constant address.
58
 
59
   H8OP_MEM_BASE
60
        A memory reference with a register as its address.
61
 
62
   H8OP_MEM_COMPLEX
63
        Some other kind of memory reference.  */
64
enum h8300_operand_class
65
{
66
  H8OP_IMMEDIATE,
67
  H8OP_REGISTER,
68
  H8OP_MEM_ABSOLUTE,
69
  H8OP_MEM_BASE,
70
  H8OP_MEM_COMPLEX,
71
  NUM_H8OPS
72
};
73
 
74
/* For a general two-operand instruction, element [X][Y] gives
75
   the length of the opcode fields when the first operand has class
76
   (X + 1) and the second has class Y.  */
77
typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
78
 
79
/* Forward declarations.  */
80
static const char *byte_reg (rtx, int);
81
static int h8300_interrupt_function_p (tree);
82
static int h8300_saveall_function_p (tree);
83
static int h8300_monitor_function_p (tree);
84
static int h8300_os_task_function_p (tree);
85
static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT);
86
static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
87
static unsigned int compute_saved_regs (void);
88
static void push (int);
89
static void pop (int);
90
static const char *cond_string (enum rtx_code);
91
static unsigned int h8300_asm_insn_count (const char *);
92
static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
93
static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
94
static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
95
#ifndef OBJECT_FORMAT_ELF
96
static void h8300_asm_named_section (const char *, unsigned int, tree);
97
#endif
98
static int h8300_and_costs (rtx);
99
static int h8300_shift_costs (rtx);
100
static void          h8300_push_pop               (int, int, int, int);
101
static int           h8300_stack_offset_p         (rtx, int);
102
static int           h8300_ldm_stm_regno          (rtx, int, int, int);
103
static void          h8300_reorg                  (void);
104
static unsigned int  h8300_constant_length        (rtx);
105
static unsigned int  h8300_displacement_length    (rtx, int);
106
static unsigned int  h8300_classify_operand       (rtx, int, enum h8300_operand_class *);
107
static unsigned int  h8300_length_from_table      (rtx, rtx, const h8300_length_table *);
108
static unsigned int  h8300_unary_length           (rtx);
109
static unsigned int  h8300_short_immediate_length (rtx);
110
static unsigned int  h8300_bitfield_length        (rtx, rtx);
111
static unsigned int  h8300_binary_length          (rtx, const h8300_length_table *);
112
static bool          h8300_short_move_mem_p       (rtx, enum rtx_code);
113
static unsigned int  h8300_move_length            (rtx *, const h8300_length_table *);
114
 
115
/* CPU_TYPE, says what cpu we're compiling for.  */
116
int cpu_type;
117
 
118
/* True if a #pragma interrupt has been seen for the current function.  */
119
static int pragma_interrupt;
120
 
121
/* True if a #pragma saveall has been seen for the current function.  */
122
static int pragma_saveall;
123
 
124
static const char *const names_big[] =
125
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
126
 
127
static const char *const names_extended[] =
128
{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
129
 
130
static const char *const names_upper_extended[] =
131
{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
132
 
133
/* Points to one of the above.  */
134
/* ??? The above could be put in an array indexed by CPU_TYPE.  */
135
const char * const *h8_reg_names;
136
 
137
/* Various operations needed by the following, indexed by CPU_TYPE.  */
138
 
139
const char *h8_push_op, *h8_pop_op, *h8_mov_op;
140
 
141
/* Value of MOVE_RATIO.  */
142
int h8300_move_ratio;
143
 
144
/* See below where shifts are handled for explanation of this enum.  */
145
 
146
enum shift_alg
147
{
148
  SHIFT_INLINE,
149
  SHIFT_ROT_AND,
150
  SHIFT_SPECIAL,
151
  SHIFT_LOOP
152
};
153
 
154
/* Symbols of the various shifts which can be used as indices.  */
155
 
156
enum shift_type
157
{
158
  SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
159
};
160
 
161
/* Macros to keep the shift algorithm tables small.  */
162
#define INL SHIFT_INLINE
163
#define ROT SHIFT_ROT_AND
164
#define LOP SHIFT_LOOP
165
#define SPC SHIFT_SPECIAL
166
 
167
/* The shift algorithms for each machine, mode, shift type, and shift
168
   count are defined below.  The three tables below correspond to
169
   QImode, HImode, and SImode, respectively.  Each table is organized
170
   by, in the order of indices, machine, shift type, and shift count.  */
171
 
172
static enum shift_alg shift_alg_qi[3][3][8] = {
173
  {
174
    /* TARGET_H8300  */
175
    /* 0    1    2    3    4    5    6    7  */
176
    { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT   */
177
    { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
178
    { INL, INL, INL, INL, INL, LOP, LOP, SPC }  /* SHIFT_ASHIFTRT */
179
  },
180
  {
181
    /* TARGET_H8300H  */
182
    /* 0    1    2    3    4    5    6    7  */
183
    { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT   */
184
    { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
185
    { INL, INL, INL, INL, INL, LOP, LOP, SPC }  /* SHIFT_ASHIFTRT */
186
  },
187
  {
188
    /* TARGET_H8300S  */
189
    /*  0    1    2    3    4    5    6    7  */
190
    { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT   */
191
    { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
192
    { INL, INL, INL, INL, INL, INL, INL, SPC }  /* SHIFT_ASHIFTRT */
193
  }
194
};
195
 
196
static enum shift_alg shift_alg_hi[3][3][16] = {
197
  {
198
    /* TARGET_H8300  */
199
    /*  0    1    2    3    4    5    6    7  */
200
    /*  8    9   10   11   12   13   14   15  */
201
    { INL, INL, INL, INL, INL, INL, INL, SPC,
202
      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT   */
203
    { INL, INL, INL, INL, INL, LOP, LOP, SPC,
204
      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
205
    { INL, INL, INL, INL, INL, LOP, LOP, SPC,
206
      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
207
  },
208
  {
209
    /* TARGET_H8300H  */
210
    /*  0    1    2    3    4    5    6    7  */
211
    /*  8    9   10   11   12   13   14   15  */
212
    { INL, INL, INL, INL, INL, INL, INL, SPC,
213
      SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT   */
214
    { INL, INL, INL, INL, INL, INL, INL, SPC,
215
      SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
216
    { INL, INL, INL, INL, INL, INL, INL, SPC,
217
      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
218
  },
219
  {
220
    /* TARGET_H8300S  */
221
    /*  0    1    2    3    4    5    6    7  */
222
    /*  8    9   10   11   12   13   14   15  */
223
    { INL, INL, INL, INL, INL, INL, INL, INL,
224
      SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT   */
225
    { INL, INL, INL, INL, INL, INL, INL, INL,
226
      SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
227
    { INL, INL, INL, INL, INL, INL, INL, INL,
228
      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
229
  }
230
};
231
 
232
static enum shift_alg shift_alg_si[3][3][32] = {
233
  {
234
    /* TARGET_H8300  */
235
    /*  0    1    2    3    4    5    6    7  */
236
    /*  8    9   10   11   12   13   14   15  */
237
    /* 16   17   18   19   20   21   22   23  */
238
    /* 24   25   26   27   28   29   30   31  */
239
    { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
240
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
241
      SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
242
      SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT   */
243
    { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
244
      SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
245
      SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
246
      SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
247
    { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
248
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
249
      SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
250
      SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
251
  },
252
  {
253
    /* TARGET_H8300H  */
254
    /*  0    1    2    3    4    5    6    7  */
255
    /*  8    9   10   11   12   13   14   15  */
256
    /* 16   17   18   19   20   21   22   23  */
257
    /* 24   25   26   27   28   29   30   31  */
258
    { INL, INL, INL, INL, INL, LOP, LOP, LOP,
259
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
260
      SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
261
      SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT   */
262
    { INL, INL, INL, INL, INL, LOP, LOP, LOP,
263
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
264
      SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
265
      SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
266
    { INL, INL, INL, INL, INL, LOP, LOP, LOP,
267
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
268
      SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
269
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
270
  },
271
  {
272
    /* TARGET_H8300S  */
273
    /*  0    1    2    3    4    5    6    7  */
274
    /*  8    9   10   11   12   13   14   15  */
275
    /* 16   17   18   19   20   21   22   23  */
276
    /* 24   25   26   27   28   29   30   31  */
277
    { INL, INL, INL, INL, INL, INL, INL, INL,
278
      INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
279
      SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
280
      SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT   */
281
    { INL, INL, INL, INL, INL, INL, INL, INL,
282
      INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
283
      SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
284
      SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
285
    { INL, INL, INL, INL, INL, INL, INL, INL,
286
      INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
287
      SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
288
      SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
289
  }
290
};
291
 
292
#undef INL
293
#undef ROT
294
#undef LOP
295
#undef SPC
296
 
297
enum h8_cpu
298
{
299
  H8_300,
300
  H8_300H,
301
  H8_S
302
};
303
 
304
/* Initialize various cpu specific globals at start up.  */
305
 
306
void
307
h8300_init_once (void)
308
{
309
  static const char *const h8_push_ops[2] = { "push" , "push.l" };
310
  static const char *const h8_pop_ops[2]  = { "pop"  , "pop.l"  };
311
  static const char *const h8_mov_ops[2]  = { "mov.w", "mov.l"  };
312
 
313
  if (TARGET_H8300)
314
    {
315
      cpu_type = (int) CPU_H8300;
316
      h8_reg_names = names_big;
317
    }
318
  else
319
    {
320
      /* For this we treat the H8/300H and H8S the same.  */
321
      cpu_type = (int) CPU_H8300H;
322
      h8_reg_names = names_extended;
323
    }
324
  h8_push_op = h8_push_ops[cpu_type];
325
  h8_pop_op = h8_pop_ops[cpu_type];
326
  h8_mov_op = h8_mov_ops[cpu_type];
327
 
328
  if (!TARGET_H8300S && TARGET_MAC)
329
    {
330
      error ("-ms2600 is used without -ms");
331
      target_flags |= MASK_H8300S_1;
332
    }
333
 
334
  if (TARGET_H8300 && TARGET_NORMAL_MODE)
335
    {
336
      error ("-mn is used without -mh or -ms");
337
      target_flags ^= MASK_NORMAL_MODE;
338
    }
339
 
340
  /* Some of the shifts are optimized for speed by default.
341
     See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
342
     If optimizing for size, change shift_alg for those shift to
343
     SHIFT_LOOP.  */
344
  if (optimize_size)
345
    {
346
      /* H8/300 */
347
      shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
348
      shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
349
      shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
350
      shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
351
 
352
      shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
353
      shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
354
 
355
      shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
356
      shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
357
 
358
      /* H8/300H */
359
      shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
360
      shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
361
 
362
      shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
363
      shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
364
 
365
      shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
366
      shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
367
      shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
368
      shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
369
 
370
      /* H8S */
371
      shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
372
    }
373
 
374
  /* Work out a value for MOVE_RATIO.  */
375
  if (!TARGET_H8300SX)
376
    {
377
      /* Memory-memory moves are quite expensive without the
378
         h8sx instructions.  */
379
      h8300_move_ratio = 3;
380
    }
381
  else if (flag_omit_frame_pointer)
382
    {
383
      /* movmd sequences are fairly cheap when er6 isn't fixed.  They can
384
         sometimes be as short as two individual memory-to-memory moves,
385
         but since they use all the call-saved registers, it seems better
386
         to allow up to three moves here.  */
387
      h8300_move_ratio = 4;
388
    }
389
  else if (optimize_size)
390
    {
391
      /* In this case we don't use movmd sequences since they tend
392
         to be longer than calls to memcpy().  Memory-to-memory
393
         moves are cheaper than for !TARGET_H8300SX, so it makes
394
         sense to have a slightly higher threshold.  */
395
      h8300_move_ratio = 4;
396
    }
397
  else
398
    {
399
      /* We use movmd sequences for some moves since it can be quicker
400
         than calling memcpy().  The sequences will need to save and
401
         restore er6 though, so bump up the cost.  */
402
      h8300_move_ratio = 6;
403
    }
404
}
405
 
406
/* Implement REG_CLASS_FROM_LETTER.
407
 
408
   Some patterns need to use er6 as a scratch register.  This is
409
   difficult to arrange since er6 is the frame pointer and usually
410
   can't be spilled.
411
 
412
   Such patterns should define two alternatives, one which allows only
413
   er6 and one which allows any general register.  The former alternative
414
   should have a 'd' constraint while the latter should be disparaged and
415
   use 'D'.
416
 
417
   Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
418
   However, there are cases where they should be NO_REGS:
419
 
420
     - 'd' should be NO_REGS when reloading a function that uses the
421
       frame pointer.  In this case, DESTINATION_REGS won't contain any
422
       spillable registers, so the first alternative can't be used.
423
 
424
     - -fno-omit-frame-pointer means that the frame pointer will
425
       always be in use.  It's therefore better to map 'd' to NO_REGS
426
       before reload so that register allocator will pick the second
427
       alternative.
428
 
429
     - we would like 'D' to be be NO_REGS when the frame pointer isn't
430
       live, but we the frame pointer may turn out to be needed after
431
       we start reload, and then we may have already decided we don't
432
       have a choice, so we can't do that.  Forcing the register
433
       allocator to use er6 if possible might produce better code for
434
       small functions: it's more efficient to save and restore er6 in
435
       the prologue & epilogue than to do it in a define_split.
436
       Hopefully disparaging 'D' will have a similar effect, without
437
       forcing a reload failure if the frame pointer is found to be
438
       needed too late.  */
439
 
440
enum reg_class
441
h8300_reg_class_from_letter (int c)
442
{
443
  switch (c)
444
    {
445
    case 'a':
446
      return MAC_REGS;
447
 
448
    case 'c':
449
      return COUNTER_REGS;
450
 
451
    case 'd':
452
      if (!flag_omit_frame_pointer && !reload_completed)
453
        return NO_REGS;
454
      if (frame_pointer_needed && reload_in_progress)
455
        return NO_REGS;
456
      return DESTINATION_REGS;
457
 
458
    case 'D':
459
      /* The meaning of a constraint shouldn't change dynamically, so
460
         we can't make this NO_REGS.  */
461
      return GENERAL_REGS;
462
 
463
    case 'f':
464
      return SOURCE_REGS;
465
 
466
    default:
467
      return NO_REGS;
468
    }
469
}
470
 
471
/* Return the byte register name for a register rtx X.  B should be 0
472
   if you want a lower byte register.  B should be 1 if you want an
473
   upper byte register.  */
474
 
475
static const char *
476
byte_reg (rtx x, int b)
477
{
478
  static const char *const names_small[] = {
479
    "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
480
    "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
481
  };
482
 
483
  gcc_assert (REG_P (x));
484
 
485
  return names_small[REGNO (x) * 2 + b];
486
}
487
 
488
/* REGNO must be saved/restored across calls if this macro is true.  */
489
 
490
#define WORD_REG_USED(regno)                                            \
491
  (regno < SP_REG                                                       \
492
   /* No need to save registers if this function will not return.  */   \
493
   && ! TREE_THIS_VOLATILE (current_function_decl)                      \
494
   && (h8300_saveall_function_p (current_function_decl)                 \
495
       /* Save any call saved register that was used.  */               \
496
       || (regs_ever_live[regno] && !call_used_regs[regno])             \
497
       /* Save the frame pointer if it was used.  */                    \
498
       || (regno == HARD_FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
499
       /* Save any register used in an interrupt handler.  */           \
500
       || (h8300_current_function_interrupt_function_p ()               \
501
           && regs_ever_live[regno])                                    \
502
       /* Save call clobbered registers in non-leaf interrupt           \
503
          handlers.  */                                                 \
504
       || (h8300_current_function_interrupt_function_p ()               \
505
           && call_used_regs[regno]                                     \
506
           && !current_function_is_leaf)))
507
 
508
/* Output assembly language to FILE for the operation OP with operand size
509
   SIZE to adjust the stack pointer.  */
510
 
511
static void
512
h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size)
513
{
514
  /* If the frame size is 0, we don't have anything to do.  */
515
  if (size == 0)
516
    return;
517
 
518
  /* H8/300 cannot add/subtract a large constant with a single
519
     instruction.  If a temporary register is available, load the
520
     constant to it and then do the addition.  */
521
  if (TARGET_H8300
522
      && size > 4
523
      && !h8300_current_function_interrupt_function_p ()
524
      && !(cfun->static_chain_decl != NULL && sign < 0))
525
    {
526
      rtx r3 = gen_rtx_REG (Pmode, 3);
527
      emit_insn (gen_movhi (r3, GEN_INT (sign * size)));
528
      emit_insn (gen_addhi3 (stack_pointer_rtx,
529
                             stack_pointer_rtx, r3));
530
    }
531
  else
532
    {
533
      /* The stack adjustment made here is further optimized by the
534
         splitter.  In case of H8/300, the splitter always splits the
535
         addition emitted here to make the adjustment
536
         interrupt-safe.  */
537
      if (Pmode == HImode)
538
        emit_insn (gen_addhi3 (stack_pointer_rtx,
539
                               stack_pointer_rtx, GEN_INT (sign * size)));
540
      else
541
        emit_insn (gen_addsi3 (stack_pointer_rtx,
542
                               stack_pointer_rtx, GEN_INT (sign * size)));
543
    }
544
}
545
 
546
/* Round up frame size SIZE.  */
547
 
548
static HOST_WIDE_INT
549
round_frame_size (HOST_WIDE_INT size)
550
{
551
  return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
552
          & -STACK_BOUNDARY / BITS_PER_UNIT);
553
}
554
 
555
/* Compute which registers to push/pop.
556
   Return a bit vector of registers.  */
557
 
558
static unsigned int
559
compute_saved_regs (void)
560
{
561
  unsigned int saved_regs = 0;
562
  int regno;
563
 
564
  /* Construct a bit vector of registers to be pushed/popped.  */
565
  for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
566
    {
567
      if (WORD_REG_USED (regno))
568
        saved_regs |= 1 << regno;
569
    }
570
 
571
  /* Don't push/pop the frame pointer as it is treated separately.  */
572
  if (frame_pointer_needed)
573
    saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
574
 
575
  return saved_regs;
576
}
577
 
578
/* Emit an insn to push register RN.  */
579
 
580
static void
581
push (int rn)
582
{
583
  rtx reg = gen_rtx_REG (word_mode, rn);
584
  rtx x;
585
 
586
  if (TARGET_H8300)
587
    x = gen_push_h8300 (reg);
588
  else if (!TARGET_NORMAL_MODE)
589
    x = gen_push_h8300hs_advanced (reg);
590
  else
591
    x = gen_push_h8300hs_normal (reg);
592
  x = emit_insn (x);
593
  REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
594
}
595
 
596
/* Emit an insn to pop register RN.  */
597
 
598
static void
599
pop (int rn)
600
{
601
  rtx reg = gen_rtx_REG (word_mode, rn);
602
  rtx x;
603
 
604
  if (TARGET_H8300)
605
    x = gen_pop_h8300 (reg);
606
  else if (!TARGET_NORMAL_MODE)
607
    x = gen_pop_h8300hs_advanced (reg);
608
  else
609
    x = gen_pop_h8300hs_normal (reg);
610
  x = emit_insn (x);
611
  REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
612
}
613
 
614
/* Emit an instruction to push or pop NREGS consecutive registers
615
   starting at register REGNO.  POP_P selects a pop rather than a
616
   push and RETURN_P is true if the instruction should return.
617
 
618
   It must be possible to do the requested operation in a single
619
   instruction.  If NREGS == 1 && !RETURN_P, use a normal push
620
   or pop insn.  Otherwise emit a parallel of the form:
621
 
622
     (parallel
623
       [(return)  ;; if RETURN_P
624
        (save or restore REGNO)
625
        (save or restore REGNO + 1)
626
        ...
627
        (save or restore REGNO + NREGS - 1)
628
        (set sp (plus sp (const_int adjust)))]  */
629
 
630
static void
631
h8300_push_pop (int regno, int nregs, int pop_p, int return_p)
632
{
633
  int i, j;
634
  rtvec vec;
635
  rtx sp, offset;
636
 
637
  /* See whether we can use a simple push or pop.  */
638
  if (!return_p && nregs == 1)
639
    {
640
      if (pop_p)
641
        pop (regno);
642
      else
643
        push (regno);
644
      return;
645
    }
646
 
647
  /* We need one element for the return insn, if present, one for each
648
     register, and one for stack adjustment.  */
649
  vec = rtvec_alloc ((return_p != 0) + nregs + 1);
650
  sp = stack_pointer_rtx;
651
  i = 0;
652
 
653
  /* Add the return instruction.  */
654
  if (return_p)
655
    {
656
      RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode);
657
      i++;
658
    }
659
 
660
  /* Add the register moves.  */
661
  for (j = 0; j < nregs; j++)
662
    {
663
      rtx lhs, rhs;
664
 
665
      if (pop_p)
666
        {
667
          /* Register REGNO + NREGS - 1 is popped first.  Before the
668
             stack adjustment, its slot is at address @sp.  */
669
          lhs = gen_rtx_REG (SImode, regno + j);
670
          rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4));
671
        }
672
      else
673
        {
674
          /* Register REGNO is pushed first and will be stored at @(-4,sp).  */
675
          lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4));
676
          rhs = gen_rtx_REG (SImode, regno + j);
677
        }
678
      RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
679
    }
680
 
681
  /* Add the stack adjustment.  */
682
  offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
683
  RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
684
                                        gen_rtx_PLUS (Pmode, sp, offset));
685
 
686
  emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
687
}
688
 
689
/* Return true if X has the value sp + OFFSET.  */
690
 
691
static int
692
h8300_stack_offset_p (rtx x, int offset)
693
{
694
  if (offset == 0)
695
    return x == stack_pointer_rtx;
696
 
697
  return (GET_CODE (x) == PLUS
698
          && XEXP (x, 0) == stack_pointer_rtx
699
          && GET_CODE (XEXP (x, 1)) == CONST_INT
700
          && INTVAL (XEXP (x, 1)) == offset);
701
}
702
 
703
/* A subroutine of h8300_ldm_stm_parallel.  X is one pattern in
704
   something that may be an ldm or stm instruction.  If it fits
705
   the required template, return the register it loads or stores,
706
   otherwise return -1.
707
 
708
   LOAD_P is true if X should be a load, false if it should be a store.
709
   NREGS is the number of registers that the whole instruction is expected
710
   to load or store.  INDEX is the index of the register that X should
711
   load or store, relative to the lowest-numbered register.  */
712
 
713
static int
714
h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
715
{
716
  int regindex, memindex, offset;
717
 
718
  if (load_p)
719
    regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
720
  else
721
    memindex = 0, regindex = 1, offset = (index + 1) * -4;
722
 
723
  if (GET_CODE (x) == SET
724
      && GET_CODE (XEXP (x, regindex)) == REG
725
      && GET_CODE (XEXP (x, memindex)) == MEM
726
      && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
727
    return REGNO (XEXP (x, regindex));
728
 
729
  return -1;
730
}
731
 
732
/* Return true if the elements of VEC starting at FIRST describe an
733
   ldm or stm instruction (LOAD_P says which).  */
734
 
735
int
736
h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
737
{
738
  rtx last;
739
  int nregs, i, regno, adjust;
740
 
741
  /* There must be a stack adjustment, a register move, and at least one
742
     other operation (a return or another register move).  */
743
  if (GET_NUM_ELEM (vec) < 3)
744
    return false;
745
 
746
  /* Get the range of registers to be pushed or popped.  */
747
  nregs = GET_NUM_ELEM (vec) - first - 1;
748
  regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
749
 
750
  /* Check that the call to h8300_ldm_stm_regno succeeded and
751
     that we're only dealing with GPRs.  */
752
  if (regno < 0 || regno + nregs > 8)
753
    return false;
754
 
755
  /* 2-register h8s instructions must start with an even-numbered register.
756
     3- and 4-register instructions must start with er0 or er4.  */
757
  if (!TARGET_H8300SX)
758
    {
759
      if ((regno & 1) != 0)
760
        return false;
761
      if (nregs > 2 && (regno & 3) != 0)
762
        return false;
763
    }
764
 
765
  /* Check the other loads or stores.  */
766
  for (i = 1; i < nregs; i++)
767
    if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
768
        != regno + i)
769
      return false;
770
 
771
  /* Check the stack adjustment.  */
772
  last = RTVEC_ELT (vec, first + nregs);
773
  adjust = (load_p ? nregs : -nregs) * 4;
774
  return (GET_CODE (last) == SET
775
          && SET_DEST (last) == stack_pointer_rtx
776
          && h8300_stack_offset_p (SET_SRC (last), adjust));
777
}
778
 
779
/* This is what the stack looks like after the prolog of
780
   a function with a frame has been set up:
781
 
782
   <args>
783
   PC
784
   FP                   <- fp
785
   <locals>
786
   <saved registers>    <- sp
787
 
788
   This is what the stack looks like after the prolog of
789
   a function which doesn't have a frame:
790
 
791
   <args>
792
   PC
793
   <locals>
794
   <saved registers>    <- sp
795
*/
796
 
797
/* Generate RTL code for the function prologue.  */
798
 
799
void
800
h8300_expand_prologue (void)
801
{
802
  int regno;
803
  int saved_regs;
804
  int n_regs;
805
 
806
  /* If the current function has the OS_Task attribute set, then
807
     we have a naked prologue.  */
808
  if (h8300_os_task_function_p (current_function_decl))
809
    return;
810
 
811
  if (h8300_monitor_function_p (current_function_decl))
812
    /* My understanding of monitor functions is they act just like
813
       interrupt functions, except the prologue must mask
814
       interrupts.  */
815
    emit_insn (gen_monitor_prologue ());
816
 
817
  if (frame_pointer_needed)
818
    {
819
      /* Push fp.  */
820
      push (HARD_FRAME_POINTER_REGNUM);
821
      emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
822
    }
823
 
824
  /* Push the rest of the registers in ascending order.  */
825
  saved_regs = compute_saved_regs ();
826
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
827
    {
828
      n_regs = 1;
829
      if (saved_regs & (1 << regno))
830
        {
831
          if (TARGET_H8300S)
832
            {
833
              /* See how many registers we can push at the same time.  */
834
              if ((!TARGET_H8300SX || (regno & 3) == 0)
835
                  && ((saved_regs >> regno) & 0x0f) == 0x0f)
836
                n_regs = 4;
837
 
838
              else if ((!TARGET_H8300SX || (regno & 3) == 0)
839
                       && ((saved_regs >> regno) & 0x07) == 0x07)
840
                n_regs = 3;
841
 
842
              else if ((!TARGET_H8300SX || (regno & 1) == 0)
843
                       && ((saved_regs >> regno) & 0x03) == 0x03)
844
                n_regs = 2;
845
            }
846
 
847
          h8300_push_pop (regno, n_regs, 0, 0);
848
        }
849
    }
850
 
851
  /* Leave room for locals.  */
852
  h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
853
}
854
 
855
/* Return nonzero if we can use "rts" for the function currently being
856
   compiled.  */
857
 
858
int
859
h8300_can_use_return_insn_p (void)
860
{
861
  return (reload_completed
862
          && !frame_pointer_needed
863
          && get_frame_size () == 0
864
          && compute_saved_regs () == 0);
865
}
866
 
867
/* Generate RTL code for the function epilogue.  */
868
 
869
void
870
h8300_expand_epilogue (void)
871
{
872
  int regno;
873
  int saved_regs;
874
  int n_regs;
875
  HOST_WIDE_INT frame_size;
876
  bool returned_p;
877
 
878
  if (h8300_os_task_function_p (current_function_decl))
879
    /* OS_Task epilogues are nearly naked -- they just have an
880
       rts instruction.  */
881
    return;
882
 
883
  frame_size = round_frame_size (get_frame_size ());
884
  returned_p = false;
885
 
886
  /* Deallocate locals.  */
887
  h8300_emit_stack_adjustment (1, frame_size);
888
 
889
  /* Pop the saved registers in descending order.  */
890
  saved_regs = compute_saved_regs ();
891
  for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
892
    {
893
      n_regs = 1;
894
      if (saved_regs & (1 << regno))
895
        {
896
          if (TARGET_H8300S)
897
            {
898
              /* See how many registers we can pop at the same time.  */
899
              if ((TARGET_H8300SX || (regno & 3) == 3)
900
                  && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
901
                n_regs = 4;
902
 
903
              else if ((TARGET_H8300SX || (regno & 3) == 2)
904
                       && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
905
                n_regs = 3;
906
 
907
              else if ((TARGET_H8300SX || (regno & 1) == 1)
908
                       && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
909
                n_regs = 2;
910
            }
911
 
912
          /* See if this pop would be the last insn before the return.
913
             If so, use rte/l or rts/l instead of pop or ldm.l.  */
914
          if (TARGET_H8300SX
915
              && !frame_pointer_needed
916
              && frame_size == 0
917
              && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
918
            returned_p = true;
919
 
920
          h8300_push_pop (regno - n_regs + 1, n_regs, 1, returned_p);
921
        }
922
    }
923
 
924
  /* Pop frame pointer if we had one.  */
925
  if (frame_pointer_needed)
926
    {
927
      if (TARGET_H8300SX)
928
        returned_p = true;
929
      h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, 1, returned_p);
930
    }
931
 
932
  if (!returned_p)
933
    emit_insn (gen_rtx_RETURN (VOIDmode));
934
}
935
 
936
/* Return nonzero if the current function is an interrupt
937
   function.  */
938
 
939
int
940
h8300_current_function_interrupt_function_p (void)
941
{
942
  return (h8300_interrupt_function_p (current_function_decl)
943
          || h8300_monitor_function_p (current_function_decl));
944
}
945
 
946
/* Output assembly code for the start of the file.  */
947
 
948
static void
949
h8300_file_start (void)
950
{
951
  default_file_start ();
952
 
953
  if (TARGET_H8300H)
954
    fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
955
  else if (TARGET_H8300SX)
956
    fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
957
  else if (TARGET_H8300S)
958
    fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
959
}
960
 
961
/* Output assembly language code for the end of file.  */
962
 
963
static void
964
h8300_file_end (void)
965
{
966
  fputs ("\t.end\n", asm_out_file);
967
}
968
 
969
/* Split an add of a small constant into two adds/subs insns.
970
 
971
   If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
972
   instead of adds/subs.  */
973
 
974
void
975
split_adds_subs (enum machine_mode mode, rtx *operands)
976
{
977
  HOST_WIDE_INT val = INTVAL (operands[1]);
978
  rtx reg = operands[0];
979
  HOST_WIDE_INT sign = 1;
980
  HOST_WIDE_INT amount;
981
  rtx (*gen_add) (rtx, rtx, rtx);
982
 
983
  /* Force VAL to be positive so that we do not have to consider the
984
     sign.  */
985
  if (val < 0)
986
    {
987
      val = -val;
988
      sign = -1;
989
    }
990
 
991
  switch (mode)
992
    {
993
    case HImode:
994
      gen_add = gen_addhi3;
995
      break;
996
 
997
    case SImode:
998
      gen_add = gen_addsi3;
999
      break;
1000
 
1001
    default:
1002
      gcc_unreachable ();
1003
    }
1004
 
1005
  /* Try different amounts in descending order.  */
1006
  for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1007
       amount > 0;
1008
       amount /= 2)
1009
    {
1010
      for (; val >= amount; val -= amount)
1011
        emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1012
    }
1013
 
1014
  return;
1015
}
1016
 
1017
/* Handle machine specific pragmas for compatibility with existing
1018
   compilers for the H8/300.
1019
 
1020
   pragma saveall generates prologue/epilogue code which saves and
1021
   restores all the registers on function entry.
1022
 
1023
   pragma interrupt saves and restores all registers, and exits with
1024
   an rte instruction rather than an rts.  A pointer to a function
1025
   with this attribute may be safely used in an interrupt vector.  */
1026
 
1027
void
1028
h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1029
{
1030
  pragma_interrupt = 1;
1031
}
1032
 
1033
void
1034
h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1035
{
1036
  pragma_saveall = 1;
1037
}
1038
 
1039
/* If the next function argument with MODE and TYPE is to be passed in
1040
   a register, return a reg RTX for the hard register in which to pass
1041
   the argument.  CUM represents the state after the last argument.
1042
   If the argument is to be pushed, NULL_RTX is returned.  */
1043
 
1044
rtx
1045
function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1046
              tree type, int named)
1047
{
1048
  static const char *const hand_list[] = {
1049
    "__main",
1050
    "__cmpsi2",
1051
    "__divhi3",
1052
    "__modhi3",
1053
    "__udivhi3",
1054
    "__umodhi3",
1055
    "__divsi3",
1056
    "__modsi3",
1057
    "__udivsi3",
1058
    "__umodsi3",
1059
    "__mulhi3",
1060
    "__mulsi3",
1061
    "__reg_memcpy",
1062
    "__reg_memset",
1063
    "__ucmpsi2",
1064
    0,
1065
  };
1066
 
1067
  rtx result = NULL_RTX;
1068
  const char *fname;
1069
  int regpass = 0;
1070
 
1071
  /* Never pass unnamed arguments in registers.  */
1072
  if (!named)
1073
    return NULL_RTX;
1074
 
1075
  /* Pass 3 regs worth of data in regs when user asked on the command line.  */
1076
  if (TARGET_QUICKCALL)
1077
    regpass = 3;
1078
 
1079
  /* If calling hand written assembler, use 4 regs of args.  */
1080
  if (cum->libcall)
1081
    {
1082
      const char * const *p;
1083
 
1084
      fname = XSTR (cum->libcall, 0);
1085
 
1086
      /* See if this libcall is one of the hand coded ones.  */
1087
      for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1088
        ;
1089
 
1090
      if (*p)
1091
        regpass = 4;
1092
    }
1093
 
1094
  if (regpass)
1095
    {
1096
      int size;
1097
 
1098
      if (mode == BLKmode)
1099
        size = int_size_in_bytes (type);
1100
      else
1101
        size = GET_MODE_SIZE (mode);
1102
 
1103
      if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1104
          && cum->nbytes / UNITS_PER_WORD <= 3)
1105
        result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1106
    }
1107
 
1108
  return result;
1109
}
1110
 
1111
/* Compute the cost of an and insn.  */
1112
 
1113
static int
1114
h8300_and_costs (rtx x)
1115
{
1116
  rtx operands[4];
1117
 
1118
  if (GET_MODE (x) == QImode)
1119
    return 1;
1120
 
1121
  if (GET_MODE (x) != HImode
1122
      && GET_MODE (x) != SImode)
1123
    return 100;
1124
 
1125
  operands[0] = NULL;
1126
  operands[1] = XEXP (x, 0);
1127
  operands[2] = XEXP (x, 1);
1128
  operands[3] = x;
1129
  return compute_logical_op_length (GET_MODE (x), operands) / 2;
1130
}
1131
 
1132
/* Compute the cost of a shift insn.  */
1133
 
1134
static int
1135
h8300_shift_costs (rtx x)
1136
{
1137
  rtx operands[4];
1138
 
1139
  if (GET_MODE (x) != QImode
1140
      && GET_MODE (x) != HImode
1141
      && GET_MODE (x) != SImode)
1142
    return 100;
1143
 
1144
  operands[0] = NULL;
1145
  operands[1] = NULL;
1146
  operands[2] = XEXP (x, 1);
1147
  operands[3] = x;
1148
  return compute_a_shift_length (NULL, operands) / 2;
1149
}
1150
 
1151
/* Worker function for TARGET_RTX_COSTS.  */
1152
 
1153
static bool
1154
h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
1155
{
1156
  if (TARGET_H8300SX && outer_code == MEM)
1157
    {
1158
      /* Estimate the number of execution states needed to calculate
1159
         the address.  */
1160
      if (register_operand (x, VOIDmode)
1161
          || GET_CODE (x) == POST_INC
1162
          || GET_CODE (x) == POST_DEC
1163
          || CONSTANT_P (x))
1164
        *total = 0;
1165
      else
1166
        *total = COSTS_N_INSNS (1);
1167
      return true;
1168
    }
1169
 
1170
  switch (code)
1171
    {
1172
    case CONST_INT:
1173
      {
1174
        HOST_WIDE_INT n = INTVAL (x);
1175
 
1176
        if (TARGET_H8300SX)
1177
          {
1178
            /* Constant operands need the same number of processor
1179
               states as register operands.  Although we could try to
1180
               use a size-based cost for optimize_size, the lack of
1181
               of a mode makes the results very unpredictable.  */
1182
            *total = 0;
1183
            return true;
1184
          }
1185
        if (-4 <= n || n <= 4)
1186
          {
1187
            switch ((int) n)
1188
              {
1189
              case 0:
1190
                *total = 0;
1191
                return true;
1192
              case 1:
1193
              case 2:
1194
              case -1:
1195
              case -2:
1196
                *total = 0 + (outer_code == SET);
1197
                return true;
1198
              case 4:
1199
              case -4:
1200
                if (TARGET_H8300H || TARGET_H8300S)
1201
                  *total = 0 + (outer_code == SET);
1202
                else
1203
                  *total = 1;
1204
                return true;
1205
              }
1206
          }
1207
        *total = 1;
1208
        return true;
1209
      }
1210
 
1211
    case CONST:
1212
    case LABEL_REF:
1213
    case SYMBOL_REF:
1214
      if (TARGET_H8300SX)
1215
        {
1216
          /* See comment for CONST_INT.  */
1217
          *total = 0;
1218
          return true;
1219
        }
1220
      *total = 3;
1221
      return true;
1222
 
1223
    case CONST_DOUBLE:
1224
      *total = 20;
1225
      return true;
1226
 
1227
    case AND:
1228
      if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1229
          || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1230
        return false;
1231
      *total = COSTS_N_INSNS (h8300_and_costs (x));
1232
      return true;
1233
 
1234
    /* We say that MOD and DIV are so expensive because otherwise we'll
1235
       generate some really horrible code for division of a power of two.  */
1236
    case MOD:
1237
    case DIV:
1238
    case UMOD:
1239
    case UDIV:
1240
      if (TARGET_H8300SX)
1241
        switch (GET_MODE (x))
1242
          {
1243
          case QImode:
1244
          case HImode:
1245
            *total = COSTS_N_INSNS (optimize_size ? 4 : 10);
1246
            return false;
1247
 
1248
          case SImode:
1249
            *total = COSTS_N_INSNS (optimize_size ? 4 : 18);
1250
            return false;
1251
 
1252
          default:
1253
            break;
1254
          }
1255
      *total = COSTS_N_INSNS (12);
1256
      return true;
1257
 
1258
    case MULT:
1259
      if (TARGET_H8300SX)
1260
        switch (GET_MODE (x))
1261
          {
1262
          case QImode:
1263
          case HImode:
1264
            *total = COSTS_N_INSNS (2);
1265
            return false;
1266
 
1267
          case SImode:
1268
            *total = COSTS_N_INSNS (5);
1269
            return false;
1270
 
1271
          default:
1272
            break;
1273
          }
1274
      *total = COSTS_N_INSNS (4);
1275
      return true;
1276
 
1277
    case ASHIFT:
1278
    case ASHIFTRT:
1279
    case LSHIFTRT:
1280
      if (h8sx_binary_shift_operator (x, VOIDmode))
1281
        {
1282
          *total = COSTS_N_INSNS (2);
1283
          return false;
1284
        }
1285
      else if (h8sx_unary_shift_operator (x, VOIDmode))
1286
        {
1287
          *total = COSTS_N_INSNS (1);
1288
          return false;
1289
        }
1290
      *total = COSTS_N_INSNS (h8300_shift_costs (x));
1291
      return true;
1292
 
1293
    case ROTATE:
1294
    case ROTATERT:
1295
      if (GET_MODE (x) == HImode)
1296
        *total = 2;
1297
      else
1298
        *total = 8;
1299
      return true;
1300
 
1301
    default:
1302
      *total = COSTS_N_INSNS (1);
1303
      return false;
1304
    }
1305
}
1306
 
1307
/* Documentation for the machine specific operand escapes:
1308
 
1309
   'E' like s but negative.
1310
   'F' like t but negative.
1311
   'G' constant just the negative
1312
   'R' print operand as a byte:8 address if appropriate, else fall back to
1313
       'X' handling.
1314
   'S' print operand as a long word
1315
   'T' print operand as a word
1316
   'V' find the set bit, and print its number.
1317
   'W' find the clear bit, and print its number.
1318
   'X' print operand as a byte
1319
   'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1320
       If this operand isn't a register, fall back to 'R' handling.
1321
   'Z' print int & 7.
1322
   'c' print the opcode corresponding to rtl
1323
   'e' first word of 32 bit value - if reg, then least reg. if mem
1324
       then least. if const then most sig word
1325
   'f' second word of 32 bit value - if reg, then biggest reg. if mem
1326
       then +2. if const then least sig word
1327
   'j' print operand as condition code.
1328
   'k' print operand as reverse condition code.
1329
   'm' convert an integer operand to a size suffix (.b, .w or .l)
1330
   'o' print an integer without a leading '#'
1331
   's' print as low byte of 16 bit value
1332
   't' print as high byte of 16 bit value
1333
   'w' print as low byte of 32 bit value
1334
   'x' print as 2nd byte of 32 bit value
1335
   'y' print as 3rd byte of 32 bit value
1336
   'z' print as msb of 32 bit value
1337
*/
1338
 
1339
/* Return assembly language string which identifies a comparison type.  */
1340
 
1341
static const char *
1342
cond_string (enum rtx_code code)
1343
{
1344
  switch (code)
1345
    {
1346
    case NE:
1347
      return "ne";
1348
    case EQ:
1349
      return "eq";
1350
    case GE:
1351
      return "ge";
1352
    case GT:
1353
      return "gt";
1354
    case LE:
1355
      return "le";
1356
    case LT:
1357
      return "lt";
1358
    case GEU:
1359
      return "hs";
1360
    case GTU:
1361
      return "hi";
1362
    case LEU:
1363
      return "ls";
1364
    case LTU:
1365
      return "lo";
1366
    default:
1367
      gcc_unreachable ();
1368
    }
1369
}
1370
 
1371
/* Print operand X using operand code CODE to assembly language output file
1372
   FILE.  */
1373
 
1374
void
1375
print_operand (FILE *file, rtx x, int code)
1376
{
1377
  /* This is used for communication between codes V,W,Z and Y.  */
1378
  static int bitint;
1379
 
1380
  switch (code)
1381
    {
1382
    case 'E':
1383
      switch (GET_CODE (x))
1384
        {
1385
        case REG:
1386
          fprintf (file, "%sl", names_big[REGNO (x)]);
1387
          break;
1388
        case CONST_INT:
1389
          fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1390
          break;
1391
        default:
1392
          gcc_unreachable ();
1393
        }
1394
      break;
1395
    case 'F':
1396
      switch (GET_CODE (x))
1397
        {
1398
        case REG:
1399
          fprintf (file, "%sh", names_big[REGNO (x)]);
1400
          break;
1401
        case CONST_INT:
1402
          fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1403
          break;
1404
        default:
1405
          gcc_unreachable ();
1406
        }
1407
      break;
1408
    case 'G':
1409
      gcc_assert (GET_CODE (x) == CONST_INT);
1410
      fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1411
      break;
1412
    case 'S':
1413
      if (GET_CODE (x) == REG)
1414
        fprintf (file, "%s", names_extended[REGNO (x)]);
1415
      else
1416
        goto def;
1417
      break;
1418
    case 'T':
1419
      if (GET_CODE (x) == REG)
1420
        fprintf (file, "%s", names_big[REGNO (x)]);
1421
      else
1422
        goto def;
1423
      break;
1424
    case 'V':
1425
      bitint = exact_log2 (INTVAL (x) & 0xff);
1426
      gcc_assert (bitint >= 0);
1427
      fprintf (file, "#%d", bitint);
1428
      break;
1429
    case 'W':
1430
      bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1431
      gcc_assert (bitint >= 0);
1432
      fprintf (file, "#%d", bitint);
1433
      break;
1434
    case 'R':
1435
    case 'X':
1436
      if (GET_CODE (x) == REG)
1437
        fprintf (file, "%s", byte_reg (x, 0));
1438
      else
1439
        goto def;
1440
      break;
1441
    case 'Y':
1442
      gcc_assert (bitint >= 0);
1443
      if (GET_CODE (x) == REG)
1444
        fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1445
      else
1446
        print_operand (file, x, 'R');
1447
      bitint = -1;
1448
      break;
1449
    case 'Z':
1450
      bitint = INTVAL (x);
1451
      fprintf (file, "#%d", bitint & 7);
1452
      break;
1453
    case 'c':
1454
      switch (GET_CODE (x))
1455
        {
1456
        case IOR:
1457
          fprintf (file, "or");
1458
          break;
1459
        case XOR:
1460
          fprintf (file, "xor");
1461
          break;
1462
        case AND:
1463
          fprintf (file, "and");
1464
          break;
1465
        default:
1466
          break;
1467
        }
1468
      break;
1469
    case 'e':
1470
      switch (GET_CODE (x))
1471
        {
1472
        case REG:
1473
          if (TARGET_H8300)
1474
            fprintf (file, "%s", names_big[REGNO (x)]);
1475
          else
1476
            fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1477
          break;
1478
        case MEM:
1479
          print_operand (file, x, 0);
1480
          break;
1481
        case CONST_INT:
1482
          fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1483
          break;
1484
        case CONST_DOUBLE:
1485
          {
1486
            long val;
1487
            REAL_VALUE_TYPE rv;
1488
            REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1489
            REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1490
            fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1491
            break;
1492
          }
1493
        default:
1494
          gcc_unreachable ();
1495
          break;
1496
        }
1497
      break;
1498
    case 'f':
1499
      switch (GET_CODE (x))
1500
        {
1501
        case REG:
1502
          if (TARGET_H8300)
1503
            fprintf (file, "%s", names_big[REGNO (x) + 1]);
1504
          else
1505
            fprintf (file, "%s", names_big[REGNO (x)]);
1506
          break;
1507
        case MEM:
1508
          x = adjust_address (x, HImode, 2);
1509
          print_operand (file, x, 0);
1510
          break;
1511
        case CONST_INT:
1512
          fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1513
          break;
1514
        case CONST_DOUBLE:
1515
          {
1516
            long val;
1517
            REAL_VALUE_TYPE rv;
1518
            REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1519
            REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1520
            fprintf (file, "#%ld", (val & 0xffff));
1521
            break;
1522
          }
1523
        default:
1524
          gcc_unreachable ();
1525
        }
1526
      break;
1527
    case 'j':
1528
      fputs (cond_string (GET_CODE (x)), file);
1529
      break;
1530
    case 'k':
1531
      fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1532
      break;
1533
    case 'm':
1534
      gcc_assert (GET_CODE (x) == CONST_INT);
1535
      switch (INTVAL (x))
1536
        {
1537
        case 1:
1538
          fputs (".b", file);
1539
          break;
1540
 
1541
        case 2:
1542
          fputs (".w", file);
1543
          break;
1544
 
1545
        case 4:
1546
          fputs (".l", file);
1547
          break;
1548
 
1549
        default:
1550
          gcc_unreachable ();
1551
        }
1552
      break;
1553
    case 'o':
1554
      print_operand_address (file, x);
1555
      break;
1556
    case 's':
1557
      if (GET_CODE (x) == CONST_INT)
1558
        fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1559
      else
1560
        fprintf (file, "%s", byte_reg (x, 0));
1561
      break;
1562
    case 't':
1563
      if (GET_CODE (x) == CONST_INT)
1564
        fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1565
      else
1566
        fprintf (file, "%s", byte_reg (x, 1));
1567
      break;
1568
    case 'w':
1569
      if (GET_CODE (x) == CONST_INT)
1570
        fprintf (file, "#%ld", INTVAL (x) & 0xff);
1571
      else
1572
        fprintf (file, "%s",
1573
                 byte_reg (x, TARGET_H8300 ? 2 : 0));
1574
      break;
1575
    case 'x':
1576
      if (GET_CODE (x) == CONST_INT)
1577
        fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1578
      else
1579
        fprintf (file, "%s",
1580
                 byte_reg (x, TARGET_H8300 ? 3 : 1));
1581
      break;
1582
    case 'y':
1583
      if (GET_CODE (x) == CONST_INT)
1584
        fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1585
      else
1586
        fprintf (file, "%s", byte_reg (x, 0));
1587
      break;
1588
    case 'z':
1589
      if (GET_CODE (x) == CONST_INT)
1590
        fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1591
      else
1592
        fprintf (file, "%s", byte_reg (x, 1));
1593
      break;
1594
 
1595
    default:
1596
    def:
1597
      switch (GET_CODE (x))
1598
        {
1599
        case REG:
1600
          switch (GET_MODE (x))
1601
            {
1602
            case QImode:
1603
#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1604
              fprintf (file, "%s", byte_reg (x, 0));
1605
#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1606
              fprintf (file, "%s", names_big[REGNO (x)]);
1607
#endif
1608
              break;
1609
            case HImode:
1610
              fprintf (file, "%s", names_big[REGNO (x)]);
1611
              break;
1612
            case SImode:
1613
            case SFmode:
1614
              fprintf (file, "%s", names_extended[REGNO (x)]);
1615
              break;
1616
            default:
1617
              gcc_unreachable ();
1618
            }
1619
          break;
1620
 
1621
        case MEM:
1622
          {
1623
            rtx addr = XEXP (x, 0);
1624
 
1625
            fprintf (file, "@");
1626
            output_address (addr);
1627
 
1628
            /* Add a length suffix to constant addresses.  Although this
1629
               is often unnecessary, it helps to avoid ambiguity in the
1630
               syntax of mova.  If we wrote an insn like:
1631
 
1632
                    mova/w.l @(1,@foo.b),er0
1633
 
1634
               then .b would be considered part of the symbol name.
1635
               Adding a length after foo will avoid this.  */
1636
            if (CONSTANT_P (addr))
1637
              switch (code)
1638
                {
1639
                case 'R':
1640
                  /* Used for mov.b and bit operations.  */
1641
                  if (h8300_eightbit_constant_address_p (addr))
1642
                    {
1643
                      fprintf (file, ":8");
1644
                      break;
1645
                    }
1646
 
1647
                  /* Fall through.  We should not get here if we are
1648
                     processing bit operations on H8/300 or H8/300H
1649
                     because 'U' constraint does not allow bit
1650
                     operations on the tiny area on these machines.  */
1651
 
1652
                case 'X':
1653
                case 'T':
1654
                case 'S':
1655
                  if (h8300_constant_length (addr) == 2)
1656
                    fprintf (file, ":16");
1657
                  else
1658
                    fprintf (file, ":32");
1659
                  break;
1660
                default:
1661
                  break;
1662
                }
1663
          }
1664
          break;
1665
 
1666
        case CONST_INT:
1667
        case SYMBOL_REF:
1668
        case CONST:
1669
        case LABEL_REF:
1670
          fprintf (file, "#");
1671
          print_operand_address (file, x);
1672
          break;
1673
        case CONST_DOUBLE:
1674
          {
1675
            long val;
1676
            REAL_VALUE_TYPE rv;
1677
            REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1678
            REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1679
            fprintf (file, "#%ld", val);
1680
            break;
1681
          }
1682
        default:
1683
          break;
1684
        }
1685
    }
1686
}
1687
 
1688
/* Output assembly language output for the address ADDR to FILE.  */
1689
 
1690
void
1691
print_operand_address (FILE *file, rtx addr)
1692
{
1693
  rtx index;
1694
  int size;
1695
 
1696
  switch (GET_CODE (addr))
1697
    {
1698
    case REG:
1699
      fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1700
      break;
1701
 
1702
    case PRE_DEC:
1703
      fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1704
      break;
1705
 
1706
    case POST_INC:
1707
      fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1708
      break;
1709
 
1710
    case PRE_INC:
1711
      fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1712
      break;
1713
 
1714
    case POST_DEC:
1715
      fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1716
      break;
1717
 
1718
    case PLUS:
1719
      fprintf (file, "(");
1720
 
1721
      index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1722
      if (GET_CODE (index) == REG)
1723
        {
1724
          /* reg,foo */
1725
          print_operand_address (file, XEXP (addr, 1));
1726
          fprintf (file, ",");
1727
          switch (size)
1728
            {
1729
            case 0:
1730
              print_operand_address (file, index);
1731
              break;
1732
 
1733
            case 1:
1734
              print_operand (file, index, 'X');
1735
              fputs (".b", file);
1736
              break;
1737
 
1738
            case 2:
1739
              print_operand (file, index, 'T');
1740
              fputs (".w", file);
1741
              break;
1742
 
1743
            case 4:
1744
              print_operand (file, index, 'S');
1745
              fputs (".l", file);
1746
              break;
1747
            }
1748
          /* print_operand_address (file, XEXP (addr, 0)); */
1749
        }
1750
      else
1751
        {
1752
          /* foo+k */
1753
          print_operand_address (file, XEXP (addr, 0));
1754
          fprintf (file, "+");
1755
          print_operand_address (file, XEXP (addr, 1));
1756
        }
1757
      fprintf (file, ")");
1758
      break;
1759
 
1760
    case CONST_INT:
1761
      {
1762
        /* Since the H8/300 only has 16 bit pointers, negative values are also
1763
           those >= 32768.  This happens for example with pointer minus a
1764
           constant.  We don't want to turn (char *p - 2) into
1765
           (char *p + 65534) because loop unrolling can build upon this
1766
           (IE: char *p + 131068).  */
1767
        int n = INTVAL (addr);
1768
        if (TARGET_H8300)
1769
          n = (int) (short) n;
1770
        fprintf (file, "%d", n);
1771
        break;
1772
      }
1773
 
1774
    default:
1775
      output_addr_const (file, addr);
1776
      break;
1777
    }
1778
}
1779
 
1780
/* Output all insn addresses and their sizes into the assembly language
1781
   output file.  This is helpful for debugging whether the length attributes
1782
   in the md file are correct.  This is not meant to be a user selectable
1783
   option.  */
1784
 
1785
void
1786
final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1787
                    int num_operands ATTRIBUTE_UNUSED)
1788
{
1789
  /* This holds the last insn address.  */
1790
  static int last_insn_address = 0;
1791
 
1792
  const int uid = INSN_UID (insn);
1793
 
1794
  if (TARGET_ADDRESSES)
1795
    {
1796
      fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1797
               INSN_ADDRESSES (uid) - last_insn_address);
1798
      last_insn_address = INSN_ADDRESSES (uid);
1799
    }
1800
}
1801
 
1802
/* Prepare for an SI sized move.  */
1803
 
1804
int
1805
h8300_expand_movsi (rtx operands[])
1806
{
1807
  rtx src = operands[1];
1808
  rtx dst = operands[0];
1809
  if (!reload_in_progress && !reload_completed)
1810
    {
1811
      if (!register_operand (dst, GET_MODE (dst)))
1812
        {
1813
          rtx tmp = gen_reg_rtx (GET_MODE (dst));
1814
          emit_move_insn (tmp, src);
1815
          operands[1] = tmp;
1816
        }
1817
    }
1818
  return 0;
1819
}
1820
 
1821
/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1822
   Define the offset between two registers, one to be eliminated, and
1823
   the other its replacement, at the start of a routine.  */
1824
 
1825
int
1826
h8300_initial_elimination_offset (int from, int to)
1827
{
1828
  /* The number of bytes that the return address takes on the stack.  */
1829
  int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1830
 
1831
  /* The number of bytes that the saved frame pointer takes on the stack.  */
1832
  int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1833
 
1834
  /* The number of bytes that the saved registers, excluding the frame
1835
     pointer, take on the stack.  */
1836
  int saved_regs_size = 0;
1837
 
1838
  /* The number of bytes that the locals takes on the stack.  */
1839
  int frame_size = round_frame_size (get_frame_size ());
1840
 
1841
  int regno;
1842
 
1843
  for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1844
    if (WORD_REG_USED (regno))
1845
      saved_regs_size += UNITS_PER_WORD;
1846
 
1847
  /* Adjust saved_regs_size because the above loop took the frame
1848
     pointer int account.  */
1849
  saved_regs_size -= fp_size;
1850
 
1851
  switch (to)
1852
    {
1853
    case HARD_FRAME_POINTER_REGNUM:
1854
      switch (from)
1855
        {
1856
        case ARG_POINTER_REGNUM:
1857
          return pc_size + fp_size;
1858
        case RETURN_ADDRESS_POINTER_REGNUM:
1859
          return fp_size;
1860
        case FRAME_POINTER_REGNUM:
1861
          return -saved_regs_size;
1862
        default:
1863
          gcc_unreachable ();
1864
        }
1865
      break;
1866
    case STACK_POINTER_REGNUM:
1867
      switch (from)
1868
        {
1869
        case ARG_POINTER_REGNUM:
1870
          return pc_size + saved_regs_size + frame_size;
1871
        case RETURN_ADDRESS_POINTER_REGNUM:
1872
          return saved_regs_size + frame_size;
1873
        case FRAME_POINTER_REGNUM:
1874
          return frame_size;
1875
        default:
1876
          gcc_unreachable ();
1877
        }
1878
      break;
1879
    default:
1880
      gcc_unreachable ();
1881
    }
1882
  gcc_unreachable ();
1883
}
1884
 
1885
/* Worker function for RETURN_ADDR_RTX.  */
1886
 
1887
rtx
1888
h8300_return_addr_rtx (int count, rtx frame)
1889
{
1890
  rtx ret;
1891
 
1892
  if (count == 0)
1893
    ret = gen_rtx_MEM (Pmode,
1894
                       gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1895
  else if (flag_omit_frame_pointer)
1896
    return (rtx) 0;
1897
  else
1898
    ret = gen_rtx_MEM (Pmode,
1899
                       memory_address (Pmode,
1900
                                       plus_constant (frame, UNITS_PER_WORD)));
1901
  set_mem_alias_set (ret, get_frame_alias_set ());
1902
  return ret;
1903
}
1904
 
1905
/* Update the condition code from the insn.  */
1906
 
1907
void
1908
notice_update_cc (rtx body, rtx insn)
1909
{
1910
  rtx set;
1911
 
1912
  switch (get_attr_cc (insn))
1913
    {
1914
    case CC_NONE:
1915
      /* Insn does not affect CC at all.  */
1916
      break;
1917
 
1918
    case CC_NONE_0HIT:
1919
      /* Insn does not change CC, but the 0'th operand has been changed.  */
1920
      if (cc_status.value1 != 0
1921
          && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1922
        cc_status.value1 = 0;
1923
      if (cc_status.value2 != 0
1924
          && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1925
        cc_status.value2 = 0;
1926
      break;
1927
 
1928
    case CC_SET_ZN:
1929
      /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1930
         The V flag is unusable.  The C flag may or may not be known but
1931
         that's ok because alter_cond will change tests to use EQ/NE.  */
1932
      CC_STATUS_INIT;
1933
      cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1934
      set = single_set (insn);
1935
      cc_status.value1 = SET_SRC (set);
1936
      if (SET_DEST (set) != cc0_rtx)
1937
        cc_status.value2 = SET_DEST (set);
1938
      break;
1939
 
1940
    case CC_SET_ZNV:
1941
      /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1942
         The C flag may or may not be known but that's ok because
1943
         alter_cond will change tests to use EQ/NE.  */
1944
      CC_STATUS_INIT;
1945
      cc_status.flags |= CC_NO_CARRY;
1946
      set = single_set (insn);
1947
      cc_status.value1 = SET_SRC (set);
1948
      if (SET_DEST (set) != cc0_rtx)
1949
        {
1950
          /* If the destination is STRICT_LOW_PART, strip off
1951
             STRICT_LOW_PART.  */
1952
          if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1953
            cc_status.value2 = XEXP (SET_DEST (set), 0);
1954
          else
1955
            cc_status.value2 = SET_DEST (set);
1956
        }
1957
      break;
1958
 
1959
    case CC_COMPARE:
1960
      /* The insn is a compare instruction.  */
1961
      CC_STATUS_INIT;
1962
      cc_status.value1 = SET_SRC (body);
1963
      break;
1964
 
1965
    case CC_CLOBBER:
1966
      /* Insn doesn't leave CC in a usable state.  */
1967
      CC_STATUS_INIT;
1968
      break;
1969
    }
1970
}
1971
 
1972
/* Given that X occurs in an address of the form (plus X constant),
1973
   return the part of X that is expected to be a register.  There are
1974
   four kinds of addressing mode to recognize:
1975
 
1976
        @(dd,Rn)
1977
        @(dd,RnL.b)
1978
        @(dd,Rn.w)
1979
        @(dd,ERn.l)
1980
 
1981
   If SIZE is nonnull, and the address is one of the last three forms,
1982
   set *SIZE to the index multiplication factor.  Set it to 0 for
1983
   plain @(dd,Rn) addresses.
1984
 
1985
   MODE is the mode of the value being accessed.  It can be VOIDmode
1986
   if the address is known to be valid, but its mode is unknown.  */
1987
 
1988
rtx
1989
h8300_get_index (rtx x, enum machine_mode mode, int *size)
1990
{
1991
  int dummy, factor;
1992
 
1993
  if (size == 0)
1994
    size = &dummy;
1995
 
1996
  factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
1997
  if (TARGET_H8300SX
1998
      && factor <= 4
1999
      && (mode == VOIDmode
2000
          || GET_MODE_CLASS (mode) == MODE_INT
2001
          || GET_MODE_CLASS (mode) == MODE_FLOAT))
2002
    {
2003
      if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2004
        {
2005
          /* When accessing byte-sized values, the index can be
2006
             a zero-extended QImode or HImode register.  */
2007
          *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2008
          return XEXP (x, 0);
2009
        }
2010
      else
2011
        {
2012
          /* We're looking for addresses of the form:
2013
 
2014
                 (mult X I)
2015
              or (mult (zero_extend X) I)
2016
 
2017
             where I is the size of the operand being accessed.
2018
             The canonical form of the second expression is:
2019
 
2020
                 (and (mult (subreg X) I) J)
2021
 
2022
             where J == GET_MODE_MASK (GET_MODE (X)) * I.  */
2023
          rtx index;
2024
 
2025
          if (GET_CODE (x) == AND
2026
              && GET_CODE (XEXP (x, 1)) == CONST_INT
2027
              && (factor == 0
2028
                  || INTVAL (XEXP (x, 1)) == 0xff * factor
2029
                  || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2030
            {
2031
              index = XEXP (x, 0);
2032
              *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2033
            }
2034
          else
2035
            {
2036
              index = x;
2037
              *size = 4;
2038
            }
2039
 
2040
          if (GET_CODE (index) == MULT
2041
              && GET_CODE (XEXP (index, 1)) == CONST_INT
2042
              && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2043
            return XEXP (index, 0);
2044
        }
2045
    }
2046
  *size = 0;
2047
  return x;
2048
}
2049
 
2050
static const h8300_length_table addb_length_table =
2051
{
2052
  /* #xx  Rs   @aa  @Rs  @xx  */
2053
  {  2,   2,   4,   4,   4  }, /* add.b xx,Rd  */
2054
  {  4,   4,   4,   4,   6  }, /* add.b xx,@aa */
2055
  {  4,   4,   4,   4,   6  }, /* add.b xx,@Rd */
2056
  {  6,   4,   4,   4,   6  }  /* add.b xx,@xx */
2057
};
2058
 
2059
static const h8300_length_table addw_length_table =
2060
{
2061
  /* #xx  Rs   @aa  @Rs  @xx  */
2062
  {  2,   2,   4,   4,   4  }, /* add.w xx,Rd  */
2063
  {  4,   4,   4,   4,   6  }, /* add.w xx,@aa */
2064
  {  4,   4,   4,   4,   6  }, /* add.w xx,@Rd */
2065
  {  4,   4,   4,   4,   6  }  /* add.w xx,@xx */
2066
};
2067
 
2068
static const h8300_length_table addl_length_table =
2069
{
2070
  /* #xx  Rs   @aa  @Rs  @xx  */
2071
  {  2,   2,   4,   4,   4  }, /* add.l xx,Rd  */
2072
  {  4,   4,   6,   6,   6  }, /* add.l xx,@aa */
2073
  {  4,   4,   6,   6,   6  }, /* add.l xx,@Rd */
2074
  {  4,   4,   6,   6,   6  }  /* add.l xx,@xx */
2075
};
2076
 
2077
#define logicb_length_table addb_length_table
2078
#define logicw_length_table addw_length_table
2079
 
2080
static const h8300_length_table logicl_length_table =
2081
{
2082
  /* #xx  Rs   @aa  @Rs  @xx  */
2083
  {  2,   4,   4,   4,   4  }, /* and.l xx,Rd  */
2084
  {  4,   4,   6,   6,   6  }, /* and.l xx,@aa */
2085
  {  4,   4,   6,   6,   6  }, /* and.l xx,@Rd */
2086
  {  4,   4,   6,   6,   6  }  /* and.l xx,@xx */
2087
};
2088
 
2089
static const h8300_length_table movb_length_table =
2090
{
2091
  /* #xx  Rs   @aa  @Rs  @xx  */
2092
  {  2,   2,   2,   2,   4  }, /* mov.b xx,Rd  */
2093
  {  4,   2,   4,   4,   4  }, /* mov.b xx,@aa */
2094
  {  4,   2,   4,   4,   4  }, /* mov.b xx,@Rd */
2095
  {  4,   4,   4,   4,   4  }  /* mov.b xx,@xx */
2096
};
2097
 
2098
#define movw_length_table movb_length_table
2099
 
2100
static const h8300_length_table movl_length_table =
2101
{
2102
  /* #xx  Rs   @aa  @Rs  @xx  */
2103
  {  2,   2,   4,   4,   4  }, /* mov.l xx,Rd  */
2104
  {  4,   4,   4,   4,   4  }, /* mov.l xx,@aa */
2105
  {  4,   4,   4,   4,   4  }, /* mov.l xx,@Rd */
2106
  {  4,   4,   4,   4,   4  }  /* mov.l xx,@xx */
2107
};
2108
 
2109
/* Return the size of the given address or displacement constant.  */
2110
 
2111
static unsigned int
2112
h8300_constant_length (rtx constant)
2113
{
2114
  /* Check for (@d:16,Reg).  */
2115
  if (GET_CODE (constant) == CONST_INT
2116
      && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2117
    return 2;
2118
 
2119
  /* Check for (@d:16,Reg) in cases where the displacement is
2120
     an absolute address.  */
2121
  if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2122
    return 2;
2123
 
2124
  return 4;
2125
}
2126
 
2127
/* Return the size of a displacement field in address ADDR, which should
2128
   have the form (plus X constant).  SIZE is the number of bytes being
2129
   accessed.  */
2130
 
2131
static unsigned int
2132
h8300_displacement_length (rtx addr, int size)
2133
{
2134
  rtx offset;
2135
 
2136
  offset = XEXP (addr, 1);
2137
 
2138
  /* Check for @(d:2,Reg).  */
2139
  if (register_operand (XEXP (addr, 0), VOIDmode)
2140
      && GET_CODE (offset) == CONST_INT
2141
      && (INTVAL (offset) == size
2142
          || INTVAL (offset) == size * 2
2143
          || INTVAL (offset) == size * 3))
2144
    return 0;
2145
 
2146
  return h8300_constant_length (offset);
2147
}
2148
 
2149
/* Store the class of operand OP in *CLASS and return the length of any
2150
   extra operand fields.  SIZE is the number of bytes in OP.  CLASS
2151
   can be null if only the length is needed.  */
2152
 
2153
static unsigned int
2154
h8300_classify_operand (rtx op, int size, enum h8300_operand_class *class)
2155
{
2156
  enum h8300_operand_class dummy;
2157
 
2158
  if (class == 0)
2159
    class = &dummy;
2160
 
2161
  if (CONSTANT_P (op))
2162
    {
2163
      *class = H8OP_IMMEDIATE;
2164
 
2165
      /* Byte-sized immediates are stored in the opcode fields.  */
2166
      if (size == 1)
2167
        return 0;
2168
 
2169
      /* If this is a 32-bit instruction, see whether the constant
2170
         will fit into a 16-bit immediate field.  */
2171
      if (TARGET_H8300SX
2172
          && size == 4
2173
          && GET_CODE (op) == CONST_INT
2174
          && IN_RANGE (INTVAL (op), 0, 0xffff))
2175
        return 2;
2176
 
2177
      return size;
2178
    }
2179
  else if (GET_CODE (op) == MEM)
2180
    {
2181
      op = XEXP (op, 0);
2182
      if (CONSTANT_P (op))
2183
        {
2184
          *class = H8OP_MEM_ABSOLUTE;
2185
          return h8300_constant_length (op);
2186
        }
2187
      else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2188
        {
2189
          *class = H8OP_MEM_COMPLEX;
2190
          return h8300_displacement_length (op, size);
2191
        }
2192
      else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2193
        {
2194
          *class = H8OP_MEM_COMPLEX;
2195
          return 0;
2196
        }
2197
      else if (register_operand (op, VOIDmode))
2198
        {
2199
          *class = H8OP_MEM_BASE;
2200
          return 0;
2201
        }
2202
    }
2203
  gcc_assert (register_operand (op, VOIDmode));
2204
  *class = H8OP_REGISTER;
2205
  return 0;
2206
}
2207
 
2208
/* Return the length of the instruction described by TABLE given that
2209
   its operands are OP1 and OP2.  OP1 must be an h8300_dst_operand
2210
   and OP2 must be an h8300_src_operand.  */
2211
 
2212
static unsigned int
2213
h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2214
{
2215
  enum h8300_operand_class op1_class, op2_class;
2216
  unsigned int size, immediate_length;
2217
 
2218
  size = GET_MODE_SIZE (GET_MODE (op1));
2219
  immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2220
                      + h8300_classify_operand (op2, size, &op2_class));
2221
  return immediate_length + (*table)[op1_class - 1][op2_class];
2222
}
2223
 
2224
/* Return the length of a unary instruction such as neg or not given that
2225
   its operand is OP.  */
2226
 
2227
unsigned int
2228
h8300_unary_length (rtx op)
2229
{
2230
  enum h8300_operand_class class;
2231
  unsigned int size, operand_length;
2232
 
2233
  size = GET_MODE_SIZE (GET_MODE (op));
2234
  operand_length = h8300_classify_operand (op, size, &class);
2235
  switch (class)
2236
    {
2237
    case H8OP_REGISTER:
2238
      return 2;
2239
 
2240
    case H8OP_MEM_BASE:
2241
      return (size == 4 ? 6 : 4);
2242
 
2243
    case H8OP_MEM_ABSOLUTE:
2244
      return operand_length + (size == 4 ? 6 : 4);
2245
 
2246
    case H8OP_MEM_COMPLEX:
2247
      return operand_length + 6;
2248
 
2249
    default:
2250
      gcc_unreachable ();
2251
    }
2252
}
2253
 
2254
/* Likewise short immediate instructions such as add.w #xx:3,OP.  */
2255
 
2256
static unsigned int
2257
h8300_short_immediate_length (rtx op)
2258
{
2259
  enum h8300_operand_class class;
2260
  unsigned int size, operand_length;
2261
 
2262
  size = GET_MODE_SIZE (GET_MODE (op));
2263
  operand_length = h8300_classify_operand (op, size, &class);
2264
 
2265
  switch (class)
2266
    {
2267
    case H8OP_REGISTER:
2268
      return 2;
2269
 
2270
    case H8OP_MEM_BASE:
2271
    case H8OP_MEM_ABSOLUTE:
2272
    case H8OP_MEM_COMPLEX:
2273
      return 4 + operand_length;
2274
 
2275
    default:
2276
      gcc_unreachable ();
2277
    }
2278
}
2279
 
2280
/* Likewise bitfield load and store instructions.  */
2281
 
2282
static unsigned int
2283
h8300_bitfield_length (rtx op, rtx op2)
2284
{
2285
  enum h8300_operand_class class;
2286
  unsigned int size, operand_length;
2287
 
2288
  if (GET_CODE (op) == REG)
2289
    op = op2;
2290
  gcc_assert (GET_CODE (op) != REG);
2291
 
2292
  size = GET_MODE_SIZE (GET_MODE (op));
2293
  operand_length = h8300_classify_operand (op, size, &class);
2294
 
2295
  switch (class)
2296
    {
2297
    case H8OP_MEM_BASE:
2298
    case H8OP_MEM_ABSOLUTE:
2299
    case H8OP_MEM_COMPLEX:
2300
      return 4 + operand_length;
2301
 
2302
    default:
2303
      gcc_unreachable ();
2304
    }
2305
}
2306
 
2307
/* Calculate the length of general binary instruction INSN using TABLE.  */
2308
 
2309
static unsigned int
2310
h8300_binary_length (rtx insn, const h8300_length_table *table)
2311
{
2312
  rtx set;
2313
 
2314
  set = single_set (insn);
2315
  gcc_assert (set);
2316
 
2317
  if (BINARY_P (SET_SRC (set)))
2318
    return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2319
                                    XEXP (SET_SRC (set), 1), table);
2320
  else
2321
    {
2322
      gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2323
      return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2324
                                      XEXP (XEXP (SET_SRC (set), 1), 1),
2325
                                      table);
2326
    }
2327
}
2328
 
2329
/* Subroutine of h8300_move_length.  Return true if OP is 1- or 2-byte
2330
   memory reference and either (1) it has the form @(d:16,Rn) or
2331
   (2) its address has the code given by INC_CODE.  */
2332
 
2333
static bool
2334
h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2335
{
2336
  rtx addr;
2337
  unsigned int size;
2338
 
2339
  if (GET_CODE (op) != MEM)
2340
    return false;
2341
 
2342
  addr = XEXP (op, 0);
2343
  size = GET_MODE_SIZE (GET_MODE (op));
2344
  if (size != 1 && size != 2)
2345
    return false;
2346
 
2347
  return (GET_CODE (addr) == inc_code
2348
          || (GET_CODE (addr) == PLUS
2349
              && GET_CODE (XEXP (addr, 0)) == REG
2350
              && h8300_displacement_length (addr, size) == 2));
2351
}
2352
 
2353
/* Calculate the length of move instruction INSN using the given length
2354
   table.  Although the tables are correct for most cases, there is some
2355
   irregularity in the length of mov.b and mov.w.  The following forms:
2356
 
2357
        mov @ERs+, Rd
2358
        mov @(d:16,ERs), Rd
2359
        mov Rs, @-ERd
2360
        mov Rs, @(d:16,ERd)
2361
 
2362
   are two bytes shorter than most other "mov Rs, @complex" or
2363
   "mov @complex,Rd" combinations.  */
2364
 
2365
static unsigned int
2366
h8300_move_length (rtx *operands, const h8300_length_table *table)
2367
{
2368
  unsigned int size;
2369
 
2370
  size = h8300_length_from_table (operands[0], operands[1], table);
2371
  if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2372
    size -= 2;
2373
  if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2374
    size -= 2;
2375
  return size;
2376
}
2377
 
2378
/* Return the length of a mova instruction with the given operands.
2379
   DEST is the register destination, SRC is the source address and
2380
   OFFSET is the 16-bit or 32-bit displacement.  */
2381
 
2382
static unsigned int
2383
h8300_mova_length (rtx dest, rtx src, rtx offset)
2384
{
2385
  unsigned int size;
2386
 
2387
  size = (2
2388
          + h8300_constant_length (offset)
2389
          + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2390
  if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2391
    size += 2;
2392
  return size;
2393
}
2394
 
2395
/* Compute the length of INSN based on its length_table attribute.
2396
   OPERANDS is the array of its operands.  */
2397
 
2398
unsigned int
2399
h8300_insn_length_from_table (rtx insn, rtx * operands)
2400
{
2401
  switch (get_attr_length_table (insn))
2402
    {
2403
    case LENGTH_TABLE_NONE:
2404
      gcc_unreachable ();
2405
 
2406
    case LENGTH_TABLE_ADDB:
2407
      return h8300_binary_length (insn, &addb_length_table);
2408
 
2409
    case LENGTH_TABLE_ADDW:
2410
      return h8300_binary_length (insn, &addw_length_table);
2411
 
2412
    case LENGTH_TABLE_ADDL:
2413
      return h8300_binary_length (insn, &addl_length_table);
2414
 
2415
    case LENGTH_TABLE_LOGICB:
2416
      return h8300_binary_length (insn, &logicb_length_table);
2417
 
2418
    case LENGTH_TABLE_MOVB:
2419
      return h8300_move_length (operands, &movb_length_table);
2420
 
2421
    case LENGTH_TABLE_MOVW:
2422
      return h8300_move_length (operands, &movw_length_table);
2423
 
2424
    case LENGTH_TABLE_MOVL:
2425
      return h8300_move_length (operands, &movl_length_table);
2426
 
2427
    case LENGTH_TABLE_MOVA:
2428
      return h8300_mova_length (operands[0], operands[1], operands[2]);
2429
 
2430
    case LENGTH_TABLE_MOVA_ZERO:
2431
      return h8300_mova_length (operands[0], operands[1], const0_rtx);
2432
 
2433
    case LENGTH_TABLE_UNARY:
2434
      return h8300_unary_length (operands[0]);
2435
 
2436
    case LENGTH_TABLE_MOV_IMM4:
2437
      return 2 + h8300_classify_operand (operands[0], 0, 0);
2438
 
2439
    case LENGTH_TABLE_SHORT_IMMEDIATE:
2440
      return h8300_short_immediate_length (operands[0]);
2441
 
2442
    case LENGTH_TABLE_BITFIELD:
2443
      return h8300_bitfield_length (operands[0], operands[1]);
2444
 
2445
    case LENGTH_TABLE_BITBRANCH:
2446
      return h8300_bitfield_length (operands[1], operands[2]) - 2;
2447
 
2448
    default:
2449
      gcc_unreachable ();
2450
    }
2451
}
2452
 
2453
/* Return true if LHS and RHS are memory references that can be mapped
2454
   to the same h8sx assembly operand.  LHS appears as the destination of
2455
   an instruction and RHS appears as a source.
2456
 
2457
   Three cases are allowed:
2458
 
2459
        - RHS is @+Rn or @-Rn, LHS is @Rn
2460
        - RHS is @Rn, LHS is @Rn+ or @Rn-
2461
        - RHS and LHS have the same address and neither has side effects.  */
2462
 
2463
bool
2464
h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2465
{
2466
  if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2467
    {
2468
      rhs = XEXP (rhs, 0);
2469
      lhs = XEXP (lhs, 0);
2470
 
2471
      if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2472
        return rtx_equal_p (XEXP (rhs, 0), lhs);
2473
 
2474
      if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2475
        return rtx_equal_p (rhs, XEXP (lhs, 0));
2476
 
2477
      if (rtx_equal_p (rhs, lhs))
2478
        return true;
2479
    }
2480
  return false;
2481
}
2482
 
2483
/* Return true if OPERANDS[1] can be mapped to the same assembly
2484
   operand as OPERANDS[0].  */
2485
 
2486
bool
2487
h8300_operands_match_p (rtx *operands)
2488
{
2489
  if (register_operand (operands[0], VOIDmode)
2490
      && register_operand (operands[1], VOIDmode))
2491
    return true;
2492
 
2493
  if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2494
    return true;
2495
 
2496
  return false;
2497
}
2498
 
2499
/* Try using movmd to move LENGTH bytes from memory region SRC to memory
2500
   region DEST.  The two regions do not overlap and have the common
2501
   alignment given by ALIGNMENT.  Return true on success.
2502
 
2503
   Using movmd for variable-length moves seems to involve some
2504
   complex trade-offs.  For instance:
2505
 
2506
      - Preparing for a movmd instruction is similar to preparing
2507
        for a memcpy.  The main difference is that the arguments
2508
        are moved into er4, er5 and er6 rather than er0, er1 and er2.
2509
 
2510
      - Since movmd clobbers the frame pointer, we need to save
2511
        and restore it somehow when frame_pointer_needed.  This can
2512
        sometimes make movmd sequences longer than calls to memcpy().
2513
 
2514
      - The counter register is 16 bits, so the instruction is only
2515
        suitable for variable-length moves when sizeof (size_t) == 2.
2516
        That's only true in normal mode.
2517
 
2518
      - We will often lack static alignment information.  Falling back
2519
        on movmd.b would likely be slower than calling memcpy(), at least
2520
        for big moves.
2521
 
2522
   This function therefore only uses movmd when the length is a
2523
   known constant, and only then if -fomit-frame-pointer is in
2524
   effect or if we're not optimizing for size.
2525
 
2526
   At the moment the function uses movmd for all in-range constants,
2527
   but it might be better to fall back on memcpy() for large moves
2528
   if ALIGNMENT == 1.  */
2529
 
2530
bool
2531
h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2532
                 HOST_WIDE_INT alignment)
2533
{
2534
  if (!flag_omit_frame_pointer && optimize_size)
2535
    return false;
2536
 
2537
  if (GET_CODE (length) == CONST_INT)
2538
    {
2539
      rtx dest_reg, src_reg, first_dest, first_src;
2540
      HOST_WIDE_INT n;
2541
      int factor;
2542
 
2543
      /* Use movmd.l if the alignment allows it, otherwise fall back
2544
         on movmd.b.  */
2545
      factor = (alignment >= 2 ? 4 : 1);
2546
 
2547
      /* Make sure the length is within range.  We can handle counter
2548
         values up to 65536, although HImode truncation will make
2549
         the count appear negative in rtl dumps.  */
2550
      n = INTVAL (length);
2551
      if (n <= 0 || n / factor > 65536)
2552
        return false;
2553
 
2554
      /* Create temporary registers for the source and destination
2555
         pointers.  Initialize them to the start of each region.  */
2556
      dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2557
      src_reg = copy_addr_to_reg (XEXP (src, 0));
2558
 
2559
      /* Create references to the movmd source and destination blocks.  */
2560
      first_dest = replace_equiv_address (dest, dest_reg);
2561
      first_src = replace_equiv_address (src, src_reg);
2562
 
2563
      set_mem_size (first_dest, GEN_INT (n & -factor));
2564
      set_mem_size (first_src, GEN_INT (n & -factor));
2565
 
2566
      length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2567
      emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2568
 
2569
      if ((n & -factor) != n)
2570
        {
2571
          /* Move SRC and DEST past the region we just copied.
2572
             This is done to update the memory attributes.  */
2573
          dest = adjust_address (dest, BLKmode, n & -factor);
2574
          src = adjust_address (src, BLKmode, n & -factor);
2575
 
2576
          /* Replace the addresses with the source and destination
2577
             registers, which movmd has left with the right values.  */
2578
          dest = replace_equiv_address (dest, dest_reg);
2579
          src = replace_equiv_address (src, src_reg);
2580
 
2581
          /* Mop up the left-over bytes.  */
2582
          if (n & 2)
2583
            emit_move_insn (adjust_address (dest, HImode, 0),
2584
                            adjust_address (src, HImode, 0));
2585
          if (n & 1)
2586
            emit_move_insn (adjust_address (dest, QImode, n & 2),
2587
                            adjust_address (src, QImode, n & 2));
2588
        }
2589
      return true;
2590
    }
2591
  return false;
2592
}
2593
 
2594
/* Move ADDR into er6 after pushing its old value onto the stack.  */
2595
 
2596
void
2597
h8300_swap_into_er6 (rtx addr)
2598
{
2599
  push (HARD_FRAME_POINTER_REGNUM);
2600
  emit_move_insn (hard_frame_pointer_rtx, addr);
2601
  if (REGNO (addr) == SP_REG)
2602
    emit_move_insn (hard_frame_pointer_rtx,
2603
                    plus_constant (hard_frame_pointer_rtx,
2604
                                   GET_MODE_SIZE (word_mode)));
2605
}
2606
 
2607
/* Move the current value of er6 into ADDR and pop its old value
2608
   from the stack.  */
2609
 
2610
void
2611
h8300_swap_out_of_er6 (rtx addr)
2612
{
2613
  if (REGNO (addr) != SP_REG)
2614
    emit_move_insn (addr, hard_frame_pointer_rtx);
2615
  pop (HARD_FRAME_POINTER_REGNUM);
2616
}
2617
 
2618
/* Return the length of mov instruction.  */
2619
 
2620
unsigned int
2621
compute_mov_length (rtx *operands)
2622
{
2623
  /* If the mov instruction involves a memory operand, we compute the
2624
     length, assuming the largest addressing mode is used, and then
2625
     adjust later in the function.  Otherwise, we compute and return
2626
     the exact length in one step.  */
2627
  enum machine_mode mode = GET_MODE (operands[0]);
2628
  rtx dest = operands[0];
2629
  rtx src = operands[1];
2630
  rtx addr;
2631
 
2632
  if (GET_CODE (src) == MEM)
2633
    addr = XEXP (src, 0);
2634
  else if (GET_CODE (dest) == MEM)
2635
    addr = XEXP (dest, 0);
2636
  else
2637
    addr = NULL_RTX;
2638
 
2639
  if (TARGET_H8300)
2640
    {
2641
      unsigned int base_length;
2642
 
2643
      switch (mode)
2644
        {
2645
        case QImode:
2646
          if (addr == NULL_RTX)
2647
            return 2;
2648
 
2649
          /* The eightbit addressing is available only in QImode, so
2650
             go ahead and take care of it.  */
2651
          if (h8300_eightbit_constant_address_p (addr))
2652
            return 2;
2653
 
2654
          base_length = 4;
2655
          break;
2656
 
2657
        case HImode:
2658
          if (addr == NULL_RTX)
2659
            {
2660
              if (REG_P (src))
2661
                return 2;
2662
 
2663
              if (src == const0_rtx)
2664
                return 2;
2665
 
2666
              return 4;
2667
            }
2668
 
2669
          base_length = 4;
2670
          break;
2671
 
2672
        case SImode:
2673
          if (addr == NULL_RTX)
2674
            {
2675
              if (REG_P (src))
2676
                return 4;
2677
 
2678
              if (GET_CODE (src) == CONST_INT)
2679
                {
2680
                  if (src == const0_rtx)
2681
                    return 4;
2682
 
2683
                  if ((INTVAL (src) & 0xffff) == 0)
2684
                    return 6;
2685
 
2686
                  if ((INTVAL (src) & 0xffff) == 0)
2687
                    return 6;
2688
 
2689
                  if ((INTVAL (src) & 0xffff)
2690
                      == ((INTVAL (src) >> 16) & 0xffff))
2691
                    return 6;
2692
                }
2693
              return 8;
2694
            }
2695
 
2696
          base_length = 8;
2697
          break;
2698
 
2699
        case SFmode:
2700
          if (addr == NULL_RTX)
2701
            {
2702
              if (REG_P (src))
2703
                return 4;
2704
 
2705
              if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2706
                return 4;
2707
 
2708
              return 8;
2709
            }
2710
 
2711
          base_length = 8;
2712
          break;
2713
 
2714
        default:
2715
          gcc_unreachable ();
2716
        }
2717
 
2718
      /* Adjust the length based on the addressing mode used.
2719
         Specifically, we subtract the difference between the actual
2720
         length and the longest one, which is @(d:16,Rs).  For SImode
2721
         and SFmode, we double the adjustment because two mov.w are
2722
         used to do the job.  */
2723
 
2724
      /* @Rs+ and @-Rd are 2 bytes shorter than the longest.  */
2725
      if (GET_CODE (addr) == PRE_DEC
2726
          || GET_CODE (addr) == POST_INC)
2727
        {
2728
          if (mode == QImode || mode == HImode)
2729
            return base_length - 2;
2730
          else
2731
            /* In SImode and SFmode, we use two mov.w instructions, so
2732
               double the adjustment.  */
2733
            return base_length - 4;
2734
        }
2735
 
2736
      /* @Rs and @Rd are 2 bytes shorter than the longest.  Note that
2737
         in SImode and SFmode, the second mov.w involves an address
2738
         with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2739
         only 2 bytes.  */
2740
      if (GET_CODE (addr) == REG)
2741
        return base_length - 2;
2742
 
2743
      return base_length;
2744
    }
2745
  else
2746
    {
2747
      unsigned int base_length;
2748
 
2749
      switch (mode)
2750
        {
2751
        case QImode:
2752
          if (addr == NULL_RTX)
2753
            return 2;
2754
 
2755
          /* The eightbit addressing is available only in QImode, so
2756
             go ahead and take care of it.  */
2757
          if (h8300_eightbit_constant_address_p (addr))
2758
            return 2;
2759
 
2760
          base_length = 8;
2761
          break;
2762
 
2763
        case HImode:
2764
          if (addr == NULL_RTX)
2765
            {
2766
              if (REG_P (src))
2767
                return 2;
2768
 
2769
              if (src == const0_rtx)
2770
                return 2;
2771
 
2772
              return 4;
2773
            }
2774
 
2775
          base_length = 8;
2776
          break;
2777
 
2778
        case SImode:
2779
          if (addr == NULL_RTX)
2780
            {
2781
              if (REG_P (src))
2782
                {
2783
                  if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2784
                    return 4;
2785
                  else
2786
                    return 2;
2787
                }
2788
 
2789
              if (GET_CODE (src) == CONST_INT)
2790
                {
2791
                  int val = INTVAL (src);
2792
 
2793
                  if (val == 0)
2794
                    return 2;
2795
 
2796
                  if (val == (val & 0x00ff) || val == (val & 0xff00))
2797
                    return 4;
2798
 
2799
                  switch (val & 0xffffffff)
2800
                    {
2801
                    case 0xffffffff:
2802
                    case 0xfffffffe:
2803
                    case 0xfffffffc:
2804
                    case 0x0000ffff:
2805
                    case 0x0000fffe:
2806
                    case 0xffff0000:
2807
                    case 0xfffe0000:
2808
                    case 0x00010000:
2809
                    case 0x00020000:
2810
                      return 4;
2811
                    }
2812
                }
2813
              return 6;
2814
            }
2815
 
2816
          base_length = 10;
2817
          break;
2818
 
2819
        case SFmode:
2820
          if (addr == NULL_RTX)
2821
            {
2822
              if (REG_P (src))
2823
                return 2;
2824
 
2825
              if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2826
                return 2;
2827
 
2828
              return 6;
2829
            }
2830
 
2831
          base_length = 10;
2832
          break;
2833
 
2834
        default:
2835
          gcc_unreachable ();
2836
        }
2837
 
2838
      /* Adjust the length based on the addressing mode used.
2839
         Specifically, we subtract the difference between the actual
2840
         length and the longest one, which is @(d:24,ERs).  */
2841
 
2842
      /* @ERs+ and @-ERd are 6 bytes shorter than the longest.  */
2843
      if (GET_CODE (addr) == PRE_DEC
2844
          || GET_CODE (addr) == POST_INC)
2845
        return base_length - 6;
2846
 
2847
      /* @ERs and @ERd are 6 bytes shorter than the longest.  */
2848
      if (GET_CODE (addr) == REG)
2849
        return base_length - 6;
2850
 
2851
      /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2852
         longest.  */
2853
      if (GET_CODE (addr) == PLUS
2854
          && GET_CODE (XEXP (addr, 0)) == REG
2855
          && GET_CODE (XEXP (addr, 1)) == CONST_INT
2856
          && INTVAL (XEXP (addr, 1)) > -32768
2857
          && INTVAL (XEXP (addr, 1)) < 32767)
2858
        return base_length - 4;
2859
 
2860
      /* @aa:16 is 4 bytes shorter than the longest.  */
2861
      if (h8300_tiny_constant_address_p (addr))
2862
        return base_length - 4;
2863
 
2864
      /* @aa:24 is 2 bytes shorter than the longest.  */
2865
      if (CONSTANT_P (addr))
2866
        return base_length - 2;
2867
 
2868
      return base_length;
2869
    }
2870
}
2871
 
2872
/* Output an addition insn.  */
2873
 
2874
const char *
2875
output_plussi (rtx *operands)
2876
{
2877
  enum machine_mode mode = GET_MODE (operands[0]);
2878
 
2879
  gcc_assert (mode == SImode);
2880
 
2881
  if (TARGET_H8300)
2882
    {
2883
      if (GET_CODE (operands[2]) == REG)
2884
        return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2885
 
2886
      if (GET_CODE (operands[2]) == CONST_INT)
2887
        {
2888
          HOST_WIDE_INT n = INTVAL (operands[2]);
2889
 
2890
          if ((n & 0xffffff) == 0)
2891
            return "add\t%z2,%z0";
2892
          if ((n & 0xffff) == 0)
2893
            return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2894
          if ((n & 0xff) == 0)
2895
            return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2896
        }
2897
 
2898
      return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2899
    }
2900
  else
2901
    {
2902
      if (GET_CODE (operands[2]) == CONST_INT
2903
          && register_operand (operands[1], VOIDmode))
2904
        {
2905
          HOST_WIDE_INT intval = INTVAL (operands[2]);
2906
 
2907
          if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2908
            return "add.l\t%S2,%S0";
2909
          if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2910
            return "sub.l\t%G2,%S0";
2911
 
2912
          /* See if we can finish with 2 bytes.  */
2913
 
2914
          switch ((unsigned int) intval & 0xffffffff)
2915
            {
2916
            case 0x00000001:
2917
            case 0x00000002:
2918
            case 0x00000004:
2919
              return "adds\t%2,%S0";
2920
 
2921
            case 0xffffffff:
2922
            case 0xfffffffe:
2923
            case 0xfffffffc:
2924
              return "subs\t%G2,%S0";
2925
 
2926
            case 0x00010000:
2927
            case 0x00020000:
2928
              operands[2] = GEN_INT (intval >> 16);
2929
              return "inc.w\t%2,%e0";
2930
 
2931
            case 0xffff0000:
2932
            case 0xfffe0000:
2933
              operands[2] = GEN_INT (intval >> 16);
2934
              return "dec.w\t%G2,%e0";
2935
            }
2936
 
2937
          /* See if we can finish with 4 bytes.  */
2938
          if ((intval & 0xffff) == 0)
2939
            {
2940
              operands[2] = GEN_INT (intval >> 16);
2941
              return "add.w\t%2,%e0";
2942
            }
2943
        }
2944
 
2945
      if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
2946
        {
2947
          operands[2] = GEN_INT (-INTVAL (operands[2]));
2948
          return "sub.l\t%S2,%S0";
2949
        }
2950
      return "add.l\t%S2,%S0";
2951
    }
2952
}
2953
 
2954
/* ??? It would be much easier to add the h8sx stuff if a single function
2955
   classified the addition as either inc/dec, adds/subs, add.w or add.l.  */
2956
/* Compute the length of an addition insn.  */
2957
 
2958
unsigned int
2959
compute_plussi_length (rtx *operands)
2960
{
2961
  enum machine_mode mode = GET_MODE (operands[0]);
2962
 
2963
  gcc_assert (mode == SImode);
2964
 
2965
  if (TARGET_H8300)
2966
    {
2967
      if (GET_CODE (operands[2]) == REG)
2968
        return 6;
2969
 
2970
      if (GET_CODE (operands[2]) == CONST_INT)
2971
        {
2972
          HOST_WIDE_INT n = INTVAL (operands[2]);
2973
 
2974
          if ((n & 0xffffff) == 0)
2975
            return 2;
2976
          if ((n & 0xffff) == 0)
2977
            return 4;
2978
          if ((n & 0xff) == 0)
2979
            return 6;
2980
        }
2981
 
2982
      return 8;
2983
    }
2984
  else
2985
    {
2986
      if (GET_CODE (operands[2]) == CONST_INT
2987
          && register_operand (operands[1], VOIDmode))
2988
        {
2989
          HOST_WIDE_INT intval = INTVAL (operands[2]);
2990
 
2991
          if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2992
            return 2;
2993
          if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2994
            return 2;
2995
 
2996
          /* See if we can finish with 2 bytes.  */
2997
 
2998
          switch ((unsigned int) intval & 0xffffffff)
2999
            {
3000
            case 0x00000001:
3001
            case 0x00000002:
3002
            case 0x00000004:
3003
              return 2;
3004
 
3005
            case 0xffffffff:
3006
            case 0xfffffffe:
3007
            case 0xfffffffc:
3008
              return 2;
3009
 
3010
            case 0x00010000:
3011
            case 0x00020000:
3012
              return 2;
3013
 
3014
            case 0xffff0000:
3015
            case 0xfffe0000:
3016
              return 2;
3017
            }
3018
 
3019
          /* See if we can finish with 4 bytes.  */
3020
          if ((intval & 0xffff) == 0)
3021
            return 4;
3022
        }
3023
 
3024
      if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3025
        return h8300_length_from_table (operands[0],
3026
                                        GEN_INT (-INTVAL (operands[2])),
3027
                                        &addl_length_table);
3028
      else
3029
        return h8300_length_from_table (operands[0], operands[2],
3030
                                        &addl_length_table);
3031
      return 6;
3032
    }
3033
}
3034
 
3035
/* Compute which flag bits are valid after an addition insn.  */
3036
 
3037
int
3038
compute_plussi_cc (rtx *operands)
3039
{
3040
  enum machine_mode mode = GET_MODE (operands[0]);
3041
 
3042
  gcc_assert (mode == SImode);
3043
 
3044
  if (TARGET_H8300)
3045
    {
3046
      return CC_CLOBBER;
3047
    }
3048
  else
3049
    {
3050
      if (GET_CODE (operands[2]) == CONST_INT
3051
          && register_operand (operands[1], VOIDmode))
3052
        {
3053
          HOST_WIDE_INT intval = INTVAL (operands[2]);
3054
 
3055
          if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3056
            return CC_SET_ZN;
3057
          if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3058
            return CC_SET_ZN;
3059
 
3060
          /* See if we can finish with 2 bytes.  */
3061
 
3062
          switch ((unsigned int) intval & 0xffffffff)
3063
            {
3064
            case 0x00000001:
3065
            case 0x00000002:
3066
            case 0x00000004:
3067
              return CC_NONE_0HIT;
3068
 
3069
            case 0xffffffff:
3070
            case 0xfffffffe:
3071
            case 0xfffffffc:
3072
              return CC_NONE_0HIT;
3073
 
3074
            case 0x00010000:
3075
            case 0x00020000:
3076
              return CC_CLOBBER;
3077
 
3078
            case 0xffff0000:
3079
            case 0xfffe0000:
3080
              return CC_CLOBBER;
3081
            }
3082
 
3083
          /* See if we can finish with 4 bytes.  */
3084
          if ((intval & 0xffff) == 0)
3085
            return CC_CLOBBER;
3086
        }
3087
 
3088
      return CC_SET_ZN;
3089
    }
3090
}
3091
 
3092
/* Output a logical insn.  */
3093
 
3094
const char *
3095
output_logical_op (enum machine_mode mode, rtx *operands)
3096
{
3097
  /* Figure out the logical op that we need to perform.  */
3098
  enum rtx_code code = GET_CODE (operands[3]);
3099
  /* Pretend that every byte is affected if both operands are registers.  */
3100
  const unsigned HOST_WIDE_INT intval =
3101
    (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3102
                              /* Always use the full instruction if the
3103
                                 first operand is in memory.  It is better
3104
                                 to use define_splits to generate the shorter
3105
                                 sequence where valid.  */
3106
                              && register_operand (operands[1], VOIDmode)
3107
                              ? INTVAL (operands[2]) : 0x55555555);
3108
  /* The determinant of the algorithm.  If we perform an AND, 0
3109
     affects a bit.  Otherwise, 1 affects a bit.  */
3110
  const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3111
  /* Break up DET into pieces.  */
3112
  const unsigned HOST_WIDE_INT b0 = (det >>  0) & 0xff;
3113
  const unsigned HOST_WIDE_INT b1 = (det >>  8) & 0xff;
3114
  const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3115
  const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3116
  const unsigned HOST_WIDE_INT w0 = (det >>  0) & 0xffff;
3117
  const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3118
  int lower_half_easy_p = 0;
3119
  int upper_half_easy_p = 0;
3120
  /* The name of an insn.  */
3121
  const char *opname;
3122
  char insn_buf[100];
3123
 
3124
  switch (code)
3125
    {
3126
    case AND:
3127
      opname = "and";
3128
      break;
3129
    case IOR:
3130
      opname = "or";
3131
      break;
3132
    case XOR:
3133
      opname = "xor";
3134
      break;
3135
    default:
3136
      gcc_unreachable ();
3137
    }
3138
 
3139
  switch (mode)
3140
    {
3141
    case HImode:
3142
      /* First, see if we can finish with one insn.  */
3143
      if ((TARGET_H8300H || TARGET_H8300S)
3144
          && b0 != 0
3145
          && b1 != 0)
3146
        {
3147
          sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3148
          output_asm_insn (insn_buf, operands);
3149
        }
3150
      else
3151
        {
3152
          /* Take care of the lower byte.  */
3153
          if (b0 != 0)
3154
            {
3155
              sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3156
              output_asm_insn (insn_buf, operands);
3157
            }
3158
          /* Take care of the upper byte.  */
3159
          if (b1 != 0)
3160
            {
3161
              sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3162
              output_asm_insn (insn_buf, operands);
3163
            }
3164
        }
3165
      break;
3166
    case SImode:
3167
      if (TARGET_H8300H || TARGET_H8300S)
3168
        {
3169
          /* Determine if the lower half can be taken care of in no more
3170
             than two bytes.  */
3171
          lower_half_easy_p = (b0 == 0
3172
                               || b1 == 0
3173
                               || (code != IOR && w0 == 0xffff));
3174
 
3175
          /* Determine if the upper half can be taken care of in no more
3176
             than two bytes.  */
3177
          upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3178
                               || (code == AND && w1 == 0xff00));
3179
        }
3180
 
3181
      /* Check if doing everything with one insn is no worse than
3182
         using multiple insns.  */
3183
      if ((TARGET_H8300H || TARGET_H8300S)
3184
          && w0 != 0 && w1 != 0
3185
          && !(lower_half_easy_p && upper_half_easy_p)
3186
          && !(code == IOR && w1 == 0xffff
3187
               && (w0 & 0x8000) != 0 && lower_half_easy_p))
3188
        {
3189
          sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3190
          output_asm_insn (insn_buf, operands);
3191
        }
3192
      else
3193
        {
3194
          /* Take care of the lower and upper words individually.  For
3195
             each word, we try different methods in the order of
3196
 
3197
             1) the special insn (in case of AND or XOR),
3198
             2) the word-wise insn, and
3199
             3) The byte-wise insn.  */
3200
          if (w0 == 0xffff
3201
              && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3202
            output_asm_insn ((code == AND)
3203
                             ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3204
                             operands);
3205
          else if ((TARGET_H8300H || TARGET_H8300S)
3206
                   && (b0 != 0)
3207
                   && (b1 != 0))
3208
            {
3209
              sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3210
              output_asm_insn (insn_buf, operands);
3211
            }
3212
          else
3213
            {
3214
              if (b0 != 0)
3215
                {
3216
                  sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3217
                  output_asm_insn (insn_buf, operands);
3218
                }
3219
              if (b1 != 0)
3220
                {
3221
                  sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3222
                  output_asm_insn (insn_buf, operands);
3223
                }
3224
            }
3225
 
3226
          if ((w1 == 0xffff)
3227
              && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3228
            output_asm_insn ((code == AND)
3229
                             ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3230
                             operands);
3231
          else if ((TARGET_H8300H || TARGET_H8300S)
3232
                   && code == IOR
3233
                   && w1 == 0xffff
3234
                   && (w0 & 0x8000) != 0)
3235
            {
3236
              output_asm_insn ("exts.l\t%S0", operands);
3237
            }
3238
          else if ((TARGET_H8300H || TARGET_H8300S)
3239
                   && code == AND
3240
                   && w1 == 0xff00)
3241
            {
3242
              output_asm_insn ("extu.w\t%e0", operands);
3243
            }
3244
          else if (TARGET_H8300H || TARGET_H8300S)
3245
            {
3246
              if (w1 != 0)
3247
                {
3248
                  sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3249
                  output_asm_insn (insn_buf, operands);
3250
                }
3251
            }
3252
          else
3253
            {
3254
              if (b2 != 0)
3255
                {
3256
                  sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3257
                  output_asm_insn (insn_buf, operands);
3258
                }
3259
              if (b3 != 0)
3260
                {
3261
                  sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3262
                  output_asm_insn (insn_buf, operands);
3263
                }
3264
            }
3265
        }
3266
      break;
3267
    default:
3268
      gcc_unreachable ();
3269
    }
3270
  return "";
3271
}
3272
 
3273
/* Compute the length of a logical insn.  */
3274
 
3275
unsigned int
3276
compute_logical_op_length (enum machine_mode mode, rtx *operands)
3277
{
3278
  /* Figure out the logical op that we need to perform.  */
3279
  enum rtx_code code = GET_CODE (operands[3]);
3280
  /* Pretend that every byte is affected if both operands are registers.  */
3281
  const unsigned HOST_WIDE_INT intval =
3282
    (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3283
                              /* Always use the full instruction if the
3284
                                 first operand is in memory.  It is better
3285
                                 to use define_splits to generate the shorter
3286
                                 sequence where valid.  */
3287
                              && register_operand (operands[1], VOIDmode)
3288
                              ? INTVAL (operands[2]) : 0x55555555);
3289
  /* The determinant of the algorithm.  If we perform an AND, 0
3290
     affects a bit.  Otherwise, 1 affects a bit.  */
3291
  const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3292
  /* Break up DET into pieces.  */
3293
  const unsigned HOST_WIDE_INT b0 = (det >>  0) & 0xff;
3294
  const unsigned HOST_WIDE_INT b1 = (det >>  8) & 0xff;
3295
  const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3296
  const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3297
  const unsigned HOST_WIDE_INT w0 = (det >>  0) & 0xffff;
3298
  const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3299
  int lower_half_easy_p = 0;
3300
  int upper_half_easy_p = 0;
3301
  /* Insn length.  */
3302
  unsigned int length = 0;
3303
 
3304
  switch (mode)
3305
    {
3306
    case HImode:
3307
      /* First, see if we can finish with one insn.  */
3308
      if ((TARGET_H8300H || TARGET_H8300S)
3309
          && b0 != 0
3310
          && b1 != 0)
3311
        {
3312
          length = h8300_length_from_table (operands[1], operands[2],
3313
                                            &logicw_length_table);
3314
        }
3315
      else
3316
        {
3317
          /* Take care of the lower byte.  */
3318
          if (b0 != 0)
3319
            length += 2;
3320
 
3321
          /* Take care of the upper byte.  */
3322
          if (b1 != 0)
3323
            length += 2;
3324
        }
3325
      break;
3326
    case SImode:
3327
      if (TARGET_H8300H || TARGET_H8300S)
3328
        {
3329
          /* Determine if the lower half can be taken care of in no more
3330
             than two bytes.  */
3331
          lower_half_easy_p = (b0 == 0
3332
                               || b1 == 0
3333
                               || (code != IOR && w0 == 0xffff));
3334
 
3335
          /* Determine if the upper half can be taken care of in no more
3336
             than two bytes.  */
3337
          upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3338
                               || (code == AND && w1 == 0xff00));
3339
        }
3340
 
3341
      /* Check if doing everything with one insn is no worse than
3342
         using multiple insns.  */
3343
      if ((TARGET_H8300H || TARGET_H8300S)
3344
          && w0 != 0 && w1 != 0
3345
          && !(lower_half_easy_p && upper_half_easy_p)
3346
          && !(code == IOR && w1 == 0xffff
3347
               && (w0 & 0x8000) != 0 && lower_half_easy_p))
3348
        {
3349
          length = h8300_length_from_table (operands[1], operands[2],
3350
                                            &logicl_length_table);
3351
        }
3352
      else
3353
        {
3354
          /* Take care of the lower and upper words individually.  For
3355
             each word, we try different methods in the order of
3356
 
3357
             1) the special insn (in case of AND or XOR),
3358
             2) the word-wise insn, and
3359
             3) The byte-wise insn.  */
3360
          if (w0 == 0xffff
3361
              && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3362
            {
3363
              length += 2;
3364
            }
3365
          else if ((TARGET_H8300H || TARGET_H8300S)
3366
                   && (b0 != 0)
3367
                   && (b1 != 0))
3368
            {
3369
              length += 4;
3370
            }
3371
          else
3372
            {
3373
              if (b0 != 0)
3374
                length += 2;
3375
 
3376
              if (b1 != 0)
3377
                length += 2;
3378
            }
3379
 
3380
          if (w1 == 0xffff
3381
              && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3382
            {
3383
              length += 2;
3384
            }
3385
          else if ((TARGET_H8300H || TARGET_H8300S)
3386
                   && code == IOR
3387
                   && w1 == 0xffff
3388
                   && (w0 & 0x8000) != 0)
3389
            {
3390
              length += 2;
3391
            }
3392
          else if ((TARGET_H8300H || TARGET_H8300S)
3393
                   && code == AND
3394
                   && w1 == 0xff00)
3395
            {
3396
              length += 2;
3397
            }
3398
          else if (TARGET_H8300H || TARGET_H8300S)
3399
            {
3400
              if (w1 != 0)
3401
                length += 4;
3402
            }
3403
          else
3404
            {
3405
              if (b2 != 0)
3406
                length += 2;
3407
 
3408
              if (b3 != 0)
3409
                length += 2;
3410
            }
3411
        }
3412
      break;
3413
    default:
3414
      gcc_unreachable ();
3415
    }
3416
  return length;
3417
}
3418
 
3419
/* Compute which flag bits are valid after a logical insn.  */
3420
 
3421
int
3422
compute_logical_op_cc (enum machine_mode mode, rtx *operands)
3423
{
3424
  /* Figure out the logical op that we need to perform.  */
3425
  enum rtx_code code = GET_CODE (operands[3]);
3426
  /* Pretend that every byte is affected if both operands are registers.  */
3427
  const unsigned HOST_WIDE_INT intval =
3428
    (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3429
                              /* Always use the full instruction if the
3430
                                 first operand is in memory.  It is better
3431
                                 to use define_splits to generate the shorter
3432
                                 sequence where valid.  */
3433
                              && register_operand (operands[1], VOIDmode)
3434
                              ? INTVAL (operands[2]) : 0x55555555);
3435
  /* The determinant of the algorithm.  If we perform an AND, 0
3436
     affects a bit.  Otherwise, 1 affects a bit.  */
3437
  const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3438
  /* Break up DET into pieces.  */
3439
  const unsigned HOST_WIDE_INT b0 = (det >>  0) & 0xff;
3440
  const unsigned HOST_WIDE_INT b1 = (det >>  8) & 0xff;
3441
  const unsigned HOST_WIDE_INT w0 = (det >>  0) & 0xffff;
3442
  const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3443
  int lower_half_easy_p = 0;
3444
  int upper_half_easy_p = 0;
3445
  /* Condition code.  */
3446
  enum attr_cc cc = CC_CLOBBER;
3447
 
3448
  switch (mode)
3449
    {
3450
    case HImode:
3451
      /* First, see if we can finish with one insn.  */
3452
      if ((TARGET_H8300H || TARGET_H8300S)
3453
          && b0 != 0
3454
          && b1 != 0)
3455
        {
3456
          cc = CC_SET_ZNV;
3457
        }
3458
      break;
3459
    case SImode:
3460
      if (TARGET_H8300H || TARGET_H8300S)
3461
        {
3462
          /* Determine if the lower half can be taken care of in no more
3463
             than two bytes.  */
3464
          lower_half_easy_p = (b0 == 0
3465
                               || b1 == 0
3466
                               || (code != IOR && w0 == 0xffff));
3467
 
3468
          /* Determine if the upper half can be taken care of in no more
3469
             than two bytes.  */
3470
          upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3471
                               || (code == AND && w1 == 0xff00));
3472
        }
3473
 
3474
      /* Check if doing everything with one insn is no worse than
3475
         using multiple insns.  */
3476
      if ((TARGET_H8300H || TARGET_H8300S)
3477
          && w0 != 0 && w1 != 0
3478
          && !(lower_half_easy_p && upper_half_easy_p)
3479
          && !(code == IOR && w1 == 0xffff
3480
               && (w0 & 0x8000) != 0 && lower_half_easy_p))
3481
        {
3482
          cc = CC_SET_ZNV;
3483
        }
3484
      else
3485
        {
3486
          if ((TARGET_H8300H || TARGET_H8300S)
3487
              && code == IOR
3488
              && w1 == 0xffff
3489
              && (w0 & 0x8000) != 0)
3490
            {
3491
              cc = CC_SET_ZNV;
3492
            }
3493
        }
3494
      break;
3495
    default:
3496
      gcc_unreachable ();
3497
    }
3498
  return cc;
3499
}
3500
 
3501
/* Expand a conditional branch.  */
3502
 
3503
void
3504
h8300_expand_branch (enum rtx_code code, rtx label)
3505
{
3506
  rtx tmp;
3507
 
3508
  tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3509
  tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3510
                              gen_rtx_LABEL_REF (VOIDmode, label),
3511
                              pc_rtx);
3512
  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3513
}
3514
 
3515
/* Shifts.
3516
 
3517
   We devote a fair bit of code to getting efficient shifts since we
3518
   can only shift one bit at a time on the H8/300 and H8/300H and only
3519
   one or two bits at a time on the H8S.
3520
 
3521
   All shift code falls into one of the following ways of
3522
   implementation:
3523
 
3524
   o SHIFT_INLINE: Emit straight line code for the shift; this is used
3525
     when a straight line shift is about the same size or smaller than
3526
     a loop.
3527
 
3528
   o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3529
     off the bits we don't need.  This is used when only a few of the
3530
     bits in the original value will survive in the shifted value.
3531
 
3532
   o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3533
     simulate a shift by 8, 16, or 24 bits.  Once moved, a few inline
3534
     shifts can be added if the shift count is slightly more than 8 or
3535
     16.  This case also includes other oddballs that are not worth
3536
     explaining here.
3537
 
3538
   o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3539
 
3540
   For each shift count, we try to use code that has no trade-off
3541
   between code size and speed whenever possible.
3542
 
3543
   If the trade-off is unavoidable, we try to be reasonable.
3544
   Specifically, the fastest version is one instruction longer than
3545
   the shortest version, we take the fastest version.  We also provide
3546
   the use a way to switch back to the shortest version with -Os.
3547
 
3548
   For the details of the shift algorithms for various shift counts,
3549
   refer to shift_alg_[qhs]i.  */
3550
 
3551
/* Classify a shift with the given mode and code.  OP is the shift amount.  */
3552
 
3553
enum h8sx_shift_type
3554
h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3555
{
3556
  if (!TARGET_H8300SX)
3557
    return H8SX_SHIFT_NONE;
3558
 
3559
  switch (code)
3560
    {
3561
    case ASHIFT:
3562
    case LSHIFTRT:
3563
      /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd).  */
3564
      if (GET_CODE (op) != CONST_INT)
3565
        return H8SX_SHIFT_BINARY;
3566
 
3567
      /* Reject out-of-range shift amounts.  */
3568
      if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3569
        return H8SX_SHIFT_NONE;
3570
 
3571
      /* Power-of-2 shifts are effectively unary operations.  */
3572
      if (exact_log2 (INTVAL (op)) >= 0)
3573
        return H8SX_SHIFT_UNARY;
3574
 
3575
      return H8SX_SHIFT_BINARY;
3576
 
3577
    case ASHIFTRT:
3578
      if (op == const1_rtx || op == const2_rtx)
3579
        return H8SX_SHIFT_UNARY;
3580
      return H8SX_SHIFT_NONE;
3581
 
3582
    case ROTATE:
3583
      if (GET_CODE (op) == CONST_INT
3584
          && (INTVAL (op) == 1
3585
              || INTVAL (op) == 2
3586
              || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3587
              || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3588
        return H8SX_SHIFT_UNARY;
3589
      return H8SX_SHIFT_NONE;
3590
 
3591
    default:
3592
      return H8SX_SHIFT_NONE;
3593
    }
3594
}
3595
 
3596
/* Return the asm template for a single h8sx shift instruction.
3597
   OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3598
   is the source and OPERANDS[3] is the shift.  SUFFIX is the
3599
   size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3600
   prefix for the destination operand.  */
3601
 
3602
const char *
3603
output_h8sx_shift (rtx *operands, int suffix, int optype)
3604
{
3605
  static char buffer[16];
3606
  const char *stem;
3607
 
3608
  switch (GET_CODE (operands[3]))
3609
    {
3610
    case ASHIFT:
3611
      stem = "shll";
3612
      break;
3613
 
3614
    case ASHIFTRT:
3615
      stem = "shar";
3616
      break;
3617
 
3618
    case LSHIFTRT:
3619
      stem = "shlr";
3620
      break;
3621
 
3622
    case ROTATE:
3623
      stem = "rotl";
3624
      if (INTVAL (operands[2]) > 2)
3625
        {
3626
          /* This is really a right rotate.  */
3627
          operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3628
                                 - INTVAL (operands[2]));
3629
          stem = "rotr";
3630
        }
3631
      break;
3632
 
3633
    default:
3634
      gcc_unreachable ();
3635
    }
3636
  if (operands[2] == const1_rtx)
3637
    sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3638
  else
3639
    sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3640
  return buffer;
3641
}
3642
 
3643
/* Emit code to do shifts.  */
3644
 
3645
bool
3646
expand_a_shift (enum machine_mode mode, int code, rtx operands[])
3647
{
3648
  switch (h8sx_classify_shift (mode, code, operands[2]))
3649
    {
3650
    case H8SX_SHIFT_BINARY:
3651
      operands[1] = force_reg (mode, operands[1]);
3652
      return false;
3653
 
3654
    case H8SX_SHIFT_UNARY:
3655
      return false;
3656
 
3657
    case H8SX_SHIFT_NONE:
3658
      break;
3659
    }
3660
 
3661
  emit_move_insn (operands[0], operands[1]);
3662
 
3663
  /* Need a loop to get all the bits we want  - we generate the
3664
     code at emit time, but need to allocate a scratch reg now.  */
3665
 
3666
  emit_insn (gen_rtx_PARALLEL
3667
             (VOIDmode,
3668
              gen_rtvec (2,
3669
                         gen_rtx_SET (VOIDmode, operands[0],
3670
                                      gen_rtx_fmt_ee (code, mode,
3671
                                                      operands[0], operands[2])),
3672
                         gen_rtx_CLOBBER (VOIDmode,
3673
                                          gen_rtx_SCRATCH (QImode)))));
3674
  return true;
3675
}
3676
 
3677
/* Symbols of the various modes which can be used as indices.  */
3678
 
3679
enum shift_mode
3680
{
3681
  QIshift, HIshift, SIshift
3682
};
3683
 
3684
/* For single bit shift insns, record assembler and what bits of the
3685
   condition code are valid afterwards (represented as various CC_FOO
3686
   bits, 0 means CC isn't left in a usable state).  */
3687
 
3688
struct shift_insn
3689
{
3690
  const char *const assembler;
3691
  const int cc_valid;
3692
};
3693
 
3694
/* Assembler instruction shift table.
3695
 
3696
   These tables are used to look up the basic shifts.
3697
   They are indexed by cpu, shift_type, and mode.  */
3698
 
3699
static const struct shift_insn shift_one[2][3][3] =
3700
{
3701
/* H8/300 */
3702
  {
3703
/* SHIFT_ASHIFT */
3704
    {
3705
      { "shll\t%X0", CC_SET_ZNV },
3706
      { "add.w\t%T0,%T0", CC_SET_ZN },
3707
      { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3708
    },
3709
/* SHIFT_LSHIFTRT */
3710
    {
3711
      { "shlr\t%X0", CC_SET_ZNV },
3712
      { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3713
      { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3714
    },
3715
/* SHIFT_ASHIFTRT */
3716
    {
3717
      { "shar\t%X0", CC_SET_ZNV },
3718
      { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3719
      { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3720
    }
3721
  },
3722
/* H8/300H */
3723
  {
3724
/* SHIFT_ASHIFT */
3725
    {
3726
      { "shll.b\t%X0", CC_SET_ZNV },
3727
      { "shll.w\t%T0", CC_SET_ZNV },
3728
      { "shll.l\t%S0", CC_SET_ZNV }
3729
    },
3730
/* SHIFT_LSHIFTRT */
3731
    {
3732
      { "shlr.b\t%X0", CC_SET_ZNV },
3733
      { "shlr.w\t%T0", CC_SET_ZNV },
3734
      { "shlr.l\t%S0", CC_SET_ZNV }
3735
    },
3736
/* SHIFT_ASHIFTRT */
3737
    {
3738
      { "shar.b\t%X0", CC_SET_ZNV },
3739
      { "shar.w\t%T0", CC_SET_ZNV },
3740
      { "shar.l\t%S0", CC_SET_ZNV }
3741
    }
3742
  }
3743
};
3744
 
3745
static const struct shift_insn shift_two[3][3] =
3746
{
3747
/* SHIFT_ASHIFT */
3748
    {
3749
      { "shll.b\t#2,%X0", CC_SET_ZNV },
3750
      { "shll.w\t#2,%T0", CC_SET_ZNV },
3751
      { "shll.l\t#2,%S0", CC_SET_ZNV }
3752
    },
3753
/* SHIFT_LSHIFTRT */
3754
    {
3755
      { "shlr.b\t#2,%X0", CC_SET_ZNV },
3756
      { "shlr.w\t#2,%T0", CC_SET_ZNV },
3757
      { "shlr.l\t#2,%S0", CC_SET_ZNV }
3758
    },
3759
/* SHIFT_ASHIFTRT */
3760
    {
3761
      { "shar.b\t#2,%X0", CC_SET_ZNV },
3762
      { "shar.w\t#2,%T0", CC_SET_ZNV },
3763
      { "shar.l\t#2,%S0", CC_SET_ZNV }
3764
    }
3765
};
3766
 
3767
/* Rotates are organized by which shift they'll be used in implementing.
3768
   There's no need to record whether the cc is valid afterwards because
3769
   it is the AND insn that will decide this.  */
3770
 
3771
static const char *const rotate_one[2][3][3] =
3772
{
3773
/* H8/300 */
3774
  {
3775
/* SHIFT_ASHIFT */
3776
    {
3777
      "rotr\t%X0",
3778
      "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3779
 
3780
    },
3781
/* SHIFT_LSHIFTRT */
3782
    {
3783
      "rotl\t%X0",
3784
      "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3785
 
3786
    },
3787
/* SHIFT_ASHIFTRT */
3788
    {
3789
      "rotl\t%X0",
3790
      "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3791
 
3792
    }
3793
  },
3794
/* H8/300H */
3795
  {
3796
/* SHIFT_ASHIFT */
3797
    {
3798
      "rotr.b\t%X0",
3799
      "rotr.w\t%T0",
3800
      "rotr.l\t%S0"
3801
    },
3802
/* SHIFT_LSHIFTRT */
3803
    {
3804
      "rotl.b\t%X0",
3805
      "rotl.w\t%T0",
3806
      "rotl.l\t%S0"
3807
    },
3808
/* SHIFT_ASHIFTRT */
3809
    {
3810
      "rotl.b\t%X0",
3811
      "rotl.w\t%T0",
3812
      "rotl.l\t%S0"
3813
    }
3814
  }
3815
};
3816
 
3817
static const char *const rotate_two[3][3] =
3818
{
3819
/* SHIFT_ASHIFT */
3820
    {
3821
      "rotr.b\t#2,%X0",
3822
      "rotr.w\t#2,%T0",
3823
      "rotr.l\t#2,%S0"
3824
    },
3825
/* SHIFT_LSHIFTRT */
3826
    {
3827
      "rotl.b\t#2,%X0",
3828
      "rotl.w\t#2,%T0",
3829
      "rotl.l\t#2,%S0"
3830
    },
3831
/* SHIFT_ASHIFTRT */
3832
    {
3833
      "rotl.b\t#2,%X0",
3834
      "rotl.w\t#2,%T0",
3835
      "rotl.l\t#2,%S0"
3836
    }
3837
};
3838
 
3839
struct shift_info {
3840
  /* Shift algorithm.  */
3841
  enum shift_alg alg;
3842
 
3843
  /* The number of bits to be shifted by shift1 and shift2.  Valid
3844
     when ALG is SHIFT_SPECIAL.  */
3845
  unsigned int remainder;
3846
 
3847
  /* Special insn for a shift.  Valid when ALG is SHIFT_SPECIAL.  */
3848
  const char *special;
3849
 
3850
  /* Insn for a one-bit shift.  Valid when ALG is either SHIFT_INLINE
3851
     or SHIFT_SPECIAL, and REMAINDER is nonzero.  */
3852
  const char *shift1;
3853
 
3854
  /* Insn for a two-bit shift.  Valid when ALG is either SHIFT_INLINE
3855
     or SHIFT_SPECIAL, and REMAINDER is nonzero.  */
3856
  const char *shift2;
3857
 
3858
  /* CC status for SHIFT_INLINE.  */
3859
  int cc_inline;
3860
 
3861
  /* CC status  for SHIFT_SPECIAL.  */
3862
  int cc_special;
3863
};
3864
 
3865
static void get_shift_alg (enum shift_type,
3866
                           enum shift_mode, unsigned int,
3867
                           struct shift_info *);
3868
 
3869
/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3870
   best algorithm for doing the shift.  The assembler code is stored
3871
   in the pointers in INFO.  We achieve the maximum efficiency in most
3872
   cases when !TARGET_H8300.  In case of TARGET_H8300, shifts in
3873
   SImode in particular have a lot of room to optimize.
3874
 
3875
   We first determine the strategy of the shift algorithm by a table
3876
   lookup.  If that tells us to use a hand crafted assembly code, we
3877
   go into the big switch statement to find what that is.  Otherwise,
3878
   we resort to a generic way, such as inlining.  In either case, the
3879
   result is returned through INFO.  */
3880
 
3881
static void
3882
get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
3883
               unsigned int count, struct shift_info *info)
3884
{
3885
  enum h8_cpu cpu;
3886
 
3887
  /* Find the target CPU.  */
3888
  if (TARGET_H8300)
3889
    cpu = H8_300;
3890
  else if (TARGET_H8300H)
3891
    cpu = H8_300H;
3892
  else
3893
    cpu = H8_S;
3894
 
3895
  /* Find the shift algorithm.  */
3896
  info->alg = SHIFT_LOOP;
3897
  switch (shift_mode)
3898
    {
3899
    case QIshift:
3900
      if (count < GET_MODE_BITSIZE (QImode))
3901
        info->alg = shift_alg_qi[cpu][shift_type][count];
3902
      break;
3903
 
3904
    case HIshift:
3905
      if (count < GET_MODE_BITSIZE (HImode))
3906
        info->alg = shift_alg_hi[cpu][shift_type][count];
3907
      break;
3908
 
3909
    case SIshift:
3910
      if (count < GET_MODE_BITSIZE (SImode))
3911
        info->alg = shift_alg_si[cpu][shift_type][count];
3912
      break;
3913
 
3914
    default:
3915
      gcc_unreachable ();
3916
    }
3917
 
3918
  /* Fill in INFO.  Return unless we have SHIFT_SPECIAL.  */
3919
  switch (info->alg)
3920
    {
3921
    case SHIFT_INLINE:
3922
      info->remainder = count;
3923
      /* Fall through.  */
3924
 
3925
    case SHIFT_LOOP:
3926
      /* It is up to the caller to know that looping clobbers cc.  */
3927
      info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3928
      info->shift2 = shift_two[shift_type][shift_mode].assembler;
3929
      info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3930
      goto end;
3931
 
3932
    case SHIFT_ROT_AND:
3933
      info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
3934
      info->shift2 = rotate_two[shift_type][shift_mode];
3935
      info->cc_inline = CC_CLOBBER;
3936
      goto end;
3937
 
3938
    case SHIFT_SPECIAL:
3939
      /* REMAINDER is 0 for most cases, so initialize it to 0.  */
3940
      info->remainder = 0;
3941
      info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3942
      info->shift2 = shift_two[shift_type][shift_mode].assembler;
3943
      info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3944
      info->cc_special = CC_CLOBBER;
3945
      break;
3946
    }
3947
 
3948
  /* Here we only deal with SHIFT_SPECIAL.  */
3949
  switch (shift_mode)
3950
    {
3951
    case QIshift:
3952
      /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3953
         through the entire value.  */
3954
      gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
3955
      info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3956
      goto end;
3957
 
3958
    case HIshift:
3959
      if (count == 7)
3960
        {
3961
          switch (shift_type)
3962
            {
3963
            case SHIFT_ASHIFT:
3964
              if (TARGET_H8300)
3965
                info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3966
              else
3967
                info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3968
              goto end;
3969
            case SHIFT_LSHIFTRT:
3970
              if (TARGET_H8300)
3971
                info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3972
              else
3973
                info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3974
              goto end;
3975
            case SHIFT_ASHIFTRT:
3976
              info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3977
              goto end;
3978
            }
3979
        }
3980
      else if ((8 <= count && count <= 13)
3981
               || (TARGET_H8300S && count == 14))
3982
        {
3983
          info->remainder = count - 8;
3984
 
3985
          switch (shift_type)
3986
            {
3987
            case SHIFT_ASHIFT:
3988
              info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3989
              goto end;
3990
            case SHIFT_LSHIFTRT:
3991
              if (TARGET_H8300)
3992
                {
3993
                  info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3994
                  info->shift1  = "shlr.b\t%s0";
3995
                  info->cc_inline = CC_SET_ZNV;
3996
                }
3997
              else
3998
                {
3999
                  info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4000
                  info->cc_special = CC_SET_ZNV;
4001
                }
4002
              goto end;
4003
            case SHIFT_ASHIFTRT:
4004
              if (TARGET_H8300)
4005
                {
4006
                  info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4007
                  info->shift1  = "shar.b\t%s0";
4008
                }
4009
              else
4010
                {
4011
                  info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4012
                  info->cc_special = CC_SET_ZNV;
4013
                }
4014
              goto end;
4015
            }
4016
        }
4017
      else if (count == 14)
4018
        {
4019
          switch (shift_type)
4020
            {
4021
            case SHIFT_ASHIFT:
4022
              if (TARGET_H8300)
4023
                info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4024
              goto end;
4025
            case SHIFT_LSHIFTRT:
4026
              if (TARGET_H8300)
4027
                info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4028
              goto end;
4029
            case SHIFT_ASHIFTRT:
4030
              if (TARGET_H8300)
4031
                info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4032
              else if (TARGET_H8300H)
4033
                {
4034
                  info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4035
                  info->cc_special = CC_SET_ZNV;
4036
                }
4037
              else /* TARGET_H8300S */
4038
                gcc_unreachable ();
4039
              goto end;
4040
            }
4041
        }
4042
      else if (count == 15)
4043
        {
4044
          switch (shift_type)
4045
            {
4046
            case SHIFT_ASHIFT:
4047
              info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4048
              goto end;
4049
            case SHIFT_LSHIFTRT:
4050
              info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4051
              goto end;
4052
            case SHIFT_ASHIFTRT:
4053
              info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4054
              goto end;
4055
            }
4056
        }
4057
      gcc_unreachable ();
4058
 
4059
    case SIshift:
4060
      if (TARGET_H8300 && 8 <= count && count <= 9)
4061
        {
4062
          info->remainder = count - 8;
4063
 
4064
          switch (shift_type)
4065
            {
4066
            case SHIFT_ASHIFT:
4067
              info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4068
              goto end;
4069
            case SHIFT_LSHIFTRT:
4070
              info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4071
              info->shift1  = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4072
              goto end;
4073
            case SHIFT_ASHIFTRT:
4074
              info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4075
              goto end;
4076
            }
4077
        }
4078
      else if (count == 8 && !TARGET_H8300)
4079
        {
4080
          switch (shift_type)
4081
            {
4082
            case SHIFT_ASHIFT:
4083
              info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4084
              goto end;
4085
            case SHIFT_LSHIFTRT:
4086
              info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4087
              goto end;
4088
            case SHIFT_ASHIFTRT:
4089
              info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4090
              goto end;
4091
            }
4092
        }
4093
      else if (count == 15 && TARGET_H8300)
4094
        {
4095
          switch (shift_type)
4096
            {
4097
            case SHIFT_ASHIFT:
4098
              gcc_unreachable ();
4099
            case SHIFT_LSHIFTRT:
4100
              info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4101
              goto end;
4102
            case SHIFT_ASHIFTRT:
4103
              info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4104
              goto end;
4105
            }
4106
        }
4107
      else if (count == 15 && !TARGET_H8300)
4108
        {
4109
          switch (shift_type)
4110
            {
4111
            case SHIFT_ASHIFT:
4112
              info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4113
              info->cc_special = CC_SET_ZNV;
4114
              goto end;
4115
            case SHIFT_LSHIFTRT:
4116
              info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4117
              info->cc_special = CC_SET_ZNV;
4118
              goto end;
4119
            case SHIFT_ASHIFTRT:
4120
              gcc_unreachable ();
4121
            }
4122
        }
4123
      else if ((TARGET_H8300 && 16 <= count && count <= 20)
4124
               || (TARGET_H8300H && 16 <= count && count <= 19)
4125
               || (TARGET_H8300S && 16 <= count && count <= 21))
4126
        {
4127
          info->remainder = count - 16;
4128
 
4129
          switch (shift_type)
4130
            {
4131
            case SHIFT_ASHIFT:
4132
              info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4133
              if (TARGET_H8300)
4134
                info->shift1 = "add.w\t%e0,%e0";
4135
              goto end;
4136
            case SHIFT_LSHIFTRT:
4137
              if (TARGET_H8300)
4138
                {
4139
                  info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4140
                  info->shift1  = "shlr\t%x0\n\trotxr\t%w0";
4141
                }
4142
              else
4143
                {
4144
                  info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4145
                  info->cc_special = CC_SET_ZNV;
4146
                }
4147
              goto end;
4148
            case SHIFT_ASHIFTRT:
4149
              if (TARGET_H8300)
4150
                {
4151
                  info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4152
                  info->shift1  = "shar\t%x0\n\trotxr\t%w0";
4153
                }
4154
              else
4155
                {
4156
                  info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4157
                  info->cc_special = CC_SET_ZNV;
4158
                }
4159
              goto end;
4160
            }
4161
        }
4162
      else if (TARGET_H8300 && 24 <= count && count <= 28)
4163
        {
4164
          info->remainder = count - 24;
4165
 
4166
          switch (shift_type)
4167
            {
4168
            case SHIFT_ASHIFT:
4169
              info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4170
              info->shift1  = "shll.b\t%z0";
4171
              info->cc_inline = CC_SET_ZNV;
4172
              goto end;
4173
            case SHIFT_LSHIFTRT:
4174
              info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4175
              info->shift1  = "shlr.b\t%w0";
4176
              info->cc_inline = CC_SET_ZNV;
4177
              goto end;
4178
            case SHIFT_ASHIFTRT:
4179
              info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4180
              info->shift1  = "shar.b\t%w0";
4181
              info->cc_inline = CC_SET_ZNV;
4182
              goto end;
4183
            }
4184
        }
4185
      else if ((TARGET_H8300H && count == 24)
4186
               || (TARGET_H8300S && 24 <= count && count <= 25))
4187
        {
4188
          info->remainder = count - 24;
4189
 
4190
          switch (shift_type)
4191
            {
4192
            case SHIFT_ASHIFT:
4193
              info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4194
              goto end;
4195
            case SHIFT_LSHIFTRT:
4196
              info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4197
              info->cc_special = CC_SET_ZNV;
4198
              goto end;
4199
            case SHIFT_ASHIFTRT:
4200
              info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4201
              info->cc_special = CC_SET_ZNV;
4202
              goto end;
4203
            }
4204
        }
4205
      else if (!TARGET_H8300 && count == 28)
4206
        {
4207
          switch (shift_type)
4208
            {
4209
            case SHIFT_ASHIFT:
4210
              if (TARGET_H8300H)
4211
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4212
              else
4213
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4214
              goto end;
4215
            case SHIFT_LSHIFTRT:
4216
              if (TARGET_H8300H)
4217
                {
4218
                  info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4219
                  info->cc_special = CC_SET_ZNV;
4220
                }
4221
              else
4222
                info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4223
              goto end;
4224
            case SHIFT_ASHIFTRT:
4225
              gcc_unreachable ();
4226
            }
4227
        }
4228
      else if (!TARGET_H8300 && count == 29)
4229
        {
4230
          switch (shift_type)
4231
            {
4232
            case SHIFT_ASHIFT:
4233
              if (TARGET_H8300H)
4234
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4235
              else
4236
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4237
              goto end;
4238
            case SHIFT_LSHIFTRT:
4239
              if (TARGET_H8300H)
4240
                {
4241
                  info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4242
                  info->cc_special = CC_SET_ZNV;
4243
                }
4244
              else
4245
                {
4246
                  info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4247
                  info->cc_special = CC_SET_ZNV;
4248
                }
4249
              goto end;
4250
            case SHIFT_ASHIFTRT:
4251
              gcc_unreachable ();
4252
            }
4253
        }
4254
      else if (!TARGET_H8300 && count == 30)
4255
        {
4256
          switch (shift_type)
4257
            {
4258
            case SHIFT_ASHIFT:
4259
              if (TARGET_H8300H)
4260
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4261
              else
4262
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4263
              goto end;
4264
            case SHIFT_LSHIFTRT:
4265
              if (TARGET_H8300H)
4266
                info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4267
              else
4268
                info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4269
              goto end;
4270
            case SHIFT_ASHIFTRT:
4271
              gcc_unreachable ();
4272
            }
4273
        }
4274
      else if (count == 31)
4275
        {
4276
          if (TARGET_H8300)
4277
            {
4278
              switch (shift_type)
4279
                {
4280
                case SHIFT_ASHIFT:
4281
                  info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4282
                  goto end;
4283
                case SHIFT_LSHIFTRT:
4284
                  info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4285
                  goto end;
4286
                case SHIFT_ASHIFTRT:
4287
                  info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4288
                  goto end;
4289
                }
4290
            }
4291
          else
4292
            {
4293
              switch (shift_type)
4294
                {
4295
                case SHIFT_ASHIFT:
4296
                  info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4297
                  info->cc_special = CC_SET_ZNV;
4298
                  goto end;
4299
                case SHIFT_LSHIFTRT:
4300
                  info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4301
                  info->cc_special = CC_SET_ZNV;
4302
                  goto end;
4303
                case SHIFT_ASHIFTRT:
4304
                  info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4305
                  info->cc_special = CC_SET_ZNV;
4306
                  goto end;
4307
                }
4308
            }
4309
        }
4310
      gcc_unreachable ();
4311
 
4312
    default:
4313
      gcc_unreachable ();
4314
    }
4315
 
4316
 end:
4317
  if (!TARGET_H8300S)
4318
    info->shift2 = NULL;
4319
}
4320
 
4321
/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4322
   needed for some shift with COUNT and MODE.  Return 0 otherwise.  */
4323
 
4324
int
4325
h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
4326
{
4327
  enum h8_cpu cpu;
4328
  int a, lr, ar;
4329
 
4330
  if (GET_MODE_BITSIZE (mode) <= count)
4331
    return 1;
4332
 
4333
  /* Find out the target CPU.  */
4334
  if (TARGET_H8300)
4335
    cpu = H8_300;
4336
  else if (TARGET_H8300H)
4337
    cpu = H8_300H;
4338
  else
4339
    cpu = H8_S;
4340
 
4341
  /* Find the shift algorithm.  */
4342
  switch (mode)
4343
    {
4344
    case QImode:
4345
      a  = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4346
      lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4347
      ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4348
      break;
4349
 
4350
    case HImode:
4351
      a  = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4352
      lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4353
      ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4354
      break;
4355
 
4356
    case SImode:
4357
      a  = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4358
      lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4359
      ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4360
      break;
4361
 
4362
    default:
4363
      gcc_unreachable ();
4364
    }
4365
 
4366
  /* On H8/300H, count == 8 uses a scratch register.  */
4367
  return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4368
          || (TARGET_H8300H && mode == SImode && count == 8));
4369
}
4370
 
4371
/* Output the assembler code for doing shifts.  */
4372
 
4373
const char *
4374
output_a_shift (rtx *operands)
4375
{
4376
  static int loopend_lab;
4377
  rtx shift = operands[3];
4378
  enum machine_mode mode = GET_MODE (shift);
4379
  enum rtx_code code = GET_CODE (shift);
4380
  enum shift_type shift_type;
4381
  enum shift_mode shift_mode;
4382
  struct shift_info info;
4383
  int n;
4384
 
4385
  loopend_lab++;
4386
 
4387
  switch (mode)
4388
    {
4389
    case QImode:
4390
      shift_mode = QIshift;
4391
      break;
4392
    case HImode:
4393
      shift_mode = HIshift;
4394
      break;
4395
    case SImode:
4396
      shift_mode = SIshift;
4397
      break;
4398
    default:
4399
      gcc_unreachable ();
4400
    }
4401
 
4402
  switch (code)
4403
    {
4404
    case ASHIFTRT:
4405
      shift_type = SHIFT_ASHIFTRT;
4406
      break;
4407
    case LSHIFTRT:
4408
      shift_type = SHIFT_LSHIFTRT;
4409
      break;
4410
    case ASHIFT:
4411
      shift_type = SHIFT_ASHIFT;
4412
      break;
4413
    default:
4414
      gcc_unreachable ();
4415
    }
4416
 
4417
  /* This case must be taken care of by one of the two splitters
4418
     that convert a variable shift into a loop.  */
4419
  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4420
 
4421
  n = INTVAL (operands[2]);
4422
 
4423
  /* If the count is negative, make it 0.  */
4424
  if (n < 0)
4425
    n = 0;
4426
  /* If the count is too big, truncate it.
4427
     ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4428
     do the intuitive thing.  */
4429
  else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4430
    n = GET_MODE_BITSIZE (mode);
4431
 
4432
  get_shift_alg (shift_type, shift_mode, n, &info);
4433
 
4434
  switch (info.alg)
4435
    {
4436
    case SHIFT_SPECIAL:
4437
      output_asm_insn (info.special, operands);
4438
      /* Fall through.  */
4439
 
4440
    case SHIFT_INLINE:
4441
      n = info.remainder;
4442
 
4443
      /* Emit two bit shifts first.  */
4444
      if (info.shift2 != NULL)
4445
        {
4446
          for (; n > 1; n -= 2)
4447
            output_asm_insn (info.shift2, operands);
4448
        }
4449
 
4450
      /* Now emit one bit shifts for any residual.  */
4451
      for (; n > 0; n--)
4452
        output_asm_insn (info.shift1, operands);
4453
      return "";
4454
 
4455
    case SHIFT_ROT_AND:
4456
      {
4457
        int m = GET_MODE_BITSIZE (mode) - n;
4458
        const int mask = (shift_type == SHIFT_ASHIFT
4459
                          ? ((1 << m) - 1) << n
4460
                          : (1 << m) - 1);
4461
        char insn_buf[200];
4462
 
4463
        /* Not all possibilities of rotate are supported.  They shouldn't
4464
           be generated, but let's watch for 'em.  */
4465
        gcc_assert (info.shift1);
4466
 
4467
        /* Emit two bit rotates first.  */
4468
        if (info.shift2 != NULL)
4469
          {
4470
            for (; m > 1; m -= 2)
4471
              output_asm_insn (info.shift2, operands);
4472
          }
4473
 
4474
        /* Now single bit rotates for any residual.  */
4475
        for (; m > 0; m--)
4476
          output_asm_insn (info.shift1, operands);
4477
 
4478
        /* Now mask off the high bits.  */
4479
        switch (mode)
4480
          {
4481
          case QImode:
4482
            sprintf (insn_buf, "and\t#%d,%%X0", mask);
4483
            break;
4484
 
4485
          case HImode:
4486
            gcc_assert (TARGET_H8300H || TARGET_H8300S);
4487
            sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4488
            break;
4489
 
4490
          default:
4491
            gcc_unreachable ();
4492
          }
4493
 
4494
        output_asm_insn (insn_buf, operands);
4495
        return "";
4496
      }
4497
 
4498
    case SHIFT_LOOP:
4499
      /* A loop to shift by a "large" constant value.
4500
         If we have shift-by-2 insns, use them.  */
4501
      if (info.shift2 != NULL)
4502
        {
4503
          fprintf (asm_out_file, "\tmov.b       #%d,%sl\n", n / 2,
4504
                   names_big[REGNO (operands[4])]);
4505
          fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4506
          output_asm_insn (info.shift2, operands);
4507
          output_asm_insn ("add #0xff,%X4", operands);
4508
          fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4509
          if (n % 2)
4510
            output_asm_insn (info.shift1, operands);
4511
        }
4512
      else
4513
        {
4514
          fprintf (asm_out_file, "\tmov.b       #%d,%sl\n", n,
4515
                   names_big[REGNO (operands[4])]);
4516
          fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4517
          output_asm_insn (info.shift1, operands);
4518
          output_asm_insn ("add #0xff,%X4", operands);
4519
          fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4520
        }
4521
      return "";
4522
 
4523
    default:
4524
      gcc_unreachable ();
4525
    }
4526
}
4527
 
4528
/* Count the number of assembly instructions in a string TEMPLATE.  */
4529
 
4530
static unsigned int
4531
h8300_asm_insn_count (const char *template)
4532
{
4533
  unsigned int count = 1;
4534
 
4535
  for (; *template; template++)
4536
    if (*template == '\n')
4537
      count++;
4538
 
4539
  return count;
4540
}
4541
 
4542
/* Compute the length of a shift insn.  */
4543
 
4544
unsigned int
4545
compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4546
{
4547
  rtx shift = operands[3];
4548
  enum machine_mode mode = GET_MODE (shift);
4549
  enum rtx_code code = GET_CODE (shift);
4550
  enum shift_type shift_type;
4551
  enum shift_mode shift_mode;
4552
  struct shift_info info;
4553
  unsigned int wlength = 0;
4554
 
4555
  switch (mode)
4556
    {
4557
    case QImode:
4558
      shift_mode = QIshift;
4559
      break;
4560
    case HImode:
4561
      shift_mode = HIshift;
4562
      break;
4563
    case SImode:
4564
      shift_mode = SIshift;
4565
      break;
4566
    default:
4567
      gcc_unreachable ();
4568
    }
4569
 
4570
  switch (code)
4571
    {
4572
    case ASHIFTRT:
4573
      shift_type = SHIFT_ASHIFTRT;
4574
      break;
4575
    case LSHIFTRT:
4576
      shift_type = SHIFT_LSHIFTRT;
4577
      break;
4578
    case ASHIFT:
4579
      shift_type = SHIFT_ASHIFT;
4580
      break;
4581
    default:
4582
      gcc_unreachable ();
4583
    }
4584
 
4585
  if (GET_CODE (operands[2]) != CONST_INT)
4586
    {
4587
      /* Get the assembler code to do one shift.  */
4588
      get_shift_alg (shift_type, shift_mode, 1, &info);
4589
 
4590
      return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4591
    }
4592
  else
4593
    {
4594
      int n = INTVAL (operands[2]);
4595
 
4596
      /* If the count is negative, make it 0.  */
4597
      if (n < 0)
4598
        n = 0;
4599
      /* If the count is too big, truncate it.
4600
         ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4601
         do the intuitive thing.  */
4602
      else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4603
        n = GET_MODE_BITSIZE (mode);
4604
 
4605
      get_shift_alg (shift_type, shift_mode, n, &info);
4606
 
4607
      switch (info.alg)
4608
        {
4609
        case SHIFT_SPECIAL:
4610
          wlength += h8300_asm_insn_count (info.special);
4611
 
4612
          /* Every assembly instruction used in SHIFT_SPECIAL case
4613
             takes 2 bytes except xor.l, which takes 4 bytes, so if we
4614
             see xor.l, we just pretend that xor.l counts as two insns
4615
             so that the insn length will be computed correctly.  */
4616
          if (strstr (info.special, "xor.l") != NULL)
4617
            wlength++;
4618
 
4619
          /* Fall through.  */
4620
 
4621
        case SHIFT_INLINE:
4622
          n = info.remainder;
4623
 
4624
          if (info.shift2 != NULL)
4625
            {
4626
              wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4627
              n = n % 2;
4628
            }
4629
 
4630
          wlength += h8300_asm_insn_count (info.shift1) * n;
4631
 
4632
          return 2 * wlength;
4633
 
4634
        case SHIFT_ROT_AND:
4635
          {
4636
            int m = GET_MODE_BITSIZE (mode) - n;
4637
 
4638
            /* Not all possibilities of rotate are supported.  They shouldn't
4639
               be generated, but let's watch for 'em.  */
4640
            gcc_assert (info.shift1);
4641
 
4642
            if (info.shift2 != NULL)
4643
              {
4644
                wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4645
                m = m % 2;
4646
              }
4647
 
4648
            wlength += h8300_asm_insn_count (info.shift1) * m;
4649
 
4650
            /* Now mask off the high bits.  */
4651
            switch (mode)
4652
              {
4653
              case QImode:
4654
                wlength += 1;
4655
                break;
4656
              case HImode:
4657
                wlength += 2;
4658
                break;
4659
              case SImode:
4660
                gcc_assert (!TARGET_H8300);
4661
                wlength += 3;
4662
                break;
4663
              default:
4664
                gcc_unreachable ();
4665
              }
4666
            return 2 * wlength;
4667
          }
4668
 
4669
        case SHIFT_LOOP:
4670
          /* A loop to shift by a "large" constant value.
4671
             If we have shift-by-2 insns, use them.  */
4672
          if (info.shift2 != NULL)
4673
            {
4674
              wlength += 3 + h8300_asm_insn_count (info.shift2);
4675
              if (n % 2)
4676
                wlength += h8300_asm_insn_count (info.shift1);
4677
            }
4678
          else
4679
            {
4680
              wlength += 3 + h8300_asm_insn_count (info.shift1);
4681
            }
4682
          return 2 * wlength;
4683
 
4684
        default:
4685
          gcc_unreachable ();
4686
        }
4687
    }
4688
}
4689
 
4690
/* Compute which flag bits are valid after a shift insn.  */
4691
 
4692
int
4693
compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4694
{
4695
  rtx shift = operands[3];
4696
  enum machine_mode mode = GET_MODE (shift);
4697
  enum rtx_code code = GET_CODE (shift);
4698
  enum shift_type shift_type;
4699
  enum shift_mode shift_mode;
4700
  struct shift_info info;
4701
  int n;
4702
 
4703
  switch (mode)
4704
    {
4705
    case QImode:
4706
      shift_mode = QIshift;
4707
      break;
4708
    case HImode:
4709
      shift_mode = HIshift;
4710
      break;
4711
    case SImode:
4712
      shift_mode = SIshift;
4713
      break;
4714
    default:
4715
      gcc_unreachable ();
4716
    }
4717
 
4718
  switch (code)
4719
    {
4720
    case ASHIFTRT:
4721
      shift_type = SHIFT_ASHIFTRT;
4722
      break;
4723
    case LSHIFTRT:
4724
      shift_type = SHIFT_LSHIFTRT;
4725
      break;
4726
    case ASHIFT:
4727
      shift_type = SHIFT_ASHIFT;
4728
      break;
4729
    default:
4730
      gcc_unreachable ();
4731
    }
4732
 
4733
  /* This case must be taken care of by one of the two splitters
4734
     that convert a variable shift into a loop.  */
4735
  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4736
 
4737
  n = INTVAL (operands[2]);
4738
 
4739
  /* If the count is negative, make it 0.  */
4740
  if (n < 0)
4741
    n = 0;
4742
  /* If the count is too big, truncate it.
4743
     ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4744
     do the intuitive thing.  */
4745
  else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4746
    n = GET_MODE_BITSIZE (mode);
4747
 
4748
  get_shift_alg (shift_type, shift_mode, n, &info);
4749
 
4750
  switch (info.alg)
4751
    {
4752
    case SHIFT_SPECIAL:
4753
      if (info.remainder == 0)
4754
        return info.cc_special;
4755
 
4756
      /* Fall through.  */
4757
 
4758
    case SHIFT_INLINE:
4759
      return info.cc_inline;
4760
 
4761
    case SHIFT_ROT_AND:
4762
      /* This case always ends with an and instruction.  */
4763
      return CC_SET_ZNV;
4764
 
4765
    case SHIFT_LOOP:
4766
      /* A loop to shift by a "large" constant value.
4767
         If we have shift-by-2 insns, use them.  */
4768
      if (info.shift2 != NULL)
4769
        {
4770
          if (n % 2)
4771
            return info.cc_inline;
4772
        }
4773
      return CC_CLOBBER;
4774
 
4775
    default:
4776
      gcc_unreachable ();
4777
    }
4778
}
4779
 
4780
/* A rotation by a non-constant will cause a loop to be generated, in
4781
   which a rotation by one bit is used.  A rotation by a constant,
4782
   including the one in the loop, will be taken care of by
4783
   output_a_rotate () at the insn emit time.  */
4784
 
4785
int
4786
expand_a_rotate (rtx operands[])
4787
{
4788
  rtx dst = operands[0];
4789
  rtx src = operands[1];
4790
  rtx rotate_amount = operands[2];
4791
  enum machine_mode mode = GET_MODE (dst);
4792
 
4793
  if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4794
    return false;
4795
 
4796
  /* We rotate in place.  */
4797
  emit_move_insn (dst, src);
4798
 
4799
  if (GET_CODE (rotate_amount) != CONST_INT)
4800
    {
4801
      rtx counter = gen_reg_rtx (QImode);
4802
      rtx start_label = gen_label_rtx ();
4803
      rtx end_label = gen_label_rtx ();
4804
 
4805
      /* If the rotate amount is less than or equal to 0,
4806
         we go out of the loop.  */
4807
      emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4808
                               QImode, 0, end_label);
4809
 
4810
      /* Initialize the loop counter.  */
4811
      emit_move_insn (counter, rotate_amount);
4812
 
4813
      emit_label (start_label);
4814
 
4815
      /* Rotate by one bit.  */
4816
      switch (mode)
4817
        {
4818
        case QImode:
4819
          emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4820
          break;
4821
        case HImode:
4822
          emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4823
          break;
4824
        case SImode:
4825
          emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4826
          break;
4827
        default:
4828
          gcc_unreachable ();
4829
        }
4830
 
4831
      /* Decrement the counter by 1.  */
4832
      emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
4833
 
4834
      /* If the loop counter is nonzero, we go back to the beginning
4835
         of the loop.  */
4836
      emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
4837
                               start_label);
4838
 
4839
      emit_label (end_label);
4840
    }
4841
  else
4842
    {
4843
      /* Rotate by AMOUNT bits.  */
4844
      switch (mode)
4845
        {
4846
        case QImode:
4847
          emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4848
          break;
4849
        case HImode:
4850
          emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4851
          break;
4852
        case SImode:
4853
          emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4854
          break;
4855
        default:
4856
          gcc_unreachable ();
4857
        }
4858
    }
4859
 
4860
  return 1;
4861
}
4862
 
4863
/* Output a rotate insn.  */
4864
 
4865
const char *
4866
output_a_rotate (enum rtx_code code, rtx *operands)
4867
{
4868
  rtx dst = operands[0];
4869
  rtx rotate_amount = operands[2];
4870
  enum shift_mode rotate_mode;
4871
  enum shift_type rotate_type;
4872
  const char *insn_buf;
4873
  int bits;
4874
  int amount;
4875
  enum machine_mode mode = GET_MODE (dst);
4876
 
4877
  gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
4878
 
4879
  switch (mode)
4880
    {
4881
    case QImode:
4882
      rotate_mode = QIshift;
4883
      break;
4884
    case HImode:
4885
      rotate_mode = HIshift;
4886
      break;
4887
    case SImode:
4888
      rotate_mode = SIshift;
4889
      break;
4890
    default:
4891
      gcc_unreachable ();
4892
    }
4893
 
4894
  switch (code)
4895
    {
4896
    case ROTATERT:
4897
      rotate_type = SHIFT_ASHIFT;
4898
      break;
4899
    case ROTATE:
4900
      rotate_type = SHIFT_LSHIFTRT;
4901
      break;
4902
    default:
4903
      gcc_unreachable ();
4904
    }
4905
 
4906
  amount = INTVAL (rotate_amount);
4907
 
4908
  /* Clean up AMOUNT.  */
4909
  if (amount < 0)
4910
    amount = 0;
4911
  if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4912
    amount = GET_MODE_BITSIZE (mode);
4913
 
4914
  /* Determine the faster direction.  After this phase, amount will be
4915
     at most a half of GET_MODE_BITSIZE (mode).  */
4916
  if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4917
    {
4918
      /* Flip the direction.  */
4919
      amount = GET_MODE_BITSIZE (mode) - amount;
4920
      rotate_type =
4921
        (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4922
    }
4923
 
4924
  /* See if a byte swap (in HImode) or a word swap (in SImode) can
4925
     boost up the rotation.  */
4926
  if ((mode == HImode && TARGET_H8300 && amount >= 5)
4927
      || (mode == HImode && TARGET_H8300H && amount >= 6)
4928
      || (mode == HImode && TARGET_H8300S && amount == 8)
4929
      || (mode == SImode && TARGET_H8300H && amount >= 10)
4930
      || (mode == SImode && TARGET_H8300S && amount >= 13))
4931
    {
4932
      switch (mode)
4933
        {
4934
        case HImode:
4935
          /* This code works on any family.  */
4936
          insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
4937
          output_asm_insn (insn_buf, operands);
4938
          break;
4939
 
4940
        case SImode:
4941
          /* This code works on the H8/300H and H8S.  */
4942
          insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
4943
          output_asm_insn (insn_buf, operands);
4944
          break;
4945
 
4946
        default:
4947
          gcc_unreachable ();
4948
        }
4949
 
4950
      /* Adjust AMOUNT and flip the direction.  */
4951
      amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4952
      rotate_type =
4953
        (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4954
    }
4955
 
4956
  /* Output rotate insns.  */
4957
  for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
4958
    {
4959
      if (bits == 2)
4960
        insn_buf = rotate_two[rotate_type][rotate_mode];
4961
      else
4962
        insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
4963
 
4964
      for (; amount >= bits; amount -= bits)
4965
        output_asm_insn (insn_buf, operands);
4966
    }
4967
 
4968
  return "";
4969
}
4970
 
4971
/* Compute the length of a rotate insn.  */
4972
 
4973
unsigned int
4974
compute_a_rotate_length (rtx *operands)
4975
{
4976
  rtx src = operands[1];
4977
  rtx amount_rtx = operands[2];
4978
  enum machine_mode mode = GET_MODE (src);
4979
  int amount;
4980
  unsigned int length = 0;
4981
 
4982
  gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
4983
 
4984
  amount = INTVAL (amount_rtx);
4985
 
4986
  /* Clean up AMOUNT.  */
4987
  if (amount < 0)
4988
    amount = 0;
4989
  if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4990
    amount = GET_MODE_BITSIZE (mode);
4991
 
4992
  /* Determine the faster direction.  After this phase, amount
4993
     will be at most a half of GET_MODE_BITSIZE (mode).  */
4994
  if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4995
    /* Flip the direction.  */
4996
    amount = GET_MODE_BITSIZE (mode) - amount;
4997
 
4998
  /* See if a byte swap (in HImode) or a word swap (in SImode) can
4999
     boost up the rotation.  */
5000
  if ((mode == HImode && TARGET_H8300 && amount >= 5)
5001
      || (mode == HImode && TARGET_H8300H && amount >= 6)
5002
      || (mode == HImode && TARGET_H8300S && amount == 8)
5003
      || (mode == SImode && TARGET_H8300H && amount >= 10)
5004
      || (mode == SImode && TARGET_H8300S && amount >= 13))
5005
    {
5006
      /* Adjust AMOUNT and flip the direction.  */
5007
      amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5008
      length += 6;
5009
    }
5010
 
5011
  /* We use 2-bit rotations on the H8S.  */
5012
  if (TARGET_H8300S)
5013
    amount = amount / 2 + amount % 2;
5014
 
5015
  /* The H8/300 uses three insns to rotate one bit, taking 6
5016
     length.  */
5017
  length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5018
 
5019
  return length;
5020
}
5021
 
5022
/* Fix the operands of a gen_xxx so that it could become a bit
5023
   operating insn.  */
5024
 
5025
int
5026
fix_bit_operand (rtx *operands, enum rtx_code code)
5027
{
5028
  /* The bit_operand predicate accepts any memory during RTL generation, but
5029
     only 'U' memory afterwards, so if this is a MEM operand, we must force
5030
     it to be valid for 'U' by reloading the address.  */
5031
 
5032
  if (code == AND
5033
      ? single_zero_operand (operands[2], QImode)
5034
      : single_one_operand (operands[2], QImode))
5035
    {
5036
      /* OK to have a memory dest.  */
5037
      if (GET_CODE (operands[0]) == MEM
5038
          && !OK_FOR_U (operands[0]))
5039
        {
5040
          rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5041
                                 copy_to_mode_reg (Pmode,
5042
                                                   XEXP (operands[0], 0)));
5043
          MEM_COPY_ATTRIBUTES (mem, operands[0]);
5044
          operands[0] = mem;
5045
        }
5046
 
5047
      if (GET_CODE (operands[1]) == MEM
5048
          && !OK_FOR_U (operands[1]))
5049
        {
5050
          rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5051
                                 copy_to_mode_reg (Pmode,
5052
                                                   XEXP (operands[1], 0)));
5053
          MEM_COPY_ATTRIBUTES (mem, operands[0]);
5054
          operands[1] = mem;
5055
        }
5056
      return 0;
5057
    }
5058
 
5059
  /* Dest and src op must be register.  */
5060
 
5061
  operands[1] = force_reg (QImode, operands[1]);
5062
  {
5063
    rtx res = gen_reg_rtx (QImode);
5064
    switch (code)
5065
      {
5066
      case AND:
5067
        emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5068
        break;
5069
      case IOR:
5070
        emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5071
        break;
5072
      case XOR:
5073
        emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5074
        break;
5075
      default:
5076
        gcc_unreachable ();
5077
      }
5078
    emit_insn (gen_movqi (operands[0], res));
5079
  }
5080
  return 1;
5081
}
5082
 
5083
/* Return nonzero if FUNC is an interrupt function as specified
5084
   by the "interrupt" attribute.  */
5085
 
5086
static int
5087
h8300_interrupt_function_p (tree func)
5088
{
5089
  tree a;
5090
 
5091
  if (TREE_CODE (func) != FUNCTION_DECL)
5092
    return 0;
5093
 
5094
  a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5095
  return a != NULL_TREE;
5096
}
5097
 
5098
/* Return nonzero if FUNC is a saveall function as specified by the
5099
   "saveall" attribute.  */
5100
 
5101
static int
5102
h8300_saveall_function_p (tree func)
5103
{
5104
  tree a;
5105
 
5106
  if (TREE_CODE (func) != FUNCTION_DECL)
5107
    return 0;
5108
 
5109
  a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5110
  return a != NULL_TREE;
5111
}
5112
 
5113
/* Return nonzero if FUNC is an OS_Task function as specified
5114
   by the "OS_Task" attribute.  */
5115
 
5116
static int
5117
h8300_os_task_function_p (tree func)
5118
{
5119
  tree a;
5120
 
5121
  if (TREE_CODE (func) != FUNCTION_DECL)
5122
    return 0;
5123
 
5124
  a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5125
  return a != NULL_TREE;
5126
}
5127
 
5128
/* Return nonzero if FUNC is a monitor function as specified
5129
   by the "monitor" attribute.  */
5130
 
5131
static int
5132
h8300_monitor_function_p (tree func)
5133
{
5134
  tree a;
5135
 
5136
  if (TREE_CODE (func) != FUNCTION_DECL)
5137
    return 0;
5138
 
5139
  a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5140
  return a != NULL_TREE;
5141
}
5142
 
5143
/* Return nonzero if FUNC is a function that should be called
5144
   through the function vector.  */
5145
 
5146
int
5147
h8300_funcvec_function_p (tree func)
5148
{
5149
  tree a;
5150
 
5151
  if (TREE_CODE (func) != FUNCTION_DECL)
5152
    return 0;
5153
 
5154
  a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5155
  return a != NULL_TREE;
5156
}
5157
 
5158
/* Return nonzero if DECL is a variable that's in the eight bit
5159
   data area.  */
5160
 
5161
int
5162
h8300_eightbit_data_p (tree decl)
5163
{
5164
  tree a;
5165
 
5166
  if (TREE_CODE (decl) != VAR_DECL)
5167
    return 0;
5168
 
5169
  a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5170
  return a != NULL_TREE;
5171
}
5172
 
5173
/* Return nonzero if DECL is a variable that's in the tiny
5174
   data area.  */
5175
 
5176
int
5177
h8300_tiny_data_p (tree decl)
5178
{
5179
  tree a;
5180
 
5181
  if (TREE_CODE (decl) != VAR_DECL)
5182
    return 0;
5183
 
5184
  a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5185
  return a != NULL_TREE;
5186
}
5187
 
5188
/* Generate an 'interrupt_handler' attribute for decls.  We convert
5189
   all the pragmas to corresponding attributes.  */
5190
 
5191
static void
5192
h8300_insert_attributes (tree node, tree *attributes)
5193
{
5194
  if (TREE_CODE (node) == FUNCTION_DECL)
5195
    {
5196
      if (pragma_interrupt)
5197
        {
5198
          pragma_interrupt = 0;
5199
 
5200
          /* Add an 'interrupt_handler' attribute.  */
5201
          *attributes = tree_cons (get_identifier ("interrupt_handler"),
5202
                                   NULL, *attributes);
5203
        }
5204
 
5205
      if (pragma_saveall)
5206
        {
5207
          pragma_saveall = 0;
5208
 
5209
          /* Add an 'saveall' attribute.  */
5210
          *attributes = tree_cons (get_identifier ("saveall"),
5211
                                   NULL, *attributes);
5212
        }
5213
    }
5214
}
5215
 
5216
/* Supported attributes:
5217
 
5218
   interrupt_handler: output a prologue and epilogue suitable for an
5219
   interrupt handler.
5220
 
5221
   saveall: output a prologue and epilogue that saves and restores
5222
   all registers except the stack pointer.
5223
 
5224
   function_vector: This function should be called through the
5225
   function vector.
5226
 
5227
   eightbit_data: This variable lives in the 8-bit data area and can
5228
   be referenced with 8-bit absolute memory addresses.
5229
 
5230
   tiny_data: This variable lives in the tiny data area and can be
5231
   referenced with 16-bit absolute memory references.  */
5232
 
5233
const struct attribute_spec h8300_attribute_table[] =
5234
{
5235
  /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5236
  { "interrupt_handler", 0, 0, true,  false, false, h8300_handle_fndecl_attribute },
5237
  { "saveall",           0, 0, true,  false, false, h8300_handle_fndecl_attribute },
5238
  { "OS_Task",           0, 0, true,  false, false, h8300_handle_fndecl_attribute },
5239
  { "monitor",           0, 0, true,  false, false, h8300_handle_fndecl_attribute },
5240
  { "function_vector",   0, 0, true,  false, false, h8300_handle_fndecl_attribute },
5241
  { "eightbit_data",     0, 0, true,  false, false, h8300_handle_eightbit_data_attribute },
5242
  { "tiny_data",         0, 0, true,  false, false, h8300_handle_tiny_data_attribute },
5243
  { NULL,                0, 0, false, false, false, NULL }
5244
};
5245
 
5246
 
5247
/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5248
   struct attribute_spec.handler.  */
5249
static tree
5250
h8300_handle_fndecl_attribute (tree *node, tree name,
5251
                               tree args ATTRIBUTE_UNUSED,
5252
                               int flags ATTRIBUTE_UNUSED,
5253
                               bool *no_add_attrs)
5254
{
5255
  if (TREE_CODE (*node) != FUNCTION_DECL)
5256
    {
5257
      warning (OPT_Wattributes, "%qs attribute only applies to functions",
5258
               IDENTIFIER_POINTER (name));
5259
      *no_add_attrs = true;
5260
    }
5261
 
5262
  return NULL_TREE;
5263
}
5264
 
5265
/* Handle an "eightbit_data" attribute; arguments as in
5266
   struct attribute_spec.handler.  */
5267
static tree
5268
h8300_handle_eightbit_data_attribute (tree *node, tree name,
5269
                                      tree args ATTRIBUTE_UNUSED,
5270
                                      int flags ATTRIBUTE_UNUSED,
5271
                                      bool *no_add_attrs)
5272
{
5273
  tree decl = *node;
5274
 
5275
  if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5276
    {
5277
      DECL_SECTION_NAME (decl) = build_string (7, ".eight");
5278
    }
5279
  else
5280
    {
5281
      warning (OPT_Wattributes, "%qs attribute ignored",
5282
               IDENTIFIER_POINTER (name));
5283
      *no_add_attrs = true;
5284
    }
5285
 
5286
  return NULL_TREE;
5287
}
5288
 
5289
/* Handle an "tiny_data" attribute; arguments as in
5290
   struct attribute_spec.handler.  */
5291
static tree
5292
h8300_handle_tiny_data_attribute (tree *node, tree name,
5293
                                  tree args ATTRIBUTE_UNUSED,
5294
                                  int flags ATTRIBUTE_UNUSED,
5295
                                  bool *no_add_attrs)
5296
{
5297
  tree decl = *node;
5298
 
5299
  if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5300
    {
5301
      DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
5302
    }
5303
  else
5304
    {
5305
      warning (OPT_Wattributes, "%qs attribute ignored",
5306
               IDENTIFIER_POINTER (name));
5307
      *no_add_attrs = true;
5308
    }
5309
 
5310
  return NULL_TREE;
5311
}
5312
 
5313
/* Mark function vectors, and various small data objects.  */
5314
 
5315
static void
5316
h8300_encode_section_info (tree decl, rtx rtl, int first)
5317
{
5318
  int extra_flags = 0;
5319
 
5320
  default_encode_section_info (decl, rtl, first);
5321
 
5322
  if (TREE_CODE (decl) == FUNCTION_DECL
5323
      && h8300_funcvec_function_p (decl))
5324
    extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5325
  else if (TREE_CODE (decl) == VAR_DECL
5326
           && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5327
    {
5328
      if (h8300_eightbit_data_p (decl))
5329
        extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5330
      else if (first && h8300_tiny_data_p (decl))
5331
        extra_flags = SYMBOL_FLAG_TINY_DATA;
5332
    }
5333
 
5334
  if (extra_flags)
5335
    SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5336
}
5337
 
5338
/* Output a single-bit extraction.  */
5339
 
5340
const char *
5341
output_simode_bld (int bild, rtx operands[])
5342
{
5343
  if (TARGET_H8300)
5344
    {
5345
      /* Clear the destination register.  */
5346
      output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5347
 
5348
      /* Now output the bit load or bit inverse load, and store it in
5349
         the destination.  */
5350
      if (bild)
5351
        output_asm_insn ("bild\t%Z2,%Y1", operands);
5352
      else
5353
        output_asm_insn ("bld\t%Z2,%Y1", operands);
5354
 
5355
      output_asm_insn ("bst\t#0,%w0", operands);
5356
    }
5357
  else
5358
    {
5359
      /* Determine if we can clear the destination first.  */
5360
      int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5361
                         && REGNO (operands[0]) != REGNO (operands[1]));
5362
 
5363
      if (clear_first)
5364
        output_asm_insn ("sub.l\t%S0,%S0", operands);
5365
 
5366
      /* Output the bit load or bit inverse load.  */
5367
      if (bild)
5368
        output_asm_insn ("bild\t%Z2,%Y1", operands);
5369
      else
5370
        output_asm_insn ("bld\t%Z2,%Y1", operands);
5371
 
5372
      if (!clear_first)
5373
        output_asm_insn ("xor.l\t%S0,%S0", operands);
5374
 
5375
      /* Perform the bit store.  */
5376
      output_asm_insn ("rotxl.l\t%S0", operands);
5377
    }
5378
 
5379
  /* All done.  */
5380
  return "";
5381
}
5382
 
5383
/* Delayed-branch scheduling is more effective if we have some idea
5384
   how long each instruction will be.  Use a shorten_branches pass
5385
   to get an initial estimate.  */
5386
 
5387
static void
5388
h8300_reorg (void)
5389
{
5390
  if (flag_delayed_branch)
5391
    shorten_branches (get_insns ());
5392
}
5393
 
5394
#ifndef OBJECT_FORMAT_ELF
5395
static void
5396
h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5397
                         tree decl)
5398
{
5399
  /* ??? Perhaps we should be using default_coff_asm_named_section.  */
5400
  fprintf (asm_out_file, "\t.section %s\n", name);
5401
}
5402
#endif /* ! OBJECT_FORMAT_ELF */
5403
 
5404
/* Nonzero if X is a constant address suitable as an 8-bit absolute,
5405
   which is a special case of the 'R' operand.  */
5406
 
5407
int
5408
h8300_eightbit_constant_address_p (rtx x)
5409
{
5410
  /* The ranges of the 8-bit area.  */
5411
  const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5412
  const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5413
  const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5414
  const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5415
  const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5416
  const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5417
 
5418
  unsigned HOST_WIDE_INT addr;
5419
 
5420
  /* We accept symbols declared with eightbit_data.  */
5421
  if (GET_CODE (x) == SYMBOL_REF)
5422
    return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5423
 
5424
  if (GET_CODE (x) != CONST_INT)
5425
    return 0;
5426
 
5427
  addr = INTVAL (x);
5428
 
5429
  return (0
5430
          || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5431
          || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5432
          || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5433
}
5434
 
5435
/* Nonzero if X is a constant address suitable as an 16-bit absolute
5436
   on H8/300H and H8S.  */
5437
 
5438
int
5439
h8300_tiny_constant_address_p (rtx x)
5440
{
5441
  /* The ranges of the 16-bit area.  */
5442
  const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5443
  const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5444
  const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5445
  const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5446
  const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5447
  const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5448
  const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5449
  const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5450
 
5451
  unsigned HOST_WIDE_INT addr;
5452
 
5453
  switch (GET_CODE (x))
5454
    {
5455
    case SYMBOL_REF:
5456
      /* In the normal mode, any symbol fits in the 16-bit absolute
5457
         address range.  We also accept symbols declared with
5458
         tiny_data.  */
5459
      return (TARGET_NORMAL_MODE
5460
              || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5461
 
5462
    case CONST_INT:
5463
      addr = INTVAL (x);
5464
      return (TARGET_NORMAL_MODE
5465
              || (TARGET_H8300H
5466
                  && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5467
              || (TARGET_H8300S
5468
                  && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5469
 
5470
    case CONST:
5471
      return TARGET_NORMAL_MODE;
5472
 
5473
    default:
5474
      return 0;
5475
    }
5476
 
5477
}
5478
 
5479
/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5480
   locations that can be accessed as a 16-bit word.  */
5481
 
5482
int
5483
byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5484
{
5485
  HOST_WIDE_INT offset1, offset2;
5486
  rtx reg1, reg2;
5487
 
5488
  if (REG_P (addr1))
5489
    {
5490
      reg1 = addr1;
5491
      offset1 = 0;
5492
    }
5493
  else if (GET_CODE (addr1) == PLUS
5494
           && REG_P (XEXP (addr1, 0))
5495
           && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5496
    {
5497
      reg1 = XEXP (addr1, 0);
5498
      offset1 = INTVAL (XEXP (addr1, 1));
5499
    }
5500
  else
5501
    return 0;
5502
 
5503
  if (REG_P (addr2))
5504
    {
5505
      reg2 = addr2;
5506
      offset2 = 0;
5507
    }
5508
  else if (GET_CODE (addr2) == PLUS
5509
           && REG_P (XEXP (addr2, 0))
5510
           && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5511
    {
5512
      reg2 = XEXP (addr2, 0);
5513
      offset2 = INTVAL (XEXP (addr2, 1));
5514
    }
5515
  else
5516
    return 0;
5517
 
5518
  if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5519
       || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5520
      && offset1 % 2 == 0
5521
      && offset1 + 1 == offset2)
5522
    return 1;
5523
 
5524
  return 0;
5525
}
5526
 
5527
/* Return nonzero if we have the same comparison insn as I3 two insns
5528
   before I3.  I3 is assumed to be a comparison insn.  */
5529
 
5530
int
5531
same_cmp_preceding_p (rtx i3)
5532
{
5533
  rtx i1, i2;
5534
 
5535
  /* Make sure we have a sequence of three insns.  */
5536
  i2 = prev_nonnote_insn (i3);
5537
  if (i2 == NULL_RTX)
5538
    return 0;
5539
  i1 = prev_nonnote_insn (i2);
5540
  if (i1 == NULL_RTX)
5541
    return 0;
5542
 
5543
  return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5544
          && any_condjump_p (i2) && onlyjump_p (i2));
5545
}
5546
 
5547
/* Return nonzero if we have the same comparison insn as I1 two insns
5548
   after I1.  I1 is assumed to be a comparison insn.  */
5549
 
5550
int
5551
same_cmp_following_p (rtx i1)
5552
{
5553
  rtx i2, i3;
5554
 
5555
  /* Make sure we have a sequence of three insns.  */
5556
  i2 = next_nonnote_insn (i1);
5557
  if (i2 == NULL_RTX)
5558
    return 0;
5559
  i3 = next_nonnote_insn (i2);
5560
  if (i3 == NULL_RTX)
5561
    return 0;
5562
 
5563
  return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5564
          && any_condjump_p (i2) && onlyjump_p (i2));
5565
}
5566
 
5567
/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5568
   (or pops) N registers.  OPERANDS are assumed to be an array of
5569
   registers.  */
5570
 
5571
int
5572
h8300_regs_ok_for_stm (int n, rtx operands[])
5573
{
5574
  switch (n)
5575
    {
5576
    case 2:
5577
      return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5578
              || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5579
              || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5580
    case 3:
5581
      return ((REGNO (operands[0]) == 0
5582
               && REGNO (operands[1]) == 1
5583
               && REGNO (operands[2]) == 2)
5584
              || (REGNO (operands[0]) == 4
5585
                  && REGNO (operands[1]) == 5
5586
                  && REGNO (operands[2]) == 6));
5587
 
5588
    case 4:
5589
      return (REGNO (operands[0]) == 0
5590
              && REGNO (operands[1]) == 1
5591
              && REGNO (operands[2]) == 2
5592
              && REGNO (operands[3]) == 3);
5593
    default:
5594
      gcc_unreachable ();
5595
    }
5596
}
5597
 
5598
/* Return nonzero if register OLD_REG can be renamed to register NEW_REG.  */
5599
 
5600
int
5601
h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5602
                            unsigned int new_reg)
5603
{
5604
  /* Interrupt functions can only use registers that have already been
5605
     saved by the prologue, even if they would normally be
5606
     call-clobbered.  */
5607
 
5608
  if (h8300_current_function_interrupt_function_p ()
5609
      && !regs_ever_live[new_reg])
5610
    return 0;
5611
 
5612
  return 1;
5613
}
5614
 
5615
/* Return nonzero if X is a legitimate constant.  */
5616
 
5617
int
5618
h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
5619
{
5620
  return 1;
5621
}
5622
 
5623
/* Return nonzero if X is a REG or SUBREG suitable as a base register.  */
5624
 
5625
static int
5626
h8300_rtx_ok_for_base_p (rtx x, int strict)
5627
{
5628
  /* Strip off SUBREG if any.  */
5629
  if (GET_CODE (x) == SUBREG)
5630
    x = SUBREG_REG (x);
5631
 
5632
  return (REG_P (x)
5633
          && (strict
5634
              ? REG_OK_FOR_BASE_STRICT_P (x)
5635
              : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5636
}
5637
 
5638
/* Return nozero if X is a legitimate address.  On the H8/300, a
5639
   legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5640
   CONSTANT_ADDRESS.  */
5641
 
5642
int
5643
h8300_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
5644
{
5645
  /* The register indirect addresses like @er0 is always valid.  */
5646
  if (h8300_rtx_ok_for_base_p (x, strict))
5647
    return 1;
5648
 
5649
  if (CONSTANT_ADDRESS_P (x))
5650
    return 1;
5651
 
5652
  if (TARGET_H8300SX
5653
      && (   GET_CODE (x) == PRE_INC
5654
          || GET_CODE (x) == PRE_DEC
5655
          || GET_CODE (x) == POST_INC
5656
          || GET_CODE (x) == POST_DEC)
5657
      && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5658
    return 1;
5659
 
5660
  if (GET_CODE (x) == PLUS
5661
      && CONSTANT_ADDRESS_P (XEXP (x, 1))
5662
      && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5663
                                                   mode, 0), strict))
5664
    return 1;
5665
 
5666
  return 0;
5667
}
5668
 
5669
/* Worker function for HARD_REGNO_NREGS.
5670
 
5671
   We pretend the MAC register is 32bits -- we don't have any data
5672
   types on the H8 series to handle more than 32bits.  */
5673
 
5674
int
5675
h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5676
{
5677
  return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5678
}
5679
 
5680
/* Worker function for HARD_REGNO_MODE_OK.  */
5681
 
5682
int
5683
h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5684
{
5685
  if (TARGET_H8300)
5686
    /* If an even reg, then anything goes.  Otherwise the mode must be
5687
       QI or HI.  */
5688
    return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5689
  else
5690
    /* MAC register can only be of SImode.  Otherwise, anything
5691
       goes.  */
5692
    return regno == MAC_REG ? mode == SImode : 1;
5693
}
5694
 
5695
/* Perform target dependent optabs initialization.  */
5696
static void
5697
h8300_init_libfuncs (void)
5698
{
5699
  set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5700
  set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5701
  set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5702
  set_optab_libfunc (smod_optab, HImode, "__modhi3");
5703
  set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5704
}
5705
 
5706
/* Worker function for TARGET_RETURN_IN_MEMORY.  */
5707
 
5708
static bool
5709
h8300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5710
{
5711
  return (TYPE_MODE (type) == BLKmode
5712
          || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5713
}
5714
 
5715
/* Initialize the GCC target structure.  */
5716
#undef TARGET_ATTRIBUTE_TABLE
5717
#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5718
 
5719
#undef TARGET_ASM_ALIGNED_HI_OP
5720
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5721
 
5722
#undef TARGET_ASM_FILE_START
5723
#define TARGET_ASM_FILE_START h8300_file_start
5724
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5725
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5726
 
5727
#undef TARGET_ASM_FILE_END
5728
#define TARGET_ASM_FILE_END h8300_file_end
5729
 
5730
#undef TARGET_ENCODE_SECTION_INFO
5731
#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5732
 
5733
#undef TARGET_INSERT_ATTRIBUTES
5734
#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5735
 
5736
#undef TARGET_RTX_COSTS
5737
#define TARGET_RTX_COSTS h8300_rtx_costs
5738
 
5739
#undef TARGET_INIT_LIBFUNCS
5740
#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5741
 
5742
#undef TARGET_RETURN_IN_MEMORY
5743
#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5744
 
5745
#undef  TARGET_MACHINE_DEPENDENT_REORG
5746
#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5747
 
5748
#undef TARGET_DEFAULT_TARGET_FLAGS
5749
#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5750
 
5751
struct gcc_target targetm = TARGET_INITIALIZER;

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