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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [iq2000/] [iq2000.md] - Blame information for rev 154

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;;  iq2000.md        Machine Description for Vitesse IQ2000 processors
2 
;;  Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
3 
 
4 
;; This file is part of GCC.
5 
 
6 
;; GCC is free software; you can redistribute it and/or modify
7 
;; it under the terms of the GNU General Public License as published by
8 
;; the Free Software Foundation; either version 3, or (at your option)
9 
;; any later version.
10 
 
11 
;; GCC is distributed in the hope that it will be useful,
12 
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 
;; GNU General Public License for more details.
15 
 
16 
;; You should have received a copy of the GNU General Public License
17 
;; along with GCC; see the file COPYING3.  If not see
18 
;; .
19 
 
20 
(define_constants
21 
  [(UNSPEC_ADO16 0)
22 
   (UNSPEC_RAM  1)
23 
   (UNSPEC_CHKHDR 2)
24 
   (UNSPEC_PKRL 3)
25 
   (UNSPEC_CFC0 4)
26 
   (UNSPEC_CFC1 5)
27 
   (UNSPEC_CFC2 6)
28 
   (UNSPEC_CFC3 7)
29 
   (UNSPEC_CTC0 8)
30 
   (UNSPEC_CTC1 9)
31 
   (UNSPEC_CTC2 10)
32 
   (UNSPEC_CTC3 11)
33 
   (UNSPEC_MFC0 12)
34 
   (UNSPEC_MFC1 13)
35 
   (UNSPEC_MFC2 14)
36 
   (UNSPEC_MFC3 15)
37 
   (UNSPEC_MTC0 16)
38 
   (UNSPEC_MTC1 17)
39 
   (UNSPEC_MTC2 18)
40 
   (UNSPEC_MTC3 19)
41 
   (UNSPEC_LUR  20)
42 
   (UNSPEC_RB   21)
43 
   (UNSPEC_RX   22)
44 
   (UNSPEC_SRRD 23)
45 
   (UNSPEC_SRWR 24)
46 
   (UNSPEC_WB   25)
47 
   (UNSPEC_WX   26)
48 
   (UNSPEC_LUC32 49)
49 
   (UNSPEC_LUC32L 27)
50 
   (UNSPEC_LUC64 28)
51 
   (UNSPEC_LUC64L 29)
52 
   (UNSPEC_LUK 30)
53 
   (UNSPEC_LULCK 31)
54 
   (UNSPEC_LUM32 32)
55 
   (UNSPEC_LUM32L 33)
56 
   (UNSPEC_LUM64 34)
57 
   (UNSPEC_LUM64L 35)
58 
   (UNSPEC_LURL 36)
59 
   (UNSPEC_MRGB 37)
60 
   (UNSPEC_SRRDL 38)
61 
   (UNSPEC_SRULCK 39)
62 
   (UNSPEC_SRWRU 40)
63 
   (UNSPEC_TRAPQFL 41)
64 
   (UNSPEC_TRAPQNE 42)
65 
   (UNSPEC_TRAPREL 43)
66 
   (UNSPEC_WBU 44)
67 
   (UNSPEC_SYSCALL 45)]
68 
)
69 
;; UNSPEC values used in iq2000.md
70 
;; Number       USE
71 
;; 0            movsi_ul
72 
;; 1            movsi_us, get_fnaddr
73 
;; 3            eh_set_return
74 
;; 20           builtin_setjmp_setup
75 
;;
76 
;; UNSPEC_VOLATILE values
77 
;; 0            blockage
78 
;; 2            loadgp
79 
;; 3            builtin_longjmp
80 
;; 4            exception_receiver
81 
;; 10           consttable_qi
82 
;; 11           consttable_hi
83 
;; 12           consttable_si
84 
;; 13           consttable_di
85 
;; 14           consttable_sf
86 
;; 15           consttable_df
87 
;; 16           align_2
88 
;; 17           align_4
89 
;; 18           align_8
90 
 
91 
 
92 
;; ....................
93 
;;
94 
;;      Attributes
95 
;;
96 
;; ....................
97 
 
98 
;; Classification of each insn.
99 
;; branch       conditional branch
100 
;; jump         unconditional jump
101 
;; call         unconditional call
102 
;; load         load instruction(s)
103 
;; store        store instruction(s)
104 
;; move         data movement within same register set
105 
;; xfer         transfer to/from coprocessor
106 
;; arith        integer arithmetic instruction
107 
;; darith       double precision integer arithmetic instructions
108 
;; imul         integer multiply
109 
;; idiv         integer divide
110 
;; icmp         integer compare
111 
;; fadd         floating point add/subtract
112 
;; fmul         floating point multiply
113 
;; fmadd        floating point multiply-add
114 
;; fdiv         floating point divide
115 
;; fabs         floating point absolute value
116 
;; fneg         floating point negation
117 
;; fcmp         floating point compare
118 
;; fcvt         floating point convert
119 
;; fsqrt        floating point square root
120 
;; multi        multiword sequence (or user asm statements)
121 
;; nop          no operation
122 
 
123 
(define_attr "type"
124 
  "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
125 
  (const_string "unknown"))
126 
 
127 
;; Main data type used by the insn
128 
(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
129 
 
130 
;; Length (in # of bytes).  A conditional branch is allowed only to a
131 
;; location within a signed 18-bit offset of the delay slot.  If that
132 
;; provides too small a range, we use the `j' instruction.  This
133 
;; instruction takes a 28-bit value, but that value is not an offset.
134 
;; Instead, it's bitwise-ored with the high-order four bits of the
135 
;; instruction in the delay slot, which means it cannot be used to
136 
;; cross a 256MB boundary.  We could fall back back on the jr,
137 
;; instruction which allows full access to the entire address space,
138 
;; but we do not do so at present.
139 
 
140 
(define_attr "length" ""
141 
   (cond [(eq_attr "type" "branch")
142 
          (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
143 
                     (const_int 131072))
144 
                 (const_int 4)]
145 
                 (const_int 12))]
146 
          (const_int 4)))
147 
 
148 
(define_attr "cpu"
149 
  "default,iq2000"
150 
  (const (symbol_ref "iq2000_cpu_attr")))
151 
 
152 
;; Does the instruction have a mandatory delay slot? has_dslot
153 
;; Can the instruction be in a delay slot? ok_in_dslot
154 
;; Can the instruction not be in a delay slot? not_in_dslot
155 
(define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot"
156 
  (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp")
157 
                (const_string "has_dslot")
158 
                (const_string "ok_in_dslot")))
159 
 
160 
;; Attribute defining whether or not we can use the branch-likely instructions
161 
 
162 
(define_attr "branch_likely" "no,yes"
163 
  (const
164 
   (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
165 
                 (const_string "yes")
166 
                 (const_string "no"))))
167 
 
168 
 
169 
;; Describe a user's asm statement.
170 
(define_asm_attributes
171 
  [(set_attr "type" "multi")])
172 
 
173 
 
174 
 
175 
;; .........................
176 
;;
177 
;;      Delay slots, can't describe load/fcmp/xfer delay slots here
178 
;;
179 
;; .........................
180 
 
181 
(define_delay (eq_attr "type" "jump")
182 
  [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
183 
   (nil)
184 
   (nil)])
185 
 
186 
(define_delay (eq_attr "type" "branch")
187 
  [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
188 
   (nil)
189 
   (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))])
190 
 
191 
(define_delay (eq_attr "type" "call")
192 
  [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
193 
   (nil)
194 
   (nil)])
195 
 
196 
(include "predicates.md")
197 
 
198 
 
199 
;; .........................
200 
;;
201 
;;      Pipeline model
202 
;;
203 
;; .........................
204 
 
205 
(define_automaton "iq2000")
206 
(define_cpu_unit "core,memory" "iq2000")
207 
 
208 
(define_insn_reservation "nonmemory" 1
209 
  (eq_attr "type" "!load,move,store,xfer")
210 
  "core")
211 
 
212 
(define_insn_reservation "iq2000_load_move" 3
213 
  (and (eq_attr "type" "load,move")
214 
       (eq_attr "cpu" "iq2000"))
215 
  "memory")
216 
 
217 
(define_insn_reservation "other_load_move" 1
218 
  (and (eq_attr "type" "load,move")
219 
       (eq_attr "cpu" "!iq2000"))
220 
  "memory")
221 
 
222 
(define_insn_reservation "store" 1
223 
  (eq_attr "type" "store")
224 
  "memory")
225 
 
226 
(define_insn_reservation "xfer" 2
227 
  (eq_attr "type" "xfer")
228 
  "memory")
229 
 
230 
;;
231 
;;  ....................
232 
;;
233 
;;      CONDITIONAL TRAPS
234 
;;
235 
;;  ....................
236 
;;
237 
 
238 
(define_insn "trap"
239 
  [(trap_if (const_int 1) (const_int 0))]
240 
  ""
241 
  "*
242 
{
243 
  return \"break\";
244 
}")
245 
 
246 
;;
247 
;;  ....................
248 
;;
249 
;;      ADDITION
250 
;;
251 
;;  ....................
252 
;;
253 
 
254 
(define_expand "addsi3"
255 
  [(set (match_operand:SI 0 "register_operand" "=d")
256 
        (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
257 
                 (match_operand:SI 2 "arith_operand" "dI")))]
258 
  ""
259 
  "")
260 
 
261 
(define_insn "addsi3_internal"
262 
  [(set (match_operand:SI 0 "register_operand" "=d,=d")
263 
        (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
264 
                 (match_operand:SI 2 "arith_operand" "d,I")))]
265 
  ""
266 
  "@
267 
   addu\\t%0,%z1,%2
268 
   addiu\\t%0,%z1,%2"
269 
  [(set_attr "type"     "arith")
270 
   (set_attr "mode"     "SI")])
271 
 
272 
;;
273 
;;  ....................
274 
;;
275 
;;      SUBTRACTION
276 
;;
277 
;;  ....................
278 
;;
279 
 
280 
(define_expand "subsi3"
281 
  [(set (match_operand:SI 0 "register_operand" "=d")
282 
        (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
283 
                  (match_operand:SI 2 "arith_operand" "dI")))]
284 
  ""
285 
  "")
286 
 
287 
(define_insn "subsi3_internal"
288 
  [(set (match_operand:SI 0 "register_operand" "=d,=d")
289 
        (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
290 
                  (match_operand:SI 2 "arith_operand" "d,I")))]
291 
  ""
292 
  "@
293 
   subu\\t%0,%z1,%2
294 
   addiu\\t%0,%z1,%n2"
295 
  [(set_attr "type"     "arith")
296 
   (set_attr "mode"     "SI")])
297 
 
298 
;;
299 
;;  ....................
300 
;;
301 
;;      NEGATION and ONE'S COMPLEMENT
302 
;;
303 
;;  ....................
304 
 
305 
(define_insn "negsi2"
306 
  [(set (match_operand:SI 0 "register_operand" "=d")
307 
        (neg:SI (match_operand:SI 1 "register_operand" "d")))]
308 
  ""
309 
  "*
310 
{
311 
  operands[2] = const0_rtx;
312 
  return \"subu\\t%0,%z2,%1\";
313 
}"
314 
  [(set_attr "type"     "arith")
315 
   (set_attr "mode"     "SI")])
316 
 
317 
(define_insn "one_cmplsi2"
318 
  [(set (match_operand:SI 0 "register_operand" "=d")
319 
        (not:SI (match_operand:SI 1 "register_operand" "d")))]
320 
  ""
321 
  "*
322 
{
323 
  operands[2] = const0_rtx;
324 
  return \"nor\\t%0,%z2,%1\";
325 
}"
326 
  [(set_attr "type"     "arith")
327 
   (set_attr "mode"     "SI")])
328 
 
329 
;;
330 
;;  ....................
331 
;;
332 
;;      LOGICAL
333 
;;
334 
;;  ....................
335 
;;
336 
 
337 
(define_expand "andsi3"
338 
  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
339 
        (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
340 
                (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
341 
  ""
342 
  "")
343 
 
344 
(define_insn ""
345 
  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
346 
        (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
347 
                (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
348 
  ""
349 
  "*
350 
{
351 
  if (which_alternative == 0)
352 
    return \"and\\t%0,%1,%2\";
353 
  else if (which_alternative == 1)
354 
    return \"andi\\t%0,%1,%x2\";
355 
  else if (which_alternative == 2)
356 
    {
357 
      if ((INTVAL (operands[2]) & 0xffff) == 0xffff)
358 
        {
359 
          operands[2] = GEN_INT (INTVAL (operands[2]) >> 16);
360 
          return \"andoui\\t%0,%1,%x2\";
361 
        }
362 
      else
363 
        {
364 
          operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
365 
          return \"andoi\\t%0,%1,%x2\";
366 
        }
367 
    }
368 
}"
369 
  [(set_attr "type"     "arith")
370 
   (set_attr "mode"     "SI")])
371 
 
372 
(define_expand "iorsi3"
373 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
374 
        (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
375 
                (match_operand:SI 2 "uns_arith_operand" "d,K")))]
376 
  ""
377 
  "")
378 
 
379 
(define_insn ""
380 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
381 
        (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
382 
                (match_operand:SI 2 "uns_arith_operand" "d,K")))]
383 
  ""
384 
  "@
385 
   or\\t%0,%1,%2
386 
   ori\\t%0,%1,%x2"
387 
  [(set_attr "type"     "arith")
388 
   (set_attr "mode"     "SI")])
389 
 
390 
(define_expand "xorsi3"
391 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
392 
        (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
393 
                (match_operand:SI 2 "uns_arith_operand" "d,K")))]
394 
  ""
395 
  "")
396 
 
397 
(define_insn ""
398 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
399 
        (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
400 
                (match_operand:SI 2 "uns_arith_operand" "d,K")))]
401 
  ""
402 
  "@
403 
   xor\\t%0,%1,%2
404 
   xori\\t%0,%1,%x2"
405 
  [(set_attr "type"     "arith")
406 
   (set_attr "mode"     "SI")])
407 
 
408 
(define_insn "*norsi3"
409 
  [(set (match_operand:SI 0 "register_operand" "=d")
410 
        (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
411 
                (not:SI (match_operand:SI 2 "register_operand" "d"))))]
412 
  ""
413 
  "nor\\t%0,%z1,%z2"
414 
  [(set_attr "type"     "arith")
415 
   (set_attr "mode"     "SI")])
416 
 
417 
;;
418 
;;  ....................
419 
;;
420 
;;      ZERO EXTENSION
421 
;;
422 
;;  ....................
423 
 
424 
;; Extension insns.
425 
;; Those for integer source operand are ordered widest source type first.
426 
 
427 
(define_expand "zero_extendhisi2"
428 
  [(set (match_operand:SI 0 "register_operand" "")
429 
        (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
430 
  ""
431 
  "")
432 
 
433 
(define_insn ""
434 
  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
435 
        (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
436 
  ""
437 
  "*
438 
{
439 
  if (which_alternative == 0)
440 
    return \"andi\\t%0,%1,0xffff\";
441 
  else
442 
    return iq2000_move_1word (operands, insn, TRUE);
443 
}"
444 
  [(set_attr "type"     "arith,load,load")
445 
   (set_attr "mode"     "SI")
446 
   (set_attr "length"   "4,4,8")])
447 
 
448 
(define_expand "zero_extendqihi2"
449 
  [(set (match_operand:HI 0 "register_operand" "")
450 
        (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
451 
  ""
452 
  "")
453 
 
454 
(define_insn ""
455 
  [(set (match_operand:HI 0 "register_operand" "=d,d,d")
456 
        (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
457 
  ""
458 
  "*
459 
{
460 
  if (which_alternative == 0)
461 
    return \"andi\\t%0,%1,0x00ff\";
462 
  else
463 
    return iq2000_move_1word (operands, insn, TRUE);
464 
}"
465 
  [(set_attr "type"     "arith,load,load")
466 
   (set_attr "mode"     "HI")
467 
   (set_attr "length"   "4,4,8")])
468 
 
469 
(define_expand "zero_extendqisi2"
470 
  [(set (match_operand:SI 0 "register_operand" "")
471 
        (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
472 
  ""
473 
  "")
474 
 
475 
(define_insn ""
476 
  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
477 
        (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
478 
  ""
479 
  "*
480 
{
481 
  if (which_alternative == 0)
482 
    return \"andi\\t%0,%1,0x00ff\";
483 
  else
484 
    return iq2000_move_1word (operands, insn, TRUE);
485 
}"
486 
  [(set_attr "type"     "arith,load,load")
487 
   (set_attr "mode"     "SI")
488 
   (set_attr "length"   "4,4,8")])
489 
 
490 
;;
491 
;;  ....................
492 
;;
493 
;;      SIGN EXTENSION
494 
;;
495 
;;  ....................
496 
 
497 
;; Extension insns.
498 
;; Those for integer source operand are ordered widest source type first.
499 
 
500 
;; These patterns originally accepted general_operands, however, slightly
501 
;; better code is generated by only accepting register_operands, and then
502 
;; letting combine generate the lh and lb insns.
503 
 
504 
(define_expand "extendhisi2"
505 
  [(set (match_operand:SI 0 "register_operand" "")
506 
        (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
507 
  ""
508 
  "
509 
{
510 
  if (optimize && GET_CODE (operands[1]) == MEM)
511 
    operands[1] = force_not_mem (operands[1]);
512 
 
513 
  if (GET_CODE (operands[1]) != MEM)
514 
    {
515 
      rtx op1   = gen_lowpart (SImode, operands[1]);
516 
      rtx temp  = gen_reg_rtx (SImode);
517 
      rtx shift = GEN_INT (16);
518 
 
519 
      emit_insn (gen_ashlsi3 (temp, op1, shift));
520 
      emit_insn (gen_ashrsi3 (operands[0], temp, shift));
521 
      DONE;
522 
    }
523 
}")
524 
 
525 
(define_insn "extendhisi2_internal"
526 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
527 
        (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
528 
  ""
529 
  "* return iq2000_move_1word (operands, insn, FALSE);"
530 
  [(set_attr "type"     "load")
531 
   (set_attr "mode"     "SI")
532 
   (set_attr "length"   "4,8")])
533 
 
534 
(define_expand "extendqihi2"
535 
  [(set (match_operand:HI 0 "register_operand" "")
536 
        (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
537 
  ""
538 
  "
539 
{
540 
  if (optimize && GET_CODE (operands[1]) == MEM)
541 
    operands[1] = force_not_mem (operands[1]);
542 
 
543 
  if (GET_CODE (operands[1]) != MEM)
544 
    {
545 
      rtx op0   = gen_lowpart (SImode, operands[0]);
546 
      rtx op1   = gen_lowpart (SImode, operands[1]);
547 
      rtx temp  = gen_reg_rtx (SImode);
548 
      rtx shift = GEN_INT (24);
549 
 
550 
      emit_insn (gen_ashlsi3 (temp, op1, shift));
551 
      emit_insn (gen_ashrsi3 (op0, temp, shift));
552 
      DONE;
553 
    }
554 
}")
555 
 
556 
(define_insn "extendqihi2_internal"
557 
  [(set (match_operand:HI 0 "register_operand" "=d,d")
558 
        (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
559 
  ""
560 
  "* return iq2000_move_1word (operands, insn, FALSE);"
561 
  [(set_attr "type"     "load")
562 
   (set_attr "mode"     "SI")
563 
   (set_attr "length"   "4,8")])
564 
 
565 
 
566 
(define_expand "extendqisi2"
567 
  [(set (match_operand:SI 0 "register_operand" "")
568 
        (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
569 
  ""
570 
  "
571 
{
572 
  if (optimize && GET_CODE (operands[1]) == MEM)
573 
    operands[1] = force_not_mem (operands[1]);
574 
 
575 
  if (GET_CODE (operands[1]) != MEM)
576 
    {
577 
      rtx op1   = gen_lowpart (SImode, operands[1]);
578 
      rtx temp  = gen_reg_rtx (SImode);
579 
      rtx shift = GEN_INT (24);
580 
 
581 
      emit_insn (gen_ashlsi3 (temp, op1, shift));
582 
      emit_insn (gen_ashrsi3 (operands[0], temp, shift));
583 
      DONE;
584 
    }
585 
}")
586 
 
587 
(define_insn "extendqisi2_insn"
588 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
589 
        (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
590 
  ""
591 
  "* return iq2000_move_1word (operands, insn, FALSE);"
592 
  [(set_attr "type"     "load")
593 
   (set_attr "mode"     "SI")
594 
   (set_attr "length"   "4,8")])
595 
 
596 
;;
597 
;;  ........................
598 
;;
599 
;;      BIT FIELD EXTRACTION
600 
;;
601 
;;  ........................
602 
 
603 
(define_insn "extzv"
604 
  [(set (match_operand:SI 0 "register_operand" "=r")
605 
        (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
606 
                         (match_operand:SI 2 "const_int_operand" "O")
607 
                         (match_operand:SI 3 "const_int_operand" "O")))]
608 
  ""
609 
  "*
610 
{
611 
  int value[4];
612 
  value[2] = INTVAL (operands[2]);
613 
  value[3] = INTVAL (operands[3]);
614 
  operands[2] = GEN_INT ((value[3]));
615 
  operands[3] = GEN_INT ((32 - value[2]));
616 
  return \"ram\\t%0,%1,%2,%3,0x0\";
617 
}"
618 
  [(set_attr "type" "arith")])
619 
 
620 
;;
621 
;;  ....................
622 
;;
623 
;;      DATA MOVEMENT
624 
;;
625 
;;  ....................
626 
 
627 
/* Take care of constants that don't fit in single instruction */
628 
(define_split
629 
  [(set (match_operand:SI 0 "register_operand" "")
630 
        (match_operand:SI 1 "general_operand" ""))]
631 
  "(reload_in_progress || reload_completed)
632 
   && large_int (operands[1], SImode)"
633 
 
634 
  [(set (match_dup 0 )
635 
        (high:SI (match_dup 1)))
636 
   (set (match_dup 0 )
637 
        (lo_sum:SI (match_dup 0)
638 
                   (match_dup 1)))]
639 
)
640 
 
641 
;; ??? iq2000_move_1word has support for HIGH, so this pattern may be
642 
;; unnecessary.
643 
 
644 
(define_insn "high"
645 
  [(set (match_operand:SI 0 "register_operand" "=r")
646 
        (high:SI (match_operand:SI 1 "immediate_operand" "")))]
647 
  ""
648 
  "lui\\t%0,%%hi(%1) # high"
649 
  [(set_attr "type"     "move")])
650 
 
651 
(define_insn "low"
652 
  [(set (match_operand:SI 0 "register_operand" "=r")
653 
        (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
654 
                   (match_operand:SI 2 "immediate_operand" "")))]
655 
  ""
656 
  "addiu\\t%0,%1,%%lo(%2) # low"
657 
  [(set_attr "type"     "arith")
658 
   (set_attr "mode"     "SI")])
659 
 
660 
;; 32-bit Integer moves
661 
 
662 
(define_split
663 
  [(set (match_operand:SI 0 "register_operand" "")
664 
        (match_operand:SI 1 "large_int" ""))]
665 
  "reload_in_progress | reload_completed"
666 
  [(set (match_dup 0)
667 
        (match_dup 2))
668 
   (set (match_dup 0)
669 
        (ior:SI (match_dup 0)
670 
                (match_dup 3)))]
671 
  "
672 
{
673 
  operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
674 
                                             & BITMASK_UPPER16,
675 
                                             SImode));
676 
  operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
677 
}")
678 
 
679 
;; Unlike most other insns, the move insns can't be split with
680 
;; different predicates, because register spilling and other parts of
681 
;; the compiler, have memoized the insn number already.
682 
 
683 
(define_expand "movsi"
684 
  [(set (match_operand:SI 0 "nonimmediate_operand" "")
685 
        (match_operand:SI 1 "general_operand" ""))]
686 
  ""
687 
  "
688 
{
689 
  if (iq2000_check_split (operands[1], SImode))
690 
    {
691 
      enum machine_mode mode = GET_MODE (operands[0]);
692 
      rtx tem = ((reload_in_progress | reload_completed)
693 
                 ? operands[0] : gen_reg_rtx (mode));
694 
 
695 
      emit_insn (gen_rtx_SET (VOIDmode, tem,
696 
                              gen_rtx_HIGH (mode, operands[1])));
697 
 
698 
      operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
699 
    }
700 
 
701 
  if ((reload_in_progress | reload_completed) == 0
702 
      && !register_operand (operands[0], SImode)
703 
      && !register_operand (operands[1], SImode)
704 
      && (GET_CODE (operands[1]) != CONST_INT
705 
          || INTVAL (operands[1]) != 0))
706 
    {
707 
      rtx temp = force_reg (SImode, operands[1]);
708 
      emit_move_insn (operands[0], temp);
709 
      DONE;
710 
    }
711 
 
712 
  /* Take care of constants that don't fit in single instruction */
713 
  if ((reload_in_progress || reload_completed)
714 
      && CONSTANT_P (operands[1])
715 
      && GET_CODE (operands[1]) != HIGH
716 
      && GET_CODE (operands[1]) != LO_SUM
717 
      && ! SMALL_INT_UNSIGNED (operands[1]))
718 
    {
719 
      rtx tem = ((reload_in_progress | reload_completed)
720 
                 ? operands[0] : gen_reg_rtx (SImode));
721 
 
722 
      emit_insn (gen_rtx_SET (VOIDmode, tem,
723 
                              gen_rtx_HIGH (SImode, operands[1])));
724 
      operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]);
725 
    }
726 
}")
727 
 
728 
;; The difference between these two is whether or not ints are allowed
729 
;; in FP registers (off by default, use -mdebugh to enable).
730 
 
731 
(define_insn "movsi_internal2"
732 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d")
733 
        (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))]
734 
  "(register_operand (operands[0], SImode)
735 
       || register_operand (operands[1], SImode)
736 
       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
737 
  "* return iq2000_move_1word (operands, insn, FALSE);"
738 
  [(set_attr "type"     "move,load,arith,arith,load,load,store,store,xfer,xfer,move,move,move,move")
739 
   (set_attr "mode"     "SI")
740 
   (set_attr "length"   "4,8,4,8,4,8,4,8,4,4,4,4,4,4")])
741 
 
742 
;; 16-bit Integer moves
743 
 
744 
;; Unlike most other insns, the move insns can't be split with
745 
;; different predicates, because register spilling and other parts of
746 
;; the compiler, have memoized the insn number already.
747 
;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
748 
 
749 
(define_expand "movhi"
750 
  [(set (match_operand:HI 0 "nonimmediate_operand" "")
751 
        (match_operand:HI 1 "general_operand" ""))]
752 
  ""
753 
  "
754 
{
755 
  if ((reload_in_progress | reload_completed) == 0
756 
      && !register_operand (operands[0], HImode)
757 
      && !register_operand (operands[1], HImode)
758 
      && ((GET_CODE (operands[1]) != CONST_INT
759 
          || INTVAL (operands[1]) != 0)))
760 
    {
761 
      rtx temp = force_reg (HImode, operands[1]);
762 
      emit_move_insn (operands[0], temp);
763 
      DONE;
764 
    }
765 
}")
766 
 
767 
;; The difference between these two is whether or not ints are allowed
768 
;; in FP registers (off by default, use -mdebugh to enable).
769 
 
770 
(define_insn "movhi_internal2"
771 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
772 
        (match_operand:HI 1 "general_operand"       "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
773 
  "(register_operand (operands[0], HImode)
774 
       || register_operand (operands[1], HImode)
775 
       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
776 
  "* return iq2000_move_1word (operands, insn, TRUE);"
777 
  [(set_attr "type"     "move,arith,load,load,store,store,xfer,xfer,move,move")
778 
   (set_attr "mode"     "HI")
779 
   (set_attr "length"   "4,4,4,8,4,8,4,4,4,4")])
780 
 
781 
;; 8-bit Integer moves
782 
 
783 
;; Unlike most other insns, the move insns can't be split with
784 
;; different predicates, because register spilling and other parts of
785 
;; the compiler, have memoized the insn number already.
786 
;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
787 
 
788 
(define_expand "movqi"
789 
  [(set (match_operand:QI 0 "nonimmediate_operand" "")
790 
        (match_operand:QI 1 "general_operand" ""))]
791 
  ""
792 
  "
793 
{
794 
  if ((reload_in_progress | reload_completed) == 0
795 
      && !register_operand (operands[0], QImode)
796 
      && !register_operand (operands[1], QImode)
797 
      && (GET_CODE (operands[1]) != CONST_INT
798 
          || INTVAL (operands[1]) != 0))
799 
    {
800 
      rtx temp = force_reg (QImode, operands[1]);
801 
      emit_move_insn (operands[0], temp);
802 
      DONE;
803 
    }
804 
}")
805 
 
806 
;; The difference between these two is whether or not ints are allowed
807 
;; in FP registers (off by default, use -mdebugh to enable).
808 
 
809 
(define_insn "movqi_internal2"
810 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
811 
        (match_operand:QI 1 "general_operand"       "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
812 
  "(register_operand (operands[0], QImode)
813 
       || register_operand (operands[1], QImode)
814 
       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
815 
  "* return iq2000_move_1word (operands, insn, TRUE);"
816 
  [(set_attr "type"     "move,arith,load,load,store,store,xfer,xfer,move,move")
817 
   (set_attr "mode"     "QI")
818 
   (set_attr "length"   "4,4,4,8,4,8,4,4,4,4")])
819 
 
820 
;; 32-bit floating point moves
821 
 
822 
(define_expand "movsf"
823 
  [(set (match_operand:SF 0 "general_operand" "")
824 
        (match_operand:SF 1 "general_operand" ""))]
825 
  ""
826 
  "
827 
{
828 
  if (!reload_in_progress
829 
      && !reload_completed
830 
      && GET_CODE (operands[0]) == MEM
831 
      && (GET_CODE (operands[1]) == MEM
832 
         || GET_CODE (operands[1]) == CONST_DOUBLE))
833 
    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
834 
 
835 
  /* Take care of reg <- SF constant */
836 
  if ( const_double_operand (operands[1], GET_MODE (operands[1]) ) )
837 
    {
838 
      emit_insn (gen_movsf_high (operands[0], operands[1]));
839 
      emit_insn (gen_movsf_lo_sum (operands[0], operands[0], operands[1]));
840 
      DONE;
841 
    }
842 
}")
843 
 
844 
(define_insn "movsf_lo_sum"
845 
  [(set (match_operand:SF 0 "register_operand" "=r")
846 
        (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
847 
                   (match_operand:SF 2 "const_double_operand" "")))]
848 
  ""
849 
  "*
850 
{
851 
  REAL_VALUE_TYPE r;
852 
  long i;
853 
 
854 
  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
855 
  REAL_VALUE_TO_TARGET_SINGLE (r, i);
856 
  operands[2] = GEN_INT (i);
857 
  return \"addiu\\t%0,%1,%%lo(%2) # low\";
858 
}"
859 
  [(set_attr "length" "4")
860 
   (set_attr "type" "arith")])
861 
 
862 
(define_insn "movsf_high"
863 
  [(set (match_operand:SF 0 "register_operand" "=r")
864 
        (high:SF (match_operand:SF 1 "const_double_operand" "")))]
865 
  ""
866 
  "*
867 
{
868 
  REAL_VALUE_TYPE r;
869 
  long i;
870 
 
871 
  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
872 
  REAL_VALUE_TO_TARGET_SINGLE (r, i);
873 
  operands[1] = GEN_INT (i);
874 
  return \"lui\\t%0,%%hi(%1) # high\";
875 
}"
876 
  [(set_attr "length" "4")
877 
   (set_attr "type" "arith")])
878 
 
879 
(define_insn "*movsf_internal"
880 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
881 
        (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))]
882 
  "!memory_operand (operands[0], SFmode) || !memory_operand (operands[1], SFmode)"
883 
  "*
884 
{
885 
  iq2000_fill_delay_slot (\"\", DELAY_LOAD, operands, insn);
886 
  if (which_alternative == 0)
887 
    return \"or\\t%0,%1,%1\";
888 
  else if (which_alternative == 1)
889 
    return \"lw\\t%0,%1\";
890 
  else if (which_alternative == 2)
891 
    return \"sw\\t%1,%0\";
892 
}"
893 
  [(set_attr "length" "4,4,4")
894 
   (set_attr "type" "arith,load,store")]
895 
)
896 
 
897 
;;
898 
;;  ....................
899 
;;
900 
;;      SHIFTS
901 
;;
902 
;;  ....................
903 
 
904 
(define_expand "ashlsi3"
905 
  [(set (match_operand:SI 0 "register_operand" "=d")
906 
        (ashift:SI (match_operand:SI 1 "register_operand" "d")
907 
                   (match_operand:SI 2 "arith_operand" "dI")))]
908 
  ""
909 
  "")
910 
 
911 
(define_insn "ashlsi3_internal1"
912 
  [(set (match_operand:SI 0 "register_operand" "=d")
913 
        (ashift:SI (match_operand:SI 1 "register_operand" "d")
914 
                   (match_operand:SI 2 "arith_operand" "dI")))]
915 
  ""
916 
  "*
917 
{
918 
  if (GET_CODE (operands[2]) == CONST_INT)
919 
    {
920 
      operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
921 
      return \"sll\\t%0,%1,%2\";
922 
    }
923 
  else
924 
    return \"sllv\\t%0,%1,%2\";
925 
}"
926 
  [(set_attr "type"     "arith")
927 
   (set_attr "mode"     "SI")])
928 
 
929 
(define_expand "ashrsi3"
930 
  [(set (match_operand:SI 0 "register_operand" "=d")
931 
        (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
932 
                     (match_operand:SI 2 "arith_operand" "dI")))]
933 
  ""
934 
  "")
935 
 
936 
(define_insn "ashrsi3_internal1"
937 
  [(set (match_operand:SI 0 "register_operand" "=d")
938 
        (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
939 
                     (match_operand:SI 2 "arith_operand" "dI")))]
940 
  ""
941 
  "*
942 
{
943 
  if (GET_CODE (operands[2]) == CONST_INT)
944 
    {
945 
      operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
946 
      return \"sra\\t%0,%1,%2\";
947 
    }
948 
  else
949 
    return \"srav\\t%0,%1,%2\";
950 
}"
951 
  [(set_attr "type"     "arith")
952 
   (set_attr "mode"     "SI")])
953 
 
954 
(define_expand "lshrsi3"
955 
  [(set (match_operand:SI 0 "register_operand" "=d")
956 
        (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
957 
                     (match_operand:SI 2 "arith_operand" "dI")))]
958 
  ""
959 
  "")
960 
 
961 
(define_insn "lshrsi3_internal1"
962 
  [(set (match_operand:SI 0 "register_operand" "=d")
963 
        (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
964 
                     (match_operand:SI 2 "arith_operand" "dI")))]
965 
  ""
966 
  "*
967 
{
968 
  if (GET_CODE (operands[2]) == CONST_INT)
969 
    {
970 
      operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
971 
      return \"srl\\t%0,%1,%2\";
972 
    }
973 
  else
974 
    return \"srlv\\t%0,%1,%2\";
975 
}"
976 
  [(set_attr "type"     "arith")
977 
   (set_attr "mode"     "SI")])
978 
 
979 
;; Rotate Right
980 
(define_insn "rotrsi3"
981 
  [(set (match_operand:SI 0 "register_operand" "=r")
982 
        (rotatert:SI (match_operand:SI 1 "register_operand" "r")
983 
                     (match_operand:SI 2 "uns_arith_operand" "O")))]
984 
  ""
985 
  "ram %0,%1,%2,0x0,0x0"
986 
  [(set_attr "type" "arith")])
987 
 
988 
 
989 
;;
990 
;;  ....................
991 
;;
992 
;;      COMPARISONS
993 
;;
994 
;;  ....................
995 
 
996 
;; Flow here is rather complex:
997 
;;
998 
;;  1)  The cmp{si,di,sf,df} routine is called.  It deposits the
999 
;;      arguments into the branch_cmp array, and the type into
1000 
;;      branch_type.  No RTL is generated.
1001 
;;
1002 
;;  2)  The appropriate branch define_expand is called, which then
1003 
;;      creates the appropriate RTL for the comparison and branch.
1004 
;;      Different CC modes are used, based on what type of branch is
1005 
;;      done, so that we can constrain things appropriately.  There
1006 
;;      are assumptions in the rest of GCC that break if we fold the
1007 
;;      operands into the branches for integer operations, and use cc0
1008 
;;      for floating point, so we use the fp status register instead.
1009 
;;      If needed, an appropriate temporary is created to hold the
1010 
;;      of the integer compare.
1011 
 
1012 
(define_expand "cmpsi"
1013 
  [(set (cc0)
1014 
        (compare:CC (match_operand:SI 0 "register_operand" "")
1015 
                    (match_operand:SI 1 "arith_operand" "")))]
1016 
  ""
1017 
  "
1018 
{
1019 
  if (operands[0])              /* avoid unused code message */
1020 
    {
1021 
      branch_cmp[0] = operands[0];
1022 
      branch_cmp[1] = operands[1];
1023 
      branch_type = CMP_SI;
1024 
      DONE;
1025 
    }
1026 
}")
1027 
 
1028 
(define_expand "tstsi"
1029 
  [(set (cc0)
1030 
        (match_operand:SI 0 "register_operand" ""))]
1031 
  ""
1032 
  "
1033 
{
1034 
  if (operands[0])              /* avoid unused code message */
1035 
    {
1036 
      branch_cmp[0] = operands[0];
1037 
      branch_cmp[1] = const0_rtx;
1038 
      branch_type = CMP_SI;
1039 
      DONE;
1040 
    }
1041 
}")
1042 
 
1043 
;;
1044 
;;  ....................
1045 
;;
1046 
;;      CONDITIONAL BRANCHES
1047 
;;
1048 
;;  ....................
1049 
 
1050 
;; Conditional branches on comparisons with zero.
1051 
 
1052 
(define_insn "branch_zero"
1053 
  [(set (pc)
1054 
        (if_then_else
1055 
         (match_operator:SI 0 "cmp_op"
1056 
                            [(match_operand:SI 2 "register_operand" "d")
1057 
                             (const_int 0)])
1058 
        (label_ref (match_operand 1 "" ""))
1059 
        (pc)))]
1060 
  ""
1061 
  "*
1062 
{
1063 
  return iq2000_output_conditional_branch (insn,
1064 
                                         operands,
1065 
                                         /*two_operands_p=*/0,
1066 
                                         /*float_p=*/0,
1067 
                                         /*inverted_p=*/0,
1068 
                                         get_attr_length (insn));
1069 
}"
1070 
  [(set_attr "type"     "branch")
1071 
   (set_attr "mode"     "none")])
1072 
 
1073 
(define_insn "branch_zero_inverted"
1074 
  [(set (pc)
1075 
        (if_then_else
1076 
         (match_operator:SI 0 "cmp_op"
1077 
                            [(match_operand:SI 2 "register_operand" "d")
1078 
                             (const_int 0)])
1079 
        (pc)
1080 
        (label_ref (match_operand 1 "" ""))))]
1081 
  ""
1082 
  "*
1083 
{
1084 
  return iq2000_output_conditional_branch (insn,
1085 
                                         operands,
1086 
                                         /*two_operands_p=*/0,
1087 
                                         /*float_p=*/0,
1088 
                                         /*inverted_p=*/1,
1089 
                                         get_attr_length (insn));
1090 
}"
1091 
  [(set_attr "type"     "branch")
1092 
   (set_attr "mode"     "none")])
1093 
 
1094 
;; Conditional branch on equality comparison.
1095 
 
1096 
(define_insn "branch_equality"
1097 
  [(set (pc)
1098 
        (if_then_else
1099 
         (match_operator:SI 0 "equality_op"
1100 
                            [(match_operand:SI 2 "register_operand" "d")
1101 
                             (match_operand:SI 3 "register_operand" "d")])
1102 
         (label_ref (match_operand 1 "" ""))
1103 
         (pc)))]
1104 
  ""
1105 
  "*
1106 
{
1107 
  return iq2000_output_conditional_branch (insn,
1108 
                                         operands,
1109 
                                         /*two_operands_p=*/1,
1110 
                                         /*float_p=*/0,
1111 
                                         /*inverted_p=*/0,
1112 
                                         get_attr_length (insn));
1113 
}"
1114 
  [(set_attr "type"     "branch")
1115 
   (set_attr "mode"     "none")])
1116 
 
1117 
(define_insn "branch_equality_inverted"
1118 
  [(set (pc)
1119 
        (if_then_else
1120 
         (match_operator:SI 0 "equality_op"
1121 
                            [(match_operand:SI 2 "register_operand" "d")
1122 
                             (match_operand:SI 3 "register_operand" "d")])
1123 
         (pc)
1124 
         (label_ref (match_operand 1 "" ""))))]
1125 
  ""
1126 
  "*
1127 
{
1128 
  return iq2000_output_conditional_branch (insn,
1129 
                                         operands,
1130 
                                         /*two_operands_p=*/1,
1131 
                                         /*float_p=*/0,
1132 
                                         /*inverted_p=*/1,
1133 
                                         get_attr_length (insn));
1134 
}"
1135 
  [(set_attr "type"     "branch")
1136 
   (set_attr "mode"     "none")])
1137 
 
1138 
(define_expand "beq"
1139 
  [(set (pc)
1140 
        (if_then_else (eq:CC (cc0)
1141 
                             (const_int 0))
1142 
                      (label_ref (match_operand 0 "" ""))
1143 
                      (pc)))]
1144 
  ""
1145 
  "
1146 
{
1147 
  if (operands[0])              /* avoid unused code warning */
1148 
    {
1149 
      gen_conditional_branch (operands, EQ);
1150 
      DONE;
1151 
    }
1152 
}")
1153 
 
1154 
(define_expand "bne"
1155 
  [(set (pc)
1156 
        (if_then_else (ne:CC (cc0)
1157 
                             (const_int 0))
1158 
                      (label_ref (match_operand 0 "" ""))
1159 
                      (pc)))]
1160 
  ""
1161 
  "
1162 
{
1163 
  if (operands[0])              /* avoid unused code warning */
1164 
    {
1165 
      gen_conditional_branch (operands, NE);
1166 
      DONE;
1167 
    }
1168 
}")
1169 
 
1170 
(define_expand "bgt"
1171 
  [(set (pc)
1172 
        (if_then_else (gt:CC (cc0)
1173 
                             (const_int 0))
1174 
                      (label_ref (match_operand 0 "" ""))
1175 
                      (pc)))]
1176 
  ""
1177 
  "
1178 
{
1179 
  if (operands[0])              /* avoid unused code warning */
1180 
    {
1181 
      gen_conditional_branch (operands, GT);
1182 
      DONE;
1183 
    }
1184 
}")
1185 
 
1186 
(define_expand "bge"
1187 
  [(set (pc)
1188 
        (if_then_else (ge:CC (cc0)
1189 
                             (const_int 0))
1190 
                      (label_ref (match_operand 0 "" ""))
1191 
                      (pc)))]
1192 
  ""
1193 
  "
1194 
{
1195 
  if (operands[0])              /* avoid unused code warning */
1196 
    {
1197 
      gen_conditional_branch (operands, GE);
1198 
      DONE;
1199 
    }
1200 
}")
1201 
 
1202 
(define_expand "blt"
1203 
  [(set (pc)
1204 
        (if_then_else (lt:CC (cc0)
1205 
                             (const_int 0))
1206 
                      (label_ref (match_operand 0 "" ""))
1207 
                      (pc)))]
1208 
  ""
1209 
  "
1210 
{
1211 
  if (operands[0])              /* avoid unused code warning */
1212 
    {
1213 
      gen_conditional_branch (operands, LT);
1214 
      DONE;
1215 
    }
1216 
}")
1217 
 
1218 
(define_expand "ble"
1219 
  [(set (pc)
1220 
        (if_then_else (le:CC (cc0)
1221 
                             (const_int 0))
1222 
                      (label_ref (match_operand 0 "" ""))
1223 
                      (pc)))]
1224 
  ""
1225 
  "
1226 
{
1227 
  if (operands[0])              /* avoid unused code warning */
1228 
    {
1229 
      gen_conditional_branch (operands, LE);
1230 
      DONE;
1231 
    }
1232 
}")
1233 
 
1234 
(define_expand "bgtu"
1235 
  [(set (pc)
1236 
        (if_then_else (gtu:CC (cc0)
1237 
                              (const_int 0))
1238 
                      (label_ref (match_operand 0 "" ""))
1239 
                      (pc)))]
1240 
  ""
1241 
  "
1242 
{
1243 
  if (operands[0])              /* avoid unused code warning */
1244 
    {
1245 
      gen_conditional_branch (operands, GTU);
1246 
      DONE;
1247 
    }
1248 
}")
1249 
 
1250 
(define_expand "bgeu"
1251 
  [(set (pc)
1252 
        (if_then_else (geu:CC (cc0)
1253 
                              (const_int 0))
1254 
                      (label_ref (match_operand 0 "" ""))
1255 
                      (pc)))]
1256 
  ""
1257 
  "
1258 
{
1259 
  if (operands[0])              /* avoid unused code warning */
1260 
    {
1261 
      gen_conditional_branch (operands, GEU);
1262 
      DONE;
1263 
    }
1264 
}")
1265 
 
1266 
 
1267 
(define_expand "bltu"
1268 
  [(set (pc)
1269 
        (if_then_else (ltu:CC (cc0)
1270 
                              (const_int 0))
1271 
                      (label_ref (match_operand 0 "" ""))
1272 
                      (pc)))]
1273 
  ""
1274 
  "
1275 
{
1276 
  if (operands[0])              /* avoid unused code warning */
1277 
    {
1278 
      gen_conditional_branch (operands, LTU);
1279 
      DONE;
1280 
    }
1281 
}")
1282 
 
1283 
(define_expand "bleu"
1284 
  [(set (pc)
1285 
        (if_then_else (leu:CC (cc0)
1286 
                              (const_int 0))
1287 
                      (label_ref (match_operand 0 "" ""))
1288 
                      (pc)))]
1289 
  ""
1290 
  "
1291 
{
1292 
  if (operands[0])              /* avoid unused code warning */
1293 
    {
1294 
      gen_conditional_branch (operands, LEU);
1295 
      DONE;
1296 
    }
1297 
}")
1298 
 
1299 
;; Recognize bbi and bbin instructions.  These use two unusual template
1300 
;; patterns, %Ax and %Px.  %Ax outputs an 'i' if operand `x' is a LABEL_REF
1301 
;; otherwise it outputs an 'in'.  %Px does nothing if `x' is PC
1302 
;; and outputs the operand if `x' is a LABEL_REF.
1303 
 
1304 
(define_insn ""
1305 
  [(set (pc)
1306 
        (if_then_else
1307 
         (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1308 
                              (const_int 1)
1309 
                              (match_operand:SI 1 "arith_operand" "I"))
1310 
             (const_int 0))
1311 
         (match_operand 2 "pc_or_label_operand" "")
1312 
         (match_operand 3 "pc_or_label_operand" "")))]
1313 
  ""
1314 
  "bb%A2\\t%0(31-%1),%P2%P3"
1315 
  [(set_attr "length" "4")
1316 
   (set_attr "type" "branch")])
1317 
 
1318 
(define_insn ""
1319 
  [(set (pc)
1320 
        (if_then_else
1321 
         (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1322 
                              (const_int 1)
1323 
                              (match_operand:SI 1 "arith_operand" "I"))
1324 
             (const_int 0))
1325 
         (match_operand 2 "pc_or_label_operand" "")
1326 
         (match_operand 3 "pc_or_label_operand" "")))]
1327 
  ""
1328 
  "bb%A3\\t%0(31-%1),%P2%P3"
1329 
  [(set_attr "length" "4")
1330 
   (set_attr "type" "branch")])
1331 
 
1332 
(define_insn ""
1333 
  [(set (pc)
1334 
        (if_then_else
1335 
         (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1336 
                              (const_int 1)
1337 
                              (match_operand:SI 1 "arith_operand" "I"))
1338 
             (const_int 0))
1339 
         (match_operand 2 "pc_or_label_operand" "")
1340 
         (match_operand 3 "pc_or_label_operand" "")))]
1341 
  ""
1342 
  "bb%A2\\t%0(31-%1),%P2%P3"
1343 
  [(set_attr "length" "4")
1344 
   (set_attr "type" "branch")])
1345 
 
1346 
(define_insn ""
1347 
  [(set (pc)
1348 
        (if_then_else
1349 
         (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1350 
                              (const_int 1)
1351 
                              (match_operand:SI 1 "arith_operand" "I"))
1352 
             (const_int 0))
1353 
         (match_operand 2 "pc_or_label_operand" "")
1354 
         (match_operand 3 "pc_or_label_operand" "")))]
1355 
  ""
1356 
  "bb%A3\\t%0(31-%1),%P2%P3"
1357 
  [(set_attr "length" "4")
1358 
   (set_attr "type" "branch")])
1359 
 
1360 
(define_insn ""
1361 
  [(set (pc)
1362 
        (if_then_else
1363 
         (eq (and:SI (match_operand:SI 0 "register_operand" "r")
1364 
                     (match_operand:SI 1 "power_of_2_operand" "I"))
1365 
              (const_int 0))
1366 
         (match_operand 2 "pc_or_label_operand" "")
1367 
         (match_operand 3 "pc_or_label_operand" "")))]
1368 
  ""
1369 
  "bb%A3\\t%0(%p1),%P2%P3"
1370 
  [(set_attr "length" "4")
1371 
   (set_attr "type" "branch")])
1372 
 
1373 
(define_insn ""
1374 
  [(set (pc)
1375 
        (if_then_else
1376 
         (ne (and:SI (match_operand:SI 0 "register_operand" "r")
1377 
                     (match_operand:SI 1 "power_of_2_operand" "I"))
1378 
             (const_int 0))
1379 
         (match_operand 2 "pc_or_label_operand" "")
1380 
         (match_operand 3 "pc_or_label_operand" "")))]
1381 
  ""
1382 
  "bb%A2\\t%0(%p1),%P2%P3"
1383 
  [(set_attr "length" "4")
1384 
   (set_attr "type" "branch")])
1385 
 
1386 
;;
1387 
;;  ....................
1388 
;;
1389 
;;      SETTING A REGISTER FROM A COMPARISON
1390 
;;
1391 
;;  ....................
1392 
 
1393 
(define_expand "seq"
1394 
  [(set (match_operand:SI 0 "register_operand" "=d")
1395 
        (eq:SI (match_dup 1)
1396 
               (match_dup 2)))]
1397 
  ""
1398 
  "
1399 
{
1400 
  if (branch_type != CMP_SI && (branch_type != CMP_DI))
1401 
    FAIL;
1402 
 
1403 
  /* Set up operands from compare.  */
1404 
  operands[1] = branch_cmp[0];
1405 
  operands[2] = branch_cmp[1];
1406 
 
1407 
  gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
1408 
  DONE;
1409 
}")
1410 
 
1411 
 
1412 
(define_insn "seq_si_zero"
1413 
  [(set (match_operand:SI 0 "register_operand" "=d")
1414 
        (eq:SI (match_operand:SI 1 "register_operand" "d")
1415 
               (const_int 0)))]
1416 
  ""
1417 
  "sltiu\\t%0,%1,1"
1418 
  [(set_attr "type"     "arith")
1419 
   (set_attr "mode"     "SI")])
1420 
 
1421 
(define_expand "sne"
1422 
  [(set (match_operand:SI 0 "register_operand" "=d")
1423 
        (ne:SI (match_dup 1)
1424 
               (match_dup 2)))]
1425 
  ""
1426 
  "
1427 
{
1428 
  if (branch_type != CMP_SI && (branch_type != CMP_DI))
1429 
    FAIL;
1430 
 
1431 
  /* Set up operands from compare.  */
1432 
  operands[1] = branch_cmp[0];
1433 
  operands[2] = branch_cmp[1];
1434 
 
1435 
  gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
1436 
  DONE;
1437 
}")
1438 
 
1439 
(define_insn "sne_si_zero"
1440 
  [(set (match_operand:SI 0 "register_operand" "=d")
1441 
        (ne:SI (match_operand:SI 1 "register_operand" "d")
1442 
               (const_int 0)))]
1443 
  ""
1444 
  "sltu\\t%0,%.,%1"
1445 
  [(set_attr "type"     "arith")
1446 
   (set_attr "mode"     "SI")])
1447 
 
1448 
(define_expand "sgt"
1449 
  [(set (match_operand:SI 0 "register_operand" "=d")
1450 
        (gt:SI (match_dup 1)
1451 
               (match_dup 2)))]
1452 
  ""
1453 
  "
1454 
{
1455 
  if (branch_type != CMP_SI && (branch_type != CMP_DI))
1456 
    FAIL;
1457 
 
1458 
  /* Set up operands from compare.  */
1459 
  operands[1] = branch_cmp[0];
1460 
  operands[2] = branch_cmp[1];
1461 
 
1462 
  gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
1463 
  DONE;
1464 
}")
1465 
 
1466 
(define_insn "sgt_si"
1467 
  [(set (match_operand:SI 0 "register_operand" "=d,=d")
1468 
        (gt:SI (match_operand:SI 1 "register_operand" "d,d")
1469 
               (match_operand:SI 2 "reg_or_0_operand" "d,J")))]
1470 
  ""
1471 
  "@
1472 
   slt\\t%0,%z2,%1
1473 
   slt\\t%0,%z2,%1"
1474 
  [(set_attr "type"     "arith,arith")
1475 
   (set_attr "mode"     "SI,SI")])
1476 
 
1477 
(define_expand "sge"
1478 
  [(set (match_operand:SI 0 "register_operand" "=d")
1479 
        (ge:SI (match_dup 1)
1480 
               (match_dup 2)))]
1481 
  ""
1482 
  "
1483 
{
1484 
  if (branch_type != CMP_SI && (branch_type != CMP_DI))
1485 
    FAIL;
1486 
 
1487 
  /* Set up operands from compare.  */
1488 
  operands[1] = branch_cmp[0];
1489 
  operands[2] = branch_cmp[1];
1490 
 
1491 
  gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
1492 
  DONE;
1493 
}")
1494 
 
1495 
(define_expand "slt"
1496 
  [(set (match_operand:SI 0 "register_operand" "=d")
1497 
        (lt:SI (match_dup 1)
1498 
               (match_dup 2)))]
1499 
  ""
1500 
  "
1501 
{
1502 
  if (branch_type != CMP_SI && (branch_type != CMP_DI))
1503 
    FAIL;
1504 
 
1505 
  /* Set up operands from compare.  */
1506 
  operands[1] = branch_cmp[0];
1507 
  operands[2] = branch_cmp[1];
1508 
 
1509 
  gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
1510 
  DONE;
1511 
}")
1512 
 
1513 
(define_insn "slt_si"
1514 
  [(set (match_operand:SI 0 "register_operand" "=d,=d")
1515 
        (lt:SI (match_operand:SI 1 "register_operand" "d,d")
1516 
               (match_operand:SI 2 "arith_operand" "d,I")))]
1517 
  ""
1518 
  "@
1519 
   slt\\t%0,%1,%2
1520 
   slti\\t%0,%1,%2"
1521 
  [(set_attr "type"     "arith,arith")
1522 
   (set_attr "mode"     "SI,SI")])
1523 
 
1524 
(define_expand "sle"
1525 
  [(set (match_operand:SI 0 "register_operand" "=d")
1526 
        (le:SI (match_dup 1)
1527 
               (match_dup 2)))]
1528 
  ""
1529 
  "
1530 
{
1531 
  if (branch_type != CMP_SI && (branch_type != CMP_DI))
1532 
    FAIL;
1533 
 
1534 
  /* Set up operands from compare.  */
1535 
  operands[1] = branch_cmp[0];
1536 
  operands[2] = branch_cmp[1];
1537 
 
1538 
  gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
1539 
  DONE;
1540 
}")
1541 
 
1542 
(define_insn "sle_si_const"
1543 
  [(set (match_operand:SI 0 "register_operand" "=d")
1544 
        (le:SI (match_operand:SI 1 "register_operand" "d")
1545 
               (match_operand:SI 2 "small_int" "I")))]
1546 
  "INTVAL (operands[2]) < 32767"
1547 
  "*
1548 
{
1549 
  operands[2] = GEN_INT (INTVAL (operands[2])+1);
1550 
  return \"slti\\t%0,%1,%2\";
1551 
}"
1552 
  [(set_attr "type"     "arith")
1553 
   (set_attr "mode"     "SI")])
1554 
 
1555 
(define_expand "sgtu"
1556 
  [(set (match_operand:SI 0 "register_operand" "=d")
1557 
        (gtu:SI (match_dup 1)
1558 
                (match_dup 2)))]
1559 
  ""
1560 
  "
1561 
{
1562 
  if (branch_type != CMP_SI && (branch_type != CMP_DI))
1563 
    FAIL;
1564 
 
1565 
  /* Set up operands from compare.  */
1566 
  operands[1] = branch_cmp[0];
1567 
  operands[2] = branch_cmp[1];
1568 
 
1569 
  gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
1570 
  DONE;
1571 
}")
1572 
 
1573 
(define_insn "sgtu_si"
1574 
  [(set (match_operand:SI 0 "register_operand" "=d")
1575 
        (gtu:SI (match_operand:SI 1 "register_operand" "d")
1576 
                (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
1577 
  ""
1578 
  "sltu\\t%0,%z2,%1"
1579 
  [(set_attr "type"     "arith")
1580 
   (set_attr "mode"     "SI")])
1581 
 
1582 
(define_insn ""
1583 
  [(set (match_operand:SI 0 "register_operand" "=t")
1584 
        (gtu:SI (match_operand:SI 1 "register_operand" "d")
1585 
                (match_operand:SI 2 "register_operand" "d")))]
1586 
  ""
1587 
  "sltu\\t%2,%1"
1588 
  [(set_attr "type"     "arith")
1589 
   (set_attr "mode"     "SI")])
1590 
 
1591 
(define_expand "sgeu"
1592 
  [(set (match_operand:SI 0 "register_operand" "=d")
1593 
        (geu:SI (match_dup 1)
1594 
                (match_dup 2)))]
1595 
  ""
1596 
  "
1597 
{
1598 
  if (branch_type != CMP_SI && (branch_type != CMP_DI))
1599 
    FAIL;
1600 
 
1601 
  /* Set up operands from compare.  */
1602 
  operands[1] = branch_cmp[0];
1603 
  operands[2] = branch_cmp[1];
1604 
 
1605 
  gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
1606 
  DONE;
1607 
}")
1608 
 
1609 
(define_expand "sltu"
1610 
  [(set (match_operand:SI 0 "register_operand" "=d")
1611 
        (ltu:SI (match_dup 1)
1612 
                (match_dup 2)))]
1613 
  ""
1614 
  "
1615 
{
1616 
  if (branch_type != CMP_SI && (branch_type != CMP_DI))
1617 
    FAIL;
1618 
 
1619 
  /* Set up operands from compare.  */
1620 
  operands[1] = branch_cmp[0];
1621 
  operands[2] = branch_cmp[1];
1622 
 
1623 
  gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
1624 
  DONE;
1625 
}")
1626 
 
1627 
(define_insn "sltu_si"
1628 
  [(set (match_operand:SI 0 "register_operand" "=d,=d")
1629 
        (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
1630 
                (match_operand:SI 2 "arith_operand" "d,I")))]
1631 
  ""
1632 
  "@
1633 
   sltu\\t%0,%1,%2
1634 
   sltiu\\t%0,%1,%2"
1635 
  [(set_attr "type"     "arith,arith")
1636 
   (set_attr "mode"     "SI,SI")])
1637 
 
1638 
(define_expand "sleu"
1639 
  [(set (match_operand:SI 0 "register_operand" "=d")
1640 
        (leu:SI (match_dup 1)
1641 
                (match_dup 2)))]
1642 
  ""
1643 
  "
1644 
{
1645 
  if (branch_type != CMP_SI && (branch_type != CMP_DI))
1646 
    FAIL;
1647 
 
1648 
  /* Set up operands from compare.  */
1649 
  operands[1] = branch_cmp[0];
1650 
  operands[2] = branch_cmp[1];
1651 
 
1652 
  gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
1653 
  DONE;
1654 
}")
1655 
 
1656 
(define_insn "sleu_si_const"
1657 
  [(set (match_operand:SI 0 "register_operand" "=d")
1658 
        (leu:SI (match_operand:SI 1 "register_operand" "d")
1659 
                (match_operand:SI 2 "small_int" "I")))]
1660 
  "INTVAL (operands[2]) < 32767"
1661 
  "*
1662 
{
1663 
  operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
1664 
  return \"sltiu\\t%0,%1,%2\";
1665 
}"
1666 
  [(set_attr "type"     "arith")
1667 
   (set_attr "mode"     "SI")])
1668 
 
1669 
 
1670 
;;
1671 
;;  ....................
1672 
;;
1673 
;;      UNCONDITIONAL BRANCHES
1674 
;;
1675 
;;  ....................
1676 
 
1677 
;; Unconditional branches.
1678 
 
1679 
(define_insn "jump"
1680 
  [(set (pc)
1681 
        (label_ref (match_operand 0 "" "")))]
1682 
  ""
1683 
  "*
1684 
{
1685 
  if (GET_CODE (operands[0]) == REG)
1686 
    return \"j\\t%0\";
1687 
  return \"j\\t%l0\";
1688 
  /* return \"b\\t%l0\";*/
1689 
}"
1690 
  [(set_attr "type"     "jump")
1691 
   (set_attr "mode"     "none")])
1692 
 
1693 
(define_expand "indirect_jump"
1694 
  [(set (pc) (match_operand 0 "register_operand" "d"))]
1695 
  ""
1696 
  "
1697 
{
1698 
  rtx dest;
1699 
 
1700 
  if (operands[0])              /* eliminate unused code warnings */
1701 
    {
1702 
      dest = operands[0];
1703 
      if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
1704 
        operands[0] = copy_to_mode_reg (Pmode, dest);
1705 
 
1706 
      if (!(Pmode == DImode))
1707 
        emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
1708 
      else
1709 
        emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
1710 
 
1711 
      DONE;
1712 
    }
1713 
}")
1714 
 
1715 
(define_insn "indirect_jump_internal1"
1716 
  [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
1717 
  "!(Pmode == DImode)"
1718 
  "j\\t%0"
1719 
  [(set_attr "type"     "jump")
1720 
   (set_attr "mode"     "none")])
1721 
 
1722 
(define_expand "tablejump"
1723 
  [(set (pc)
1724 
        (match_operand 0 "register_operand" "d"))
1725 
   (use (label_ref (match_operand 1 "" "")))]
1726 
  ""
1727 
  "
1728 
{
1729 
  if (operands[0])              /* eliminate unused code warnings */
1730 
    {
1731 
      gcc_assert (GET_MODE (operands[0]) == Pmode);
1732 
 
1733 
      if (!(Pmode == DImode))
1734 
        emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
1735 
      else
1736 
        emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
1737 
 
1738 
      DONE;
1739 
    }
1740 
}")
1741 
 
1742 
(define_insn "tablejump_internal1"
1743 
  [(set (pc)
1744 
        (match_operand:SI 0 "register_operand" "d"))
1745 
   (use (label_ref (match_operand 1 "" "")))]
1746 
  "!(Pmode == DImode)"
1747 
  "j\\t%0"
1748 
  [(set_attr "type"     "jump")
1749 
   (set_attr "mode"     "none")])
1750 
 
1751 
(define_expand "tablejump_internal3"
1752 
  [(parallel [(set (pc)
1753 
                   (plus:SI (match_operand:SI 0 "register_operand" "d")
1754 
                            (label_ref:SI (match_operand 1 "" ""))))
1755 
              (use (label_ref:SI (match_dup 1)))])]
1756 
  ""
1757 
  "")
1758 
 
1759 
;;; Make sure that this only matches the insn before ADDR_DIFF_VEC.  Otherwise
1760 
;;; it is not valid.  ??? With the USE, the condition tests may not be required
1761 
;;; any longer.
1762 
 
1763 
;;; ??? The length depends on the ABI.  It is two for o32, and one for n32.
1764 
;;; We just use the conservative number here.
1765 
 
1766 
(define_insn ""
1767 
  [(set (pc)
1768 
        (plus:SI (match_operand:SI 0 "register_operand" "d")
1769 
                 (label_ref:SI (match_operand 1 "" ""))))
1770 
   (use (label_ref:SI (match_dup 1)))]
1771 
  "!(Pmode == DImode) && next_active_insn (insn) != 0
1772 
   && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
1773 
   && PREV_INSN (next_active_insn (insn)) == operands[1]"
1774 
  "*
1775 
{
1776 
  return \"j\\t%0\";
1777 
}"
1778 
  [(set_attr "type"     "jump")
1779 
   (set_attr "mode"     "none")
1780 
   (set_attr "length"   "8")])
1781 
 
1782 
;;
1783 
;;  ....................
1784 
;;
1785 
;;      Function prologue/epilogue
1786 
;;
1787 
;;  ....................
1788 
;;
1789 
 
1790 
(define_expand "prologue"
1791 
  [(const_int 1)]
1792 
  ""
1793 
  "
1794 
{
1795 
  if (iq2000_isa >= 0)          /* avoid unused code warnings */
1796 
    {
1797 
      iq2000_expand_prologue ();
1798 
      DONE;
1799 
    }
1800 
}")
1801 
 
1802 
;; Block any insns from being moved before this point, since the
1803 
;; profiling call to mcount can use various registers that aren't
1804 
;; saved or used to pass arguments.
1805 
 
1806 
(define_insn "blockage"
1807 
  [(unspec_volatile [(const_int 0)] 0)]
1808 
  ""
1809 
  ""
1810 
  [(set_attr "type"     "unknown")
1811 
   (set_attr "mode"     "none")
1812 
   (set_attr "length"   "0")])
1813 
 
1814 
(define_expand "epilogue"
1815 
  [(const_int 2)]
1816 
  ""
1817 
  "
1818 
{
1819 
  if (iq2000_isa >= 0)            /* avoid unused code warnings */
1820 
    {
1821 
      iq2000_expand_epilogue ();
1822 
      DONE;
1823 
    }
1824 
}")
1825 
 
1826 
;; Trivial return.  Make it look like a normal return insn as that
1827 
;; allows jump optimizations to work better .
1828 
(define_insn "return"
1829 
  [(return)]
1830 
  "iq2000_can_use_return_insn ()"
1831 
  "j\\t%%31"
1832 
  [(set_attr "type"     "jump")
1833 
   (set_attr "mode"     "none")])
1834 
 
1835 
;; Normal return.
1836 
 
1837 
(define_insn "return_internal"
1838 
  [(use (match_operand 0 "pmode_register_operand" ""))
1839 
   (return)]
1840 
  ""
1841 
  "*
1842 
{
1843 
  return \"j\\t%0\";
1844 
}"
1845 
  [(set_attr "type"     "jump")
1846 
   (set_attr "mode"     "none")])
1847 
 
1848 
(define_insn "eh_return_internal"
1849 
  [(const_int 4)
1850 
   (return)
1851 
   (use (reg:SI 26))
1852 
   (use (reg:SI 31))]
1853 
  ""
1854 
  "j\\t%%26"
1855 
  [(set_attr "type"     "jump")
1856 
   (set_attr "mode"     "none")])
1857 
 
1858 
(define_expand "eh_return"
1859 
  [(use (match_operand:SI 0 "register_operand" "r"))]
1860 
  ""
1861 
  "
1862 
{
1863 
  iq2000_expand_eh_return (operands[0]);
1864 
  DONE;
1865 
}")
1866 
 
1867 
 
1868 
;;
1869 
;;  ....................
1870 
;;
1871 
;;      FUNCTION CALLS
1872 
;;
1873 
;;  ....................
1874 
 
1875 
;; calls.c now passes a third argument, make saber happy
1876 
 
1877 
(define_expand "call"
1878 
  [(parallel [(call (match_operand 0 "memory_operand" "m")
1879 
                    (match_operand 1 "" "i"))
1880 
              (clobber (reg:SI 31))
1881 
              (use (match_operand 2 "" ""))             ;; next_arg_reg
1882 
              (use (match_operand 3 "" ""))])]          ;; struct_value_size_rtx
1883 
  ""
1884 
  "
1885 
{
1886 
  rtx addr;
1887 
 
1888 
  if (operands[0])              /* eliminate unused code warnings */
1889 
    {
1890 
      addr = XEXP (operands[0], 0);
1891 
      if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1892 
          || ! call_insn_operand (addr, VOIDmode))
1893 
        XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
1894 
 
1895 
      /* In order to pass small structures by value in registers
1896 
         compatibly with the IQ2000 compiler, we need to shift the value
1897 
         into the high part of the register.  Function_arg has encoded
1898 
         a PARALLEL rtx, holding a vector of adjustments to be made
1899 
         as the next_arg_reg variable, so we split up the insns,
1900 
         and emit them separately.  */
1901 
 
1902 
      if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
1903 
        {
1904 
          rtvec adjust = XVEC (operands[2], 0);
1905 
          int num = GET_NUM_ELEM (adjust);
1906 
          int i;
1907 
 
1908 
          for (i = 0; i < num; i++)
1909 
            emit_insn (RTVEC_ELT (adjust, i));
1910 
        }
1911 
 
1912 
      emit_call_insn (gen_call_internal0 (operands[0], operands[1],
1913 
                                          gen_rtx_REG (SImode,
1914 
                                                       GP_REG_FIRST + 31)));
1915 
      DONE;
1916 
    }
1917 
}")
1918 
 
1919 
(define_expand "call_internal0"
1920 
  [(parallel [(call (match_operand 0 "" "")
1921 
                    (match_operand 1 "" ""))
1922 
              (clobber (match_operand:SI 2 "" ""))])]
1923 
  ""
1924 
  "")
1925 
 
1926 
(define_insn "call_internal1"
1927 
  [(call (mem (match_operand 0 "call_insn_operand" "ri"))
1928 
         (match_operand 1 "" "i"))
1929 
   (clobber (match_operand:SI 2 "register_operand" "=d"))]
1930 
  ""
1931 
  "*
1932 
{
1933 
  register rtx target = operands[0];
1934 
 
1935 
  if (GET_CODE (target) == CONST_INT)
1936 
    return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\";
1937 
  else if (CONSTANT_ADDRESS_P (target))
1938 
    return \"jal\\t%0\";
1939 
  else
1940 
    return \"jalr\\t%2,%0\";
1941 
}"
1942 
  [(set_attr "type"     "call")
1943 
   (set_attr "mode"     "none")])
1944 
 
1945 
;; calls.c now passes a fourth argument, make saber happy
1946 
 
1947 
(define_expand "call_value"
1948 
  [(parallel [(set (match_operand 0 "register_operand" "=df")
1949 
                   (call (match_operand 1 "memory_operand" "m")
1950 
                         (match_operand 2 "" "i")))
1951 
              (clobber (reg:SI 31))
1952 
              (use (match_operand 3 "" ""))])]          ;; next_arg_reg
1953 
  ""
1954 
  "
1955 
{
1956 
  rtx addr;
1957 
 
1958 
  if (operands[0])              /* eliminate unused code warning */
1959 
    {
1960 
      addr = XEXP (operands[1], 0);
1961 
      if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1962 
          || ! call_insn_operand (addr, VOIDmode))
1963 
        XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
1964 
 
1965 
      /* In order to pass small structures by value in registers
1966 
         compatibly with the IQ2000 compiler, we need to shift the value
1967 
         into the high part of the register.  Function_arg has encoded
1968 
         a PARALLEL rtx, holding a vector of adjustments to be made
1969 
         as the next_arg_reg variable, so we split up the insns,
1970 
         and emit them separately.  */
1971 
 
1972 
      if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
1973 
        {
1974 
          rtvec adjust = XVEC (operands[3], 0);
1975 
          int num = GET_NUM_ELEM (adjust);
1976 
          int i;
1977 
 
1978 
          for (i = 0; i < num; i++)
1979 
            emit_insn (RTVEC_ELT (adjust, i));
1980 
        }
1981 
 
1982 
      if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
1983 
        {
1984 
          emit_call_insn (gen_call_value_multiple_internal0
1985 
                          (XEXP (XVECEXP (operands[0], 0, 0), 0),
1986 
                           operands[1], operands[2],
1987 
                           XEXP (XVECEXP (operands[0], 0, 1), 0),
1988 
                           gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
1989 
          DONE;
1990 
        }
1991 
 
1992 
      /* We have a call returning a DImode structure in an FP reg.
1993 
         Strip off the now unnecessary PARALLEL.  */
1994 
      if (GET_CODE (operands[0]) == PARALLEL)
1995 
        operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
1996 
 
1997 
      emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
1998 
                                                gen_rtx_REG (SImode,
1999 
                                                             GP_REG_FIRST + 31)));
2000 
 
2001 
      DONE;
2002 
    }
2003 
}")
2004 
 
2005 
(define_expand "call_value_internal0"
2006 
  [(parallel [(set (match_operand 0 "" "")
2007 
                   (call (match_operand 1 "" "")
2008 
                         (match_operand 2 "" "")))
2009 
              (clobber (match_operand:SI 3 "" ""))])]
2010 
  ""
2011 
  "")
2012 
 
2013 
(define_insn "call_value_internal1"
2014 
  [(set (match_operand 0 "register_operand" "=df")
2015 
        (call (mem (match_operand 1 "call_insn_operand" "ri"))
2016 
              (match_operand 2 "" "i")))
2017 
   (clobber (match_operand:SI 3 "register_operand" "=d"))]
2018 
  ""
2019 
  "*
2020 
{
2021 
  register rtx target = operands[1];
2022 
 
2023 
  if (GET_CODE (target) == CONST_INT)
2024 
    return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
2025 
  else if (CONSTANT_ADDRESS_P (target))
2026 
    return \"jal\\t%1\";
2027 
  else
2028 
    return \"jalr\\t%3,%1\";
2029 
}"
2030 
  [(set_attr "type"     "call")
2031 
   (set_attr "mode"     "none")])
2032 
 
2033 
(define_expand "call_value_multiple_internal0"
2034 
  [(parallel [(set (match_operand 0 "" "")
2035 
                   (call (match_operand 1 "" "")
2036 
                         (match_operand 2 "" "")))
2037 
              (set (match_operand 3 "" "")
2038 
                   (call (match_dup 1)
2039 
                         (match_dup 2)))
2040 
              (clobber (match_operand:SI 4 "" ""))])]
2041 
  ""
2042 
  "")
2043 
 
2044 
;; ??? May eventually need all 6 versions of the call patterns with multiple
2045 
;; return values.
2046 
 
2047 
(define_insn "call_value_multiple_internal1"
2048 
  [(set (match_operand 0 "register_operand" "=df")
2049 
        (call (mem (match_operand 1 "call_insn_operand" "ri"))
2050 
              (match_operand 2 "" "i")))
2051 
   (set (match_operand 3 "register_operand" "=df")
2052 
        (call (mem (match_dup 1))
2053 
              (match_dup 2)))
2054 
  (clobber (match_operand:SI 4 "register_operand" "=d"))]
2055 
  ""
2056 
  "*
2057 
{
2058 
  register rtx target = operands[1];
2059 
 
2060 
  if (GET_CODE (target) == CONST_INT)
2061 
    return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
2062 
  else if (CONSTANT_ADDRESS_P (target))
2063 
    return \"jal\\t%1\";
2064 
  else
2065 
    return \"jalr\\t%4,%1\";
2066 
}"
2067 
  [(set_attr "type"     "call")
2068 
   (set_attr "mode"     "none")])
2069 
 
2070 
;; Call subroutine returning any type.
2071 
 
2072 
(define_expand "untyped_call"
2073 
  [(parallel [(call (match_operand 0 "" "")
2074 
                    (const_int 0))
2075 
              (match_operand 1 "" "")
2076 
              (match_operand 2 "" "")])]
2077 
  ""
2078 
  "
2079 
{
2080 
  if (operands[0])              /* silence statement not reached warnings */
2081 
    {
2082 
      int i;
2083 
 
2084 
      emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
2085 
 
2086 
      for (i = 0; i < XVECLEN (operands[2], 0); i++)
2087 
        {
2088 
          rtx set = XVECEXP (operands[2], 0, i);
2089 
          emit_move_insn (SET_DEST (set), SET_SRC (set));
2090 
        }
2091 
 
2092 
      emit_insn (gen_blockage ());
2093 
      DONE;
2094 
    }
2095 
}")
2096 
 
2097 
;;
2098 
;;  ....................
2099 
;;
2100 
;;      MISC.
2101 
;;
2102 
;;  ....................
2103 
;;
2104 
 
2105 
(define_insn "nop"
2106 
  [(const_int 0)]
2107 
  ""
2108 
  "nop"
2109 
  [(set_attr "type"     "nop")
2110 
   (set_attr "mode"     "none")])
2111 
 
2112 
 
2113 
;; For the rare case where we need to load an address into a register
2114 
;; that cannot be recognized by the normal movsi/addsi instructions.
2115 
;; I have no idea how many insns this can actually generate.  It should
2116 
;; be rare, so over-estimating as 10 instructions should not have any
2117 
;; real performance impact.
2118 
(define_insn "leasi"
2119 
  [(set (match_operand:SI 0 "register_operand" "=d")
2120 
        (match_operand:SI 1 "address_operand" "p"))]
2121 
  "Pmode == SImode"
2122 
  "*
2123 
{
2124 
  rtx xoperands [3];
2125 
 
2126 
  xoperands[0] = operands[0];
2127 
  xoperands[1] = XEXP (operands[1], 0);
2128 
  xoperands[2] = XEXP (operands[1], 1);
2129 
  output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands);
2130 
  return \"\";
2131 
}"
2132 
  [(set_attr "type"     "arith")
2133 
   (set_attr "mode"     "SI")
2134 
   (set_attr "length"   "40")])
2135 
 
2136 
(define_insn "ado16"
2137 
  [(set (match_operand:SI             0 "register_operand" "=r")
2138 
        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2139 
                    (match_operand:SI 2 "register_operand" "r")]
2140 
                UNSPEC_ADO16))]
2141 
  ""
2142 
  "ado16\\t%0, %1, %2"
2143 
)
2144 
 
2145 
(define_insn "ram"
2146 
  [(set (match_operand:SI             0 "register_operand" "=r")
2147 
              (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2148 
                                (match_operand:SI 2 "const_int_operand" "I")
2149 
                                (match_operand:SI 3 "const_int_operand" "I")
2150 
                                (match_operand:SI 4 "const_int_operand" "I")]
2151 
                     UNSPEC_RAM))]
2152 
  ""
2153 
  "ram\\t%0, %1, %2, %3, %4"
2154 
)
2155 
 
2156 
(define_insn "chkhdr"
2157 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r")
2158 
                (match_operand:SI 1 "register_operand" "r")]
2159 
                UNSPEC_CHKHDR)]
2160 
  ""
2161 
  "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);"
2162 
  [(set_attr "dslot"    "not_in_dslot")]
2163 
)
2164 
 
2165 
(define_insn "pkrl"
2166 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2167 
                (match_operand:SI 1 "register_operand" "r")]
2168 
                UNSPEC_PKRL)]
2169 
  ""
2170 
  "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);"
2171 
  [(set_attr "dslot"    "not_in_dslot")]
2172 
)
2173 
 
2174 
(define_insn "cfc0"
2175 
   [(set (match_operand:SI                0 "register_operand" "=r")
2176 
    (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2177 
                UNSPEC_CFC0))]
2178 
  ""
2179 
  "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2180 
  [(set_attr "dslot"    "ok_in_dslot")]
2181 
)
2182 
 
2183 
(define_insn "cfc1"
2184 
   [(set (match_operand:SI                0 "register_operand" "=r")
2185 
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2186 
                UNSPEC_CFC1))]
2187 
  ""
2188 
  "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2189 
  [(set_attr "dslot"    "ok_in_dslot")]
2190 
)
2191 
 
2192 
(define_insn "cfc2"
2193 
   [(set (match_operand:SI                0 "register_operand" "=r")
2194 
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2195 
                UNSPEC_CFC2))]
2196 
  ""
2197 
  "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2198 
  [(set_attr "dslot"    "not_in_dslot")]
2199 
)
2200 
 
2201 
(define_insn "cfc3"
2202 
   [(set (match_operand:SI                0 "register_operand" "=r")
2203 
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2204 
                UNSPEC_CFC3))]
2205 
  ""
2206 
  "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2207 
  [(set_attr "dslot"    "not_in_dslot")]
2208 
)
2209 
 
2210 
(define_insn "ctc0"
2211 
  [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2212 
                (match_operand:SI 1 "const_int_operand" "I")]
2213 
                UNSPEC_CTC0)]
2214 
  ""
2215 
  "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2216 
  [(set_attr "dslot"    "ok_in_dslot")]
2217 
)
2218 
 
2219 
(define_insn "ctc1"
2220 
  [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2221 
                (match_operand:SI 1 "const_int_operand" "I")]
2222 
                UNSPEC_CTC1)]
2223 
  ""
2224 
  "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2225 
  [(set_attr "dslot"    "ok_in_dslot")]
2226 
)
2227 
 
2228 
(define_insn "ctc2"
2229 
  [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2230 
                (match_operand:SI 1 "const_int_operand" "I")]
2231 
                UNSPEC_CTC2)]
2232 
  ""
2233 
  "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2234 
  [(set_attr "dslot"    "ok_in_dslot")]
2235 
)
2236 
 
2237 
(define_insn "ctc3"
2238 
  [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2239 
                (match_operand:SI 1 "const_int_operand" "I")]
2240 
                UNSPEC_CTC3)]
2241 
  ""
2242 
  "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2243 
  [(set_attr "dslot"    "ok_in_dslot")]
2244 
)
2245 
 
2246 
(define_insn "mfc0"
2247 
   [(set (match_operand:SI                0 "register_operand" "=r")
2248 
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2249 
                UNSPEC_MFC0))]
2250 
  ""
2251 
  "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2252 
  [(set_attr "dslot"    "ok_in_dslot")]
2253 
)
2254 
 
2255 
(define_insn "mfc1"
2256 
   [(set (match_operand:SI                0 "register_operand" "=r")
2257 
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2258 
                UNSPEC_MFC1))]
2259 
  ""
2260 
  "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2261 
  [(set_attr "dslot"    "ok_in_dslot")]
2262 
)
2263 
 
2264 
(define_insn "mfc2"
2265 
   [(set (match_operand:SI                0 "register_operand" "=r")
2266 
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2267 
                UNSPEC_MFC2))]
2268 
  ""
2269 
  "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2270 
  [(set_attr "dslot"    "not_in_dslot")]
2271 
)
2272 
 
2273 
(define_insn "mfc3"
2274 
   [(set (match_operand:SI                0 "register_operand" "=r")
2275 
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2276 
                UNSPEC_MFC3))]
2277 
  ""
2278 
  "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2279 
  [(set_attr "dslot"    "not_in_dslot")]
2280 
)
2281 
 
2282 
(define_insn "mtc0"
2283 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2284 
                (match_operand:SI 1 "const_int_operand" "I")]
2285 
                UNSPEC_MTC0)]
2286 
  ""
2287 
  "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2288 
  [(set_attr "dslot"    "ok_in_dslot")]
2289 
)
2290 
 
2291 
(define_insn "mtc1"
2292 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2293 
                (match_operand:SI 1 "const_int_operand" "I")]
2294 
                UNSPEC_MTC1)]
2295 
  ""
2296 
  "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2297 
  [(set_attr "dslot"    "ok_in_dslot")]
2298 
)
2299 
 
2300 
(define_insn "mtc2"
2301 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2302 
                (match_operand:SI 1 "const_int_operand" "I")]
2303 
                UNSPEC_MTC2)]
2304 
  ""
2305 
  "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2306 
  [(set_attr "dslot"    "ok_in_dslot")]
2307 
)
2308 
 
2309 
(define_insn "mtc3"
2310 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2311 
                (match_operand:SI 1 "const_int_operand" "I")]
2312 
                UNSPEC_MTC3)]
2313 
  ""
2314 
  "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2315 
  [(set_attr "dslot"    "ok_in_dslot")]
2316 
)
2317 
 
2318 
(define_insn "lur"
2319 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2320 
                (match_operand:SI 1 "register_operand" "r")]
2321 
                UNSPEC_LUR)]
2322 
  ""
2323 
  "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);"
2324 
  [(set_attr "dslot"    "not_in_dslot")]
2325 
)
2326 
 
2327 
(define_insn "rb"
2328 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2329 
                (match_operand:SI 1 "register_operand" "r")]
2330 
                UNSPEC_RB)]
2331 
  ""
2332 
  "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);"
2333 
  [(set_attr "dslot"    "not_in_dslot")]
2334 
)
2335 
 
2336 
(define_insn "rx"
2337 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2338 
                (match_operand:SI 1 "register_operand" "r")]
2339 
                UNSPEC_RX)]
2340 
  ""
2341 
  "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);"
2342 
  [(set_attr "dslot"    "not_in_dslot")]
2343 
)
2344 
 
2345 
(define_insn "srrd"
2346 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2347 
                UNSPEC_SRRD)]
2348 
  ""
2349 
  "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);"
2350 
  [(set_attr "dslot"    "not_in_dslot")]
2351 
)
2352 
 
2353 
(define_insn "srwr"
2354 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2355 
                (match_operand:SI 1 "register_operand" "r")]
2356 
                UNSPEC_SRWR)]
2357 
  ""
2358 
  "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);"
2359 
  [(set_attr "dslot"    "not_in_dslot")]
2360 
)
2361 
 
2362 
(define_insn "wb"
2363 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2364 
                (match_operand:SI 1 "register_operand" "r")]
2365 
                UNSPEC_WB)]
2366 
  ""
2367 
  "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);"
2368 
  [(set_attr "dslot"    "not_in_dslot")]
2369 
)
2370 
 
2371 
(define_insn "wx"
2372 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2373 
                (match_operand:SI 1 "register_operand" "r")]
2374 
                UNSPEC_WX)]
2375 
  ""
2376 
  "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);"
2377 
  [(set_attr "dslot"    "not_in_dslot")]
2378 
)
2379 
 
2380 
(define_insn "luc32"
2381 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2382 
                (match_operand:SI 1 "register_operand" "r")]
2383 
                UNSPEC_LUC32)]
2384 
  ""
2385 
  "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);"
2386 
  [(set_attr "dslot"    "not_in_dslot")]
2387 
)
2388 
 
2389 
(define_insn "luc32l"
2390 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2391 
                (match_operand:SI 1 "register_operand" "r")]
2392 
                UNSPEC_LUC32L)]
2393 
  ""
2394 
  "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2395 
  [(set_attr "dslot"    "not_in_dslot")]
2396 
)
2397 
 
2398 
(define_insn "luc64"
2399 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2400 
                (match_operand:SI 1 "register_operand" "r")]
2401 
                UNSPEC_LUC64)]
2402 
  ""
2403 
  "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);"
2404 
  [(set_attr "dslot"    "not_in_dslot")]
2405 
)
2406 
 
2407 
(define_insn "luc64l"
2408 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2409 
                (match_operand:SI 1 "register_operand" "r")]
2410 
                UNSPEC_LUC64L)]
2411 
  ""
2412 
  "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2413 
  [(set_attr "dslot"    "not_in_dslot")]
2414 
)
2415 
 
2416 
(define_insn "luk"
2417 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2418 
                (match_operand:SI 1 "register_operand" "r")]
2419 
                UNSPEC_LUK)]
2420 
  ""
2421 
  "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);"
2422 
  [(set_attr "dslot"    "ok_in_dslot")]
2423 
)
2424 
 
2425 
(define_insn "lulck"
2426 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2427 
                UNSPEC_LULCK)]
2428 
  ""
2429 
  "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);"
2430 
  [(set_attr "dslot"    "not_in_dslot")]
2431 
)
2432 
 
2433 
(define_insn "lum32"
2434 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2435 
                (match_operand:SI 1 "register_operand" "r")]
2436 
                UNSPEC_LUM32)]
2437 
  ""
2438 
  "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);"
2439 
  [(set_attr "dslot"    "not_in_dslot")]
2440 
)
2441 
 
2442 
(define_insn "lum32l"
2443 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2444 
                (match_operand:SI 1 "register_operand" "r")]
2445 
                UNSPEC_LUM32L)]
2446 
  ""
2447 
  "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2448 
  [(set_attr "dslot"    "not_in_dslot")]
2449 
)
2450 
 
2451 
(define_insn "lum64"
2452 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2453 
                (match_operand:SI 1 "register_operand" "r")]
2454 
                UNSPEC_LUM64)]
2455 
  ""
2456 
  "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);"
2457 
  [(set_attr "dslot"    "not_in_dslot")]
2458 
)
2459 
 
2460 
(define_insn "lum64l"
2461 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2462 
                (match_operand:SI 1 "register_operand" "r")]
2463 
                UNSPEC_LUM64L)]
2464 
  ""
2465 
  "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2466 
  [(set_attr "dslot"    "not_in_dslot")]
2467 
)
2468 
 
2469 
(define_insn "lurl"
2470 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2471 
                (match_operand:SI 1 "register_operand" "r")]
2472 
                UNSPEC_LURL)]
2473 
  ""
2474 
  "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);"
2475 
  [(set_attr "dslot"    "not_in_dslot")]
2476 
)
2477 
 
2478 
(define_insn "mrgb"
2479 
  [(set (match_operand:SI                 0 "register_operand" "=r")
2480 
        (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
2481 
                (match_operand:SI 2 "register_operand" "r")
2482 
                (match_operand:SI 3 "const_int_operand" "I")]
2483 
                UNSPEC_MRGB))]
2484 
  ""
2485 
  "* return iq2000_fill_delay_slot (\"mrgb\\t%0, %1, %2, %3\", DELAY_LOAD, operands, insn);"
2486 
  [(set_attr "dslot"    "ok_in_dslot")]
2487 
)
2488 
 
2489 
(define_insn "srrdl"
2490 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2491 
                UNSPEC_SRRDL)]
2492 
  ""
2493 
  "* return iq2000_fill_delay_slot (\"srrdl\\t%0\", DELAY_NONE, operands, insn);"
2494 
  [(set_attr "dslot"    "not_in_dslot")]
2495 
)
2496 
 
2497 
(define_insn "srulck"
2498 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2499 
                UNSPEC_SRULCK)]
2500 
  ""
2501 
  "* return iq2000_fill_delay_slot (\"srulck\\t%0\", DELAY_NONE, operands, insn);"
2502 
  [(set_attr "dslot"    "not_in_dslot")]
2503 
)
2504 
 
2505 
(define_insn "srwru"
2506 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2507 
                (match_operand:SI 1 "register_operand" "r")]
2508 
                UNSPEC_SRWRU)]
2509 
  ""
2510 
  "* return iq2000_fill_delay_slot (\"srwru\\t%0, %1\", DELAY_NONE, operands, insn);"
2511 
  [(set_attr "dslot"    "not_in_dslot")]
2512 
)
2513 
 
2514 
(define_insn "trapqfl"
2515 
  [(unspec_volatile:SI [(const_int 1)] UNSPEC_TRAPQFL)]
2516 
  ""
2517 
  "* return iq2000_fill_delay_slot (\"trapqfl\", DELAY_NONE, operands, insn);"
2518 
  [(set_attr "dslot"    "not_in_dslot")]
2519 
)
2520 
 
2521 
(define_insn "trapqne"
2522 
  [(unspec_volatile:SI [(const_int 2)] UNSPEC_TRAPQNE)]
2523 
  ""
2524 
  "* return iq2000_fill_delay_slot (\"trapqne\", DELAY_NONE, operands, insn);"
2525 
  [(set_attr "dslot"    "not_in_dslot")]
2526 
)
2527 
 
2528 
(define_insn "traprel"
2529 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2530 
                UNSPEC_TRAPREL)]
2531 
  ""
2532 
  "* return iq2000_fill_delay_slot (\"traprel %0\", DELAY_NONE, operands, insn);"
2533 
  [(set_attr "dslot"    "not_in_dslot")]
2534 
)
2535 
 
2536 
(define_insn "wbu"
2537 
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2538 
                (match_operand:SI 1 "register_operand" "r")]
2539 
                UNSPEC_WBU)]
2540 
  ""
2541 
  "* return iq2000_fill_delay_slot (\"wbu\\t%0, %1\", DELAY_NONE, operands, insn);"
2542 
  [(set_attr "dslot"    "not_in_dslot")]
2543 
)
2544 
 
2545 
(define_insn "syscall"
2546 
  [(unspec_volatile:SI [(const_int 2)] UNSPEC_SYSCALL)]
2547 
  ""
2548 
  "syscall"
2549 
  [(set_attr "dslot"    "not_in_dslot")]
2550 
)

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