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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [m32c/] [muldiv.md] - Blame information for rev 154

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1 38 julius
;; Machine Descriptions for R8C/M16C/M32C
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;; Copyright (C) 2005, 2007
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;; Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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;; multiply and divide
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; Here is the pattern for the const_int.
25
(define_insn "mulqihi3_c"
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  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
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                 (match_operand 2 "immediate_operand" "i,i")))]
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  ""
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  "mul.b\t%2,%1"
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  [(set_attr "flags" "o")]
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)
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; Here is the pattern for registers and such.
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(define_insn "mulqihi3_r"
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  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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                 (sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
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  ""
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  "mul.b\t%2,%1"
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  [(set_attr "flags" "o")]
42
)
43
 
44
; Don't try to sign_extend a const_int.  Same for all other multiplies.
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(define_expand "mulqihi3"
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  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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                 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
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  ""
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  "{ if (GET_MODE (operands[2]) != VOIDmode)
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      operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
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)
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54
(define_insn "umulqihi3_c"
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  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
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                 (match_operand 2 "immediate_operand" "i,i")))]
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  ""
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  "mulu.b\t%U2,%1"
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  [(set_attr "flags" "o")]
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)
62
 
63
(define_insn "umulqihi3_r"
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  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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                 (zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
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  ""
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  "mulu.b\t%U2,%1"
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  [(set_attr "flags" "o")]
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)
71
 
72
(define_expand "umulqihi3"
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  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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                 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
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  ""
77
  "{ if (GET_MODE (operands[2]) != VOIDmode)
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      operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
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)
80
 
81
(define_insn "mulhisi3_c"
82
  [(set (match_operand:SI 0 "ra_operand" "=Rsi")
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        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
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                 (match_operand 2 "immediate_operand" "i")))]
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  ""
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  "mul.w\t%2,%1"
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  [(set_attr "flags" "o")]
88
)
89
 
90
(define_insn "mulhisi3_r"
91
  [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
92
        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
93
                 (sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
94
  ""
95
  "mul.w\t%2,%1"
96
  [(set_attr "flags" "o")]
97
)
98
 
99
(define_expand "mulhisi3"
100
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
101
        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
102
                 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
103
  ""
104
  "{ if (GET_MODE (operands[2]) != VOIDmode)
105
      operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
106
)
107
 
108
(define_insn "umulhisi3_c"
109
  [(set (match_operand:SI 0 "ra_operand" "=Rsi")
110
        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
111
                 (match_operand 2 "immediate_operand" "i")))]
112
  ""
113
  "mulu.w\t%u2,%1"
114
  [(set_attr "flags" "o")]
115
)
116
 
117
(define_insn "umulhisi3_r"
118
  [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
119
        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
120
                 (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
121
  ""
122
  "mulu.w\t%u2,%1"
123
  [(set_attr "flags" "o")]
124
)
125
 
126
(define_expand "umulhisi3"
127
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
128
        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
129
                 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
130
  ""
131
  "{ if (GET_MODE (operands[2]) != VOIDmode)
132
      operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
133
)
134
 
135
 
136
; GCC expects to be able to multiply pointer-sized integers too, but
137
; fortunately it only multiplies by powers of two, although sometimes
138
; they're negative.
139
(define_insn "mulpsi3_op"
140
  [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
141
        (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
142
                  (match_operand 2 "m32c_psi_scale" "Ilb")))]
143
  "TARGET_A24"
144
  "shl.l\t%b2,%0"
145
  [(set_attr "flags" "szc")]
146
  )
147
 
148
(define_expand "mulpsi3"
149
  [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
150
        (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
151
                  (match_operand 2 "m32c_psi_scale" "Ilb")))]
152
  "TARGET_A24"
153
  "if (GET_CODE (operands[2]) != CONST_INT
154
       || ! m32c_psi_scale (operands[2], PSImode))
155
     {
156
       m32c_expand_neg_mulpsi3 (operands);
157
       DONE;
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     }"
159
  )
160
 
161
 
162
 
163
(define_expand "divmodqi4"
164
  [(set (match_dup 4)
165
        (sign_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
166
   (parallel [(set (match_operand:QI 0 "register_operand" "=R0w,R0w")
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                   (div:QI (match_dup 4)
168
                           (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
169
              (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
170
                   (mod:QI (match_dup 4) (match_dup 2)))
171
              ])]
172
  "0"
173
  "operands[4] = gen_reg_rtx (HImode);"
174
  )
175
 
176
(define_insn "divmodqi4_n"
177
  [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
178
        (div:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
179
                (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
180
   (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
181
        (mod:QI (match_dup 1) (match_dup 2)))
182
   ]
183
  "0"
184
  "div.b\t%2"
185
  [(set_attr "flags" "o")]
186
  )
187
 
188
(define_expand "udivmodqi4"
189
  [(set (match_dup 4)
190
        (zero_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
191
   (parallel [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
192
                   (udiv:QI (match_dup 4)
193
                           (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
194
              (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
195
                   (umod:QI (match_dup 4) (match_dup 2)))
196
              ])]
197
  "0"
198
  "operands[4] = gen_reg_rtx (HImode);"
199
  )
200
 
201
(define_insn "udivmodqi4_n"
202
  [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
203
        (udiv:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
204
                (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
205
   (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
206
        (umod:QI (match_dup 1) (match_dup 2)))
207
   ]
208
  "0"
209
  "divu.b\t%2"
210
  [(set_attr "flags" "o")]
211
  )
212
 
213
(define_expand "divmodhi4"
214
  [(set (match_dup 4)
215
        (sign_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
216
   (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
217
                   (div:HI (match_dup 4)
218
                           (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
219
              (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
220
                   (mod:HI (match_dup 4) (match_dup 2)))
221
              ])]
222
  ""
223
  "operands[4] = gen_reg_rtx (SImode);"
224
  )
225
 
226
(define_insn "divmodhi4_n"
227
  [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
228
        (div:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
229
                (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
230
   (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
231
        (mod:HI (match_dup 1) (match_dup 2)))
232
   ]
233
  ""
234
  "div.w\t%2"
235
  [(set_attr "flags" "o")]
236
  )
237
 
238
(define_expand "udivmodhi4"
239
  [(set (match_dup 4)
240
        (zero_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
241
   (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
242
                   (udiv:HI (match_dup 4)
243
                           (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
244
              (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
245
                   (umod:HI (match_dup 4) (match_dup 2)))
246
              ])]
247
  ""
248
  "operands[4] = gen_reg_rtx (SImode);"
249
  )
250
 
251
(define_insn "udivmodhi4_n"
252
  [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
253
        (udiv:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
254
                (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
255
   (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
256
        (umod:HI (match_dup 1) (match_dup 2)))
257
   ]
258
  ""
259
  "divu.w\t%2"
260
  [(set_attr "flags" "o")]
261
  )

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