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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [m32r/] [m32r.c] - Blame information for rev 199

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1 38 julius
/* Subroutines used for code generation on the Renesas M32R cpu.
2
   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3
   2005, 2007 Free Software Foundation, Inc.
4
 
5
   This file is part of GCC.
6
 
7
   GCC is free software; you can redistribute it and/or modify it
8
   under the terms of the GNU General Public License as published
9
   by the Free Software Foundation; either version 3, or (at your
10
   option) any later version.
11
 
12
   GCC is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GCC; see the file COPYING3.  If not see
19
   <http://www.gnu.org/licenses/>.  */
20
 
21
#include "config.h"
22
#include "system.h"
23
#include "coretypes.h"
24
#include "tm.h"
25
#include "tree.h"
26
#include "rtl.h"
27
#include "regs.h"
28
#include "hard-reg-set.h"
29
#include "real.h"
30
#include "insn-config.h"
31
#include "conditions.h"
32
#include "output.h"
33
#include "insn-attr.h"
34
#include "flags.h"
35
#include "expr.h"
36
#include "function.h"
37
#include "recog.h"
38
#include "toplev.h"
39
#include "ggc.h"
40
#include "integrate.h"
41
#include "tm_p.h"
42
#include "target.h"
43
#include "target-def.h"
44
 
45
/* Save the operands last given to a compare for use when we
46
   generate a scc or bcc insn.  */
47
rtx m32r_compare_op0, m32r_compare_op1;
48
 
49
/* Array of valid operand punctuation characters.  */
50
char m32r_punct_chars[256];
51
 
52
/* Selected code model.  */
53
enum m32r_model m32r_model = M32R_MODEL_DEFAULT;
54
 
55
/* Selected SDA support.  */
56
enum m32r_sdata m32r_sdata = M32R_SDATA_DEFAULT;
57
 
58
/* Machine-specific symbol_ref flags.  */
59
#define SYMBOL_FLAG_MODEL_SHIFT         SYMBOL_FLAG_MACH_DEP_SHIFT
60
#define SYMBOL_REF_MODEL(X) \
61
  ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
62
 
63
/* For string literals, etc.  */
64
#define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
65
 
66
/* Forward declaration.  */
67
static bool  m32r_handle_option (size_t, const char *, int);
68
static void  init_reg_tables (void);
69
static void  block_move_call (rtx, rtx, rtx);
70
static int   m32r_is_insn (rtx);
71
const struct attribute_spec m32r_attribute_table[];
72
static tree  m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
73
static void  m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
74
static void  m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
75
 
76
static void  m32r_file_start (void);
77
 
78
static int    m32r_adjust_priority (rtx, int);
79
static int    m32r_issue_rate (void);
80
 
81
static void m32r_encode_section_info (tree, rtx, int);
82
static bool m32r_in_small_data_p (tree);
83
static bool m32r_return_in_memory (tree, tree);
84
static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
85
                                         tree, int *, int);
86
static void init_idents (void);
87
static bool m32r_rtx_costs (rtx, int, int, int *);
88
static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
89
                                    tree, bool);
90
static int m32r_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
91
                                   tree, bool);
92
 
93
/* Initialize the GCC target structure.  */
94
#undef  TARGET_ATTRIBUTE_TABLE
95
#define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
96
 
97
#undef  TARGET_ASM_ALIGNED_HI_OP
98
#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
99
#undef  TARGET_ASM_ALIGNED_SI_OP
100
#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
101
 
102
#undef  TARGET_ASM_FUNCTION_PROLOGUE
103
#define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
104
#undef  TARGET_ASM_FUNCTION_EPILOGUE
105
#define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
106
 
107
#undef  TARGET_ASM_FILE_START
108
#define TARGET_ASM_FILE_START m32r_file_start
109
 
110
#undef  TARGET_SCHED_ADJUST_PRIORITY
111
#define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
112
#undef  TARGET_SCHED_ISSUE_RATE
113
#define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
114
 
115
#undef  TARGET_DEFAULT_TARGET_FLAGS
116
#define TARGET_DEFAULT_TARGET_FLAGS TARGET_CPU_DEFAULT
117
#undef  TARGET_HANDLE_OPTION
118
#define TARGET_HANDLE_OPTION m32r_handle_option
119
 
120
#undef  TARGET_ENCODE_SECTION_INFO
121
#define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
122
#undef  TARGET_IN_SMALL_DATA_P
123
#define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
124
 
125
#undef  TARGET_RTX_COSTS
126
#define TARGET_RTX_COSTS m32r_rtx_costs
127
#undef  TARGET_ADDRESS_COST
128
#define TARGET_ADDRESS_COST hook_int_rtx_0
129
 
130
#undef  TARGET_PROMOTE_PROTOTYPES
131
#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
132
#undef  TARGET_RETURN_IN_MEMORY
133
#define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
134
#undef  TARGET_SETUP_INCOMING_VARARGS
135
#define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
136
#undef  TARGET_MUST_PASS_IN_STACK
137
#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
138
#undef  TARGET_PASS_BY_REFERENCE
139
#define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
140
#undef  TARGET_ARG_PARTIAL_BYTES
141
#define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
142
 
143
struct gcc_target targetm = TARGET_INITIALIZER;
144
 
145
/* Implement TARGET_HANDLE_OPTION.  */
146
 
147
static bool
148
m32r_handle_option (size_t code, const char *arg, int value)
149
{
150
  switch (code)
151
    {
152
    case OPT_m32r:
153
      target_flags &= ~(MASK_M32R2 | MASK_M32RX);
154
      return true;
155
 
156
    case OPT_mmodel_:
157
      if (strcmp (arg, "small") == 0)
158
        m32r_model = M32R_MODEL_SMALL;
159
      else if (strcmp (arg, "medium") == 0)
160
        m32r_model = M32R_MODEL_MEDIUM;
161
      else if (strcmp (arg, "large") == 0)
162
        m32r_model = M32R_MODEL_LARGE;
163
      else
164
        return false;
165
      return true;
166
 
167
    case OPT_msdata_:
168
      if (strcmp (arg, "none") == 0)
169
        m32r_sdata = M32R_SDATA_NONE;
170
      else if (strcmp (arg, "sdata") == 0)
171
        m32r_sdata = M32R_SDATA_SDATA;
172
      else if (strcmp (arg, "use") == 0)
173
        m32r_sdata = M32R_SDATA_USE;
174
      else
175
        return false;
176
      return true;
177
 
178
    case OPT_mno_flush_func:
179
      m32r_cache_flush_func = NULL;
180
      return true;
181
 
182
    case OPT_mflush_trap_:
183
      return value <= 15;
184
 
185
    case OPT_mno_flush_trap:
186
      m32r_cache_flush_trap = -1;
187
      return true;
188
 
189
    default:
190
      return true;
191
    }
192
}
193
 
194
/* Called by OVERRIDE_OPTIONS to initialize various things.  */
195
 
196
void
197
m32r_init (void)
198
{
199
  init_reg_tables ();
200
 
201
  /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P.  */
202
  memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
203
  m32r_punct_chars['#'] = 1;
204
  m32r_punct_chars['@'] = 1; /* ??? no longer used */
205
 
206
  /* Provide default value if not specified.  */
207
  if (!g_switch_set)
208
    g_switch_value = SDATA_DEFAULT_SIZE;
209
}
210
 
211
/* Vectors to keep interesting information about registers where it can easily
212
   be got.  We use to use the actual mode value as the bit number, but there
213
   is (or may be) more than 32 modes now.  Instead we use two tables: one
214
   indexed by hard register number, and one indexed by mode.  */
215
 
216
/* The purpose of m32r_mode_class is to shrink the range of modes so that
217
   they all fit (as bit numbers) in a 32 bit word (again).  Each real mode is
218
   mapped into one m32r_mode_class mode.  */
219
 
220
enum m32r_mode_class
221
{
222
  C_MODE,
223
  S_MODE, D_MODE, T_MODE, O_MODE,
224
  SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
225
};
226
 
227
/* Modes for condition codes.  */
228
#define C_MODES (1 << (int) C_MODE)
229
 
230
/* Modes for single-word and smaller quantities.  */
231
#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
232
 
233
/* Modes for double-word and smaller quantities.  */
234
#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
235
 
236
/* Modes for quad-word and smaller quantities.  */
237
#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
238
 
239
/* Modes for accumulators.  */
240
#define A_MODES (1 << (int) A_MODE)
241
 
242
/* Value is 1 if register/mode pair is acceptable on arc.  */
243
 
244
const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
245
{
246
  T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
247
  T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
248
  S_MODES, C_MODES, A_MODES, A_MODES
249
};
250
 
251
unsigned int m32r_mode_class [NUM_MACHINE_MODES];
252
 
253
enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
254
 
255
static void
256
init_reg_tables (void)
257
{
258
  int i;
259
 
260
  for (i = 0; i < NUM_MACHINE_MODES; i++)
261
    {
262
      switch (GET_MODE_CLASS (i))
263
        {
264
        case MODE_INT:
265
        case MODE_PARTIAL_INT:
266
        case MODE_COMPLEX_INT:
267
          if (GET_MODE_SIZE (i) <= 4)
268
            m32r_mode_class[i] = 1 << (int) S_MODE;
269
          else if (GET_MODE_SIZE (i) == 8)
270
            m32r_mode_class[i] = 1 << (int) D_MODE;
271
          else if (GET_MODE_SIZE (i) == 16)
272
            m32r_mode_class[i] = 1 << (int) T_MODE;
273
          else if (GET_MODE_SIZE (i) == 32)
274
            m32r_mode_class[i] = 1 << (int) O_MODE;
275
          else
276
            m32r_mode_class[i] = 0;
277
          break;
278
        case MODE_FLOAT:
279
        case MODE_COMPLEX_FLOAT:
280
          if (GET_MODE_SIZE (i) <= 4)
281
            m32r_mode_class[i] = 1 << (int) SF_MODE;
282
          else if (GET_MODE_SIZE (i) == 8)
283
            m32r_mode_class[i] = 1 << (int) DF_MODE;
284
          else if (GET_MODE_SIZE (i) == 16)
285
            m32r_mode_class[i] = 1 << (int) TF_MODE;
286
          else if (GET_MODE_SIZE (i) == 32)
287
            m32r_mode_class[i] = 1 << (int) OF_MODE;
288
          else
289
            m32r_mode_class[i] = 0;
290
          break;
291
        case MODE_CC:
292
          m32r_mode_class[i] = 1 << (int) C_MODE;
293
          break;
294
        default:
295
          m32r_mode_class[i] = 0;
296
          break;
297
        }
298
    }
299
 
300
  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
301
    {
302
      if (GPR_P (i))
303
        m32r_regno_reg_class[i] = GENERAL_REGS;
304
      else if (i == ARG_POINTER_REGNUM)
305
        m32r_regno_reg_class[i] = GENERAL_REGS;
306
      else
307
        m32r_regno_reg_class[i] = NO_REGS;
308
    }
309
}
310
 
311
/* M32R specific attribute support.
312
 
313
   interrupt - for interrupt functions
314
 
315
   model - select code model used to access object
316
 
317
        small: addresses use 24 bits, use bl to make calls
318
        medium: addresses use 32 bits, use bl to make calls
319
        large: addresses use 32 bits, use seth/add3/jl to make calls
320
 
321
        Grep for MODEL in m32r.h for more info.  */
322
 
323
static tree small_ident1;
324
static tree small_ident2;
325
static tree medium_ident1;
326
static tree medium_ident2;
327
static tree large_ident1;
328
static tree large_ident2;
329
 
330
static void
331
init_idents (void)
332
{
333
  if (small_ident1 == 0)
334
    {
335
      small_ident1 = get_identifier ("small");
336
      small_ident2 = get_identifier ("__small__");
337
      medium_ident1 = get_identifier ("medium");
338
      medium_ident2 = get_identifier ("__medium__");
339
      large_ident1 = get_identifier ("large");
340
      large_ident2 = get_identifier ("__large__");
341
    }
342
}
343
 
344
const struct attribute_spec m32r_attribute_table[] =
345
{
346
  /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
347
  { "interrupt", 0, 0, true,  false, false, NULL },
348
  { "model",     1, 1, true,  false, false, m32r_handle_model_attribute },
349
  { NULL,        0, 0, false, false, false, NULL }
350
};
351
 
352
 
353
/* Handle an "model" attribute; arguments as in
354
   struct attribute_spec.handler.  */
355
static tree
356
m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
357
                             tree args, int flags ATTRIBUTE_UNUSED,
358
                             bool *no_add_attrs)
359
{
360
  tree arg;
361
 
362
  init_idents ();
363
  arg = TREE_VALUE (args);
364
 
365
  if (arg != small_ident1
366
      && arg != small_ident2
367
      && arg != medium_ident1
368
      && arg != medium_ident2
369
      && arg != large_ident1
370
      && arg != large_ident2)
371
    {
372
      warning (OPT_Wattributes, "invalid argument of %qs attribute",
373
               IDENTIFIER_POINTER (name));
374
      *no_add_attrs = true;
375
    }
376
 
377
  return NULL_TREE;
378
}
379
 
380
/* Encode section information of DECL, which is either a VAR_DECL,
381
   FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
382
 
383
   For the M32R we want to record:
384
 
385
   - whether the object lives in .sdata/.sbss.
386
   - what code model should be used to access the object
387
*/
388
 
389
static void
390
m32r_encode_section_info (tree decl, rtx rtl, int first)
391
{
392
  int extra_flags = 0;
393
  tree model_attr;
394
  enum m32r_model model;
395
 
396
  default_encode_section_info (decl, rtl, first);
397
 
398
  if (!DECL_P (decl))
399
    return;
400
 
401
  model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
402
  if (model_attr)
403
    {
404
      tree id;
405
 
406
      init_idents ();
407
 
408
      id = TREE_VALUE (TREE_VALUE (model_attr));
409
 
410
      if (id == small_ident1 || id == small_ident2)
411
        model = M32R_MODEL_SMALL;
412
      else if (id == medium_ident1 || id == medium_ident2)
413
        model = M32R_MODEL_MEDIUM;
414
      else if (id == large_ident1 || id == large_ident2)
415
        model = M32R_MODEL_LARGE;
416
      else
417
        gcc_unreachable (); /* shouldn't happen */
418
    }
419
  else
420
    {
421
      if (TARGET_MODEL_SMALL)
422
        model = M32R_MODEL_SMALL;
423
      else if (TARGET_MODEL_MEDIUM)
424
        model = M32R_MODEL_MEDIUM;
425
      else if (TARGET_MODEL_LARGE)
426
        model = M32R_MODEL_LARGE;
427
      else
428
        gcc_unreachable (); /* shouldn't happen */
429
    }
430
  extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
431
 
432
  if (extra_flags)
433
    SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
434
}
435
 
436
/* Only mark the object as being small data area addressable if
437
   it hasn't been explicitly marked with a code model.
438
 
439
   The user can explicitly put an object in the small data area with the
440
   section attribute.  If the object is in sdata/sbss and marked with a
441
   code model do both [put the object in .sdata and mark it as being
442
   addressed with a specific code model - don't mark it as being addressed
443
   with an SDA reloc though].  This is ok and might be useful at times.  If
444
   the object doesn't fit the linker will give an error.  */
445
 
446
static bool
447
m32r_in_small_data_p (tree decl)
448
{
449
  tree section;
450
 
451
  if (TREE_CODE (decl) != VAR_DECL)
452
    return false;
453
 
454
  if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
455
    return false;
456
 
457
  section = DECL_SECTION_NAME (decl);
458
  if (section)
459
    {
460
      char *name = (char *) TREE_STRING_POINTER (section);
461
      if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
462
        return true;
463
    }
464
  else
465
    {
466
      if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
467
        {
468
          int size = int_size_in_bytes (TREE_TYPE (decl));
469
 
470
          if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
471
            return true;
472
        }
473
    }
474
 
475
  return false;
476
}
477
 
478
/* Do anything needed before RTL is emitted for each function.  */
479
 
480
void
481
m32r_init_expanders (void)
482
{
483
  /* ??? At one point there was code here.  The function is left in
484
     to make it easy to experiment.  */
485
}
486
 
487
int
488
call_operand (rtx op, enum machine_mode mode)
489
{
490
  if (GET_CODE (op) != MEM)
491
    return 0;
492
  op = XEXP (op, 0);
493
  return call_address_operand (op, mode);
494
}
495
 
496
/* Return 1 if OP is a reference to an object in .sdata/.sbss.  */
497
 
498
int
499
small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
500
{
501
  if (! TARGET_SDATA_USE)
502
    return 0;
503
 
504
  if (GET_CODE (op) == SYMBOL_REF)
505
    return SYMBOL_REF_SMALL_P (op);
506
 
507
  if (GET_CODE (op) == CONST
508
      && GET_CODE (XEXP (op, 0)) == PLUS
509
      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
510
      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
511
      && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
512
    return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
513
 
514
  return 0;
515
}
516
 
517
/* Return 1 if OP is a symbol that can use 24 bit addressing.  */
518
 
519
int
520
addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
521
{
522
  rtx sym;
523
 
524
  if (flag_pic)
525
    return 0;
526
 
527
  if (GET_CODE (op) == LABEL_REF)
528
    return TARGET_ADDR24;
529
 
530
  if (GET_CODE (op) == SYMBOL_REF)
531
    sym = op;
532
  else if (GET_CODE (op) == CONST
533
           && GET_CODE (XEXP (op, 0)) == PLUS
534
           && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
535
           && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
536
           && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
537
    sym = XEXP (XEXP (op, 0), 0);
538
  else
539
    return 0;
540
 
541
  if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
542
    return 1;
543
 
544
  if (TARGET_ADDR24
545
      && (CONSTANT_POOL_ADDRESS_P (sym)
546
          || LIT_NAME_P (XSTR (sym, 0))))
547
    return 1;
548
 
549
  return 0;
550
}
551
 
552
/* Return 1 if OP is a symbol that needs 32 bit addressing.  */
553
 
554
int
555
addr32_operand (rtx op, enum machine_mode mode)
556
{
557
  rtx sym;
558
 
559
  if (GET_CODE (op) == LABEL_REF)
560
    return TARGET_ADDR32;
561
 
562
  if (GET_CODE (op) == SYMBOL_REF)
563
    sym = op;
564
  else if (GET_CODE (op) == CONST
565
           && GET_CODE (XEXP (op, 0)) == PLUS
566
           && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
567
           && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
568
           && ! flag_pic)
569
    sym = XEXP (XEXP (op, 0), 0);
570
  else
571
    return 0;
572
 
573
  return (! addr24_operand (sym, mode)
574
          && ! small_data_operand (sym, mode));
575
}
576
 
577
/* Return 1 if OP is a function that can be called with the `bl' insn.  */
578
 
579
int
580
call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
581
{
582
  if (flag_pic)
583
    return 1;
584
 
585
  if (GET_CODE (op) == SYMBOL_REF)
586
    return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
587
 
588
  return TARGET_CALL26;
589
}
590
 
591
/* Return 1 if OP is a DImode const we want to handle inline.
592
   This must match the code in the movdi pattern.
593
   It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER.  */
594
 
595
int
596
easy_di_const (rtx op)
597
{
598
  rtx high_rtx, low_rtx;
599
  HOST_WIDE_INT high, low;
600
 
601
  split_double (op, &high_rtx, &low_rtx);
602
  high = INTVAL (high_rtx);
603
  low = INTVAL (low_rtx);
604
  /* Pick constants loadable with 2 16 bit `ldi' insns.  */
605
  if (high >= -128 && high <= 127
606
      && low >= -128 && low <= 127)
607
    return 1;
608
  return 0;
609
}
610
 
611
/* Return 1 if OP is a DFmode const we want to handle inline.
612
   This must match the code in the movdf pattern.
613
   It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER.  */
614
 
615
int
616
easy_df_const (rtx op)
617
{
618
  REAL_VALUE_TYPE r;
619
  long l[2];
620
 
621
  REAL_VALUE_FROM_CONST_DOUBLE (r, op);
622
  REAL_VALUE_TO_TARGET_DOUBLE (r, l);
623
  if (l[0] == 0 && l[1] == 0)
624
    return 1;
625
  if ((l[0] & 0xffff) == 0 && l[1] == 0)
626
    return 1;
627
  return 0;
628
}
629
 
630
/* Return 1 if OP is (mem (reg ...)).
631
   This is used in insn length calcs.  */
632
 
633
int
634
memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
635
{
636
  return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
637
}
638
 
639
/* Return nonzero if TYPE must be passed by indirect reference.  */
640
 
641
static bool
642
m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
643
                        enum machine_mode mode, tree type,
644
                        bool named ATTRIBUTE_UNUSED)
645
{
646
  int size;
647
 
648
  if (type)
649
    size = int_size_in_bytes (type);
650
  else
651
    size = GET_MODE_SIZE (mode);
652
 
653
  return (size < 0 || size > 8);
654
}
655
 
656
/* Comparisons.  */
657
 
658
/* X and Y are two things to compare using CODE.  Emit the compare insn and
659
   return the rtx for compare [arg0 of the if_then_else].
660
   If need_compare is true then the comparison insn must be generated, rather
661
   than being subsumed into the following branch instruction.  */
662
 
663
rtx
664
gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
665
{
666
  enum rtx_code compare_code;
667
  enum rtx_code branch_code;
668
  rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
669
  int must_swap = 0;
670
 
671
  switch (code)
672
    {
673
    case EQ:  compare_code = EQ;  branch_code = NE; break;
674
    case NE:  compare_code = EQ;  branch_code = EQ; break;
675
    case LT:  compare_code = LT;  branch_code = NE; break;
676
    case LE:  compare_code = LT;  branch_code = EQ; must_swap = 1; break;
677
    case GT:  compare_code = LT;  branch_code = NE; must_swap = 1; break;
678
    case GE:  compare_code = LT;  branch_code = EQ; break;
679
    case LTU: compare_code = LTU; branch_code = NE; break;
680
    case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
681
    case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
682
    case GEU: compare_code = LTU; branch_code = EQ; break;
683
 
684
    default:
685
      gcc_unreachable ();
686
    }
687
 
688
  if (need_compare)
689
    {
690
      switch (compare_code)
691
        {
692
        case EQ:
693
          if (GET_CODE (y) == CONST_INT
694
              && CMP_INT16_P (INTVAL (y))               /* Reg equal to small const.  */
695
              && y != const0_rtx)
696
            {
697
              rtx tmp = gen_reg_rtx (SImode);
698
 
699
              emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
700
              x = tmp;
701
              y = const0_rtx;
702
            }
703
          else if (CONSTANT_P (y))                      /* Reg equal to const.  */
704
            {
705
              rtx tmp = force_reg (GET_MODE (x), y);
706
              y = tmp;
707
            }
708
 
709
          if (register_operand (y, SImode)              /* Reg equal to reg.  */
710
              || y == const0_rtx)                       /* Reg equal to zero.  */
711
            {
712
              emit_insn (gen_cmp_eqsi_insn (x, y));
713
 
714
              return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
715
            }
716
          break;
717
 
718
        case LT:
719
          if (register_operand (y, SImode)
720
              || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
721
            {
722
              rtx tmp = gen_reg_rtx (SImode);         /* Reg compared to reg.  */
723
 
724
              switch (code)
725
                {
726
                case LT:
727
                  emit_insn (gen_cmp_ltsi_insn (x, y));
728
                  code = EQ;
729
                  break;
730
                case LE:
731
                  if (y == const0_rtx)
732
                    tmp = const1_rtx;
733
                  else
734
                    emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
735
                  emit_insn (gen_cmp_ltsi_insn (x, tmp));
736
                  code = EQ;
737
                  break;
738
                case GT:
739
                  if (GET_CODE (y) == CONST_INT)
740
                    tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
741
                  else
742
                    emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
743
                  emit_insn (gen_cmp_ltsi_insn (x, tmp));
744
                  code = NE;
745
                  break;
746
                case GE:
747
                  emit_insn (gen_cmp_ltsi_insn (x, y));
748
                  code = NE;
749
                  break;
750
                default:
751
                  gcc_unreachable ();
752
                }
753
 
754
              return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
755
            }
756
          break;
757
 
758
        case LTU:
759
          if (register_operand (y, SImode)
760
              || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
761
            {
762
              rtx tmp = gen_reg_rtx (SImode);         /* Reg (unsigned) compared to reg.  */
763
 
764
              switch (code)
765
                {
766
                case LTU:
767
                  emit_insn (gen_cmp_ltusi_insn (x, y));
768
                  code = EQ;
769
                  break;
770
                case LEU:
771
                  if (y == const0_rtx)
772
                    tmp = const1_rtx;
773
                  else
774
                    emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
775
                  emit_insn (gen_cmp_ltusi_insn (x, tmp));
776
                  code = EQ;
777
                  break;
778
                case GTU:
779
                  if (GET_CODE (y) == CONST_INT)
780
                    tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
781
                  else
782
                    emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
783
                  emit_insn (gen_cmp_ltusi_insn (x, tmp));
784
                  code = NE;
785
                  break;
786
                case GEU:
787
                  emit_insn (gen_cmp_ltusi_insn (x, y));
788
                  code = NE;
789
                  break;
790
                default:
791
                  gcc_unreachable ();
792
                }
793
 
794
              return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
795
            }
796
          break;
797
 
798
        default:
799
          gcc_unreachable ();
800
        }
801
    }
802
  else
803
    {
804
      /* Reg/reg equal comparison.  */
805
      if (compare_code == EQ
806
          && register_operand (y, SImode))
807
        return gen_rtx_fmt_ee (code, CCmode, x, y);
808
 
809
      /* Reg/zero signed comparison.  */
810
      if ((compare_code == EQ || compare_code == LT)
811
          && y == const0_rtx)
812
        return gen_rtx_fmt_ee (code, CCmode, x, y);
813
 
814
      /* Reg/smallconst equal comparison.  */
815
      if (compare_code == EQ
816
          && GET_CODE (y) == CONST_INT
817
          && CMP_INT16_P (INTVAL (y)))
818
        {
819
          rtx tmp = gen_reg_rtx (SImode);
820
 
821
          emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
822
          return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
823
        }
824
 
825
      /* Reg/const equal comparison.  */
826
      if (compare_code == EQ
827
          && CONSTANT_P (y))
828
        {
829
          rtx tmp = force_reg (GET_MODE (x), y);
830
 
831
          return gen_rtx_fmt_ee (code, CCmode, x, tmp);
832
        }
833
    }
834
 
835
  if (CONSTANT_P (y))
836
    {
837
      if (must_swap)
838
        y = force_reg (GET_MODE (x), y);
839
      else
840
        {
841
          int ok_const = reg_or_int16_operand (y, GET_MODE (y));
842
 
843
          if (! ok_const)
844
            y = force_reg (GET_MODE (x), y);
845
        }
846
    }
847
 
848
  switch (compare_code)
849
    {
850
    case EQ :
851
      emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
852
      break;
853
    case LT :
854
      emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
855
      break;
856
    case LTU :
857
      emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
858
      break;
859
 
860
    default:
861
      gcc_unreachable ();
862
    }
863
 
864
  return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
865
}
866
 
867
/* Split a 2 word move (DI or DF) into component parts.  */
868
 
869
rtx
870
gen_split_move_double (rtx operands[])
871
{
872
  enum machine_mode mode = GET_MODE (operands[0]);
873
  rtx dest = operands[0];
874
  rtx src  = operands[1];
875
  rtx val;
876
 
877
  /* We might have (SUBREG (MEM)) here, so just get rid of the
878
     subregs to make this code simpler.  It is safe to call
879
     alter_subreg any time after reload.  */
880
  if (GET_CODE (dest) == SUBREG)
881
    alter_subreg (&dest);
882
  if (GET_CODE (src) == SUBREG)
883
    alter_subreg (&src);
884
 
885
  start_sequence ();
886
  if (GET_CODE (dest) == REG)
887
    {
888
      int dregno = REGNO (dest);
889
 
890
      /* Reg = reg.  */
891
      if (GET_CODE (src) == REG)
892
        {
893
          int sregno = REGNO (src);
894
 
895
          int reverse = (dregno == sregno + 1);
896
 
897
          /* We normally copy the low-numbered register first.  However, if
898
             the first register operand 0 is the same as the second register of
899
             operand 1, we must copy in the opposite order.  */
900
          emit_insn (gen_rtx_SET (VOIDmode,
901
                                  operand_subword (dest, reverse, TRUE, mode),
902
                                  operand_subword (src,  reverse, TRUE, mode)));
903
 
904
          emit_insn (gen_rtx_SET (VOIDmode,
905
                                  operand_subword (dest, !reverse, TRUE, mode),
906
                                  operand_subword (src,  !reverse, TRUE, mode)));
907
        }
908
 
909
      /* Reg = constant.  */
910
      else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
911
        {
912
          rtx words[2];
913
          split_double (src, &words[0], &words[1]);
914
          emit_insn (gen_rtx_SET (VOIDmode,
915
                                  operand_subword (dest, 0, TRUE, mode),
916
                                  words[0]));
917
 
918
          emit_insn (gen_rtx_SET (VOIDmode,
919
                                  operand_subword (dest, 1, TRUE, mode),
920
                                  words[1]));
921
        }
922
 
923
      /* Reg = mem.  */
924
      else if (GET_CODE (src) == MEM)
925
        {
926
          /* If the high-address word is used in the address, we must load it
927
             last.  Otherwise, load it first.  */
928
          int reverse
929
            = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
930
 
931
          /* We used to optimize loads from single registers as
932
 
933
                ld r1,r3+; ld r2,r3
934
 
935
             if r3 were not used subsequently.  However, the REG_NOTES aren't
936
             propagated correctly by the reload phase, and it can cause bad
937
             code to be generated.  We could still try:
938
 
939
                ld r1,r3+; ld r2,r3; addi r3,-4
940
 
941
             which saves 2 bytes and doesn't force longword alignment.  */
942
          emit_insn (gen_rtx_SET (VOIDmode,
943
                                  operand_subword (dest, reverse, TRUE, mode),
944
                                  adjust_address (src, SImode,
945
                                                  reverse * UNITS_PER_WORD)));
946
 
947
          emit_insn (gen_rtx_SET (VOIDmode,
948
                                  operand_subword (dest, !reverse, TRUE, mode),
949
                                  adjust_address (src, SImode,
950
                                                  !reverse * UNITS_PER_WORD)));
951
        }
952
      else
953
        gcc_unreachable ();
954
    }
955
 
956
  /* Mem = reg.  */
957
  /* We used to optimize loads from single registers as
958
 
959
        st r1,r3; st r2,+r3
960
 
961
     if r3 were not used subsequently.  However, the REG_NOTES aren't
962
     propagated correctly by the reload phase, and it can cause bad
963
     code to be generated.  We could still try:
964
 
965
        st r1,r3; st r2,+r3; addi r3,-4
966
 
967
     which saves 2 bytes and doesn't force longword alignment.  */
968
  else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
969
    {
970
      emit_insn (gen_rtx_SET (VOIDmode,
971
                              adjust_address (dest, SImode, 0),
972
                              operand_subword (src, 0, TRUE, mode)));
973
 
974
      emit_insn (gen_rtx_SET (VOIDmode,
975
                              adjust_address (dest, SImode, UNITS_PER_WORD),
976
                              operand_subword (src, 1, TRUE, mode)));
977
    }
978
 
979
  else
980
    gcc_unreachable ();
981
 
982
  val = get_insns ();
983
  end_sequence ();
984
  return val;
985
}
986
 
987
 
988
static int
989
m32r_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
990
                        tree type, bool named ATTRIBUTE_UNUSED)
991
{
992
  int words;
993
  unsigned int size =
994
    (((mode == BLKmode && type)
995
      ? (unsigned int) int_size_in_bytes (type)
996
      : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
997
    / UNITS_PER_WORD;
998
 
999
  if (*cum >= M32R_MAX_PARM_REGS)
1000
    words = 0;
1001
  else if (*cum + size > M32R_MAX_PARM_REGS)
1002
    words = (*cum + size) - M32R_MAX_PARM_REGS;
1003
  else
1004
    words = 0;
1005
 
1006
  return words * UNITS_PER_WORD;
1007
}
1008
 
1009
/* Worker function for TARGET_RETURN_IN_MEMORY.  */
1010
 
1011
static bool
1012
m32r_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
1013
{
1014
  return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false);
1015
}
1016
 
1017
/* Do any needed setup for a variadic function.  For the M32R, we must
1018
   create a register parameter block, and then copy any anonymous arguments
1019
   in registers to memory.
1020
 
1021
   CUM has not been updated for the last named argument which has type TYPE
1022
   and mode MODE, and we rely on this fact.  */
1023
 
1024
static void
1025
m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1026
                             tree type, int *pretend_size, int no_rtl)
1027
{
1028
  int first_anon_arg;
1029
 
1030
  if (no_rtl)
1031
    return;
1032
 
1033
  /* All BLKmode values are passed by reference.  */
1034
  gcc_assert (mode != BLKmode);
1035
 
1036
  first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1037
                    + ROUND_ADVANCE_ARG (mode, type));
1038
 
1039
  if (first_anon_arg < M32R_MAX_PARM_REGS)
1040
    {
1041
      /* Note that first_reg_offset < M32R_MAX_PARM_REGS.  */
1042
      int first_reg_offset = first_anon_arg;
1043
      /* Size in words to "pretend" allocate.  */
1044
      int size = M32R_MAX_PARM_REGS - first_reg_offset;
1045
      rtx regblock;
1046
 
1047
      regblock = gen_rtx_MEM (BLKmode,
1048
                              plus_constant (arg_pointer_rtx,
1049
                                             FIRST_PARM_OFFSET (0)));
1050
      set_mem_alias_set (regblock, get_varargs_alias_set ());
1051
      move_block_from_reg (first_reg_offset, regblock, size);
1052
 
1053
      *pretend_size = (size * UNITS_PER_WORD);
1054
    }
1055
}
1056
 
1057
 
1058
/* Return true if INSN is real instruction bearing insn.  */
1059
 
1060
static int
1061
m32r_is_insn (rtx insn)
1062
{
1063
  return (INSN_P (insn)
1064
          && GET_CODE (PATTERN (insn)) != USE
1065
          && GET_CODE (PATTERN (insn)) != CLOBBER
1066
          && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1067
}
1068
 
1069
/* Increase the priority of long instructions so that the
1070
   short instructions are scheduled ahead of the long ones.  */
1071
 
1072
static int
1073
m32r_adjust_priority (rtx insn, int priority)
1074
{
1075
  if (m32r_is_insn (insn)
1076
      && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1077
    priority <<= 3;
1078
 
1079
  return priority;
1080
}
1081
 
1082
 
1083
/* Indicate how many instructions can be issued at the same time.
1084
   This is sort of a lie.  The m32r can issue only 1 long insn at
1085
   once, but it can issue 2 short insns.  The default therefore is
1086
   set at 2, but this can be overridden by the command line option
1087
   -missue-rate=1.  */
1088
 
1089
static int
1090
m32r_issue_rate (void)
1091
{
1092
  return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1093
}
1094
 
1095
/* Cost functions.  */
1096
 
1097
static bool
1098
m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total)
1099
{
1100
  switch (code)
1101
    {
1102
      /* Small integers are as cheap as registers.  4 byte values can be
1103
         fetched as immediate constants - let's give that the cost of an
1104
         extra insn.  */
1105
    case CONST_INT:
1106
      if (INT16_P (INTVAL (x)))
1107
        {
1108
          *total = 0;
1109
          return true;
1110
        }
1111
      /* FALLTHRU */
1112
 
1113
    case CONST:
1114
    case LABEL_REF:
1115
    case SYMBOL_REF:
1116
      *total = COSTS_N_INSNS (1);
1117
      return true;
1118
 
1119
    case CONST_DOUBLE:
1120
      {
1121
        rtx high, low;
1122
 
1123
        split_double (x, &high, &low);
1124
        *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1125
                                + !INT16_P (INTVAL (low)));
1126
        return true;
1127
      }
1128
 
1129
    case MULT:
1130
      *total = COSTS_N_INSNS (3);
1131
      return true;
1132
 
1133
    case DIV:
1134
    case UDIV:
1135
    case MOD:
1136
    case UMOD:
1137
      *total = COSTS_N_INSNS (10);
1138
      return true;
1139
 
1140
    default:
1141
      return false;
1142
    }
1143
}
1144
 
1145
/* Type of function DECL.
1146
 
1147
   The result is cached.  To reset the cache at the end of a function,
1148
   call with DECL = NULL_TREE.  */
1149
 
1150
enum m32r_function_type
1151
m32r_compute_function_type (tree decl)
1152
{
1153
  /* Cached value.  */
1154
  static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1155
  /* Last function we were called for.  */
1156
  static tree last_fn = NULL_TREE;
1157
 
1158
  /* Resetting the cached value?  */
1159
  if (decl == NULL_TREE)
1160
    {
1161
      fn_type = M32R_FUNCTION_UNKNOWN;
1162
      last_fn = NULL_TREE;
1163
      return fn_type;
1164
    }
1165
 
1166
  if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1167
    return fn_type;
1168
 
1169
  /* Compute function type.  */
1170
  fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1171
             ? M32R_FUNCTION_INTERRUPT
1172
             : M32R_FUNCTION_NORMAL);
1173
 
1174
  last_fn = decl;
1175
  return fn_type;
1176
}
1177
/* Function prologue/epilogue handlers.  */
1178
 
1179
/* M32R stack frames look like:
1180
 
1181
             Before call                       After call
1182
        +-----------------------+       +-----------------------+
1183
        |                       |       |                       |
1184
   high |  local variables,     |       |  local variables,     |
1185
   mem  |  reg save area, etc.  |       |  reg save area, etc.  |
1186
        |                       |       |                       |
1187
        +-----------------------+       +-----------------------+
1188
        |                       |       |                       |
1189
        |  arguments on stack.  |       |  arguments on stack.  |
1190
        |                       |       |                       |
1191
  SP+0->+-----------------------+       +-----------------------+
1192
                                        |  reg parm save area,  |
1193
                                        |  only created for     |
1194
                                        |  variable argument    |
1195
                                        |  functions            |
1196
                                        +-----------------------+
1197
                                        |   previous frame ptr  |
1198
                                        +-----------------------+
1199
                                        |                       |
1200
                                        |  register save area   |
1201
                                        |                       |
1202
                                        +-----------------------+
1203
                                        |    return address     |
1204
                                        +-----------------------+
1205
                                        |                       |
1206
                                        |  local variables      |
1207
                                        |                       |
1208
                                        +-----------------------+
1209
                                        |                       |
1210
                                        |  alloca allocations   |
1211
                                        |                       |
1212
                                        +-----------------------+
1213
                                        |                       |
1214
   low                                  |  arguments on stack   |
1215
   memory                               |                       |
1216
                                  SP+0->+-----------------------+
1217
 
1218
Notes:
1219
1) The "reg parm save area" does not exist for non variable argument fns.
1220
2) The "reg parm save area" can be eliminated completely if we saved regs
1221
   containing anonymous args separately but that complicates things too
1222
   much (so it's not done).
1223
3) The return address is saved after the register save area so as to have as
1224
   many insns as possible between the restoration of `lr' and the `jmp lr'.  */
1225
 
1226
/* Structure to be filled in by m32r_compute_frame_size with register
1227
   save masks, and offsets for the current function.  */
1228
struct m32r_frame_info
1229
{
1230
  unsigned int total_size;      /* # bytes that the entire frame takes up.  */
1231
  unsigned int extra_size;      /* # bytes of extra stuff.  */
1232
  unsigned int pretend_size;    /* # bytes we push and pretend caller did.  */
1233
  unsigned int args_size;       /* # bytes that outgoing arguments take up.  */
1234
  unsigned int reg_size;        /* # bytes needed to store regs.  */
1235
  unsigned int var_size;        /* # bytes that variables take up.  */
1236
  unsigned int gmask;           /* Mask of saved gp registers.  */
1237
  unsigned int save_fp;         /* Nonzero if fp must be saved.  */
1238
  unsigned int save_lr;         /* Nonzero if lr (return addr) must be saved.  */
1239
  int          initialized;     /* Nonzero if frame size already calculated.  */
1240
};
1241
 
1242
/* Current frame information calculated by m32r_compute_frame_size.  */
1243
static struct m32r_frame_info current_frame_info;
1244
 
1245
/* Zero structure to initialize current_frame_info.  */
1246
static struct m32r_frame_info zero_frame_info;
1247
 
1248
#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1249
#define RETURN_ADDR_MASK   (1 << (RETURN_ADDR_REGNUM))
1250
 
1251
/* Tell prologue and epilogue if register REGNO should be saved / restored.
1252
   The return address and frame pointer are treated separately.
1253
   Don't consider them here.  */
1254
#define MUST_SAVE_REGISTER(regno, interrupt_p) \
1255
  ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1256
  && (regs_ever_live[regno] && (!call_really_used_regs[regno] || interrupt_p)))
1257
 
1258
#define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1259
#define MUST_SAVE_RETURN_ADDR   (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1260
 
1261
#define SHORT_INSN_SIZE 2       /* Size of small instructions.  */
1262
#define LONG_INSN_SIZE 4        /* Size of long instructions.  */
1263
 
1264
/* Return the bytes needed to compute the frame pointer from the current
1265
   stack pointer.
1266
 
1267
   SIZE is the size needed for local variables.  */
1268
 
1269
unsigned int
1270
m32r_compute_frame_size (int size)      /* # of var. bytes allocated.  */
1271
{
1272
  int regno;
1273
  unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1274
  unsigned int reg_size, frame_size;
1275
  unsigned int gmask;
1276
  enum m32r_function_type fn_type;
1277
  int interrupt_p;
1278
  int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1279
                                  | current_function_profile);
1280
 
1281
  var_size      = M32R_STACK_ALIGN (size);
1282
  args_size     = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1283
  pretend_size  = current_function_pretend_args_size;
1284
  extra_size    = FIRST_PARM_OFFSET (0);
1285
  total_size    = extra_size + pretend_size + args_size + var_size;
1286
  reg_size      = 0;
1287
  gmask         = 0;
1288
 
1289
  /* See if this is an interrupt handler.  Call used registers must be saved
1290
     for them too.  */
1291
  fn_type = m32r_compute_function_type (current_function_decl);
1292
  interrupt_p = M32R_INTERRUPT_P (fn_type);
1293
 
1294
  /* Calculate space needed for registers.  */
1295
  for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1296
    {
1297
      if (MUST_SAVE_REGISTER (regno, interrupt_p)
1298
          || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1299
        {
1300
          reg_size += UNITS_PER_WORD;
1301
          gmask |= 1 << regno;
1302
        }
1303
    }
1304
 
1305
  current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1306
  current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
1307
 
1308
  reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1309
               * UNITS_PER_WORD);
1310
  total_size += reg_size;
1311
 
1312
  /* ??? Not sure this is necessary, and I don't think the epilogue
1313
     handler will do the right thing if this changes total_size.  */
1314
  total_size = M32R_STACK_ALIGN (total_size);
1315
 
1316
  frame_size = total_size - (pretend_size + reg_size);
1317
 
1318
  /* Save computed information.  */
1319
  current_frame_info.total_size   = total_size;
1320
  current_frame_info.extra_size   = extra_size;
1321
  current_frame_info.pretend_size = pretend_size;
1322
  current_frame_info.var_size     = var_size;
1323
  current_frame_info.args_size    = args_size;
1324
  current_frame_info.reg_size     = reg_size;
1325
  current_frame_info.gmask        = gmask;
1326
  current_frame_info.initialized  = reload_completed;
1327
 
1328
  /* Ok, we're done.  */
1329
  return total_size;
1330
}
1331
 
1332
/* The table we use to reference PIC data.  */
1333
static rtx global_offset_table;
1334
 
1335
static void
1336
m32r_reload_lr (rtx sp, int size)
1337
{
1338
  rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1339
 
1340
  if (size == 0)
1341
    emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, sp)));
1342
  else if (size < 32768)
1343
    emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode,
1344
                                           gen_rtx_PLUS (Pmode, sp,
1345
                                                         GEN_INT (size)))));
1346
  else
1347
    {
1348
      rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1349
 
1350
      emit_insn (gen_movsi (tmp, GEN_INT (size)));
1351
      emit_insn (gen_addsi3 (tmp, tmp, sp));
1352
      emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, tmp)));
1353
    }
1354
 
1355
  emit_insn (gen_rtx_USE (VOIDmode, lr));
1356
}
1357
 
1358
void
1359
m32r_load_pic_register (void)
1360
{
1361
  global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1362
  emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
1363
                         GEN_INT (TARGET_MODEL_SMALL)));
1364
 
1365
  /* Need to emit this whether or not we obey regdecls,
1366
     since setjmp/longjmp can cause life info to screw up.  */
1367
  emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1368
}
1369
 
1370
/* Expand the m32r prologue as a series of insns.  */
1371
 
1372
void
1373
m32r_expand_prologue (void)
1374
{
1375
  int regno;
1376
  int frame_size;
1377
  unsigned int gmask;
1378
  int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1379
                                  | current_function_profile);
1380
 
1381
  if (! current_frame_info.initialized)
1382
    m32r_compute_frame_size (get_frame_size ());
1383
 
1384
  gmask = current_frame_info.gmask;
1385
 
1386
  /* These cases shouldn't happen.  Catch them now.  */
1387
  gcc_assert (current_frame_info.total_size || !gmask);
1388
 
1389
  /* Allocate space for register arguments if this is a variadic function.  */
1390
  if (current_frame_info.pretend_size != 0)
1391
    {
1392
      /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1393
         the wrong result on a 64-bit host.  */
1394
      HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1395
      emit_insn (gen_addsi3 (stack_pointer_rtx,
1396
                             stack_pointer_rtx,
1397
                             GEN_INT (-pretend_size)));
1398
    }
1399
 
1400
  /* Save any registers we need to and set up fp.  */
1401
  if (current_frame_info.save_fp)
1402
    emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1403
 
1404
  gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1405
 
1406
  /* Save any needed call-saved regs (and call-used if this is an
1407
     interrupt handler).  */
1408
  for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1409
    {
1410
      if ((gmask & (1 << regno)) != 0)
1411
        emit_insn (gen_movsi_push (stack_pointer_rtx,
1412
                                   gen_rtx_REG (Pmode, regno)));
1413
    }
1414
 
1415
  if (current_frame_info.save_lr)
1416
    emit_insn (gen_movsi_push (stack_pointer_rtx,
1417
                               gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1418
 
1419
  /* Allocate the stack frame.  */
1420
  frame_size = (current_frame_info.total_size
1421
                - (current_frame_info.pretend_size
1422
                   + current_frame_info.reg_size));
1423
 
1424
  if (frame_size == 0)
1425
    ; /* Nothing to do.  */
1426
  else if (frame_size <= 32768)
1427
    emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1428
                           GEN_INT (-frame_size)));
1429
  else
1430
    {
1431
      rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1432
 
1433
      emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1434
      emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1435
    }
1436
 
1437
  if (frame_pointer_needed)
1438
    emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1439
 
1440
  if (current_function_profile)
1441
    /* Push lr for mcount (form_pc, x).  */
1442
    emit_insn (gen_movsi_push (stack_pointer_rtx,
1443
                               gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1444
 
1445
  if (pic_reg_used)
1446
    {
1447
      m32r_load_pic_register ();
1448
      m32r_reload_lr (stack_pointer_rtx,
1449
                      (current_function_profile ? 0 : frame_size));
1450
    }
1451
 
1452
  if (current_function_profile && !pic_reg_used)
1453
    emit_insn (gen_blockage ());
1454
}
1455
 
1456
 
1457
/* Set up the stack and frame pointer (if desired) for the function.
1458
   Note, if this is changed, you need to mirror the changes in
1459
   m32r_compute_frame_size which calculates the prolog size.  */
1460
 
1461
static void
1462
m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
1463
{
1464
  enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1465
 
1466
  /* If this is an interrupt handler, mark it as such.  */
1467
  if (M32R_INTERRUPT_P (fn_type))
1468
    fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
1469
 
1470
  if (! current_frame_info.initialized)
1471
    m32r_compute_frame_size (size);
1472
 
1473
  /* This is only for the human reader.  */
1474
  fprintf (file,
1475
           "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1476
           ASM_COMMENT_START,
1477
           current_frame_info.var_size,
1478
           current_frame_info.reg_size / 4,
1479
           current_frame_info.args_size,
1480
           current_frame_info.extra_size);
1481
}
1482
 
1483
/* Do any necessary cleanup after a function to restore stack, frame,
1484
   and regs.  */
1485
 
1486
static void
1487
m32r_output_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1488
{
1489
  int regno;
1490
  int noepilogue = FALSE;
1491
  int total_size;
1492
  enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1493
 
1494
  /* This is only for the human reader.  */
1495
  fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
1496
 
1497
  gcc_assert (current_frame_info.initialized);
1498
  total_size = current_frame_info.total_size;
1499
 
1500
  if (total_size == 0)
1501
    {
1502
      rtx insn = get_last_insn ();
1503
 
1504
      /* If the last insn was a BARRIER, we don't have to write any code
1505
         because a jump (aka return) was put there.  */
1506
      if (GET_CODE (insn) == NOTE)
1507
        insn = prev_nonnote_insn (insn);
1508
      if (insn && GET_CODE (insn) == BARRIER)
1509
        noepilogue = TRUE;
1510
    }
1511
 
1512
  if (!noepilogue)
1513
    {
1514
      unsigned int var_size = current_frame_info.var_size;
1515
      unsigned int args_size = current_frame_info.args_size;
1516
      unsigned int gmask = current_frame_info.gmask;
1517
      int can_trust_sp_p = !current_function_calls_alloca;
1518
      const char * sp_str = reg_names[STACK_POINTER_REGNUM];
1519
      const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
1520
 
1521
      /* The first thing to do is point the sp at the bottom of the register
1522
         save area.  */
1523
      if (can_trust_sp_p)
1524
        {
1525
          unsigned int reg_offset = var_size + args_size;
1526
          if (reg_offset == 0)
1527
            ; /* Nothing to do.  */
1528
          else if (reg_offset < 128)
1529
            fprintf (file, "\taddi %s,%s%d\n",
1530
                     sp_str, IMMEDIATE_PREFIX, reg_offset);
1531
          else if (reg_offset < 32768)
1532
            fprintf (file, "\tadd3 %s,%s,%s%d\n",
1533
                     sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
1534
          else if (reg_offset < (1 << 24))
1535
            fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1536
                     reg_names[PROLOGUE_TMP_REGNUM],
1537
                     IMMEDIATE_PREFIX, reg_offset,
1538
                     sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1539
          else
1540
            fprintf (file, "\tseth %s,%s%d\n\tor3 %s,%s,%s%d\n\tadd %s,%s\n",
1541
                     reg_names[PROLOGUE_TMP_REGNUM],
1542
                     IMMEDIATE_PREFIX, reg_offset >> 16,
1543
                     reg_names[PROLOGUE_TMP_REGNUM],
1544
                     reg_names[PROLOGUE_TMP_REGNUM],
1545
                     IMMEDIATE_PREFIX, reg_offset & 0xffff,
1546
                     sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1547
        }
1548
      else if (frame_pointer_needed)
1549
        {
1550
          unsigned int reg_offset = var_size + args_size;
1551
 
1552
          if (reg_offset == 0)
1553
            fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
1554
          else if (reg_offset < 32768)
1555
            fprintf (file, "\tadd3 %s,%s,%s%d\n",
1556
                     sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
1557
          else if (reg_offset < (1 << 24))
1558
            fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1559
                     reg_names[PROLOGUE_TMP_REGNUM],
1560
                     IMMEDIATE_PREFIX, reg_offset,
1561
                     sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1562
          else
1563
            fprintf (file, "\tseth %s,%s%d\n\tor3 %s,%s,%s%d\n\tadd %s,%s\n",
1564
                     reg_names[PROLOGUE_TMP_REGNUM],
1565
                     IMMEDIATE_PREFIX, reg_offset >> 16,
1566
                     reg_names[PROLOGUE_TMP_REGNUM],
1567
                     reg_names[PROLOGUE_TMP_REGNUM],
1568
                     IMMEDIATE_PREFIX, reg_offset & 0xffff,
1569
                     sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1570
        }
1571
      else
1572
        gcc_unreachable ();
1573
 
1574
      if (current_frame_info.save_lr)
1575
        fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
1576
 
1577
      /* Restore any saved registers, in reverse order of course.  */
1578
      gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1579
      for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1580
        {
1581
          if ((gmask & (1L << regno)) != 0)
1582
            fprintf (file, "\tpop %s\n", reg_names[regno]);
1583
        }
1584
 
1585
      if (current_frame_info.save_fp)
1586
        fprintf (file, "\tpop %s\n", fp_str);
1587
 
1588
      /* Remove varargs area if present.  */
1589
      if (current_frame_info.pretend_size != 0)
1590
        fprintf (file, "\taddi %s,%s%d\n",
1591
                 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
1592
 
1593
      /* Emit the return instruction.  */
1594
      if (M32R_INTERRUPT_P (fn_type))
1595
        fprintf (file, "\trte\n");
1596
      else
1597
        fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
1598
    }
1599
 
1600
  /* Reset state info for each function.  */
1601
  current_frame_info = zero_frame_info;
1602
  m32r_compute_function_type (NULL_TREE);
1603
}
1604
 
1605
/* Return nonzero if this function is known to have a null or 1 instruction
1606
   epilogue.  */
1607
 
1608
int
1609
direct_return (void)
1610
{
1611
  if (!reload_completed)
1612
    return FALSE;
1613
 
1614
  if (! current_frame_info.initialized)
1615
    m32r_compute_frame_size (get_frame_size ());
1616
 
1617
   return current_frame_info.total_size == 0;
1618
}
1619
 
1620
 
1621
/* PIC.  */
1622
 
1623
int
1624
m32r_legitimate_pic_operand_p (rtx x)
1625
{
1626
  if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1627
    return 0;
1628
 
1629
  if (GET_CODE (x) == CONST
1630
      && GET_CODE (XEXP (x, 0)) == PLUS
1631
      && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1632
          || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
1633
      && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1634
    return 0;
1635
 
1636
  return 1;
1637
}
1638
 
1639
rtx
1640
m32r_legitimize_pic_address (rtx orig, rtx reg)
1641
{
1642
#ifdef DEBUG_PIC
1643
  printf("m32r_legitimize_pic_address()\n");
1644
#endif
1645
 
1646
  if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1647
    {
1648
      rtx pic_ref, address;
1649
      rtx insn;
1650
      int subregs = 0;
1651
 
1652
      if (reg == 0)
1653
        {
1654
          gcc_assert (!reload_in_progress && !reload_completed);
1655
          reg = gen_reg_rtx (Pmode);
1656
 
1657
          subregs = 1;
1658
        }
1659
 
1660
      if (subregs)
1661
        address = gen_reg_rtx (Pmode);
1662
      else
1663
        address = reg;
1664
 
1665
      current_function_uses_pic_offset_table = 1;
1666
 
1667
      if (GET_CODE (orig) == LABEL_REF
1668
          || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1669
        {
1670
          emit_insn (gen_gotoff_load_addr (reg, orig));
1671
          emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1672
          return reg;
1673
        }
1674
 
1675
      emit_insn (gen_pic_load_addr (address, orig));
1676
 
1677
      emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
1678
      pic_ref = gen_const_mem (Pmode, address);
1679
      insn = emit_move_insn (reg, pic_ref);
1680
#if 0
1681
      /* Put a REG_EQUAL note on this insn, so that it can be optimized
1682
         by loop.  */
1683
      REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1684
                  REG_NOTES (insn));
1685
#endif
1686
      return reg;
1687
    }
1688
  else if (GET_CODE (orig) == CONST)
1689
    {
1690
      rtx base, offset;
1691
 
1692
      if (GET_CODE (XEXP (orig, 0)) == PLUS
1693
          && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
1694
        return orig;
1695
 
1696
      if (reg == 0)
1697
        {
1698
          gcc_assert (!reload_in_progress && !reload_completed);
1699
          reg = gen_reg_rtx (Pmode);
1700
        }
1701
 
1702
      if (GET_CODE (XEXP (orig, 0)) == PLUS)
1703
        {
1704
          base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
1705
          if (base == reg)
1706
            offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
1707
          else
1708
            offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
1709
        }
1710
      else
1711
        return orig;
1712
 
1713
      if (GET_CODE (offset) == CONST_INT)
1714
        {
1715
          if (INT16_P (INTVAL (offset)))
1716
            return plus_constant (base, INTVAL (offset));
1717
          else
1718
            {
1719
              gcc_assert (! reload_in_progress && ! reload_completed);
1720
              offset = force_reg (Pmode, offset);
1721
            }
1722
        }
1723
 
1724
      return gen_rtx_PLUS (Pmode, base, offset);
1725
    }
1726
 
1727
  return orig;
1728
}
1729
 
1730
/* Nested function support.  */
1731
 
1732
/* Emit RTL insns to initialize the variable parts of a trampoline.
1733
   FNADDR is an RTX for the address of the function's pure code.
1734
   CXT is an RTX for the static chain value for the function.  */
1735
 
1736
void
1737
m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
1738
                            rtx fnaddr ATTRIBUTE_UNUSED,
1739
                            rtx cxt ATTRIBUTE_UNUSED)
1740
{
1741
}
1742
 
1743
static void
1744
m32r_file_start (void)
1745
{
1746
  default_file_start ();
1747
 
1748
  if (flag_verbose_asm)
1749
    fprintf (asm_out_file,
1750
             "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
1751
             ASM_COMMENT_START, g_switch_value);
1752
 
1753
  if (TARGET_LITTLE_ENDIAN)
1754
    fprintf (asm_out_file, "\t.little\n");
1755
}
1756
 
1757
/* Print operand X (an rtx) in assembler syntax to file FILE.
1758
   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1759
   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
1760
 
1761
void
1762
m32r_print_operand (FILE * file, rtx x, int code)
1763
{
1764
  rtx addr;
1765
 
1766
  switch (code)
1767
    {
1768
      /* The 's' and 'p' codes are used by output_block_move() to
1769
         indicate post-increment 's'tores and 'p're-increment loads.  */
1770
    case 's':
1771
      if (GET_CODE (x) == REG)
1772
        fprintf (file, "@+%s", reg_names [REGNO (x)]);
1773
      else
1774
        output_operand_lossage ("invalid operand to %%s code");
1775
      return;
1776
 
1777
    case 'p':
1778
      if (GET_CODE (x) == REG)
1779
        fprintf (file, "@%s+", reg_names [REGNO (x)]);
1780
      else
1781
        output_operand_lossage ("invalid operand to %%p code");
1782
      return;
1783
 
1784
    case 'R' :
1785
      /* Write second word of DImode or DFmode reference,
1786
         register or memory.  */
1787
      if (GET_CODE (x) == REG)
1788
        fputs (reg_names[REGNO (x)+1], file);
1789
      else if (GET_CODE (x) == MEM)
1790
        {
1791
          fprintf (file, "@(");
1792
          /* Handle possible auto-increment.  Since it is pre-increment and
1793
             we have already done it, we can just use an offset of four.  */
1794
          /* ??? This is taken from rs6000.c I think.  I don't think it is
1795
             currently necessary, but keep it around.  */
1796
          if (GET_CODE (XEXP (x, 0)) == PRE_INC
1797
              || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1798
            output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1799
          else
1800
            output_address (plus_constant (XEXP (x, 0), 4));
1801
          fputc (')', file);
1802
        }
1803
      else
1804
        output_operand_lossage ("invalid operand to %%R code");
1805
      return;
1806
 
1807
    case 'H' : /* High word.  */
1808
    case 'L' : /* Low word.  */
1809
      if (GET_CODE (x) == REG)
1810
        {
1811
          /* L = least significant word, H = most significant word.  */
1812
          if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
1813
            fputs (reg_names[REGNO (x)], file);
1814
          else
1815
            fputs (reg_names[REGNO (x)+1], file);
1816
        }
1817
      else if (GET_CODE (x) == CONST_INT
1818
               || GET_CODE (x) == CONST_DOUBLE)
1819
        {
1820
          rtx first, second;
1821
 
1822
          split_double (x, &first, &second);
1823
          fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1824
                   code == 'L' ? INTVAL (first) : INTVAL (second));
1825
        }
1826
      else
1827
        output_operand_lossage ("invalid operand to %%H/%%L code");
1828
      return;
1829
 
1830
    case 'A' :
1831
      {
1832
        char str[30];
1833
 
1834
        if (GET_CODE (x) != CONST_DOUBLE
1835
            || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
1836
          fatal_insn ("bad insn for 'A'", x);
1837
 
1838
        real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
1839
        fprintf (file, "%s", str);
1840
        return;
1841
      }
1842
 
1843
    case 'B' : /* Bottom half.  */
1844
    case 'T' : /* Top half.  */
1845
      /* Output the argument to a `seth' insn (sets the Top half-word).
1846
         For constants output arguments to a seth/or3 pair to set Top and
1847
         Bottom halves.  For symbols output arguments to a seth/add3 pair to
1848
         set Top and Bottom halves.  The difference exists because for
1849
         constants seth/or3 is more readable but for symbols we need to use
1850
         the same scheme as `ld' and `st' insns (16 bit addend is signed).  */
1851
      switch (GET_CODE (x))
1852
        {
1853
        case CONST_INT :
1854
        case CONST_DOUBLE :
1855
          {
1856
            rtx first, second;
1857
 
1858
            split_double (x, &first, &second);
1859
            x = WORDS_BIG_ENDIAN ? second : first;
1860
            fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1861
                     (code == 'B'
1862
                      ? INTVAL (x) & 0xffff
1863
                      : (INTVAL (x) >> 16) & 0xffff));
1864
          }
1865
          return;
1866
        case CONST :
1867
        case SYMBOL_REF :
1868
          if (code == 'B'
1869
              && small_data_operand (x, VOIDmode))
1870
            {
1871
              fputs ("sda(", file);
1872
              output_addr_const (file, x);
1873
              fputc (')', file);
1874
              return;
1875
            }
1876
          /* fall through */
1877
        case LABEL_REF :
1878
          fputs (code == 'T' ? "shigh(" : "low(", file);
1879
          output_addr_const (file, x);
1880
          fputc (')', file);
1881
          return;
1882
        default :
1883
          output_operand_lossage ("invalid operand to %%T/%%B code");
1884
          return;
1885
        }
1886
      break;
1887
 
1888
    case 'U' :
1889
      /* ??? wip */
1890
      /* Output a load/store with update indicator if appropriate.  */
1891
      if (GET_CODE (x) == MEM)
1892
        {
1893
          if (GET_CODE (XEXP (x, 0)) == PRE_INC
1894
              || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1895
            fputs (".a", file);
1896
        }
1897
      else
1898
        output_operand_lossage ("invalid operand to %%U code");
1899
      return;
1900
 
1901
    case 'N' :
1902
      /* Print a constant value negated.  */
1903
      if (GET_CODE (x) == CONST_INT)
1904
        output_addr_const (file, GEN_INT (- INTVAL (x)));
1905
      else
1906
        output_operand_lossage ("invalid operand to %%N code");
1907
      return;
1908
 
1909
    case 'X' :
1910
      /* Print a const_int in hex.  Used in comments.  */
1911
      if (GET_CODE (x) == CONST_INT)
1912
        fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
1913
      return;
1914
 
1915
    case '#' :
1916
      fputs (IMMEDIATE_PREFIX, file);
1917
      return;
1918
 
1919
    case 0 :
1920
      /* Do nothing special.  */
1921
      break;
1922
 
1923
    default :
1924
      /* Unknown flag.  */
1925
      output_operand_lossage ("invalid operand output code");
1926
    }
1927
 
1928
  switch (GET_CODE (x))
1929
    {
1930
    case REG :
1931
      fputs (reg_names[REGNO (x)], file);
1932
      break;
1933
 
1934
    case MEM :
1935
      addr = XEXP (x, 0);
1936
      if (GET_CODE (addr) == PRE_INC)
1937
        {
1938
          if (GET_CODE (XEXP (addr, 0)) != REG)
1939
            fatal_insn ("pre-increment address is not a register", x);
1940
 
1941
          fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
1942
        }
1943
      else if (GET_CODE (addr) == PRE_DEC)
1944
        {
1945
          if (GET_CODE (XEXP (addr, 0)) != REG)
1946
            fatal_insn ("pre-decrement address is not a register", x);
1947
 
1948
          fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
1949
        }
1950
      else if (GET_CODE (addr) == POST_INC)
1951
        {
1952
          if (GET_CODE (XEXP (addr, 0)) != REG)
1953
            fatal_insn ("post-increment address is not a register", x);
1954
 
1955
          fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
1956
        }
1957
      else
1958
        {
1959
          fputs ("@(", file);
1960
          output_address (XEXP (x, 0));
1961
          fputc (')', file);
1962
        }
1963
      break;
1964
 
1965
    case CONST_DOUBLE :
1966
      /* We handle SFmode constants here as output_addr_const doesn't.  */
1967
      if (GET_MODE (x) == SFmode)
1968
        {
1969
          REAL_VALUE_TYPE d;
1970
          long l;
1971
 
1972
          REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1973
          REAL_VALUE_TO_TARGET_SINGLE (d, l);
1974
          fprintf (file, "0x%08lx", l);
1975
          break;
1976
        }
1977
 
1978
      /* Fall through.  Let output_addr_const deal with it.  */
1979
 
1980
    default :
1981
      output_addr_const (file, x);
1982
      break;
1983
    }
1984
}
1985
 
1986
/* Print a memory address as an operand to reference that memory location.  */
1987
 
1988
void
1989
m32r_print_operand_address (FILE * file, rtx addr)
1990
{
1991
  rtx base;
1992
  rtx index = 0;
1993
  int offset = 0;
1994
 
1995
  switch (GET_CODE (addr))
1996
    {
1997
    case REG :
1998
      fputs (reg_names[REGNO (addr)], file);
1999
      break;
2000
 
2001
    case PLUS :
2002
      if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2003
        offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2004
      else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2005
        offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2006
      else
2007
        base = XEXP (addr, 0), index = XEXP (addr, 1);
2008
      if (GET_CODE (base) == REG)
2009
        {
2010
          /* Print the offset first (if present) to conform to the manual.  */
2011
          if (index == 0)
2012
            {
2013
              if (offset != 0)
2014
                fprintf (file, "%d,", offset);
2015
              fputs (reg_names[REGNO (base)], file);
2016
            }
2017
          /* The chip doesn't support this, but left in for generality.  */
2018
          else if (GET_CODE (index) == REG)
2019
            fprintf (file, "%s,%s",
2020
                     reg_names[REGNO (base)], reg_names[REGNO (index)]);
2021
          /* Not sure this can happen, but leave in for now.  */
2022
          else if (GET_CODE (index) == SYMBOL_REF)
2023
            {
2024
              output_addr_const (file, index);
2025
              fputc (',', file);
2026
              fputs (reg_names[REGNO (base)], file);
2027
            }
2028
          else
2029
            fatal_insn ("bad address", addr);
2030
        }
2031
      else if (GET_CODE (base) == LO_SUM)
2032
        {
2033
          gcc_assert (!index && GET_CODE (XEXP (base, 0)) == REG);
2034
          if (small_data_operand (XEXP (base, 1), VOIDmode))
2035
            fputs ("sda(", file);
2036
          else
2037
            fputs ("low(", file);
2038
          output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2039
          fputs ("),", file);
2040
          fputs (reg_names[REGNO (XEXP (base, 0))], file);
2041
        }
2042
      else
2043
        fatal_insn ("bad address", addr);
2044
      break;
2045
 
2046
    case LO_SUM :
2047
      if (GET_CODE (XEXP (addr, 0)) != REG)
2048
        fatal_insn ("lo_sum not of register", addr);
2049
      if (small_data_operand (XEXP (addr, 1), VOIDmode))
2050
        fputs ("sda(", file);
2051
      else
2052
        fputs ("low(", file);
2053
      output_addr_const (file, XEXP (addr, 1));
2054
      fputs ("),", file);
2055
      fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2056
      break;
2057
 
2058
    case PRE_INC :      /* Assume SImode.  */
2059
      fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2060
      break;
2061
 
2062
    case PRE_DEC :      /* Assume SImode.  */
2063
      fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2064
      break;
2065
 
2066
    case POST_INC :     /* Assume SImode.  */
2067
      fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2068
      break;
2069
 
2070
    default :
2071
      output_addr_const (file, addr);
2072
      break;
2073
    }
2074
}
2075
 
2076
/* Return true if the operands are the constants 0 and 1.  */
2077
 
2078
int
2079
zero_and_one (rtx operand1, rtx operand2)
2080
{
2081
  return
2082
       GET_CODE (operand1) == CONST_INT
2083
    && GET_CODE (operand2) == CONST_INT
2084
    && (  ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2085
        ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2086
}
2087
 
2088
/* Generate the correct assembler code to handle the conditional loading of a
2089
   value into a register.  It is known that the operands satisfy the
2090
   conditional_move_operand() function above.  The destination is operand[0].
2091
   The condition is operand [1].  The 'true' value is operand [2] and the
2092
   'false' value is operand [3].  */
2093
 
2094
char *
2095
emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
2096
{
2097
  static char buffer [100];
2098
  const char * dest = reg_names [REGNO (operands [0])];
2099
 
2100
  buffer [0] = 0;
2101
 
2102
  /* Destination must be a register.  */
2103
  gcc_assert (GET_CODE (operands [0]) == REG);
2104
  gcc_assert (conditional_move_operand (operands [2], SImode));
2105
  gcc_assert (conditional_move_operand (operands [3], SImode));
2106
 
2107
  /* Check to see if the test is reversed.  */
2108
  if (GET_CODE (operands [1]) == NE)
2109
    {
2110
      rtx tmp = operands [2];
2111
      operands [2] = operands [3];
2112
      operands [3] = tmp;
2113
    }
2114
 
2115
  sprintf (buffer, "mvfc %s, cbr", dest);
2116
 
2117
  /* If the true value was '0' then we need to invert the results of the move.  */
2118
  if (INTVAL (operands [2]) == 0)
2119
    sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2120
             dest, dest);
2121
 
2122
  return buffer;
2123
}
2124
 
2125
/* Returns true if the registers contained in the two
2126
   rtl expressions are different.  */
2127
 
2128
int
2129
m32r_not_same_reg (rtx a, rtx b)
2130
{
2131
  int reg_a = -1;
2132
  int reg_b = -2;
2133
 
2134
  while (GET_CODE (a) == SUBREG)
2135
    a = SUBREG_REG (a);
2136
 
2137
  if (GET_CODE (a) == REG)
2138
    reg_a = REGNO (a);
2139
 
2140
  while (GET_CODE (b) == SUBREG)
2141
    b = SUBREG_REG (b);
2142
 
2143
  if (GET_CODE (b) == REG)
2144
    reg_b = REGNO (b);
2145
 
2146
  return reg_a != reg_b;
2147
}
2148
 
2149
 
2150
rtx
2151
m32r_function_symbol (const char *name)
2152
{
2153
  int extra_flags = 0;
2154
  enum m32r_model model;
2155
  rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2156
 
2157
  if (TARGET_MODEL_SMALL)
2158
    model = M32R_MODEL_SMALL;
2159
  else if (TARGET_MODEL_MEDIUM)
2160
    model = M32R_MODEL_MEDIUM;
2161
  else if (TARGET_MODEL_LARGE)
2162
    model = M32R_MODEL_LARGE;
2163
  else
2164
    gcc_unreachable (); /* Shouldn't happen.  */
2165
  extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
2166
 
2167
  if (extra_flags)
2168
    SYMBOL_REF_FLAGS (sym) |= extra_flags;
2169
 
2170
  return sym;
2171
}
2172
 
2173
/* Use a library function to move some bytes.  */
2174
 
2175
static void
2176
block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
2177
{
2178
  /* We want to pass the size as Pmode, which will normally be SImode
2179
     but will be DImode if we are using 64 bit longs and pointers.  */
2180
  if (GET_MODE (bytes_rtx) != VOIDmode
2181
      && GET_MODE (bytes_rtx) != Pmode)
2182
    bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2183
 
2184
  emit_library_call (m32r_function_symbol ("memcpy"), 0,
2185
                     VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2186
                     convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2187
                                      TYPE_UNSIGNED (sizetype)),
2188
                     TYPE_MODE (sizetype));
2189
}
2190
 
2191
/* Expand string/block move operations.
2192
 
2193
   operands[0] is the pointer to the destination.
2194
   operands[1] is the pointer to the source.
2195
   operands[2] is the number of bytes to move.
2196
   operands[3] is the alignment.
2197
 
2198
   Returns 1 upon success, 0 otherwise.  */
2199
 
2200
int
2201
m32r_expand_block_move (rtx operands[])
2202
{
2203
  rtx           orig_dst  = operands[0];
2204
  rtx           orig_src  = operands[1];
2205
  rtx           bytes_rtx = operands[2];
2206
  rtx           align_rtx = operands[3];
2207
  int           constp    = GET_CODE (bytes_rtx) == CONST_INT;
2208
  HOST_WIDE_INT bytes     = constp ? INTVAL (bytes_rtx) : 0;
2209
  int           align     = INTVAL (align_rtx);
2210
  int           leftover;
2211
  rtx           src_reg;
2212
  rtx           dst_reg;
2213
 
2214
  if (constp && bytes <= 0)
2215
    return 1;
2216
 
2217
  /* Move the address into scratch registers.  */
2218
  dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2219
  src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2220
 
2221
  if (align > UNITS_PER_WORD)
2222
    align = UNITS_PER_WORD;
2223
 
2224
  /* If we prefer size over speed, always use a function call.
2225
     If we do not know the size, use a function call.
2226
     If the blocks are not word aligned, use a function call.  */
2227
  if (optimize_size || ! constp || align != UNITS_PER_WORD)
2228
    {
2229
      block_move_call (dst_reg, src_reg, bytes_rtx);
2230
      return 0;
2231
    }
2232
 
2233
  leftover = bytes % MAX_MOVE_BYTES;
2234
  bytes   -= leftover;
2235
 
2236
  /* If necessary, generate a loop to handle the bulk of the copy.  */
2237
  if (bytes)
2238
    {
2239
      rtx label = NULL_RTX;
2240
      rtx final_src = NULL_RTX;
2241
      rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2242
      rtx rounded_total = GEN_INT (bytes);
2243
      rtx new_dst_reg = gen_reg_rtx (SImode);
2244
      rtx new_src_reg = gen_reg_rtx (SImode);
2245
 
2246
      /* If we are going to have to perform this loop more than
2247
         once, then generate a label and compute the address the
2248
         source register will contain upon completion of the final
2249
         iteration.  */
2250
      if (bytes > MAX_MOVE_BYTES)
2251
        {
2252
          final_src = gen_reg_rtx (Pmode);
2253
 
2254
          if (INT16_P(bytes))
2255
            emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2256
          else
2257
            {
2258
              emit_insn (gen_movsi (final_src, rounded_total));
2259
              emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2260
            }
2261
 
2262
          label = gen_label_rtx ();
2263
          emit_label (label);
2264
        }
2265
 
2266
      /* It is known that output_block_move() will update src_reg to point
2267
         to the word after the end of the source block, and dst_reg to point
2268
         to the last word of the destination block, provided that the block
2269
         is MAX_MOVE_BYTES long.  */
2270
      emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
2271
                                        new_dst_reg, new_src_reg));
2272
      emit_move_insn (dst_reg, new_dst_reg);
2273
      emit_move_insn (src_reg, new_src_reg);
2274
      emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2275
 
2276
      if (bytes > MAX_MOVE_BYTES)
2277
        {
2278
          emit_insn (gen_cmpsi (src_reg, final_src));
2279
          emit_jump_insn (gen_bne (label));
2280
        }
2281
    }
2282
 
2283
  if (leftover)
2284
    emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
2285
                                      gen_reg_rtx (SImode),
2286
                                      gen_reg_rtx (SImode)));
2287
  return 1;
2288
}
2289
 
2290
 
2291
/* Emit load/stores for a small constant word aligned block_move.
2292
 
2293
   operands[0] is the memory address of the destination.
2294
   operands[1] is the memory address of the source.
2295
   operands[2] is the number of bytes to move.
2296
   operands[3] is a temp register.
2297
   operands[4] is a temp register.  */
2298
 
2299
void
2300
m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
2301
{
2302
  HOST_WIDE_INT bytes = INTVAL (operands[2]);
2303
  int           first_time;
2304
  int           got_extra = 0;
2305
 
2306
  gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES);
2307
 
2308
  /* We do not have a post-increment store available, so the first set of
2309
     stores are done without any increment, then the remaining ones can use
2310
     the pre-increment addressing mode.
2311
 
2312
     Note: expand_block_move() also relies upon this behavior when building
2313
     loops to copy large blocks.  */
2314
  first_time = 1;
2315
 
2316
  while (bytes > 0)
2317
    {
2318
      if (bytes >= 8)
2319
        {
2320
          if (first_time)
2321
            {
2322
              output_asm_insn ("ld\t%5, %p1", operands);
2323
              output_asm_insn ("ld\t%6, %p1", operands);
2324
              output_asm_insn ("st\t%5, @%0", operands);
2325
              output_asm_insn ("st\t%6, %s0", operands);
2326
            }
2327
          else
2328
            {
2329
              output_asm_insn ("ld\t%5, %p1", operands);
2330
              output_asm_insn ("ld\t%6, %p1", operands);
2331
              output_asm_insn ("st\t%5, %s0", operands);
2332
              output_asm_insn ("st\t%6, %s0", operands);
2333
            }
2334
 
2335
          bytes -= 8;
2336
        }
2337
      else if (bytes >= 4)
2338
        {
2339
          if (bytes > 4)
2340
            got_extra = 1;
2341
 
2342
          output_asm_insn ("ld\t%5, %p1", operands);
2343
 
2344
          if (got_extra)
2345
            output_asm_insn ("ld\t%6, %p1", operands);
2346
 
2347
          if (first_time)
2348
            output_asm_insn ("st\t%5, @%0", operands);
2349
          else
2350
            output_asm_insn ("st\t%5, %s0", operands);
2351
 
2352
          bytes -= 4;
2353
        }
2354
      else
2355
        {
2356
          /* Get the entire next word, even though we do not want all of it.
2357
             The saves us from doing several smaller loads, and we assume that
2358
             we cannot cause a page fault when at least part of the word is in
2359
             valid memory [since we don't get called if things aren't properly
2360
             aligned].  */
2361
          int dst_offset = first_time ? 0 : 4;
2362
          /* The amount of increment we have to make to the
2363
             destination pointer.  */
2364
          int dst_inc_amount = dst_offset + bytes - 4;
2365
          /* The same for the source pointer.  */
2366
          int src_inc_amount = bytes;
2367
          int last_shift;
2368
          rtx my_operands[3];
2369
 
2370
          /* If got_extra is true then we have already loaded
2371
             the next word as part of loading and storing the previous word.  */
2372
          if (! got_extra)
2373
            output_asm_insn ("ld\t%6, @%1", operands);
2374
 
2375
          if (bytes >= 2)
2376
            {
2377
              bytes -= 2;
2378
 
2379
              output_asm_insn ("sra3\t%5, %6, #16", operands);
2380
              my_operands[0] = operands[5];
2381
              my_operands[1] = GEN_INT (dst_offset);
2382
              my_operands[2] = operands[0];
2383
              output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2384
 
2385
              /* If there is a byte left to store then increment the
2386
                 destination address and shift the contents of the source
2387
                 register down by 8 bits.  We could not do the address
2388
                 increment in the store half word instruction, because it does
2389
                 not have an auto increment mode.  */
2390
              if (bytes > 0)  /* assert (bytes == 1) */
2391
                {
2392
                  dst_offset += 2;
2393
                  last_shift = 8;
2394
                }
2395
            }
2396
          else
2397
            last_shift = 24;
2398
 
2399
          if (bytes > 0)
2400
            {
2401
              my_operands[0] = operands[6];
2402
              my_operands[1] = GEN_INT (last_shift);
2403
              output_asm_insn ("srai\t%0, #%1", my_operands);
2404
              my_operands[0] = operands[6];
2405
              my_operands[1] = GEN_INT (dst_offset);
2406
              my_operands[2] = operands[0];
2407
              output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2408
            }
2409
 
2410
          /* Update the destination pointer if needed.  We have to do
2411
             this so that the patterns matches what we output in this
2412
             function.  */
2413
          if (dst_inc_amount
2414
              && !find_reg_note (insn, REG_UNUSED, operands[0]))
2415
            {
2416
              my_operands[0] = operands[0];
2417
              my_operands[1] = GEN_INT (dst_inc_amount);
2418
              output_asm_insn ("addi\t%0, #%1", my_operands);
2419
            }
2420
 
2421
          /* Update the source pointer if needed.  We have to do this
2422
             so that the patterns matches what we output in this
2423
             function.  */
2424
          if (src_inc_amount
2425
              && !find_reg_note (insn, REG_UNUSED, operands[1]))
2426
            {
2427
              my_operands[0] = operands[1];
2428
              my_operands[1] = GEN_INT (src_inc_amount);
2429
              output_asm_insn ("addi\t%0, #%1", my_operands);
2430
            }
2431
 
2432
          bytes = 0;
2433
        }
2434
 
2435
      first_time = 0;
2436
    }
2437
}
2438
 
2439
/* Return true if using NEW_REG in place of OLD_REG is ok.  */
2440
 
2441
int
2442
m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2443
                           unsigned int new_reg)
2444
{
2445
  /* Interrupt routines can't clobber any register that isn't already used.  */
2446
  if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2447
      && !regs_ever_live[new_reg])
2448
    return 0;
2449
 
2450
  /* We currently emit epilogues as text, not rtl, so the liveness
2451
     of the return address register isn't visible.  */
2452
  if (current_function_is_leaf && new_reg == RETURN_ADDR_REGNUM)
2453
    return 0;
2454
 
2455
  return 1;
2456
}
2457
 
2458
rtx
2459
m32r_return_addr (int count)
2460
{
2461
  if (count != 0)
2462
    return const0_rtx;
2463
 
2464
  return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
2465
}

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