OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [m68hc11/] [m68hc12.h] - Blame information for rev 294

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
/* Definitions of target machine for GNU compiler, for m68hc12.
2
   Copyright (C) 1999, 2000, 2001, 2003, 2007 Free Software Foundation, Inc.
3
   Contributed by Stephane Carrez (stcarrez@nerim.fr).
4
 
5
This file is part of GCC.
6
 
7
GCC is free software; you can redistribute it and/or modify
8
it under the terms of the GNU General Public License as published by
9
the Free Software Foundation; either version 3, or (at your option)
10
any later version.
11
 
12
GCC is distributed in the hope that it will be useful,
13
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
GNU General Public License for more details.
16
 
17
You should have received a copy of the GNU General Public License
18
along with GCC; see the file COPYING3.  If not see
19
<http://www.gnu.org/licenses/>.  */
20
 
21
/* Compile and assemble for a 68hc12 unless there is a -m68hc11 option.  */
22
#define ASM_SPEC                                                \
23
"%{m68hc11:-m68hc11}"                                           \
24
"%{m68hcs12:-m68hcs12}"                                         \
25
"%{!m68hc11:%{!m68hcs12:-m68hc12}}"
26
#define LIB_SPEC       ""
27
#define CC1_SPEC       ""
28
 
29
/* We need to tell the linker the target elf format.  Just pass an
30
   emulation option.  This can be overridden by -Wl option of gcc.  */
31
#define LINK_SPEC                                               \
32
"%{m68hc11:-m m68hc11elf}"                                      \
33
"%{m68hcs12:-m m68hc12elf}"                                     \
34
"%{!m68hc11:%{!m68hcs12:-m m68hc11elf}} %{mrelax:-relax}"
35
 
36
#define CPP_SPEC  \
37
"%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16}\
38
 %{!mshort:-D__INT__=32}\
39
 %{m68hc11:-Dmc6811 -DMC6811 -Dmc68hc11}\
40
 %{!m68hc11:%{!m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}}\
41
 %{m68hcs12:-Dmc6812 -DMC6812 -Dmc68hcs12}\
42
 %{fshort-double:-D__HAVE_SHORT_DOUBLE__}"
43
 
44
/* Default target_flags if no switches specified.  */
45
#define TARGET_DEFAULT          (MASK_M6812)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.