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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [mips/] [5400.md] - Blame information for rev 455

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Line No. Rev Author Line
1 38 julius 
;; DFA-based pipeline description for 5400
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(define_automaton "vr54")
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(define_cpu_unit "vr54_dp0"     "vr54")
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(define_cpu_unit "vr54_dp1"     "vr54")
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(define_cpu_unit "vr54_mem"     "vr54")
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(define_cpu_unit "vr54_mac"     "vr54")
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;;
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;; The ordering of the instruction-execution-path/resource-usage
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;; descriptions (also known as reservation RTL) is roughly ordered
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;; based on the define attribute RTL for the "type" classification.
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;; When modifying, remember that the first test that matches is the
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;; reservation used!
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;;
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(define_insn_reservation "ir_vr54_unknown" 1
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "unknown"))
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  "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")
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;; Assume prediction fails.
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(define_insn_reservation "ir_vr54_branch" 3
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "branch,jump,call"))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_load" 2
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "load,fpload,fpidxload"))
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  "vr54_mem")
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(define_insn_reservation "ir_vr54_store" 1
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "store"))
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  "vr54_mem")
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(define_insn_reservation "ir_vr54_fstore" 1
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "fpstore,fpidxstore"))
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  "vr54_mem")
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;; This reservation is for conditional move based on integer
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;; or floating point CC.
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(define_insn_reservation "ir_vr54_condmove" 4
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "condmove"))
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  "vr54_dp0|vr54_dp1")
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;; Move to/from FPU registers
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(define_insn_reservation "ir_vr54_xfer" 2
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "xfer"))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_hilo" 1
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "mthilo,mfhilo"))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_arith" 1
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_imul_si" 3
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "imul,imul3")
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            (eq_attr "mode" "SI")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_imul_di" 4
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "imul,imul3")
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            (eq_attr "mode" "DI")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_imadd_si" 3
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "imul,imul3"))
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  "vr54_mac")
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(define_insn_reservation "ir_vr54_idiv_si" 42
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "idiv")
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            (eq_attr "mode" "SI")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_idiv_di" 74
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "idiv")
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            (eq_attr "mode" "DI")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_fadd" 4
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "fadd"))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_fmul_sf" 5
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "fmul")
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            (eq_attr "mode" "SF")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_fmul_df" 6
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "fmul")
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            (eq_attr "mode" "DF")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_fmadd_sf" 9
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "fmadd")
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            (eq_attr "mode" "SF")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_fmadd_df" 10
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "fmadd")
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            (eq_attr "mode" "DF")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_fdiv_sf" 42
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "fdiv,frdiv,fsqrt")
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            (eq_attr "mode" "SF")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_fdiv_df" 72
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "fdiv,frdiv,fsqrt")
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            (eq_attr "mode" "DF")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_fabs" 2
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "fabs,fneg,fmove"))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_fcmp" 2
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "fcmp"))
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  "vr54_dp0|vr54_dp1")
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146 
(define_insn_reservation "ir_vr54_fcvt" 6
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "fcvt"))
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  "vr54_dp0|vr54_dp1")
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151 
(define_insn_reservation "ir_vr54_frsqrt_sf" 61
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "frsqrt")
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            (eq_attr "mode" "SF")))
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  "vr54_dp0|vr54_dp1")
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157 
(define_insn_reservation "ir_vr54_frsqrt_df" 121
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  (and (eq_attr "cpu" "r5400")
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       (and (eq_attr "type" "frsqrt")
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            (eq_attr "mode" "DF")))
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  "vr54_dp0|vr54_dp1")
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(define_insn_reservation "ir_vr54_multi" 1
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  (and (eq_attr "cpu" "r5400")
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       (eq_attr "type" "multi"))
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  "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")

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