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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [mips/] [5500.md] - Blame information for rev 294

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Line No. Rev Author Line
1 38 julius 
;; DFA-based pipeline description for 5500
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(define_automaton "vr55")
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(define_cpu_unit "vr55_dp0"     "vr55")
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(define_cpu_unit "vr55_dp1"     "vr55")
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(define_cpu_unit "vr55_mem"     "vr55")
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(define_cpu_unit "vr55_mac"     "vr55")
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(define_cpu_unit "vr55_fp"      "vr55")
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(define_cpu_unit "vr55_bru"     "vr55")
9 
 
10 
;;
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;; The ordering of the instruction-execution-path/resource-usage
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;; descriptions (also known as reservation RTL) is roughly ordered
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;; based on the define attribute RTL for the "type" classification.
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;; When modifying, remember that the first test that matches is the
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;; reservation used!
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;;
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18 
(define_insn_reservation "ir_vr55_unknown" 1
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "unknown"))
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  "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru")
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23 
;; Assume prediction fails.
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(define_insn_reservation "ir_vr55_branch" 2
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "branch,jump,call"))
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  "vr55_bru")
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29 
(define_insn_reservation "ir_vr55_load" 3
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "load,fpload,fpidxload"))
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  "vr55_mem")
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34 
(define_bypass 4
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  "ir_vr55_load"
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  "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd,
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   ir_vr55_idiv_si,ir_vr55_idiv_di")
38 
 
39 
(define_insn_reservation "ir_vr55_store" 0
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "store,fpstore,fpidxstore"))
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  "vr55_mem")
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44 
;; This reservation is for conditional move based on integer
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;; or floating point CC.
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(define_insn_reservation "ir_vr55_condmove" 2
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "condmove"))
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  "vr55_dp0|vr55_dp1")
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51 
;; Move to/from FPU registers
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(define_insn_reservation "ir_vr55_xfer" 2
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "xfer"))
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  "vr55_dp0|vr55_dp1")
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57 
(define_insn_reservation "ir_vr55_arith" 1
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
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  "vr55_dp0|vr55_dp1")
61 
 
62 
(define_bypass 2
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  "ir_vr55_arith"
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  "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd,
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   ir_vr55_idiv_si,ir_vr55_idiv_di")
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(define_insn_reservation "ir_vr55_mthilo" 1
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "mthilo"))
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  "vr55_mac")
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72 
(define_insn_reservation "ir_vr55_mfhilo" 5
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "mfhilo"))
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  "vr55_mac")
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77 
;; The default latency is for the GPR result of a mul.  Bypasses handle the
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;; latency of {mul,mult}->{mfhi,mflo}.
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(define_insn_reservation "ir_vr55_imul_si" 5
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  (and (eq_attr "cpu" "r5500")
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       (and (eq_attr "type" "imul,imul3")
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            (eq_attr "mode" "SI")))
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  "vr55_mac")
84 
 
85 
;; The default latency is for pre-reload scheduling and handles the case
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;; where a pseudo destination will be stored in a GPR (as it usually is).
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;; The delay includes the latency of the dmult itself and the anticipated
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;; mflo or mfhi.
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;;
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;; Once the mflo or mfhi has been created, bypasses handle the latency
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;; between it and the dmult.
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(define_insn_reservation "ir_vr55_imul_di" 9
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  (and (eq_attr "cpu" "r5500")
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       (and (eq_attr "type" "imul,imul3")
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            (eq_attr "mode" "DI")))
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  "vr55_mac*4")
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;; The default latency is as for ir_vr55_imul_si.
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(define_insn_reservation "ir_vr55_imadd" 5
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "imadd"))
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  "vr55_mac")
103 
 
104 
(define_bypass 1
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  "ir_vr55_imul_si,ir_vr55_imadd"
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  "ir_vr55_imadd"
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  "mips_linked_madd_p")
108 
 
109 
(define_bypass 2
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  "ir_vr55_imul_si,ir_vr55_imadd"
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  "ir_vr55_mfhilo")
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113 
(define_bypass 4
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  "ir_vr55_imul_di"
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  "ir_vr55_mfhilo")
116 
 
117 
;; Divide algorithm is early out with best latency of 7 pcycles.
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;; Use worst case for scheduling purposes.
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(define_insn_reservation "ir_vr55_idiv_si" 42
120 
  (and (eq_attr "cpu" "r5500")
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       (and (eq_attr "type" "idiv")
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            (eq_attr "mode" "SI")))
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  "vr55_mac")
124 
 
125 
(define_insn_reservation "ir_vr55_idiv_di" 74
126 
  (and (eq_attr "cpu" "r5500")
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       (and (eq_attr "type" "idiv")
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            (eq_attr "mode" "DI")))
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  "vr55_mac")
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131 
(define_insn_reservation "ir_vr55_fadd" 4
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "fadd"))
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  "vr55_fp")
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(define_insn_reservation "ir_vr55_fmul_sf" 5
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  (and (eq_attr "cpu" "r5500")
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       (and (eq_attr "type" "fmul")
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            (eq_attr "mode" "SF")))
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  "vr55_mac")
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142 
(define_insn_reservation "ir_vr55_fmul_df" 6
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  (and (eq_attr "cpu" "r5500")
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       (and (eq_attr "type" "fmul")
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            (eq_attr "mode" "DF")))
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  "vr55_mac")
147 
 
148 
(define_insn_reservation "ir_vr55_fmadd_sf" 9
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  (and (eq_attr "cpu" "r5500")
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       (and (eq_attr "type" "fmadd")
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            (eq_attr "mode" "SF")))
152 
  "vr55_mac")
153 
 
154 
(define_insn_reservation "ir_vr55_fmadd_df" 10
155 
  (and (eq_attr "cpu" "r5500")
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       (and (eq_attr "type" "fmadd")
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            (eq_attr "mode" "DF")))
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  "vr55_mac")
159 
 
160 
(define_insn_reservation "ir_vr55_fdiv_sf" 30
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  (and (eq_attr "cpu" "r5500")
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       (and (eq_attr "type" "fdiv,frdiv,fsqrt")
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            (eq_attr "mode" "SF")))
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  "vr55_mac")
165 
 
166 
(define_insn_reservation "ir_vr55_fdiv_df" 59
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  (and (eq_attr "cpu" "r5500")
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       (and (eq_attr "type" "fdiv,frdiv,fsqrt")
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            (eq_attr "mode" "DF")))
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  "vr55_mac")
171 
 
172 
(define_insn_reservation "ir_vr55_fabs" 2
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  (and (eq_attr "cpu" "r5500")
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       (eq_attr "type" "fabs,fneg,fmove"))
175 
  "vr55_fp")
176 
 
177 
(define_insn_reservation "ir_vr55_fcmp" 2
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  (and (eq_attr "cpu" "r5500")
179 
       (eq_attr "type" "fcmp"))
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  "vr55_fp")
181 
 
182 
(define_insn_reservation "ir_vr55_fcvt_sf" 4
183 
  (and (eq_attr "cpu" "r5500")
184 
       (and (eq_attr "type" "fcvt")
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            (eq_attr "mode" "SF")))
186 
  "vr55_fp")
187 
 
188 
(define_insn_reservation "ir_vr55_fcvt_df" 6
189 
  (and (eq_attr "cpu" "r5500")
190 
       (and (eq_attr "type" "fcvt")
191 
            (eq_attr "mode" "DF")))
192 
  "vr55_fp")
193 
 
194 
(define_insn_reservation "ir_vr55_frsqrt_sf" 60
195 
  (and (eq_attr "cpu" "r5500")
196 
       (and (eq_attr "type" "frsqrt")
197 
            (eq_attr "mode" "SF")))
198 
  "vr55_mac")
199 
 
200 
(define_insn_reservation "ir_vr55_frsqrt_df" 118
201 
  (and (eq_attr "cpu" "r5500")
202 
       (and (eq_attr "type" "frsqrt")
203 
            (eq_attr "mode" "DF")))
204 
  "vr55_mac")
205 
 
206 
(define_insn_reservation "ir_vr55_multi" 1
207 
  (and (eq_attr "cpu" "r5500")
208 
       (eq_attr "type" "multi"))
209 
  "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru")

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