OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [mips/] [mips-modes.def] - Blame information for rev 199

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
/* MIPS extra machine modes.
2
   Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
3
 
4
This file is part of GCC.
5
 
6
GCC is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 3, or (at your option)
9
any later version.
10
 
11
GCC is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with GCC; see the file COPYING3.  If not see
18
.  */
19
 
20
/* MIPS has a quirky almost-IEEE format for all its
21
   floating point.  */
22
RESET_FLOAT_FORMAT (SF, mips_single_format);
23
RESET_FLOAT_FORMAT (DF, mips_double_format);
24
 
25
/* Irix6 will override this via MIPS_TFMODE_FORMAT.  */
26
FLOAT_MODE (TF, 16, mips_quad_format);
27
 
28
/* Vector modes.  */
29
VECTOR_MODES (FLOAT, 8);      /*            V4HF V2SF */
30
VECTOR_MODES (INT, 4);        /*            V4QI V2HI */
31
 
32
/* Paired single comparison instructions use 2 or 4 CC.  */
33
CC_MODE (CCV2);
34
ADJUST_BYTESIZE (CCV2, 8);
35
ADJUST_ALIGNMENT (CCV2, 8);
36
 
37
CC_MODE (CCV4);
38
ADJUST_BYTESIZE (CCV4, 16);
39
ADJUST_ALIGNMENT (CCV4, 16);
40
 
41
/* For MIPS DSP control registers.  */
42
CC_MODE (CCDSP);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.