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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [mips/] [mips.c] - Blame information for rev 154

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1 38 julius
/* Subroutines used for MIPS code generation.
2
   Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3
   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
4
   Contributed by A. Lichnewsky, lich@inria.inria.fr.
5
   Changes by Michael Meissner, meissner@osf.org.
6
   64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7
   Brendan Eich, brendan@microunity.com.
8
 
9
This file is part of GCC.
10
 
11
GCC is free software; you can redistribute it and/or modify
12
it under the terms of the GNU General Public License as published by
13
the Free Software Foundation; either version 3, or (at your option)
14
any later version.
15
 
16
GCC is distributed in the hope that it will be useful,
17
but WITHOUT ANY WARRANTY; without even the implied warranty of
18
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
GNU General Public License for more details.
20
 
21
You should have received a copy of the GNU General Public License
22
along with GCC; see the file COPYING3.  If not see
23
<http://www.gnu.org/licenses/>.  */
24
 
25
#include "config.h"
26
#include "system.h"
27
#include "coretypes.h"
28
#include "tm.h"
29
#include <signal.h>
30
#include "rtl.h"
31
#include "regs.h"
32
#include "hard-reg-set.h"
33
#include "real.h"
34
#include "insn-config.h"
35
#include "conditions.h"
36
#include "insn-attr.h"
37
#include "recog.h"
38
#include "toplev.h"
39
#include "output.h"
40
#include "tree.h"
41
#include "function.h"
42
#include "expr.h"
43
#include "optabs.h"
44
#include "flags.h"
45
#include "reload.h"
46
#include "tm_p.h"
47
#include "ggc.h"
48
#include "gstab.h"
49
#include "hashtab.h"
50
#include "debug.h"
51
#include "target.h"
52
#include "target-def.h"
53
#include "integrate.h"
54
#include "langhooks.h"
55
#include "cfglayout.h"
56
#include "sched-int.h"
57
#include "tree-gimple.h"
58
#include "bitmap.h"
59
 
60
/* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF.  */
61
#define UNSPEC_ADDRESS_P(X)                                     \
62
  (GET_CODE (X) == UNSPEC                                       \
63
   && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST                       \
64
   && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
65
 
66
/* Extract the symbol or label from UNSPEC wrapper X.  */
67
#define UNSPEC_ADDRESS(X) \
68
  XVECEXP (X, 0, 0)
69
 
70
/* Extract the symbol type from UNSPEC wrapper X.  */
71
#define UNSPEC_ADDRESS_TYPE(X) \
72
  ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
73
 
74
/* The maximum distance between the top of the stack frame and the
75
   value $sp has when we save & restore registers.
76
 
77
   Use a maximum gap of 0x100 in the mips16 case.  We can then use
78
   unextended instructions to save and restore registers, and to
79
   allocate and deallocate the top part of the frame.
80
 
81
   The value in the !mips16 case must be a SMALL_OPERAND and must
82
   preserve the maximum stack alignment.  */
83
#define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
84
 
85
/* True if INSN is a mips.md pattern or asm statement.  */
86
#define USEFUL_INSN_P(INSN)                                             \
87
  (INSN_P (INSN)                                                        \
88
   && GET_CODE (PATTERN (INSN)) != USE                                  \
89
   && GET_CODE (PATTERN (INSN)) != CLOBBER                              \
90
   && GET_CODE (PATTERN (INSN)) != ADDR_VEC                             \
91
   && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
92
 
93
/* If INSN is a delayed branch sequence, return the first instruction
94
   in the sequence, otherwise return INSN itself.  */
95
#define SEQ_BEGIN(INSN)                                                 \
96
  (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE               \
97
   ? XVECEXP (PATTERN (INSN), 0, 0)                                       \
98
   : (INSN))
99
 
100
/* Likewise for the last instruction in a delayed branch sequence.  */
101
#define SEQ_END(INSN)                                                   \
102
  (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE               \
103
   ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
104
   : (INSN))
105
 
106
/* Execute the following loop body with SUBINSN set to each instruction
107
   between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive.  */
108
#define FOR_EACH_SUBINSN(SUBINSN, INSN)                                 \
109
  for ((SUBINSN) = SEQ_BEGIN (INSN);                                    \
110
       (SUBINSN) != NEXT_INSN (SEQ_END (INSN));                         \
111
       (SUBINSN) = NEXT_INSN (SUBINSN))
112
 
113
/* Classifies an address.
114
 
115
   ADDRESS_REG
116
       A natural register + offset address.  The register satisfies
117
       mips_valid_base_register_p and the offset is a const_arith_operand.
118
 
119
   ADDRESS_LO_SUM
120
       A LO_SUM rtx.  The first operand is a valid base register and
121
       the second operand is a symbolic address.
122
 
123
   ADDRESS_CONST_INT
124
       A signed 16-bit constant address.
125
 
126
   ADDRESS_SYMBOLIC:
127
       A constant symbolic address (equivalent to CONSTANT_SYMBOLIC).  */
128
enum mips_address_type {
129
  ADDRESS_REG,
130
  ADDRESS_LO_SUM,
131
  ADDRESS_CONST_INT,
132
  ADDRESS_SYMBOLIC
133
};
134
 
135
/* Classifies the prototype of a builtin function.  */
136
enum mips_function_type
137
{
138
  MIPS_V2SF_FTYPE_V2SF,
139
  MIPS_V2SF_FTYPE_V2SF_V2SF,
140
  MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
141
  MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
142
  MIPS_V2SF_FTYPE_SF_SF,
143
  MIPS_INT_FTYPE_V2SF_V2SF,
144
  MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
145
  MIPS_INT_FTYPE_SF_SF,
146
  MIPS_INT_FTYPE_DF_DF,
147
  MIPS_SF_FTYPE_V2SF,
148
  MIPS_SF_FTYPE_SF,
149
  MIPS_SF_FTYPE_SF_SF,
150
  MIPS_DF_FTYPE_DF,
151
  MIPS_DF_FTYPE_DF_DF,
152
 
153
  /* For MIPS DSP ASE  */
154
  MIPS_DI_FTYPE_DI_SI,
155
  MIPS_DI_FTYPE_DI_SI_SI,
156
  MIPS_DI_FTYPE_DI_V2HI_V2HI,
157
  MIPS_DI_FTYPE_DI_V4QI_V4QI,
158
  MIPS_SI_FTYPE_DI_SI,
159
  MIPS_SI_FTYPE_PTR_SI,
160
  MIPS_SI_FTYPE_SI,
161
  MIPS_SI_FTYPE_SI_SI,
162
  MIPS_SI_FTYPE_V2HI,
163
  MIPS_SI_FTYPE_V2HI_V2HI,
164
  MIPS_SI_FTYPE_V4QI,
165
  MIPS_SI_FTYPE_V4QI_V4QI,
166
  MIPS_SI_FTYPE_VOID,
167
  MIPS_V2HI_FTYPE_SI,
168
  MIPS_V2HI_FTYPE_SI_SI,
169
  MIPS_V2HI_FTYPE_V2HI,
170
  MIPS_V2HI_FTYPE_V2HI_SI,
171
  MIPS_V2HI_FTYPE_V2HI_V2HI,
172
  MIPS_V2HI_FTYPE_V4QI,
173
  MIPS_V2HI_FTYPE_V4QI_V2HI,
174
  MIPS_V4QI_FTYPE_SI,
175
  MIPS_V4QI_FTYPE_V2HI_V2HI,
176
  MIPS_V4QI_FTYPE_V4QI_SI,
177
  MIPS_V4QI_FTYPE_V4QI_V4QI,
178
  MIPS_VOID_FTYPE_SI_SI,
179
  MIPS_VOID_FTYPE_V2HI_V2HI,
180
  MIPS_VOID_FTYPE_V4QI_V4QI,
181
 
182
  /* The last type.  */
183
  MIPS_MAX_FTYPE_MAX
184
};
185
 
186
/* Specifies how a builtin function should be converted into rtl.  */
187
enum mips_builtin_type
188
{
189
  /* The builtin corresponds directly to an .md pattern.  The return
190
     value is mapped to operand 0 and the arguments are mapped to
191
     operands 1 and above.  */
192
  MIPS_BUILTIN_DIRECT,
193
 
194
  /* The builtin corresponds directly to an .md pattern.  There is no return
195
     value and the arguments are mapped to operands 0 and above.  */
196
  MIPS_BUILTIN_DIRECT_NO_TARGET,
197
 
198
  /* The builtin corresponds to a comparison instruction followed by
199
     a mips_cond_move_tf_ps pattern.  The first two arguments are the
200
     values to compare and the second two arguments are the vector
201
     operands for the movt.ps or movf.ps instruction (in assembly order).  */
202
  MIPS_BUILTIN_MOVF,
203
  MIPS_BUILTIN_MOVT,
204
 
205
  /* The builtin corresponds to a V2SF comparison instruction.  Operand 0
206
     of this instruction is the result of the comparison, which has mode
207
     CCV2 or CCV4.  The function arguments are mapped to operands 1 and
208
     above.  The function's return value is an SImode boolean that is
209
     true under the following conditions:
210
 
211
     MIPS_BUILTIN_CMP_ANY: one of the registers is true
212
     MIPS_BUILTIN_CMP_ALL: all of the registers are true
213
     MIPS_BUILTIN_CMP_LOWER: the first register is true
214
     MIPS_BUILTIN_CMP_UPPER: the second register is true.  */
215
  MIPS_BUILTIN_CMP_ANY,
216
  MIPS_BUILTIN_CMP_ALL,
217
  MIPS_BUILTIN_CMP_UPPER,
218
  MIPS_BUILTIN_CMP_LOWER,
219
 
220
  /* As above, but the instruction only sets a single $fcc register.  */
221
  MIPS_BUILTIN_CMP_SINGLE,
222
 
223
  /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */
224
  MIPS_BUILTIN_BPOSGE32
225
};
226
 
227
/* Invokes MACRO (COND) for each c.cond.fmt condition.  */
228
#define MIPS_FP_CONDITIONS(MACRO) \
229
  MACRO (f),    \
230
  MACRO (un),   \
231
  MACRO (eq),   \
232
  MACRO (ueq),  \
233
  MACRO (olt),  \
234
  MACRO (ult),  \
235
  MACRO (ole),  \
236
  MACRO (ule),  \
237
  MACRO (sf),   \
238
  MACRO (ngle), \
239
  MACRO (seq),  \
240
  MACRO (ngl),  \
241
  MACRO (lt),   \
242
  MACRO (nge),  \
243
  MACRO (le),   \
244
  MACRO (ngt)
245
 
246
/* Enumerates the codes above as MIPS_FP_COND_<X>.  */
247
#define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
248
enum mips_fp_condition {
249
  MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
250
};
251
 
252
/* Index X provides the string representation of MIPS_FP_COND_<X>.  */
253
#define STRINGIFY(X) #X
254
static const char *const mips_fp_conditions[] = {
255
  MIPS_FP_CONDITIONS (STRINGIFY)
256
};
257
 
258
/* A function to save or store a register.  The first argument is the
259
   register and the second is the stack slot.  */
260
typedef void (*mips_save_restore_fn) (rtx, rtx);
261
 
262
struct mips16_constant;
263
struct mips_arg_info;
264
struct mips_address_info;
265
struct mips_integer_op;
266
struct mips_sim;
267
 
268
static enum mips_symbol_type mips_classify_symbol (rtx);
269
static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
270
static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
271
static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
272
static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
273
static bool mips_classify_address (struct mips_address_info *, rtx,
274
                                   enum machine_mode, int);
275
static bool mips_cannot_force_const_mem (rtx);
276
static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
277
static int mips_symbol_insns (enum mips_symbol_type);
278
static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
279
static rtx mips_force_temporary (rtx, rtx);
280
static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
281
static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
282
static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
283
static unsigned int mips_build_lower (struct mips_integer_op *,
284
                                      unsigned HOST_WIDE_INT);
285
static unsigned int mips_build_integer (struct mips_integer_op *,
286
                                        unsigned HOST_WIDE_INT);
287
static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
288
static int m16_check_op (rtx, int, int, int);
289
static bool mips_rtx_costs (rtx, int, int, int *);
290
static int mips_address_cost (rtx);
291
static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
292
static void mips_load_call_address (rtx, rtx, int);
293
static bool mips_function_ok_for_sibcall (tree, tree);
294
static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
295
static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
296
static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
297
static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
298
                           tree, int, struct mips_arg_info *);
299
static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
300
static void mips_set_architecture (const struct mips_cpu_info *);
301
static void mips_set_tune (const struct mips_cpu_info *);
302
static bool mips_handle_option (size_t, const char *, int);
303
static struct machine_function *mips_init_machine_status (void);
304
static void print_operand_reloc (FILE *, rtx, const char **);
305
#if TARGET_IRIX
306
static void irix_output_external_libcall (rtx);
307
#endif
308
static void mips_file_start (void);
309
static void mips_file_end (void);
310
static bool mips_rewrite_small_data_p (rtx);
311
static int mips_small_data_pattern_1 (rtx *, void *);
312
static int mips_rewrite_small_data_1 (rtx *, void *);
313
static bool mips_function_has_gp_insn (void);
314
static unsigned int mips_global_pointer (void);
315
static bool mips_save_reg_p (unsigned int);
316
static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
317
                                   mips_save_restore_fn);
318
static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
319
static void mips_output_cplocal (void);
320
static void mips_emit_loadgp (void);
321
static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
322
static void mips_set_frame_expr (rtx);
323
static rtx mips_frame_set (rtx, rtx);
324
static void mips_save_reg (rtx, rtx);
325
static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
326
static void mips_restore_reg (rtx, rtx);
327
static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
328
                                  HOST_WIDE_INT, tree);
329
static int symbolic_expression_p (rtx);
330
static section *mips_select_rtx_section (enum machine_mode, rtx,
331
                                         unsigned HOST_WIDE_INT);
332
static section *mips_function_rodata_section (tree);
333
static bool mips_in_small_data_p (tree);
334
static bool mips_use_anchors_for_symbol_p (rtx);
335
static int mips_fpr_return_fields (tree, tree *);
336
static bool mips_return_in_msb (tree);
337
static rtx mips_return_fpr_pair (enum machine_mode mode,
338
                                 enum machine_mode mode1, HOST_WIDE_INT,
339
                                 enum machine_mode mode2, HOST_WIDE_INT);
340
static rtx mips16_gp_pseudo_reg (void);
341
static void mips16_fp_args (FILE *, int, int);
342
static void build_mips16_function_stub (FILE *);
343
static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
344
static void dump_constants (struct mips16_constant *, rtx);
345
static int mips16_insn_length (rtx);
346
static int mips16_rewrite_pool_refs (rtx *, void *);
347
static void mips16_lay_out_constants (void);
348
static void mips_sim_reset (struct mips_sim *);
349
static void mips_sim_init (struct mips_sim *, state_t);
350
static void mips_sim_next_cycle (struct mips_sim *);
351
static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
352
static int mips_sim_wait_regs_2 (rtx *, void *);
353
static void mips_sim_wait_regs_1 (rtx *, void *);
354
static void mips_sim_wait_regs (struct mips_sim *, rtx);
355
static void mips_sim_wait_units (struct mips_sim *, rtx);
356
static void mips_sim_wait_insn (struct mips_sim *, rtx);
357
static void mips_sim_record_set (rtx, rtx, void *);
358
static void mips_sim_issue_insn (struct mips_sim *, rtx);
359
static void mips_sim_issue_nop (struct mips_sim *);
360
static void mips_sim_finish_insn (struct mips_sim *, rtx);
361
static void vr4130_avoid_branch_rt_conflict (rtx);
362
static void vr4130_align_insns (void);
363
static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
364
static void mips_avoid_hazards (void);
365
static void mips_reorg (void);
366
static bool mips_strict_matching_cpu_name_p (const char *, const char *);
367
static bool mips_matching_cpu_name_p (const char *, const char *);
368
static const struct mips_cpu_info *mips_parse_cpu (const char *);
369
static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
370
static bool mips_return_in_memory (tree, tree);
371
static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
372
static void mips_macc_chains_record (rtx);
373
static void mips_macc_chains_reorder (rtx *, int);
374
static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
375
static bool vr4130_true_reg_dependence_p (rtx);
376
static bool vr4130_swap_insns_p (rtx, rtx);
377
static void vr4130_reorder (rtx *, int);
378
static void mips_promote_ready (rtx *, int, int);
379
static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
380
static int mips_variable_issue (FILE *, int, rtx, int);
381
static int mips_adjust_cost (rtx, rtx, rtx, int);
382
static int mips_issue_rate (void);
383
static int mips_multipass_dfa_lookahead (void);
384
static void mips_init_libfuncs (void);
385
static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
386
                                         tree, int *, int);
387
static tree mips_build_builtin_va_list (void);
388
static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
389
static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
390
                                    tree, bool);
391
static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
392
                                tree, bool);
393
static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
394
                                   tree, bool);
395
static bool mips_valid_pointer_mode (enum machine_mode);
396
static bool mips_vector_mode_supported_p (enum machine_mode);
397
static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
398
static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
399
static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
400
static void mips_init_builtins (void);
401
static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
402
static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
403
                                      enum insn_code, enum mips_fp_condition,
404
                                      rtx, tree);
405
static rtx mips_expand_builtin_compare (enum mips_builtin_type,
406
                                        enum insn_code, enum mips_fp_condition,
407
                                        rtx, tree);
408
static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
409
static void mips_encode_section_info (tree, rtx, int);
410
static void mips_extra_live_on_entry (bitmap);
411
static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
412
 
413
/* Structure to be filled in by compute_frame_size with register
414
   save masks, and offsets for the current function.  */
415
 
416
struct mips_frame_info GTY(())
417
{
418
  HOST_WIDE_INT total_size;     /* # bytes that the entire frame takes up */
419
  HOST_WIDE_INT var_size;       /* # bytes that variables take up */
420
  HOST_WIDE_INT args_size;      /* # bytes that outgoing arguments take up */
421
  HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
422
  HOST_WIDE_INT gp_reg_size;    /* # bytes needed to store gp regs */
423
  HOST_WIDE_INT fp_reg_size;    /* # bytes needed to store fp regs */
424
  unsigned int mask;            /* mask of saved gp registers */
425
  unsigned int fmask;           /* mask of saved fp registers */
426
  HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
427
  HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
428
  HOST_WIDE_INT gp_sp_offset;   /* offset from new sp to store gp registers */
429
  HOST_WIDE_INT fp_sp_offset;   /* offset from new sp to store fp registers */
430
  bool initialized;             /* true if frame size already calculated */
431
  int num_gp;                   /* number of gp registers saved */
432
  int num_fp;                   /* number of fp registers saved */
433
};
434
 
435
struct machine_function GTY(()) {
436
  /* Pseudo-reg holding the value of $28 in a mips16 function which
437
     refers to GP relative global variables.  */
438
  rtx mips16_gp_pseudo_rtx;
439
 
440
  /* The number of extra stack bytes taken up by register varargs.
441
     This area is allocated by the callee at the very top of the frame.  */
442
  int varargs_size;
443
 
444
  /* Current frame information, calculated by compute_frame_size.  */
445
  struct mips_frame_info frame;
446
 
447
  /* The register to use as the global pointer within this function.  */
448
  unsigned int global_pointer;
449
 
450
  /* True if mips_adjust_insn_length should ignore an instruction's
451
     hazard attribute.  */
452
  bool ignore_hazard_length_p;
453
 
454
  /* True if the whole function is suitable for .set noreorder and
455
     .set nomacro.  */
456
  bool all_noreorder_p;
457
 
458
  /* True if the function is known to have an instruction that needs $gp.  */
459
  bool has_gp_insn_p;
460
};
461
 
462
/* Information about a single argument.  */
463
struct mips_arg_info
464
{
465
  /* True if the argument is passed in a floating-point register, or
466
     would have been if we hadn't run out of registers.  */
467
  bool fpr_p;
468
 
469
  /* The number of words passed in registers, rounded up.  */
470
  unsigned int reg_words;
471
 
472
  /* For EABI, the offset of the first register from GP_ARG_FIRST or
473
     FP_ARG_FIRST.  For other ABIs, the offset of the first register from
474
     the start of the ABI's argument structure (see the CUMULATIVE_ARGS
475
     comment for details).
476
 
477
     The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
478
     on the stack.  */
479
  unsigned int reg_offset;
480
 
481
  /* The number of words that must be passed on the stack, rounded up.  */
482
  unsigned int stack_words;
483
 
484
  /* The offset from the start of the stack overflow area of the argument's
485
     first stack word.  Only meaningful when STACK_WORDS is nonzero.  */
486
  unsigned int stack_offset;
487
};
488
 
489
 
490
/* Information about an address described by mips_address_type.
491
 
492
   ADDRESS_CONST_INT
493
       No fields are used.
494
 
495
   ADDRESS_REG
496
       REG is the base register and OFFSET is the constant offset.
497
 
498
   ADDRESS_LO_SUM
499
       REG is the register that contains the high part of the address,
500
       OFFSET is the symbolic address being referenced and SYMBOL_TYPE
501
       is the type of OFFSET's symbol.
502
 
503
   ADDRESS_SYMBOLIC
504
       SYMBOL_TYPE is the type of symbol being referenced.  */
505
 
506
struct mips_address_info
507
{
508
  enum mips_address_type type;
509
  rtx reg;
510
  rtx offset;
511
  enum mips_symbol_type symbol_type;
512
};
513
 
514
 
515
/* One stage in a constant building sequence.  These sequences have
516
   the form:
517
 
518
        A = VALUE[0]
519
        A = A CODE[1] VALUE[1]
520
        A = A CODE[2] VALUE[2]
521
        ...
522
 
523
   where A is an accumulator, each CODE[i] is a binary rtl operation
524
   and each VALUE[i] is a constant integer.  */
525
struct mips_integer_op {
526
  enum rtx_code code;
527
  unsigned HOST_WIDE_INT value;
528
};
529
 
530
 
531
/* The largest number of operations needed to load an integer constant.
532
   The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
533
   When the lowest bit is clear, we can try, but reject a sequence with
534
   an extra SLL at the end.  */
535
#define MIPS_MAX_INTEGER_OPS 7
536
 
537
 
538
/* Global variables for machine-dependent things.  */
539
 
540
/* Threshold for data being put into the small data/bss area, instead
541
   of the normal data area.  */
542
int mips_section_threshold = -1;
543
 
544
/* Count the number of .file directives, so that .loc is up to date.  */
545
int num_source_filenames = 0;
546
 
547
/* Count the number of sdb related labels are generated (to find block
548
   start and end boundaries).  */
549
int sdb_label_count = 0;
550
 
551
/* Next label # for each statement for Silicon Graphics IRIS systems.  */
552
int sym_lineno = 0;
553
 
554
/* Linked list of all externals that are to be emitted when optimizing
555
   for the global pointer if they haven't been declared by the end of
556
   the program with an appropriate .comm or initialization.  */
557
 
558
struct extern_list GTY (())
559
{
560
  struct extern_list *next;     /* next external */
561
  const char *name;             /* name of the external */
562
  int size;                     /* size in bytes */
563
};
564
 
565
static GTY (()) struct extern_list *extern_head = 0;
566
 
567
/* Name of the file containing the current function.  */
568
const char *current_function_file = "";
569
 
570
/* Number of nested .set noreorder, noat, nomacro, and volatile requests.  */
571
int set_noreorder;
572
int set_noat;
573
int set_nomacro;
574
int set_volatile;
575
 
576
/* The next branch instruction is a branch likely, not branch normal.  */
577
int mips_branch_likely;
578
 
579
/* The operands passed to the last cmpMM expander.  */
580
rtx cmp_operands[2];
581
 
582
/* The target cpu for code generation.  */
583
enum processor_type mips_arch;
584
const struct mips_cpu_info *mips_arch_info;
585
 
586
/* The target cpu for optimization and scheduling.  */
587
enum processor_type mips_tune;
588
const struct mips_cpu_info *mips_tune_info;
589
 
590
/* Which instruction set architecture to use.  */
591
int mips_isa;
592
 
593
/* Which ABI to use.  */
594
int mips_abi = MIPS_ABI_DEFAULT;
595
 
596
/* Cost information to use.  */
597
const struct mips_rtx_cost_data *mips_cost;
598
 
599
/* Whether we are generating mips16 hard float code.  In mips16 mode
600
   we always set TARGET_SOFT_FLOAT; this variable is nonzero if
601
   -msoft-float was not specified by the user, which means that we
602
   should arrange to call mips32 hard floating point code.  */
603
int mips16_hard_float;
604
 
605
/* The architecture selected by -mipsN.  */
606
static const struct mips_cpu_info *mips_isa_info;
607
 
608
/* If TRUE, we split addresses into their high and low parts in the RTL.  */
609
int mips_split_addresses;
610
 
611
/* Mode used for saving/restoring general purpose registers.  */
612
static enum machine_mode gpr_mode;
613
 
614
/* Array giving truth value on whether or not a given hard register
615
   can support a given mode.  */
616
char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
617
 
618
/* List of all MIPS punctuation characters used by print_operand.  */
619
char mips_print_operand_punct[256];
620
 
621
/* Map GCC register number to debugger register number.  */
622
int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
623
 
624
/* A copy of the original flag_delayed_branch: see override_options.  */
625
static int mips_flag_delayed_branch;
626
 
627
static GTY (()) int mips_output_filename_first_time = 1;
628
 
629
/* mips_split_p[X] is true if symbols of type X can be split by
630
   mips_split_symbol().  */
631
bool mips_split_p[NUM_SYMBOL_TYPES];
632
 
633
/* mips_lo_relocs[X] is the relocation to use when a symbol of type X
634
   appears in a LO_SUM.  It can be null if such LO_SUMs aren't valid or
635
   if they are matched by a special .md file pattern.  */
636
static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
637
 
638
/* Likewise for HIGHs.  */
639
static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
640
 
641
/* Map hard register number to register class */
642
const enum reg_class mips_regno_to_class[] =
643
{
644
  LEA_REGS,     LEA_REGS,       M16_NA_REGS,    V1_REG,
645
  M16_REGS,     M16_REGS,       M16_REGS,       M16_REGS,
646
  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
647
  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
648
  M16_NA_REGS,  M16_NA_REGS,    LEA_REGS,       LEA_REGS,
649
  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
650
  T_REG,        PIC_FN_ADDR_REG, LEA_REGS,      LEA_REGS,
651
  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
652
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
653
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
654
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
655
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
656
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
657
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
658
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
659
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
660
  HI_REG,       LO_REG,         NO_REGS,        ST_REGS,
661
  ST_REGS,      ST_REGS,        ST_REGS,        ST_REGS,
662
  ST_REGS,      ST_REGS,        ST_REGS,        NO_REGS,
663
  NO_REGS,      ALL_REGS,       ALL_REGS,       NO_REGS,
664
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
665
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
666
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
667
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
668
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
669
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
670
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
671
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
672
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
673
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
674
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
675
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
676
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
677
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
678
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
679
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
680
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
681
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
682
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
683
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
684
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
685
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
686
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
687
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
688
  DSP_ACC_REGS, DSP_ACC_REGS,   DSP_ACC_REGS,   DSP_ACC_REGS,
689
  DSP_ACC_REGS, DSP_ACC_REGS,   ALL_REGS,       ALL_REGS,
690
  ALL_REGS,     ALL_REGS,       ALL_REGS,       ALL_REGS
691
};
692
 
693
/* Table of machine dependent attributes.  */
694
const struct attribute_spec mips_attribute_table[] =
695
{
696
  { "long_call",   0, 0, false, true,  true,  NULL },
697
  { NULL,          0, 0, false, false, false, NULL }
698
};
699
 
700
/* A table describing all the processors gcc knows about.  Names are
701
   matched in the order listed.  The first mention of an ISA level is
702
   taken as the canonical name for that ISA.
703
 
704
   To ease comparison, please keep this table in the same order as
705
   gas's mips_cpu_info_table[].  */
706
const struct mips_cpu_info mips_cpu_info_table[] = {
707
  /* Entries for generic ISAs */
708
  { "mips1", PROCESSOR_R3000, 1 },
709
  { "mips2", PROCESSOR_R6000, 2 },
710
  { "mips3", PROCESSOR_R4000, 3 },
711
  { "mips4", PROCESSOR_R8000, 4 },
712
  { "mips32", PROCESSOR_4KC, 32 },
713
  { "mips32r2", PROCESSOR_M4K, 33 },
714
  { "mips64", PROCESSOR_5KC, 64 },
715
 
716
  /* MIPS I */
717
  { "r3000", PROCESSOR_R3000, 1 },
718
  { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
719
  { "r3900", PROCESSOR_R3900, 1 },
720
 
721
  /* MIPS II */
722
  { "r6000", PROCESSOR_R6000, 2 },
723
 
724
  /* MIPS III */
725
  { "r4000", PROCESSOR_R4000, 3 },
726
  { "vr4100", PROCESSOR_R4100, 3 },
727
  { "vr4111", PROCESSOR_R4111, 3 },
728
  { "vr4120", PROCESSOR_R4120, 3 },
729
  { "vr4130", PROCESSOR_R4130, 3 },
730
  { "vr4300", PROCESSOR_R4300, 3 },
731
  { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
732
  { "r4600", PROCESSOR_R4600, 3 },
733
  { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
734
  { "r4650", PROCESSOR_R4650, 3 },
735
 
736
  /* MIPS IV */
737
  { "r8000", PROCESSOR_R8000, 4 },
738
  { "vr5000", PROCESSOR_R5000, 4 },
739
  { "vr5400", PROCESSOR_R5400, 4 },
740
  { "vr5500", PROCESSOR_R5500, 4 },
741
  { "rm7000", PROCESSOR_R7000, 4 },
742
  { "rm9000", PROCESSOR_R9000, 4 },
743
 
744
  /* MIPS32 */
745
  { "4kc", PROCESSOR_4KC, 32 },
746
  { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
747
  { "4kp", PROCESSOR_4KP, 32 },
748
 
749
  /* MIPS32 Release 2 */
750
  { "m4k", PROCESSOR_M4K, 33 },
751
  { "24k", PROCESSOR_24K, 33 },
752
  { "24kc", PROCESSOR_24K, 33 },  /* 24K  no FPU */
753
  { "24kf", PROCESSOR_24K, 33 },  /* 24K 1:2 FPU */
754
  { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
755
 
756
  /* MIPS64 */
757
  { "5kc", PROCESSOR_5KC, 64 },
758
  { "5kf", PROCESSOR_5KF, 64 },
759
  { "20kc", PROCESSOR_20KC, 64 },
760
  { "sb1", PROCESSOR_SB1, 64 },
761
  { "sb1a", PROCESSOR_SB1A, 64 },
762
  { "sr71000", PROCESSOR_SR71000, 64 },
763
 
764
  /* End marker */
765
  { 0, 0, 0 }
766
};
767
 
768
/* Default costs. If these are used for a processor we should look
769
   up the actual costs.  */
770
#define DEFAULT_COSTS COSTS_N_INSNS (6),  /* fp_add */       \
771
                      COSTS_N_INSNS (7),  /* fp_mult_sf */   \
772
                      COSTS_N_INSNS (8),  /* fp_mult_df */   \
773
                      COSTS_N_INSNS (23), /* fp_div_sf */    \
774
                      COSTS_N_INSNS (36), /* fp_div_df */    \
775
                      COSTS_N_INSNS (10), /* int_mult_si */  \
776
                      COSTS_N_INSNS (10), /* int_mult_di */  \
777
                      COSTS_N_INSNS (69), /* int_div_si */   \
778
                      COSTS_N_INSNS (69), /* int_div_di */   \
779
                                       2, /* branch_cost */  \
780
                                       4  /* memory_latency */
781
 
782
/* Need to replace these with the costs of calling the appropriate
783
   libgcc routine.  */
784
#define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */       \
785
                      COSTS_N_INSNS (256), /* fp_mult_sf */   \
786
                      COSTS_N_INSNS (256), /* fp_mult_df */   \
787
                      COSTS_N_INSNS (256), /* fp_div_sf */    \
788
                      COSTS_N_INSNS (256)  /* fp_div_df */
789
 
790
static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
791
  {
792
    { /* R3000 */
793
      COSTS_N_INSNS (2),            /* fp_add */
794
      COSTS_N_INSNS (4),            /* fp_mult_sf */
795
      COSTS_N_INSNS (5),            /* fp_mult_df */
796
      COSTS_N_INSNS (12),           /* fp_div_sf */
797
      COSTS_N_INSNS (19),           /* fp_div_df */
798
      COSTS_N_INSNS (12),           /* int_mult_si */
799
      COSTS_N_INSNS (12),           /* int_mult_di */
800
      COSTS_N_INSNS (35),           /* int_div_si */
801
      COSTS_N_INSNS (35),           /* int_div_di */
802
                       1,           /* branch_cost */
803
                       4            /* memory_latency */
804
 
805
    },
806
    { /* 4KC */
807
      SOFT_FP_COSTS,
808
      COSTS_N_INSNS (6),            /* int_mult_si */
809
      COSTS_N_INSNS (6),            /* int_mult_di */
810
      COSTS_N_INSNS (36),           /* int_div_si */
811
      COSTS_N_INSNS (36),           /* int_div_di */
812
                       1,           /* branch_cost */
813
                       4            /* memory_latency */
814
    },
815
    { /* 4KP */
816
      SOFT_FP_COSTS,
817
      COSTS_N_INSNS (36),           /* int_mult_si */
818
      COSTS_N_INSNS (36),           /* int_mult_di */
819
      COSTS_N_INSNS (37),           /* int_div_si */
820
      COSTS_N_INSNS (37),           /* int_div_di */
821
                       1,           /* branch_cost */
822
                       4            /* memory_latency */
823
    },
824
    { /* 5KC */
825
      SOFT_FP_COSTS,
826
      COSTS_N_INSNS (4),            /* int_mult_si */
827
      COSTS_N_INSNS (11),           /* int_mult_di */
828
      COSTS_N_INSNS (36),           /* int_div_si */
829
      COSTS_N_INSNS (68),           /* int_div_di */
830
                       1,           /* branch_cost */
831
                       4            /* memory_latency */
832
    },
833
    { /* 5KF */
834
      COSTS_N_INSNS (4),            /* fp_add */
835
      COSTS_N_INSNS (4),            /* fp_mult_sf */
836
      COSTS_N_INSNS (5),            /* fp_mult_df */
837
      COSTS_N_INSNS (17),           /* fp_div_sf */
838
      COSTS_N_INSNS (32),           /* fp_div_df */
839
      COSTS_N_INSNS (4),            /* int_mult_si */
840
      COSTS_N_INSNS (11),           /* int_mult_di */
841
      COSTS_N_INSNS (36),           /* int_div_si */
842
      COSTS_N_INSNS (68),           /* int_div_di */
843
                       1,           /* branch_cost */
844
                       4            /* memory_latency */
845
    },
846
    { /* 20KC */
847
      DEFAULT_COSTS
848
    },
849
    { /* 24k */
850
      COSTS_N_INSNS (8),            /* fp_add */
851
      COSTS_N_INSNS (8),            /* fp_mult_sf */
852
      COSTS_N_INSNS (10),           /* fp_mult_df */
853
      COSTS_N_INSNS (34),           /* fp_div_sf */
854
      COSTS_N_INSNS (64),           /* fp_div_df */
855
      COSTS_N_INSNS (5),            /* int_mult_si */
856
      COSTS_N_INSNS (5),            /* int_mult_di */
857
      COSTS_N_INSNS (41),           /* int_div_si */
858
      COSTS_N_INSNS (41),           /* int_div_di */
859
                       1,           /* branch_cost */
860
                       4            /* memory_latency */
861
    },
862
    { /* 24kx */
863
      COSTS_N_INSNS (4),            /* fp_add */
864
      COSTS_N_INSNS (4),            /* fp_mult_sf */
865
      COSTS_N_INSNS (5),            /* fp_mult_df */
866
      COSTS_N_INSNS (17),           /* fp_div_sf */
867
      COSTS_N_INSNS (32),           /* fp_div_df */
868
      COSTS_N_INSNS (5),            /* int_mult_si */
869
      COSTS_N_INSNS (5),            /* int_mult_di */
870
      COSTS_N_INSNS (41),           /* int_div_si */
871
      COSTS_N_INSNS (41),           /* int_div_di */
872
                       1,           /* branch_cost */
873
                       4            /* memory_latency */
874
    },
875
    { /* M4k */
876
      DEFAULT_COSTS
877
    },
878
    { /* R3900 */
879
      COSTS_N_INSNS (2),            /* fp_add */
880
      COSTS_N_INSNS (4),            /* fp_mult_sf */
881
      COSTS_N_INSNS (5),            /* fp_mult_df */
882
      COSTS_N_INSNS (12),           /* fp_div_sf */
883
      COSTS_N_INSNS (19),           /* fp_div_df */
884
      COSTS_N_INSNS (2),            /* int_mult_si */
885
      COSTS_N_INSNS (2),            /* int_mult_di */
886
      COSTS_N_INSNS (35),           /* int_div_si */
887
      COSTS_N_INSNS (35),           /* int_div_di */
888
                       1,           /* branch_cost */
889
                       4            /* memory_latency */
890
    },
891
    { /* R6000 */
892
      COSTS_N_INSNS (3),            /* fp_add */
893
      COSTS_N_INSNS (5),            /* fp_mult_sf */
894
      COSTS_N_INSNS (6),            /* fp_mult_df */
895
      COSTS_N_INSNS (15),           /* fp_div_sf */
896
      COSTS_N_INSNS (16),           /* fp_div_df */
897
      COSTS_N_INSNS (17),           /* int_mult_si */
898
      COSTS_N_INSNS (17),           /* int_mult_di */
899
      COSTS_N_INSNS (38),           /* int_div_si */
900
      COSTS_N_INSNS (38),           /* int_div_di */
901
                       2,           /* branch_cost */
902
                       6            /* memory_latency */
903
    },
904
    { /* R4000 */
905
       COSTS_N_INSNS (6),           /* fp_add */
906
       COSTS_N_INSNS (7),           /* fp_mult_sf */
907
       COSTS_N_INSNS (8),           /* fp_mult_df */
908
       COSTS_N_INSNS (23),          /* fp_div_sf */
909
       COSTS_N_INSNS (36),          /* fp_div_df */
910
       COSTS_N_INSNS (10),          /* int_mult_si */
911
       COSTS_N_INSNS (10),          /* int_mult_di */
912
       COSTS_N_INSNS (69),          /* int_div_si */
913
       COSTS_N_INSNS (69),          /* int_div_di */
914
                        2,          /* branch_cost */
915
                        6           /* memory_latency */
916
    },
917
    { /* R4100 */
918
      DEFAULT_COSTS
919
    },
920
    { /* R4111 */
921
      DEFAULT_COSTS
922
    },
923
    { /* R4120 */
924
      DEFAULT_COSTS
925
    },
926
    { /* R4130 */
927
      /* The only costs that appear to be updated here are
928
         integer multiplication.  */
929
      SOFT_FP_COSTS,
930
      COSTS_N_INSNS (4),            /* int_mult_si */
931
      COSTS_N_INSNS (6),            /* int_mult_di */
932
      COSTS_N_INSNS (69),           /* int_div_si */
933
      COSTS_N_INSNS (69),           /* int_div_di */
934
                       1,           /* branch_cost */
935
                       4            /* memory_latency */
936
    },
937
    { /* R4300 */
938
      DEFAULT_COSTS
939
    },
940
    { /* R4600 */
941
      DEFAULT_COSTS
942
    },
943
    { /* R4650 */
944
      DEFAULT_COSTS
945
    },
946
    { /* R5000 */
947
      COSTS_N_INSNS (6),            /* fp_add */
948
      COSTS_N_INSNS (4),            /* fp_mult_sf */
949
      COSTS_N_INSNS (5),            /* fp_mult_df */
950
      COSTS_N_INSNS (23),           /* fp_div_sf */
951
      COSTS_N_INSNS (36),           /* fp_div_df */
952
      COSTS_N_INSNS (5),            /* int_mult_si */
953
      COSTS_N_INSNS (5),            /* int_mult_di */
954
      COSTS_N_INSNS (36),           /* int_div_si */
955
      COSTS_N_INSNS (36),           /* int_div_di */
956
                       1,           /* branch_cost */
957
                       4            /* memory_latency */
958
    },
959
    { /* R5400 */
960
      COSTS_N_INSNS (6),            /* fp_add */
961
      COSTS_N_INSNS (5),            /* fp_mult_sf */
962
      COSTS_N_INSNS (6),            /* fp_mult_df */
963
      COSTS_N_INSNS (30),           /* fp_div_sf */
964
      COSTS_N_INSNS (59),           /* fp_div_df */
965
      COSTS_N_INSNS (3),            /* int_mult_si */
966
      COSTS_N_INSNS (4),            /* int_mult_di */
967
      COSTS_N_INSNS (42),           /* int_div_si */
968
      COSTS_N_INSNS (74),           /* int_div_di */
969
                       1,           /* branch_cost */
970
                       4            /* memory_latency */
971
    },
972
    { /* R5500 */
973
      COSTS_N_INSNS (6),            /* fp_add */
974
      COSTS_N_INSNS (5),            /* fp_mult_sf */
975
      COSTS_N_INSNS (6),            /* fp_mult_df */
976
      COSTS_N_INSNS (30),           /* fp_div_sf */
977
      COSTS_N_INSNS (59),           /* fp_div_df */
978
      COSTS_N_INSNS (5),            /* int_mult_si */
979
      COSTS_N_INSNS (9),            /* int_mult_di */
980
      COSTS_N_INSNS (42),           /* int_div_si */
981
      COSTS_N_INSNS (74),           /* int_div_di */
982
                       1,           /* branch_cost */
983
                       4            /* memory_latency */
984
    },
985
    { /* R7000 */
986
      /* The only costs that are changed here are
987
         integer multiplication.  */
988
      COSTS_N_INSNS (6),            /* fp_add */
989
      COSTS_N_INSNS (7),            /* fp_mult_sf */
990
      COSTS_N_INSNS (8),            /* fp_mult_df */
991
      COSTS_N_INSNS (23),           /* fp_div_sf */
992
      COSTS_N_INSNS (36),           /* fp_div_df */
993
      COSTS_N_INSNS (5),            /* int_mult_si */
994
      COSTS_N_INSNS (9),            /* int_mult_di */
995
      COSTS_N_INSNS (69),           /* int_div_si */
996
      COSTS_N_INSNS (69),           /* int_div_di */
997
                       1,           /* branch_cost */
998
                       4            /* memory_latency */
999
    },
1000
    { /* R8000 */
1001
      DEFAULT_COSTS
1002
    },
1003
    { /* R9000 */
1004
      /* The only costs that are changed here are
1005
         integer multiplication.  */
1006
      COSTS_N_INSNS (6),            /* fp_add */
1007
      COSTS_N_INSNS (7),            /* fp_mult_sf */
1008
      COSTS_N_INSNS (8),            /* fp_mult_df */
1009
      COSTS_N_INSNS (23),           /* fp_div_sf */
1010
      COSTS_N_INSNS (36),           /* fp_div_df */
1011
      COSTS_N_INSNS (3),            /* int_mult_si */
1012
      COSTS_N_INSNS (8),            /* int_mult_di */
1013
      COSTS_N_INSNS (69),           /* int_div_si */
1014
      COSTS_N_INSNS (69),           /* int_div_di */
1015
                       1,           /* branch_cost */
1016
                       4            /* memory_latency */
1017
    },
1018
    { /* SB1 */
1019
      /* These costs are the same as the SB-1A below.  */
1020
      COSTS_N_INSNS (4),            /* fp_add */
1021
      COSTS_N_INSNS (4),            /* fp_mult_sf */
1022
      COSTS_N_INSNS (4),            /* fp_mult_df */
1023
      COSTS_N_INSNS (24),           /* fp_div_sf */
1024
      COSTS_N_INSNS (32),           /* fp_div_df */
1025
      COSTS_N_INSNS (3),            /* int_mult_si */
1026
      COSTS_N_INSNS (4),            /* int_mult_di */
1027
      COSTS_N_INSNS (36),           /* int_div_si */
1028
      COSTS_N_INSNS (68),           /* int_div_di */
1029
                       1,           /* branch_cost */
1030
                       4            /* memory_latency */
1031
    },
1032
    { /* SB1-A */
1033
      /* These costs are the same as the SB-1 above.  */
1034
      COSTS_N_INSNS (4),            /* fp_add */
1035
      COSTS_N_INSNS (4),            /* fp_mult_sf */
1036
      COSTS_N_INSNS (4),            /* fp_mult_df */
1037
      COSTS_N_INSNS (24),           /* fp_div_sf */
1038
      COSTS_N_INSNS (32),           /* fp_div_df */
1039
      COSTS_N_INSNS (3),            /* int_mult_si */
1040
      COSTS_N_INSNS (4),            /* int_mult_di */
1041
      COSTS_N_INSNS (36),           /* int_div_si */
1042
      COSTS_N_INSNS (68),           /* int_div_di */
1043
                       1,           /* branch_cost */
1044
                       4            /* memory_latency */
1045
    },
1046
    { /* SR71000 */
1047
      DEFAULT_COSTS
1048
    },
1049
  };
1050
 
1051
 
1052
/* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT.  */
1053
#ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1054
#define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1055
#endif
1056
 
1057
/* Initialize the GCC target structure.  */
1058
#undef TARGET_ASM_ALIGNED_HI_OP
1059
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1060
#undef TARGET_ASM_ALIGNED_SI_OP
1061
#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1062
#undef TARGET_ASM_ALIGNED_DI_OP
1063
#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1064
 
1065
#undef TARGET_ASM_FUNCTION_PROLOGUE
1066
#define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1067
#undef TARGET_ASM_FUNCTION_EPILOGUE
1068
#define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1069
#undef TARGET_ASM_SELECT_RTX_SECTION
1070
#define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1071
#undef TARGET_ASM_FUNCTION_RODATA_SECTION
1072
#define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1073
 
1074
#undef TARGET_SCHED_REORDER
1075
#define TARGET_SCHED_REORDER mips_sched_reorder
1076
#undef TARGET_SCHED_VARIABLE_ISSUE
1077
#define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1078
#undef TARGET_SCHED_ADJUST_COST
1079
#define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1080
#undef TARGET_SCHED_ISSUE_RATE
1081
#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1082
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1083
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1084
  mips_multipass_dfa_lookahead
1085
 
1086
#undef TARGET_DEFAULT_TARGET_FLAGS
1087
#define TARGET_DEFAULT_TARGET_FLAGS             \
1088
  (TARGET_DEFAULT                               \
1089
   | TARGET_CPU_DEFAULT                         \
1090
   | TARGET_ENDIAN_DEFAULT                      \
1091
   | TARGET_FP_EXCEPTIONS_DEFAULT               \
1092
   | MASK_CHECK_ZERO_DIV                        \
1093
   | MASK_FUSED_MADD)
1094
#undef TARGET_HANDLE_OPTION
1095
#define TARGET_HANDLE_OPTION mips_handle_option
1096
 
1097
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
1098
#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1099
 
1100
#undef TARGET_VALID_POINTER_MODE
1101
#define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1102
#undef TARGET_RTX_COSTS
1103
#define TARGET_RTX_COSTS mips_rtx_costs
1104
#undef TARGET_ADDRESS_COST
1105
#define TARGET_ADDRESS_COST mips_address_cost
1106
 
1107
#undef TARGET_IN_SMALL_DATA_P
1108
#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1109
 
1110
#undef TARGET_MACHINE_DEPENDENT_REORG
1111
#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1112
 
1113
#undef TARGET_ASM_FILE_START
1114
#undef TARGET_ASM_FILE_END
1115
#define TARGET_ASM_FILE_START mips_file_start
1116
#define TARGET_ASM_FILE_END mips_file_end
1117
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1118
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1119
 
1120
#undef TARGET_INIT_LIBFUNCS
1121
#define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1122
 
1123
#undef TARGET_BUILD_BUILTIN_VA_LIST
1124
#define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1125
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
1126
#define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1127
 
1128
#undef TARGET_PROMOTE_FUNCTION_ARGS
1129
#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1130
#undef TARGET_PROMOTE_FUNCTION_RETURN
1131
#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1132
#undef TARGET_PROMOTE_PROTOTYPES
1133
#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1134
 
1135
#undef TARGET_RETURN_IN_MEMORY
1136
#define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1137
#undef TARGET_RETURN_IN_MSB
1138
#define TARGET_RETURN_IN_MSB mips_return_in_msb
1139
 
1140
#undef TARGET_ASM_OUTPUT_MI_THUNK
1141
#define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1142
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1143
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1144
 
1145
#undef TARGET_SETUP_INCOMING_VARARGS
1146
#define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1147
#undef TARGET_STRICT_ARGUMENT_NAMING
1148
#define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1149
#undef TARGET_MUST_PASS_IN_STACK
1150
#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1151
#undef TARGET_PASS_BY_REFERENCE
1152
#define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1153
#undef TARGET_CALLEE_COPIES
1154
#define TARGET_CALLEE_COPIES mips_callee_copies
1155
#undef TARGET_ARG_PARTIAL_BYTES
1156
#define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1157
 
1158
#undef TARGET_MODE_REP_EXTENDED
1159
#define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1160
 
1161
#undef TARGET_VECTOR_MODE_SUPPORTED_P
1162
#define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1163
 
1164
#undef TARGET_INIT_BUILTINS
1165
#define TARGET_INIT_BUILTINS mips_init_builtins
1166
#undef TARGET_EXPAND_BUILTIN
1167
#define TARGET_EXPAND_BUILTIN mips_expand_builtin
1168
 
1169
#undef TARGET_HAVE_TLS
1170
#define TARGET_HAVE_TLS HAVE_AS_TLS
1171
 
1172
#undef TARGET_CANNOT_FORCE_CONST_MEM
1173
#define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1174
 
1175
#undef TARGET_ENCODE_SECTION_INFO
1176
#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1177
 
1178
#undef TARGET_ATTRIBUTE_TABLE
1179
#define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1180
 
1181
#undef TARGET_EXTRA_LIVE_ON_ENTRY
1182
#define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1183
 
1184
#undef TARGET_MIN_ANCHOR_OFFSET
1185
#define TARGET_MIN_ANCHOR_OFFSET -32768
1186
#undef TARGET_MAX_ANCHOR_OFFSET
1187
#define TARGET_MAX_ANCHOR_OFFSET 32767
1188
#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1189
#define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1190
#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1191
#define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1192
 
1193
struct gcc_target targetm = TARGET_INITIALIZER;
1194
 
1195
/* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF.  */
1196
 
1197
static enum mips_symbol_type
1198
mips_classify_symbol (rtx x)
1199
{
1200
  if (GET_CODE (x) == LABEL_REF)
1201
    {
1202
      if (TARGET_MIPS16)
1203
        return SYMBOL_CONSTANT_POOL;
1204
      if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1205
        return SYMBOL_GOT_LOCAL;
1206
      return SYMBOL_GENERAL;
1207
    }
1208
 
1209
  gcc_assert (GET_CODE (x) == SYMBOL_REF);
1210
 
1211
  if (SYMBOL_REF_TLS_MODEL (x))
1212
    return SYMBOL_TLS;
1213
 
1214
  if (CONSTANT_POOL_ADDRESS_P (x))
1215
    {
1216
      if (TARGET_MIPS16)
1217
        return SYMBOL_CONSTANT_POOL;
1218
 
1219
      if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1220
        return SYMBOL_SMALL_DATA;
1221
    }
1222
 
1223
  /* Do not use small-data accesses for weak symbols; they may end up
1224
     being zero.  */
1225
  if (SYMBOL_REF_SMALL_P (x)
1226
      && !SYMBOL_REF_WEAK (x))
1227
    return SYMBOL_SMALL_DATA;
1228
 
1229
  if (TARGET_ABICALLS)
1230
    {
1231
      if (SYMBOL_REF_DECL (x) == 0)
1232
        {
1233
          if (!SYMBOL_REF_LOCAL_P (x))
1234
            return SYMBOL_GOT_GLOBAL;
1235
        }
1236
      else
1237
        {
1238
          /* Don't use GOT accesses for locally-binding symbols if
1239
             TARGET_ABSOLUTE_ABICALLS.  Otherwise, there are three
1240
             cases to consider:
1241
 
1242
                - o32 PIC (either with or without explicit relocs)
1243
                - n32/n64 PIC without explicit relocs
1244
                - n32/n64 PIC with explicit relocs
1245
 
1246
             In the first case, both local and global accesses will use an
1247
             R_MIPS_GOT16 relocation.  We must correctly predict which of
1248
             the two semantics (local or global) the assembler and linker
1249
             will apply.  The choice doesn't depend on the symbol's
1250
             visibility, so we deliberately ignore decl_visibility and
1251
             binds_local_p here.
1252
 
1253
             In the second case, the assembler will not use R_MIPS_GOT16
1254
             relocations, but it chooses between local and global accesses
1255
             in the same way as for o32 PIC.
1256
 
1257
             In the third case we have more freedom since both forms of
1258
             access will work for any kind of symbol.  However, there seems
1259
             little point in doing things differently.  */
1260
          if (DECL_P (SYMBOL_REF_DECL (x))
1261
              && TREE_PUBLIC (SYMBOL_REF_DECL (x))
1262
              && !(TARGET_ABSOLUTE_ABICALLS
1263
                   && targetm.binds_local_p (SYMBOL_REF_DECL (x))))
1264
            return SYMBOL_GOT_GLOBAL;
1265
        }
1266
 
1267
      if (!TARGET_ABSOLUTE_ABICALLS)
1268
        return SYMBOL_GOT_LOCAL;
1269
    }
1270
 
1271
  return SYMBOL_GENERAL;
1272
}
1273
 
1274
 
1275
/* Split X into a base and a constant offset, storing them in *BASE
1276
   and *OFFSET respectively.  */
1277
 
1278
static void
1279
mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1280
{
1281
  *offset = 0;
1282
 
1283
  if (GET_CODE (x) == CONST)
1284
    {
1285
      x = XEXP (x, 0);
1286
      if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1287
        {
1288
          *offset += INTVAL (XEXP (x, 1));
1289
          x = XEXP (x, 0);
1290
        }
1291
    }
1292
  *base = x;
1293
}
1294
 
1295
/* Classify symbolic expression X, given that it appears in context
1296
   CONTEXT.  */
1297
 
1298
static enum mips_symbol_type
1299
mips_classify_symbolic_expression (rtx x)
1300
{
1301
  HOST_WIDE_INT offset;
1302
 
1303
  mips_split_const (x, &x, &offset);
1304
  if (UNSPEC_ADDRESS_P (x))
1305
    return UNSPEC_ADDRESS_TYPE (x);
1306
 
1307
  return mips_classify_symbol (x);
1308
}
1309
 
1310
/* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1311
   to the same object as SYMBOL, or to the same object_block.  */
1312
 
1313
static bool
1314
mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1315
{
1316
  if (GET_CODE (symbol) != SYMBOL_REF)
1317
    return false;
1318
 
1319
  if (CONSTANT_POOL_ADDRESS_P (symbol)
1320
      && offset >= 0
1321
      && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1322
    return true;
1323
 
1324
  if (SYMBOL_REF_DECL (symbol) != 0
1325
      && offset >= 0
1326
      && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1327
    return true;
1328
 
1329
  if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)
1330
      && SYMBOL_REF_BLOCK (symbol)
1331
      && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0
1332
      && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)
1333
          < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size))
1334
    return true;
1335
 
1336
  return false;
1337
}
1338
 
1339
 
1340
/* Return true if X is a symbolic constant that can be calculated in
1341
   the same way as a bare symbol.  If it is, store the type of the
1342
   symbol in *SYMBOL_TYPE.  */
1343
 
1344
bool
1345
mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1346
{
1347
  HOST_WIDE_INT offset;
1348
 
1349
  mips_split_const (x, &x, &offset);
1350
  if (UNSPEC_ADDRESS_P (x))
1351
    *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1352
  else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1353
    {
1354
      *symbol_type = mips_classify_symbol (x);
1355
      if (*symbol_type == SYMBOL_TLS)
1356
        return false;
1357
    }
1358
  else
1359
    return false;
1360
 
1361
  if (offset == 0)
1362
    return true;
1363
 
1364
  /* Check whether a nonzero offset is valid for the underlying
1365
     relocations.  */
1366
  switch (*symbol_type)
1367
    {
1368
    case SYMBOL_GENERAL:
1369
    case SYMBOL_64_HIGH:
1370
    case SYMBOL_64_MID:
1371
    case SYMBOL_64_LOW:
1372
      /* If the target has 64-bit pointers and the object file only
1373
         supports 32-bit symbols, the values of those symbols will be
1374
         sign-extended.  In this case we can't allow an arbitrary offset
1375
         in case the 32-bit value X + OFFSET has a different sign from X.  */
1376
      if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1377
        return mips_offset_within_object_p (x, offset);
1378
 
1379
      /* In other cases the relocations can handle any offset.  */
1380
      return true;
1381
 
1382
    case SYMBOL_CONSTANT_POOL:
1383
      /* Allow constant pool references to be converted to LABEL+CONSTANT.
1384
         In this case, we no longer have access to the underlying constant,
1385
         but the original symbol-based access was known to be valid.  */
1386
      if (GET_CODE (x) == LABEL_REF)
1387
        return true;
1388
 
1389
      /* Fall through.  */
1390
 
1391
    case SYMBOL_SMALL_DATA:
1392
      /* Make sure that the offset refers to something within the
1393
         underlying object.  This should guarantee that the final
1394
         PC- or GP-relative offset is within the 16-bit limit.  */
1395
      return mips_offset_within_object_p (x, offset);
1396
 
1397
    case SYMBOL_GOT_LOCAL:
1398
    case SYMBOL_GOTOFF_PAGE:
1399
      /* The linker should provide enough local GOT entries for a
1400
         16-bit offset.  Larger offsets may lead to GOT overflow.  */
1401
      return SMALL_OPERAND (offset);
1402
 
1403
    case SYMBOL_GOT_GLOBAL:
1404
    case SYMBOL_GOTOFF_GLOBAL:
1405
    case SYMBOL_GOTOFF_CALL:
1406
    case SYMBOL_GOTOFF_LOADGP:
1407
    case SYMBOL_TLSGD:
1408
    case SYMBOL_TLSLDM:
1409
    case SYMBOL_DTPREL:
1410
    case SYMBOL_TPREL:
1411
    case SYMBOL_GOTTPREL:
1412
    case SYMBOL_TLS:
1413
      return false;
1414
    }
1415
  gcc_unreachable ();
1416
}
1417
 
1418
 
1419
/* This function is used to implement REG_MODE_OK_FOR_BASE_P.  */
1420
 
1421
int
1422
mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1423
{
1424
  if (regno >= FIRST_PSEUDO_REGISTER)
1425
    {
1426
      if (!strict)
1427
        return true;
1428
      regno = reg_renumber[regno];
1429
    }
1430
 
1431
  /* These fake registers will be eliminated to either the stack or
1432
     hard frame pointer, both of which are usually valid base registers.
1433
     Reload deals with the cases where the eliminated form isn't valid.  */
1434
  if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1435
    return true;
1436
 
1437
  /* In mips16 mode, the stack pointer can only address word and doubleword
1438
     values, nothing smaller.  There are two problems here:
1439
 
1440
       (a) Instantiating virtual registers can introduce new uses of the
1441
           stack pointer.  If these virtual registers are valid addresses,
1442
           the stack pointer should be too.
1443
 
1444
       (b) Most uses of the stack pointer are not made explicit until
1445
           FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1446
           We don't know until that stage whether we'll be eliminating to the
1447
           stack pointer (which needs the restriction) or the hard frame
1448
           pointer (which doesn't).
1449
 
1450
     All in all, it seems more consistent to only enforce this restriction
1451
     during and after reload.  */
1452
  if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1453
    return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1454
 
1455
  return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1456
}
1457
 
1458
 
1459
/* Return true if X is a valid base register for the given mode.
1460
   Allow only hard registers if STRICT.  */
1461
 
1462
static bool
1463
mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1464
{
1465
  if (!strict && GET_CODE (x) == SUBREG)
1466
    x = SUBREG_REG (x);
1467
 
1468
  return (REG_P (x)
1469
          && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1470
}
1471
 
1472
 
1473
/* Return true if symbols of type SYMBOL_TYPE can directly address a value
1474
   with mode MODE.  This is used for both symbolic and LO_SUM addresses.  */
1475
 
1476
static bool
1477
mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1478
                         enum machine_mode mode)
1479
{
1480
  switch (symbol_type)
1481
    {
1482
    case SYMBOL_GENERAL:
1483
      return !TARGET_MIPS16;
1484
 
1485
    case SYMBOL_SMALL_DATA:
1486
      return true;
1487
 
1488
    case SYMBOL_CONSTANT_POOL:
1489
      /* PC-relative addressing is only available for lw and ld.  */
1490
      return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1491
 
1492
    case SYMBOL_GOT_LOCAL:
1493
      return true;
1494
 
1495
    case SYMBOL_GOT_GLOBAL:
1496
      /* The address will have to be loaded from the GOT first.  */
1497
      return false;
1498
 
1499
    case SYMBOL_GOTOFF_PAGE:
1500
    case SYMBOL_GOTOFF_GLOBAL:
1501
    case SYMBOL_GOTOFF_CALL:
1502
    case SYMBOL_GOTOFF_LOADGP:
1503
    case SYMBOL_TLS:
1504
    case SYMBOL_TLSGD:
1505
    case SYMBOL_TLSLDM:
1506
    case SYMBOL_DTPREL:
1507
    case SYMBOL_GOTTPREL:
1508
    case SYMBOL_TPREL:
1509
    case SYMBOL_64_HIGH:
1510
    case SYMBOL_64_MID:
1511
    case SYMBOL_64_LOW:
1512
      return true;
1513
    }
1514
  gcc_unreachable ();
1515
}
1516
 
1517
 
1518
/* Return true if X is a valid address for machine mode MODE.  If it is,
1519
   fill in INFO appropriately.  STRICT is true if we should only accept
1520
   hard base registers.  */
1521
 
1522
static bool
1523
mips_classify_address (struct mips_address_info *info, rtx x,
1524
                       enum machine_mode mode, int strict)
1525
{
1526
  switch (GET_CODE (x))
1527
    {
1528
    case REG:
1529
    case SUBREG:
1530
      info->type = ADDRESS_REG;
1531
      info->reg = x;
1532
      info->offset = const0_rtx;
1533
      return mips_valid_base_register_p (info->reg, mode, strict);
1534
 
1535
    case PLUS:
1536
      info->type = ADDRESS_REG;
1537
      info->reg = XEXP (x, 0);
1538
      info->offset = XEXP (x, 1);
1539
      return (mips_valid_base_register_p (info->reg, mode, strict)
1540
              && const_arith_operand (info->offset, VOIDmode));
1541
 
1542
    case LO_SUM:
1543
      info->type = ADDRESS_LO_SUM;
1544
      info->reg = XEXP (x, 0);
1545
      info->offset = XEXP (x, 1);
1546
      /* We have to trust the creator of the LO_SUM to do something vaguely
1547
         sane.  Target-independent code that creates a LO_SUM should also
1548
         create and verify the matching HIGH.  Target-independent code that
1549
         adds an offset to a LO_SUM must prove that the offset will not
1550
         induce a carry.  Failure to do either of these things would be
1551
         a bug, and we are not required to check for it here.  The MIPS
1552
         backend itself should only create LO_SUMs for valid symbolic
1553
         constants, with the high part being either a HIGH or a copy
1554
         of _gp. */
1555
      info->symbol_type = mips_classify_symbolic_expression (info->offset);
1556
      return (mips_valid_base_register_p (info->reg, mode, strict)
1557
              && mips_symbolic_address_p (info->symbol_type, mode)
1558
              && mips_lo_relocs[info->symbol_type] != 0);
1559
 
1560
    case CONST_INT:
1561
      /* Small-integer addresses don't occur very often, but they
1562
         are legitimate if $0 is a valid base register.  */
1563
      info->type = ADDRESS_CONST_INT;
1564
      return !TARGET_MIPS16 && SMALL_INT (x);
1565
 
1566
    case CONST:
1567
    case LABEL_REF:
1568
    case SYMBOL_REF:
1569
      info->type = ADDRESS_SYMBOLIC;
1570
      return (mips_symbolic_constant_p (x, &info->symbol_type)
1571
              && mips_symbolic_address_p (info->symbol_type, mode)
1572
              && !mips_split_p[info->symbol_type]);
1573
 
1574
    default:
1575
      return false;
1576
    }
1577
}
1578
 
1579
/* Return true if X is a thread-local symbol.  */
1580
 
1581
static bool
1582
mips_tls_operand_p (rtx x)
1583
{
1584
  return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1585
}
1586
 
1587
/* Return true if X can not be forced into a constant pool.  */
1588
 
1589
static int
1590
mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1591
{
1592
  return mips_tls_operand_p (*x);
1593
}
1594
 
1595
/* Return true if X can not be forced into a constant pool.  */
1596
 
1597
static bool
1598
mips_cannot_force_const_mem (rtx x)
1599
{
1600
  rtx base;
1601
  HOST_WIDE_INT offset;
1602
 
1603
  if (!TARGET_MIPS16)
1604
    {
1605
      /* As an optimization, reject constants that mips_legitimize_move
1606
         can expand inline.
1607
 
1608
         Suppose we have a multi-instruction sequence that loads constant C
1609
         into register R.  If R does not get allocated a hard register, and
1610
         R is used in an operand that allows both registers and memory
1611
         references, reload will consider forcing C into memory and using
1612
         one of the instruction's memory alternatives.  Returning false
1613
         here will force it to use an input reload instead.  */
1614
      if (GET_CODE (x) == CONST_INT)
1615
        return true;
1616
 
1617
      mips_split_const (x, &base, &offset);
1618
      if (symbolic_operand (base, VOIDmode) && SMALL_OPERAND (offset))
1619
        return true;
1620
    }
1621
 
1622
  if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1623
    return true;
1624
 
1625
  return false;
1626
}
1627
 
1628
/* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P.  MIPS16 uses per-function
1629
   constant pools, but normal-mode code doesn't need to.  */
1630
 
1631
static bool
1632
mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1633
                                rtx x ATTRIBUTE_UNUSED)
1634
{
1635
  return !TARGET_MIPS16;
1636
}
1637
 
1638
/* Return the number of instructions needed to load a symbol of the
1639
   given type into a register.  If valid in an address, the same number
1640
   of instructions are needed for loads and stores.  Treat extended
1641
   mips16 instructions as two instructions.  */
1642
 
1643
static int
1644
mips_symbol_insns (enum mips_symbol_type type)
1645
{
1646
  switch (type)
1647
    {
1648
    case SYMBOL_GENERAL:
1649
      /* In mips16 code, general symbols must be fetched from the
1650
         constant pool.  */
1651
      if (TARGET_MIPS16)
1652
        return 0;
1653
 
1654
      /* When using 64-bit symbols, we need 5 preparatory instructions,
1655
         such as:
1656
 
1657
             lui     $at,%highest(symbol)
1658
             daddiu  $at,$at,%higher(symbol)
1659
             dsll    $at,$at,16
1660
             daddiu  $at,$at,%hi(symbol)
1661
             dsll    $at,$at,16
1662
 
1663
         The final address is then $at + %lo(symbol).  With 32-bit
1664
         symbols we just need a preparatory lui.  */
1665
      return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1666
 
1667
    case SYMBOL_SMALL_DATA:
1668
      return 1;
1669
 
1670
    case SYMBOL_CONSTANT_POOL:
1671
      /* This case is for mips16 only.  Assume we'll need an
1672
         extended instruction.  */
1673
      return 2;
1674
 
1675
    case SYMBOL_GOT_LOCAL:
1676
    case SYMBOL_GOT_GLOBAL:
1677
      /* Unless -funit-at-a-time is in effect, we can't be sure whether
1678
         the local/global classification is accurate.  See override_options
1679
         for details.
1680
 
1681
         The worst cases are:
1682
 
1683
         (1) For local symbols when generating o32 or o64 code.  The assembler
1684
             will use:
1685
 
1686
                 lw           $at,%got(symbol)
1687
                 nop
1688
 
1689
             ...and the final address will be $at + %lo(symbol).
1690
 
1691
         (2) For global symbols when -mxgot.  The assembler will use:
1692
 
1693
                 lui     $at,%got_hi(symbol)
1694
                 (d)addu $at,$at,$gp
1695
 
1696
             ...and the final address will be $at + %got_lo(symbol).  */
1697
      return 3;
1698
 
1699
    case SYMBOL_GOTOFF_PAGE:
1700
    case SYMBOL_GOTOFF_GLOBAL:
1701
    case SYMBOL_GOTOFF_CALL:
1702
    case SYMBOL_GOTOFF_LOADGP:
1703
    case SYMBOL_64_HIGH:
1704
    case SYMBOL_64_MID:
1705
    case SYMBOL_64_LOW:
1706
    case SYMBOL_TLSGD:
1707
    case SYMBOL_TLSLDM:
1708
    case SYMBOL_DTPREL:
1709
    case SYMBOL_GOTTPREL:
1710
    case SYMBOL_TPREL:
1711
      /* Check whether the offset is a 16- or 32-bit value.  */
1712
      return mips_split_p[type] ? 2 : 1;
1713
 
1714
    case SYMBOL_TLS:
1715
      /* We don't treat a bare TLS symbol as a constant.  */
1716
      return 0;
1717
    }
1718
  gcc_unreachable ();
1719
}
1720
 
1721
/* Return true if X is a legitimate $sp-based address for mode MDOE.  */
1722
 
1723
bool
1724
mips_stack_address_p (rtx x, enum machine_mode mode)
1725
{
1726
  struct mips_address_info addr;
1727
 
1728
  return (mips_classify_address (&addr, x, mode, false)
1729
          && addr.type == ADDRESS_REG
1730
          && addr.reg == stack_pointer_rtx);
1731
}
1732
 
1733
/* Return true if a value at OFFSET bytes from BASE can be accessed
1734
   using an unextended mips16 instruction.  MODE is the mode of the
1735
   value.
1736
 
1737
   Usually the offset in an unextended instruction is a 5-bit field.
1738
   The offset is unsigned and shifted left once for HIs, twice
1739
   for SIs, and so on.  An exception is SImode accesses off the
1740
   stack pointer, which have an 8-bit immediate field.  */
1741
 
1742
static bool
1743
mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1744
{
1745
  if (TARGET_MIPS16
1746
      && GET_CODE (offset) == CONST_INT
1747
      && INTVAL (offset) >= 0
1748
      && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1749
    {
1750
      if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1751
        return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1752
      return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1753
    }
1754
  return false;
1755
}
1756
 
1757
 
1758
/* Return the number of instructions needed to load or store a value
1759
   of mode MODE at X.  Return 0 if X isn't valid for MODE.
1760
 
1761
   For mips16 code, count extended instructions as two instructions.  */
1762
 
1763
int
1764
mips_address_insns (rtx x, enum machine_mode mode)
1765
{
1766
  struct mips_address_info addr;
1767
  int factor;
1768
 
1769
  if (mode == BLKmode)
1770
    /* BLKmode is used for single unaligned loads and stores.  */
1771
    factor = 1;
1772
  else
1773
    /* Each word of a multi-word value will be accessed individually.  */
1774
    factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1775
 
1776
  if (mips_classify_address (&addr, x, mode, false))
1777
    switch (addr.type)
1778
      {
1779
      case ADDRESS_REG:
1780
        if (TARGET_MIPS16
1781
            && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1782
          return factor * 2;
1783
        return factor;
1784
 
1785
      case ADDRESS_LO_SUM:
1786
        return (TARGET_MIPS16 ? factor * 2 : factor);
1787
 
1788
      case ADDRESS_CONST_INT:
1789
        return factor;
1790
 
1791
      case ADDRESS_SYMBOLIC:
1792
        return factor * mips_symbol_insns (addr.symbol_type);
1793
      }
1794
  return 0;
1795
}
1796
 
1797
 
1798
/* Likewise for constant X.  */
1799
 
1800
int
1801
mips_const_insns (rtx x)
1802
{
1803
  struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1804
  enum mips_symbol_type symbol_type;
1805
  HOST_WIDE_INT offset;
1806
 
1807
  switch (GET_CODE (x))
1808
    {
1809
    case HIGH:
1810
      if (TARGET_MIPS16
1811
          || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1812
          || !mips_split_p[symbol_type])
1813
        return 0;
1814
 
1815
      return 1;
1816
 
1817
    case CONST_INT:
1818
      if (TARGET_MIPS16)
1819
        /* Unsigned 8-bit constants can be loaded using an unextended
1820
           LI instruction.  Unsigned 16-bit constants can be loaded
1821
           using an extended LI.  Negative constants must be loaded
1822
           using LI and then negated.  */
1823
        return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1824
                : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1825
                : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1826
                : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1827
                : 0);
1828
 
1829
      return mips_build_integer (codes, INTVAL (x));
1830
 
1831
    case CONST_DOUBLE:
1832
    case CONST_VECTOR:
1833
      return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1834
 
1835
    case CONST:
1836
      if (CONST_GP_P (x))
1837
        return 1;
1838
 
1839
      /* See if we can refer to X directly.  */
1840
      if (mips_symbolic_constant_p (x, &symbol_type))
1841
        return mips_symbol_insns (symbol_type);
1842
 
1843
      /* Otherwise try splitting the constant into a base and offset.
1844
         16-bit offsets can be added using an extra addiu.  Larger offsets
1845
         must be calculated separately and then added to the base.  */
1846
      mips_split_const (x, &x, &offset);
1847
      if (offset != 0)
1848
        {
1849
          int n = mips_const_insns (x);
1850
          if (n != 0)
1851
            {
1852
              if (SMALL_OPERAND (offset))
1853
                return n + 1;
1854
              else
1855
                return n + 1 + mips_build_integer (codes, offset);
1856
            }
1857
        }
1858
      return 0;
1859
 
1860
    case SYMBOL_REF:
1861
    case LABEL_REF:
1862
      return mips_symbol_insns (mips_classify_symbol (x));
1863
 
1864
    default:
1865
      return 0;
1866
    }
1867
}
1868
 
1869
 
1870
/* Return the number of instructions needed for memory reference X.
1871
   Count extended mips16 instructions as two instructions.  */
1872
 
1873
int
1874
mips_fetch_insns (rtx x)
1875
{
1876
  gcc_assert (MEM_P (x));
1877
  return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1878
}
1879
 
1880
 
1881
/* Return the number of instructions needed for an integer division.  */
1882
 
1883
int
1884
mips_idiv_insns (void)
1885
{
1886
  int count;
1887
 
1888
  count = 1;
1889
  if (TARGET_CHECK_ZERO_DIV)
1890
    {
1891
      if (GENERATE_DIVIDE_TRAPS)
1892
        count++;
1893
      else
1894
        count += 2;
1895
    }
1896
 
1897
  if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1898
    count++;
1899
  return count;
1900
}
1901
 
1902
/* This function is used to implement GO_IF_LEGITIMATE_ADDRESS.  It
1903
   returns a nonzero value if X is a legitimate address for a memory
1904
   operand of the indicated MODE.  STRICT is nonzero if this function
1905
   is called during reload.  */
1906
 
1907
bool
1908
mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1909
{
1910
  struct mips_address_info addr;
1911
 
1912
  return mips_classify_address (&addr, x, mode, strict);
1913
}
1914
 
1915
 
1916
/* Copy VALUE to a register and return that register.  If new psuedos
1917
   are allowed, copy it into a new register, otherwise use DEST.  */
1918
 
1919
static rtx
1920
mips_force_temporary (rtx dest, rtx value)
1921
{
1922
  if (!no_new_pseudos)
1923
    return force_reg (Pmode, value);
1924
  else
1925
    {
1926
      emit_move_insn (copy_rtx (dest), value);
1927
      return dest;
1928
    }
1929
}
1930
 
1931
 
1932
/* Return a LO_SUM expression for ADDR.  TEMP is as for mips_force_temporary
1933
   and is used to load the high part into a register.  */
1934
 
1935
rtx
1936
mips_split_symbol (rtx temp, rtx addr)
1937
{
1938
  rtx high;
1939
 
1940
  if (TARGET_MIPS16)
1941
    high = mips16_gp_pseudo_reg ();
1942
  else
1943
    high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1944
  return gen_rtx_LO_SUM (Pmode, high, addr);
1945
}
1946
 
1947
 
1948
/* Return an UNSPEC address with underlying address ADDRESS and symbol
1949
   type SYMBOL_TYPE.  */
1950
 
1951
rtx
1952
mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1953
{
1954
  rtx base;
1955
  HOST_WIDE_INT offset;
1956
 
1957
  mips_split_const (address, &base, &offset);
1958
  base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1959
                         UNSPEC_ADDRESS_FIRST + symbol_type);
1960
  return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1961
}
1962
 
1963
 
1964
/* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1965
   high part to BASE and return the result.  Just return BASE otherwise.
1966
   TEMP is available as a temporary register if needed.
1967
 
1968
   The returned expression can be used as the first operand to a LO_SUM.  */
1969
 
1970
static rtx
1971
mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1972
                         enum mips_symbol_type symbol_type)
1973
{
1974
  if (mips_split_p[symbol_type])
1975
    {
1976
      addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1977
      addr = mips_force_temporary (temp, addr);
1978
      return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1979
    }
1980
  return base;
1981
}
1982
 
1983
 
1984
/* Return a legitimate address for REG + OFFSET.  TEMP is as for
1985
   mips_force_temporary; it is only needed when OFFSET is not a
1986
   SMALL_OPERAND.  */
1987
 
1988
static rtx
1989
mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1990
{
1991
  if (!SMALL_OPERAND (offset))
1992
    {
1993
      rtx high;
1994
      if (TARGET_MIPS16)
1995
        {
1996
          /* Load the full offset into a register so that we can use
1997
             an unextended instruction for the address itself.  */
1998
          high = GEN_INT (offset);
1999
          offset = 0;
2000
        }
2001
      else
2002
        {
2003
          /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.  */
2004
          high = GEN_INT (CONST_HIGH_PART (offset));
2005
          offset = CONST_LOW_PART (offset);
2006
        }
2007
      high = mips_force_temporary (temp, high);
2008
      reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2009
    }
2010
  return plus_constant (reg, offset);
2011
}
2012
 
2013
/* Emit a call to __tls_get_addr.  SYM is the TLS symbol we are
2014
   referencing, and TYPE is the symbol type to use (either global
2015
   dynamic or local dynamic).  V0 is an RTX for the return value
2016
   location.  The entire insn sequence is returned.  */
2017
 
2018
static GTY(()) rtx mips_tls_symbol;
2019
 
2020
static rtx
2021
mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2022
{
2023
  rtx insn, loc, tga, a0;
2024
 
2025
  a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2026
 
2027
  if (!mips_tls_symbol)
2028
    mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2029
 
2030
  loc = mips_unspec_address (sym, type);
2031
 
2032
  start_sequence ();
2033
 
2034
  emit_insn (gen_rtx_SET (Pmode, a0,
2035
                          gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2036
  tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2037
  insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2038
  CONST_OR_PURE_CALL_P (insn) = 1;
2039
  use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2040
  use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2041
  insn = get_insns ();
2042
 
2043
  end_sequence ();
2044
 
2045
  return insn;
2046
}
2047
 
2048
/* Generate the code to access LOC, a thread local SYMBOL_REF.  The
2049
   return value will be a valid address and move_operand (either a REG
2050
   or a LO_SUM).  */
2051
 
2052
static rtx
2053
mips_legitimize_tls_address (rtx loc)
2054
{
2055
  rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2056
  enum tls_model model;
2057
 
2058
  v0 = gen_rtx_REG (Pmode, GP_RETURN);
2059
  v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2060
 
2061
  model = SYMBOL_REF_TLS_MODEL (loc);
2062
  /* Only TARGET_ABICALLS code can have more than one module; other
2063
     code must be be static and should not use a GOT.  All TLS models
2064
     reduce to local exec in this situation.  */
2065
  if (!TARGET_ABICALLS)
2066
    model = TLS_MODEL_LOCAL_EXEC;
2067
 
2068
  switch (model)
2069
    {
2070
    case TLS_MODEL_GLOBAL_DYNAMIC:
2071
      insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2072
      dest = gen_reg_rtx (Pmode);
2073
      emit_libcall_block (insn, dest, v0, loc);
2074
      break;
2075
 
2076
    case TLS_MODEL_LOCAL_DYNAMIC:
2077
      insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2078
      tmp1 = gen_reg_rtx (Pmode);
2079
 
2080
      /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2081
         share the LDM result with other LD model accesses.  */
2082
      eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2083
                            UNSPEC_TLS_LDM);
2084
      emit_libcall_block (insn, tmp1, v0, eqv);
2085
 
2086
      tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2087
      dest = gen_rtx_LO_SUM (Pmode, tmp2,
2088
                             mips_unspec_address (loc, SYMBOL_DTPREL));
2089
      break;
2090
 
2091
    case TLS_MODEL_INITIAL_EXEC:
2092
      tmp1 = gen_reg_rtx (Pmode);
2093
      tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2094
      if (Pmode == DImode)
2095
        {
2096
          emit_insn (gen_tls_get_tp_di (v1));
2097
          emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2098
        }
2099
      else
2100
        {
2101
          emit_insn (gen_tls_get_tp_si (v1));
2102
          emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2103
        }
2104
      dest = gen_reg_rtx (Pmode);
2105
      emit_insn (gen_add3_insn (dest, tmp1, v1));
2106
      break;
2107
 
2108
    case TLS_MODEL_LOCAL_EXEC:
2109
      if (Pmode == DImode)
2110
        emit_insn (gen_tls_get_tp_di (v1));
2111
      else
2112
        emit_insn (gen_tls_get_tp_si (v1));
2113
 
2114
      tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2115
      dest = gen_rtx_LO_SUM (Pmode, tmp1,
2116
                             mips_unspec_address (loc, SYMBOL_TPREL));
2117
      break;
2118
 
2119
    default:
2120
      gcc_unreachable ();
2121
    }
2122
 
2123
  return dest;
2124
}
2125
 
2126
/* This function is used to implement LEGITIMIZE_ADDRESS.  If *XLOC can
2127
   be legitimized in a way that the generic machinery might not expect,
2128
   put the new address in *XLOC and return true.  MODE is the mode of
2129
   the memory being accessed.  */
2130
 
2131
bool
2132
mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2133
{
2134
  enum mips_symbol_type symbol_type;
2135
 
2136
  if (mips_tls_operand_p (*xloc))
2137
    {
2138
      *xloc = mips_legitimize_tls_address (*xloc);
2139
      return true;
2140
    }
2141
 
2142
  /* See if the address can split into a high part and a LO_SUM.  */
2143
  if (mips_symbolic_constant_p (*xloc, &symbol_type)
2144
      && mips_symbolic_address_p (symbol_type, mode)
2145
      && mips_split_p[symbol_type])
2146
    {
2147
      *xloc = mips_split_symbol (0, *xloc);
2148
      return true;
2149
    }
2150
 
2151
  if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2152
    {
2153
      /* Handle REG + CONSTANT using mips_add_offset.  */
2154
      rtx reg;
2155
 
2156
      reg = XEXP (*xloc, 0);
2157
      if (!mips_valid_base_register_p (reg, mode, 0))
2158
        reg = copy_to_mode_reg (Pmode, reg);
2159
      *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2160
      return true;
2161
    }
2162
 
2163
  return false;
2164
}
2165
 
2166
 
2167
/* Subroutine of mips_build_integer (with the same interface).
2168
   Assume that the final action in the sequence should be a left shift.  */
2169
 
2170
static unsigned int
2171
mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2172
{
2173
  unsigned int i, shift;
2174
 
2175
  /* Shift VALUE right until its lowest bit is set.  Shift arithmetically
2176
     since signed numbers are easier to load than unsigned ones.  */
2177
  shift = 0;
2178
  while ((value & 1) == 0)
2179
    value /= 2, shift++;
2180
 
2181
  i = mips_build_integer (codes, value);
2182
  codes[i].code = ASHIFT;
2183
  codes[i].value = shift;
2184
  return i + 1;
2185
}
2186
 
2187
 
2188
/* As for mips_build_shift, but assume that the final action will be
2189
   an IOR or PLUS operation.  */
2190
 
2191
static unsigned int
2192
mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2193
{
2194
  unsigned HOST_WIDE_INT high;
2195
  unsigned int i;
2196
 
2197
  high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2198
  if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2199
    {
2200
      /* The constant is too complex to load with a simple lui/ori pair
2201
         so our goal is to clear as many trailing zeros as possible.
2202
         In this case, we know bit 16 is set and that the low 16 bits
2203
         form a negative number.  If we subtract that number from VALUE,
2204
         we will clear at least the lowest 17 bits, maybe more.  */
2205
      i = mips_build_integer (codes, CONST_HIGH_PART (value));
2206
      codes[i].code = PLUS;
2207
      codes[i].value = CONST_LOW_PART (value);
2208
    }
2209
  else
2210
    {
2211
      i = mips_build_integer (codes, high);
2212
      codes[i].code = IOR;
2213
      codes[i].value = value & 0xffff;
2214
    }
2215
  return i + 1;
2216
}
2217
 
2218
 
2219
/* Fill CODES with a sequence of rtl operations to load VALUE.
2220
   Return the number of operations needed.  */
2221
 
2222
static unsigned int
2223
mips_build_integer (struct mips_integer_op *codes,
2224
                    unsigned HOST_WIDE_INT value)
2225
{
2226
  if (SMALL_OPERAND (value)
2227
      || SMALL_OPERAND_UNSIGNED (value)
2228
      || LUI_OPERAND (value))
2229
    {
2230
      /* The value can be loaded with a single instruction.  */
2231
      codes[0].code = UNKNOWN;
2232
      codes[0].value = value;
2233
      return 1;
2234
    }
2235
  else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2236
    {
2237
      /* Either the constant is a simple LUI/ORI combination or its
2238
         lowest bit is set.  We don't want to shift in this case.  */
2239
      return mips_build_lower (codes, value);
2240
    }
2241
  else if ((value & 0xffff) == 0)
2242
    {
2243
      /* The constant will need at least three actions.  The lowest
2244
         16 bits are clear, so the final action will be a shift.  */
2245
      return mips_build_shift (codes, value);
2246
    }
2247
  else
2248
    {
2249
      /* The final action could be a shift, add or inclusive OR.
2250
         Rather than use a complex condition to select the best
2251
         approach, try both mips_build_shift and mips_build_lower
2252
         and pick the one that gives the shortest sequence.
2253
         Note that this case is only used once per constant.  */
2254
      struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2255
      unsigned int cost, alt_cost;
2256
 
2257
      cost = mips_build_shift (codes, value);
2258
      alt_cost = mips_build_lower (alt_codes, value);
2259
      if (alt_cost < cost)
2260
        {
2261
          memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2262
          cost = alt_cost;
2263
        }
2264
      return cost;
2265
    }
2266
}
2267
 
2268
 
2269
/* Load VALUE into DEST, using TEMP as a temporary register if need be.  */
2270
 
2271
void
2272
mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2273
{
2274
  struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2275
  enum machine_mode mode;
2276
  unsigned int i, cost;
2277
  rtx x;
2278
 
2279
  mode = GET_MODE (dest);
2280
  cost = mips_build_integer (codes, value);
2281
 
2282
  /* Apply each binary operation to X.  Invariant: X is a legitimate
2283
     source operand for a SET pattern.  */
2284
  x = GEN_INT (codes[0].value);
2285
  for (i = 1; i < cost; i++)
2286
    {
2287
      if (no_new_pseudos)
2288
        {
2289
          emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2290
          x = temp;
2291
        }
2292
      else
2293
        x = force_reg (mode, x);
2294
      x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2295
    }
2296
 
2297
  emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2298
}
2299
 
2300
 
2301
/* Subroutine of mips_legitimize_move.  Move constant SRC into register
2302
   DEST given that SRC satisfies immediate_operand but doesn't satisfy
2303
   move_operand.  */
2304
 
2305
static void
2306
mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2307
{
2308
  rtx base;
2309
  HOST_WIDE_INT offset;
2310
 
2311
  /* Split moves of big integers into smaller pieces.  */
2312
  if (splittable_const_int_operand (src, mode))
2313
    {
2314
      mips_move_integer (dest, dest, INTVAL (src));
2315
      return;
2316
    }
2317
 
2318
  /* Split moves of symbolic constants into high/low pairs.  */
2319
  if (splittable_symbolic_operand (src, mode))
2320
    {
2321
      emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2322
      return;
2323
    }
2324
 
2325
  if (mips_tls_operand_p (src))
2326
    {
2327
      emit_move_insn (dest, mips_legitimize_tls_address (src));
2328
      return;
2329
    }
2330
 
2331
  /* If we have (const (plus symbol offset)), load the symbol first
2332
     and then add in the offset.  This is usually better than forcing
2333
     the constant into memory, at least in non-mips16 code.  */
2334
  mips_split_const (src, &base, &offset);
2335
  if (!TARGET_MIPS16
2336
      && offset != 0
2337
      && (!no_new_pseudos || SMALL_OPERAND (offset)))
2338
    {
2339
      base = mips_force_temporary (dest, base);
2340
      emit_move_insn (dest, mips_add_offset (0, base, offset));
2341
      return;
2342
    }
2343
 
2344
  src = force_const_mem (mode, src);
2345
 
2346
  /* When using explicit relocs, constant pool references are sometimes
2347
     not legitimate addresses.  */
2348
  if (!memory_operand (src, VOIDmode))
2349
    src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2350
  emit_move_insn (dest, src);
2351
}
2352
 
2353
 
2354
/* If (set DEST SRC) is not a valid instruction, emit an equivalent
2355
   sequence that is valid.  */
2356
 
2357
bool
2358
mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2359
{
2360
  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2361
    {
2362
      emit_move_insn (dest, force_reg (mode, src));
2363
      return true;
2364
    }
2365
 
2366
  /* Check for individual, fully-reloaded mflo and mfhi instructions.  */
2367
  if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2368
      && REG_P (src) && MD_REG_P (REGNO (src))
2369
      && REG_P (dest) && GP_REG_P (REGNO (dest)))
2370
    {
2371
      int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2372
      if (GET_MODE_SIZE (mode) <= 4)
2373
        emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2374
                                  gen_rtx_REG (SImode, REGNO (src)),
2375
                                  gen_rtx_REG (SImode, other_regno)));
2376
      else
2377
        emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2378
                                  gen_rtx_REG (DImode, REGNO (src)),
2379
                                  gen_rtx_REG (DImode, other_regno)));
2380
      return true;
2381
    }
2382
 
2383
  /* We need to deal with constants that would be legitimate
2384
     immediate_operands but not legitimate move_operands.  */
2385
  if (CONSTANT_P (src) && !move_operand (src, mode))
2386
    {
2387
      mips_legitimize_const_move (mode, dest, src);
2388
      set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2389
      return true;
2390
    }
2391
  return false;
2392
}
2393
 
2394
/* We need a lot of little routines to check constant values on the
2395
   mips16.  These are used to figure out how long the instruction will
2396
   be.  It would be much better to do this using constraints, but
2397
   there aren't nearly enough letters available.  */
2398
 
2399
static int
2400
m16_check_op (rtx op, int low, int high, int mask)
2401
{
2402
  return (GET_CODE (op) == CONST_INT
2403
          && INTVAL (op) >= low
2404
          && INTVAL (op) <= high
2405
          && (INTVAL (op) & mask) == 0);
2406
}
2407
 
2408
int
2409
m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2410
{
2411
  return m16_check_op (op, 0x1, 0x8, 0);
2412
}
2413
 
2414
int
2415
m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2416
{
2417
  return m16_check_op (op, - 0x8, 0x7, 0);
2418
}
2419
 
2420
int
2421
m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2422
{
2423
  return m16_check_op (op, - 0x7, 0x8, 0);
2424
}
2425
 
2426
int
2427
m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2428
{
2429
  return m16_check_op (op, - 0x10, 0xf, 0);
2430
}
2431
 
2432
int
2433
m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2434
{
2435
  return m16_check_op (op, - 0xf, 0x10, 0);
2436
}
2437
 
2438
int
2439
m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2440
{
2441
  return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2442
}
2443
 
2444
int
2445
m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2446
{
2447
  return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2448
}
2449
 
2450
int
2451
m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2452
{
2453
  return m16_check_op (op, - 0x80, 0x7f, 0);
2454
}
2455
 
2456
int
2457
m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2458
{
2459
  return m16_check_op (op, - 0x7f, 0x80, 0);
2460
}
2461
 
2462
int
2463
m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2464
{
2465
  return m16_check_op (op, 0x0, 0xff, 0);
2466
}
2467
 
2468
int
2469
m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2470
{
2471
  return m16_check_op (op, - 0xff, 0x0, 0);
2472
}
2473
 
2474
int
2475
m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2476
{
2477
  return m16_check_op (op, - 0x1, 0xfe, 0);
2478
}
2479
 
2480
int
2481
m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2482
{
2483
  return m16_check_op (op, 0x0, 0xff << 2, 3);
2484
}
2485
 
2486
int
2487
m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2488
{
2489
  return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2490
}
2491
 
2492
int
2493
m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2494
{
2495
  return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2496
}
2497
 
2498
int
2499
m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2500
{
2501
  return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2502
}
2503
 
2504
static bool
2505
mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2506
{
2507
  enum machine_mode mode = GET_MODE (x);
2508
  bool float_mode_p = FLOAT_MODE_P (mode);
2509
 
2510
  switch (code)
2511
    {
2512
    case CONST_INT:
2513
      if (TARGET_MIPS16)
2514
        {
2515
          /* A number between 1 and 8 inclusive is efficient for a shift.
2516
             Otherwise, we will need an extended instruction.  */
2517
          if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2518
              || (outer_code) == LSHIFTRT)
2519
            {
2520
              if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2521
                *total = 0;
2522
              else
2523
                *total = COSTS_N_INSNS (1);
2524
              return true;
2525
            }
2526
 
2527
          /* We can use cmpi for an xor with an unsigned 16 bit value.  */
2528
          if ((outer_code) == XOR
2529
              && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2530
            {
2531
              *total = 0;
2532
              return true;
2533
            }
2534
 
2535
          /* We may be able to use slt or sltu for a comparison with a
2536
             signed 16 bit value.  (The boundary conditions aren't quite
2537
             right, but this is just a heuristic anyhow.)  */
2538
          if (((outer_code) == LT || (outer_code) == LE
2539
               || (outer_code) == GE || (outer_code) == GT
2540
               || (outer_code) == LTU || (outer_code) == LEU
2541
               || (outer_code) == GEU || (outer_code) == GTU)
2542
              && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2543
            {
2544
              *total = 0;
2545
              return true;
2546
            }
2547
 
2548
          /* Equality comparisons with 0 are cheap.  */
2549
          if (((outer_code) == EQ || (outer_code) == NE)
2550
              && INTVAL (x) == 0)
2551
            {
2552
              *total = 0;
2553
              return true;
2554
            }
2555
 
2556
          /* Constants in the range 0...255 can be loaded with an unextended
2557
             instruction.  They are therefore as cheap as a register move.
2558
 
2559
             Given the choice between "li R1,0...255" and "move R1,R2"
2560
             (where R2 is a known constant), it is usually better to use "li",
2561
             since we do not want to unnecessarily extend the lifetime
2562
             of R2.  */
2563
          if (outer_code == SET
2564
              && INTVAL (x) >= 0
2565
              && INTVAL (x) < 256)
2566
            {
2567
              *total = 0;
2568
              return true;
2569
            }
2570
        }
2571
      else
2572
        {
2573
          /* These can be used anywhere. */
2574
          *total = 0;
2575
          return true;
2576
        }
2577
 
2578
      /* Otherwise fall through to the handling below because
2579
         we'll need to construct the constant.  */
2580
 
2581
    case CONST:
2582
    case SYMBOL_REF:
2583
    case LABEL_REF:
2584
    case CONST_DOUBLE:
2585
      if (LEGITIMATE_CONSTANT_P (x))
2586
        {
2587
          *total = COSTS_N_INSNS (1);
2588
          return true;
2589
        }
2590
      else
2591
        {
2592
          /* The value will need to be fetched from the constant pool.  */
2593
          *total = CONSTANT_POOL_COST;
2594
          return true;
2595
        }
2596
 
2597
    case MEM:
2598
      {
2599
        /* If the address is legitimate, return the number of
2600
           instructions it needs, otherwise use the default handling.  */
2601
        int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2602
        if (n > 0)
2603
          {
2604
            *total = COSTS_N_INSNS (n + 1);
2605
            return true;
2606
          }
2607
        return false;
2608
      }
2609
 
2610
    case FFS:
2611
      *total = COSTS_N_INSNS (6);
2612
      return true;
2613
 
2614
    case NOT:
2615
      *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2616
      return true;
2617
 
2618
    case AND:
2619
    case IOR:
2620
    case XOR:
2621
      if (mode == DImode && !TARGET_64BIT)
2622
        {
2623
          *total = COSTS_N_INSNS (2);
2624
          return true;
2625
        }
2626
      return false;
2627
 
2628
    case ASHIFT:
2629
    case ASHIFTRT:
2630
    case LSHIFTRT:
2631
      if (mode == DImode && !TARGET_64BIT)
2632
        {
2633
          *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2634
                                  ? 4 : 12);
2635
          return true;
2636
        }
2637
      return false;
2638
 
2639
    case ABS:
2640
      if (float_mode_p)
2641
        *total = COSTS_N_INSNS (1);
2642
      else
2643
        *total = COSTS_N_INSNS (4);
2644
      return true;
2645
 
2646
    case LO_SUM:
2647
      *total = COSTS_N_INSNS (1);
2648
      return true;
2649
 
2650
    case PLUS:
2651
    case MINUS:
2652
      if (float_mode_p)
2653
        {
2654
          *total = mips_cost->fp_add;
2655
          return true;
2656
        }
2657
 
2658
      else if (mode == DImode && !TARGET_64BIT)
2659
        {
2660
          *total = COSTS_N_INSNS (4);
2661
          return true;
2662
        }
2663
      return false;
2664
 
2665
    case NEG:
2666
      if (mode == DImode && !TARGET_64BIT)
2667
        {
2668
          *total = COSTS_N_INSNS (4);
2669
          return true;
2670
        }
2671
      return false;
2672
 
2673
    case MULT:
2674
      if (mode == SFmode)
2675
        *total = mips_cost->fp_mult_sf;
2676
 
2677
      else if (mode == DFmode)
2678
        *total = mips_cost->fp_mult_df;
2679
 
2680
      else if (mode == SImode)
2681
        *total = mips_cost->int_mult_si;
2682
 
2683
      else
2684
        *total = mips_cost->int_mult_di;
2685
 
2686
      return true;
2687
 
2688
    case DIV:
2689
    case MOD:
2690
      if (float_mode_p)
2691
        {
2692
          if (mode == SFmode)
2693
            *total = mips_cost->fp_div_sf;
2694
          else
2695
            *total = mips_cost->fp_div_df;
2696
 
2697
          return true;
2698
        }
2699
      /* Fall through.  */
2700
 
2701
    case UDIV:
2702
    case UMOD:
2703
      if (mode == DImode)
2704
        *total = mips_cost->int_div_di;
2705
      else
2706
        *total = mips_cost->int_div_si;
2707
 
2708
      return true;
2709
 
2710
    case SIGN_EXTEND:
2711
      /* A sign extend from SImode to DImode in 64 bit mode is often
2712
         zero instructions, because the result can often be used
2713
         directly by another instruction; we'll call it one.  */
2714
      if (TARGET_64BIT && mode == DImode
2715
          && GET_MODE (XEXP (x, 0)) == SImode)
2716
        *total = COSTS_N_INSNS (1);
2717
      else
2718
        *total = COSTS_N_INSNS (2);
2719
      return true;
2720
 
2721
    case ZERO_EXTEND:
2722
      if (TARGET_64BIT && mode == DImode
2723
          && GET_MODE (XEXP (x, 0)) == SImode)
2724
        *total = COSTS_N_INSNS (2);
2725
      else
2726
        *total = COSTS_N_INSNS (1);
2727
      return true;
2728
 
2729
    case FLOAT:
2730
    case UNSIGNED_FLOAT:
2731
    case FIX:
2732
    case FLOAT_EXTEND:
2733
    case FLOAT_TRUNCATE:
2734
    case SQRT:
2735
      *total = mips_cost->fp_add;
2736
      return true;
2737
 
2738
    default:
2739
      return false;
2740
    }
2741
}
2742
 
2743
/* Provide the costs of an addressing mode that contains ADDR.
2744
   If ADDR is not a valid address, its cost is irrelevant.  */
2745
 
2746
static int
2747
mips_address_cost (rtx addr)
2748
{
2749
  return mips_address_insns (addr, SImode);
2750
}
2751
 
2752
/* Return one word of double-word value OP, taking into account the fixed
2753
   endianness of certain registers.  HIGH_P is true to select the high part,
2754
   false to select the low part.  */
2755
 
2756
rtx
2757
mips_subword (rtx op, int high_p)
2758
{
2759
  unsigned int byte;
2760
  enum machine_mode mode;
2761
 
2762
  mode = GET_MODE (op);
2763
  if (mode == VOIDmode)
2764
    mode = DImode;
2765
 
2766
  if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2767
    byte = UNITS_PER_WORD;
2768
  else
2769
    byte = 0;
2770
 
2771
  if (REG_P (op))
2772
    {
2773
      if (FP_REG_P (REGNO (op)))
2774
        return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2775
      if (ACC_HI_REG_P (REGNO (op)))
2776
        return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2777
    }
2778
 
2779
  if (MEM_P (op))
2780
    return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2781
 
2782
  return simplify_gen_subreg (word_mode, op, mode, byte);
2783
}
2784
 
2785
 
2786
/* Return true if a 64-bit move from SRC to DEST should be split into two.  */
2787
 
2788
bool
2789
mips_split_64bit_move_p (rtx dest, rtx src)
2790
{
2791
  if (TARGET_64BIT)
2792
    return false;
2793
 
2794
  /* FP->FP moves can be done in a single instruction.  */
2795
  if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2796
    return false;
2797
 
2798
  /* Check for floating-point loads and stores.  They can be done using
2799
     ldc1 and sdc1 on MIPS II and above.  */
2800
  if (mips_isa > 1)
2801
    {
2802
      if (FP_REG_RTX_P (dest) && MEM_P (src))
2803
        return false;
2804
      if (FP_REG_RTX_P (src) && MEM_P (dest))
2805
        return false;
2806
    }
2807
  return true;
2808
}
2809
 
2810
 
2811
/* Split a 64-bit move from SRC to DEST assuming that
2812
   mips_split_64bit_move_p holds.
2813
 
2814
   Moves into and out of FPRs cause some difficulty here.  Such moves
2815
   will always be DFmode, since paired FPRs are not allowed to store
2816
   DImode values.  The most natural representation would be two separate
2817
   32-bit moves, such as:
2818
 
2819
        (set (reg:SI $f0) (mem:SI ...))
2820
        (set (reg:SI $f1) (mem:SI ...))
2821
 
2822
   However, the second insn is invalid because odd-numbered FPRs are
2823
   not allowed to store independent values.  Use the patterns load_df_low,
2824
   load_df_high and store_df_high instead.  */
2825
 
2826
void
2827
mips_split_64bit_move (rtx dest, rtx src)
2828
{
2829
  if (FP_REG_RTX_P (dest))
2830
    {
2831
      /* Loading an FPR from memory or from GPRs.  */
2832
      emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2833
      emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2834
                                   copy_rtx (dest)));
2835
    }
2836
  else if (FP_REG_RTX_P (src))
2837
    {
2838
      /* Storing an FPR into memory or GPRs.  */
2839
      emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2840
      emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2841
    }
2842
  else
2843
    {
2844
      /* The operation can be split into two normal moves.  Decide in
2845
         which order to do them.  */
2846
      rtx low_dest;
2847
 
2848
      low_dest = mips_subword (dest, 0);
2849
      if (REG_P (low_dest)
2850
          && reg_overlap_mentioned_p (low_dest, src))
2851
        {
2852
          emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2853
          emit_move_insn (low_dest, mips_subword (src, 0));
2854
        }
2855
      else
2856
        {
2857
          emit_move_insn (low_dest, mips_subword (src, 0));
2858
          emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2859
        }
2860
    }
2861
}
2862
 
2863
/* Return the appropriate instructions to move SRC into DEST.  Assume
2864
   that SRC is operand 1 and DEST is operand 0.  */
2865
 
2866
const char *
2867
mips_output_move (rtx dest, rtx src)
2868
{
2869
  enum rtx_code dest_code, src_code;
2870
  bool dbl_p;
2871
 
2872
  dest_code = GET_CODE (dest);
2873
  src_code = GET_CODE (src);
2874
  dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2875
 
2876
  if (dbl_p && mips_split_64bit_move_p (dest, src))
2877
    return "#";
2878
 
2879
  if ((src_code == REG && GP_REG_P (REGNO (src)))
2880
      || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2881
    {
2882
      if (dest_code == REG)
2883
        {
2884
          if (GP_REG_P (REGNO (dest)))
2885
            return "move\t%0,%z1";
2886
 
2887
          if (MD_REG_P (REGNO (dest)))
2888
            return "mt%0\t%z1";
2889
 
2890
          if (DSP_ACC_REG_P (REGNO (dest)))
2891
            {
2892
              static char retval[] = "mt__\t%z1,%q0";
2893
              retval[2] = reg_names[REGNO (dest)][4];
2894
              retval[3] = reg_names[REGNO (dest)][5];
2895
              return retval;
2896
            }
2897
 
2898
          if (FP_REG_P (REGNO (dest)))
2899
            return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2900
 
2901
          if (ALL_COP_REG_P (REGNO (dest)))
2902
            {
2903
              static char retval[] = "dmtc_\t%z1,%0";
2904
 
2905
              retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2906
              return (dbl_p ? retval : retval + 1);
2907
            }
2908
        }
2909
      if (dest_code == MEM)
2910
        return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2911
    }
2912
  if (dest_code == REG && GP_REG_P (REGNO (dest)))
2913
    {
2914
      if (src_code == REG)
2915
        {
2916
          if (DSP_ACC_REG_P (REGNO (src)))
2917
            {
2918
              static char retval[] = "mf__\t%0,%q1";
2919
              retval[2] = reg_names[REGNO (src)][4];
2920
              retval[3] = reg_names[REGNO (src)][5];
2921
              return retval;
2922
            }
2923
 
2924
          if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2925
            return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2926
 
2927
          if (FP_REG_P (REGNO (src)))
2928
            return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2929
 
2930
          if (ALL_COP_REG_P (REGNO (src)))
2931
            {
2932
              static char retval[] = "dmfc_\t%0,%1";
2933
 
2934
              retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2935
              return (dbl_p ? retval : retval + 1);
2936
            }
2937
        }
2938
 
2939
      if (src_code == MEM)
2940
        return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2941
 
2942
      if (src_code == CONST_INT)
2943
        {
2944
          /* Don't use the X format, because that will give out of
2945
             range numbers for 64 bit hosts and 32 bit targets.  */
2946
          if (!TARGET_MIPS16)
2947
            return "li\t%0,%1\t\t\t# %X1";
2948
 
2949
          if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2950
            return "li\t%0,%1";
2951
 
2952
          if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2953
            return "#";
2954
        }
2955
 
2956
      if (src_code == HIGH)
2957
        return "lui\t%0,%h1";
2958
 
2959
      if (CONST_GP_P (src))
2960
        return "move\t%0,%1";
2961
 
2962
      if (symbolic_operand (src, VOIDmode))
2963
        return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2964
    }
2965
  if (src_code == REG && FP_REG_P (REGNO (src)))
2966
    {
2967
      if (dest_code == REG && FP_REG_P (REGNO (dest)))
2968
        {
2969
          if (GET_MODE (dest) == V2SFmode)
2970
            return "mov.ps\t%0,%1";
2971
          else
2972
            return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2973
        }
2974
 
2975
      if (dest_code == MEM)
2976
        return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2977
    }
2978
  if (dest_code == REG && FP_REG_P (REGNO (dest)))
2979
    {
2980
      if (src_code == MEM)
2981
        return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2982
    }
2983
  if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2984
    {
2985
      static char retval[] = "l_c_\t%0,%1";
2986
 
2987
      retval[1] = (dbl_p ? 'd' : 'w');
2988
      retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2989
      return retval;
2990
    }
2991
  if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2992
    {
2993
      static char retval[] = "s_c_\t%1,%0";
2994
 
2995
      retval[1] = (dbl_p ? 'd' : 'w');
2996
      retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2997
      return retval;
2998
    }
2999
  gcc_unreachable ();
3000
}
3001
 
3002
/* Restore $gp from its save slot.  Valid only when using o32 or
3003
   o64 abicalls.  */
3004
 
3005
void
3006
mips_restore_gp (void)
3007
{
3008
  rtx address, slot;
3009
 
3010
  gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
3011
 
3012
  address = mips_add_offset (pic_offset_table_rtx,
3013
                             frame_pointer_needed
3014
                             ? hard_frame_pointer_rtx
3015
                             : stack_pointer_rtx,
3016
                             current_function_outgoing_args_size);
3017
  slot = gen_rtx_MEM (Pmode, address);
3018
 
3019
  emit_move_insn (pic_offset_table_rtx, slot);
3020
  if (!TARGET_EXPLICIT_RELOCS)
3021
    emit_insn (gen_blockage ());
3022
}
3023
 
3024
/* Emit an instruction of the form (set TARGET (CODE OP0 OP1)).  */
3025
 
3026
static void
3027
mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3028
{
3029
  emit_insn (gen_rtx_SET (VOIDmode, target,
3030
                          gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3031
}
3032
 
3033
/* Return true if CMP1 is a suitable second operand for relational
3034
   operator CODE.  See also the *sCC patterns in mips.md.  */
3035
 
3036
static bool
3037
mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3038
{
3039
  switch (code)
3040
    {
3041
    case GT:
3042
    case GTU:
3043
      return reg_or_0_operand (cmp1, VOIDmode);
3044
 
3045
    case GE:
3046
    case GEU:
3047
      return !TARGET_MIPS16 && cmp1 == const1_rtx;
3048
 
3049
    case LT:
3050
    case LTU:
3051
      return arith_operand (cmp1, VOIDmode);
3052
 
3053
    case LE:
3054
      return sle_operand (cmp1, VOIDmode);
3055
 
3056
    case LEU:
3057
      return sleu_operand (cmp1, VOIDmode);
3058
 
3059
    default:
3060
      gcc_unreachable ();
3061
    }
3062
}
3063
 
3064
/* Canonicalize LE or LEU comparisons into LT comparisons when
3065
   possible to avoid extra instructions or inverting the
3066
   comparison.  */
3067
 
3068
static bool
3069
mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3070
                              enum machine_mode mode)
3071
{
3072
  HOST_WIDE_INT original, plus_one;
3073
 
3074
  if (GET_CODE (*cmp1) != CONST_INT)
3075
    return false;
3076
 
3077
  original = INTVAL (*cmp1);
3078
  plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3079
 
3080
  switch (*code)
3081
    {
3082
    case LE:
3083
      if (original < plus_one)
3084
        {
3085
          *code = LT;
3086
          *cmp1 = force_reg (mode, GEN_INT (plus_one));
3087
          return true;
3088
        }
3089
      break;
3090
 
3091
    case LEU:
3092
      if (plus_one != 0)
3093
        {
3094
          *code = LTU;
3095
          *cmp1 = force_reg (mode, GEN_INT (plus_one));
3096
          return true;
3097
        }
3098
      break;
3099
 
3100
    default:
3101
      return false;
3102
   }
3103
 
3104
  return false;
3105
 
3106
}
3107
 
3108
/* Compare CMP0 and CMP1 using relational operator CODE and store the
3109
   result in TARGET.  CMP0 and TARGET are register_operands that have
3110
   the same integer mode.  If INVERT_PTR is nonnull, it's OK to set
3111
   TARGET to the inverse of the result and flip *INVERT_PTR instead.  */
3112
 
3113
static void
3114
mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3115
                          rtx target, rtx cmp0, rtx cmp1)
3116
{
3117
  /* First see if there is a MIPS instruction that can do this operation
3118
     with CMP1 in its current form. If not, try to canonicalize the
3119
     comparison to LT. If that fails, try doing the same for the
3120
     inverse operation.  If that also fails, force CMP1 into a register
3121
     and try again.  */
3122
  if (mips_relational_operand_ok_p (code, cmp1))
3123
    mips_emit_binary (code, target, cmp0, cmp1);
3124
  else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3125
    mips_emit_binary (code, target, cmp0, cmp1);
3126
  else
3127
    {
3128
      enum rtx_code inv_code = reverse_condition (code);
3129
      if (!mips_relational_operand_ok_p (inv_code, cmp1))
3130
        {
3131
          cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3132
          mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3133
        }
3134
      else if (invert_ptr == 0)
3135
        {
3136
          rtx inv_target = gen_reg_rtx (GET_MODE (target));
3137
          mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3138
          mips_emit_binary (XOR, target, inv_target, const1_rtx);
3139
        }
3140
      else
3141
        {
3142
          *invert_ptr = !*invert_ptr;
3143
          mips_emit_binary (inv_code, target, cmp0, cmp1);
3144
        }
3145
    }
3146
}
3147
 
3148
/* Return a register that is zero iff CMP0 and CMP1 are equal.
3149
   The register will have the same mode as CMP0.  */
3150
 
3151
static rtx
3152
mips_zero_if_equal (rtx cmp0, rtx cmp1)
3153
{
3154
  if (cmp1 == const0_rtx)
3155
    return cmp0;
3156
 
3157
  if (uns_arith_operand (cmp1, VOIDmode))
3158
    return expand_binop (GET_MODE (cmp0), xor_optab,
3159
                         cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3160
 
3161
  return expand_binop (GET_MODE (cmp0), sub_optab,
3162
                       cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3163
}
3164
 
3165
/* Convert *CODE into a code that can be used in a floating-point
3166
   scc instruction (c.<cond>.<fmt>).  Return true if the values of
3167
   the condition code registers will be inverted, with 0 indicating
3168
   that the condition holds.  */
3169
 
3170
static bool
3171
mips_reverse_fp_cond_p (enum rtx_code *code)
3172
{
3173
  switch (*code)
3174
    {
3175
    case NE:
3176
    case LTGT:
3177
    case ORDERED:
3178
      *code = reverse_condition_maybe_unordered (*code);
3179
      return true;
3180
 
3181
    default:
3182
      return false;
3183
    }
3184
}
3185
 
3186
/* Convert a comparison into something that can be used in a branch or
3187
   conditional move.  cmp_operands[0] and cmp_operands[1] are the values
3188
   being compared and *CODE is the code used to compare them.
3189
 
3190
   Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3191
   If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3192
   otherwise any standard branch condition can be used.  The standard branch
3193
   conditions are:
3194
 
3195
      - EQ/NE between two registers.
3196
      - any comparison between a register and zero.  */
3197
 
3198
static void
3199
mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3200
{
3201
  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3202
    {
3203
      if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3204
        {
3205
          *op0 = cmp_operands[0];
3206
          *op1 = cmp_operands[1];
3207
        }
3208
      else if (*code == EQ || *code == NE)
3209
        {
3210
          if (need_eq_ne_p)
3211
            {
3212
              *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3213
              *op1 = const0_rtx;
3214
            }
3215
          else
3216
            {
3217
              *op0 = cmp_operands[0];
3218
              *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3219
            }
3220
        }
3221
      else
3222
        {
3223
          /* The comparison needs a separate scc instruction.  Store the
3224
             result of the scc in *OP0 and compare it against zero.  */
3225
          bool invert = false;
3226
          *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3227
          *op1 = const0_rtx;
3228
          mips_emit_int_relational (*code, &invert, *op0,
3229
                                    cmp_operands[0], cmp_operands[1]);
3230
          *code = (invert ? EQ : NE);
3231
        }
3232
    }
3233
  else
3234
    {
3235
      enum rtx_code cmp_code;
3236
 
3237
      /* Floating-point tests use a separate c.cond.fmt comparison to
3238
         set a condition code register.  The branch or conditional move
3239
         will then compare that register against zero.
3240
 
3241
         Set CMP_CODE to the code of the comparison instruction and
3242
         *CODE to the code that the branch or move should use.  */
3243
      cmp_code = *code;
3244
      *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3245
      *op0 = (ISA_HAS_8CC
3246
              ? gen_reg_rtx (CCmode)
3247
              : gen_rtx_REG (CCmode, FPSW_REGNUM));
3248
      *op1 = const0_rtx;
3249
      mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3250
    }
3251
}
3252
 
3253
/* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3254
   Store the result in TARGET and return true if successful.
3255
 
3256
   On 64-bit targets, TARGET may be wider than cmp_operands[0].  */
3257
 
3258
bool
3259
mips_emit_scc (enum rtx_code code, rtx target)
3260
{
3261
  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3262
    return false;
3263
 
3264
  target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3265
  if (code == EQ || code == NE)
3266
    {
3267
      rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3268
      mips_emit_binary (code, target, zie, const0_rtx);
3269
    }
3270
  else
3271
    mips_emit_int_relational (code, 0, target,
3272
                              cmp_operands[0], cmp_operands[1]);
3273
  return true;
3274
}
3275
 
3276
/* Emit the common code for doing conditional branches.
3277
   operand[0] is the label to jump to.
3278
   The comparison operands are saved away by cmp{si,di,sf,df}.  */
3279
 
3280
void
3281
gen_conditional_branch (rtx *operands, enum rtx_code code)
3282
{
3283
  rtx op0, op1, condition;
3284
 
3285
  mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3286
  condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3287
  emit_jump_insn (gen_condjump (condition, operands[0]));
3288
}
3289
 
3290
/* Implement:
3291
 
3292
   (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3293
   (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS))  */
3294
 
3295
void
3296
mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3297
                       enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3298
{
3299
  rtx cmp_result;
3300
  bool reversed_p;
3301
 
3302
  reversed_p = mips_reverse_fp_cond_p (&cond);
3303
  cmp_result = gen_reg_rtx (CCV2mode);
3304
  emit_insn (gen_scc_ps (cmp_result,
3305
                         gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3306
  if (reversed_p)
3307
    emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3308
                                         cmp_result));
3309
  else
3310
    emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3311
                                         cmp_result));
3312
}
3313
 
3314
/* Emit the common code for conditional moves.  OPERANDS is the array
3315
   of operands passed to the conditional move define_expand.  */
3316
 
3317
void
3318
gen_conditional_move (rtx *operands)
3319
{
3320
  enum rtx_code code;
3321
  rtx op0, op1;
3322
 
3323
  code = GET_CODE (operands[1]);
3324
  mips_emit_compare (&code, &op0, &op1, true);
3325
  emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3326
                          gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3327
                                                gen_rtx_fmt_ee (code,
3328
                                                                GET_MODE (op0),
3329
                                                                op0, op1),
3330
                                                operands[2], operands[3])));
3331
}
3332
 
3333
/* Emit a conditional trap.  OPERANDS is the array of operands passed to
3334
   the conditional_trap expander.  */
3335
 
3336
void
3337
mips_gen_conditional_trap (rtx *operands)
3338
{
3339
  rtx op0, op1;
3340
  enum rtx_code cmp_code = GET_CODE (operands[0]);
3341
  enum machine_mode mode = GET_MODE (cmp_operands[0]);
3342
 
3343
  /* MIPS conditional trap machine instructions don't have GT or LE
3344
     flavors, so we must invert the comparison and convert to LT and
3345
     GE, respectively.  */
3346
  switch (cmp_code)
3347
    {
3348
    case GT: cmp_code = LT; break;
3349
    case LE: cmp_code = GE; break;
3350
    case GTU: cmp_code = LTU; break;
3351
    case LEU: cmp_code = GEU; break;
3352
    default: break;
3353
    }
3354
  if (cmp_code == GET_CODE (operands[0]))
3355
    {
3356
      op0 = cmp_operands[0];
3357
      op1 = cmp_operands[1];
3358
    }
3359
  else
3360
    {
3361
      op0 = cmp_operands[1];
3362
      op1 = cmp_operands[0];
3363
    }
3364
  op0 = force_reg (mode, op0);
3365
  if (!arith_operand (op1, mode))
3366
    op1 = force_reg (mode, op1);
3367
 
3368
  emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3369
                              gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3370
                              operands[1]));
3371
}
3372
 
3373
/* Load function address ADDR into register DEST.  SIBCALL_P is true
3374
   if the address is needed for a sibling call.  */
3375
 
3376
static void
3377
mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3378
{
3379
  /* If we're generating PIC, and this call is to a global function,
3380
     try to allow its address to be resolved lazily.  This isn't
3381
     possible for NewABI sibcalls since the value of $gp on entry
3382
     to the stub would be our caller's gp, not ours.  */
3383
  if (TARGET_EXPLICIT_RELOCS
3384
      && !(sibcall_p && TARGET_NEWABI)
3385
      && global_got_operand (addr, VOIDmode))
3386
    {
3387
      rtx high, lo_sum_symbol;
3388
 
3389
      high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3390
                                      addr, SYMBOL_GOTOFF_CALL);
3391
      lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3392
      if (Pmode == SImode)
3393
        emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3394
      else
3395
        emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3396
    }
3397
  else
3398
    emit_move_insn (dest, addr);
3399
}
3400
 
3401
 
3402
/* Expand a call or call_value instruction.  RESULT is where the
3403
   result will go (null for calls), ADDR is the address of the
3404
   function, ARGS_SIZE is the size of the arguments and AUX is
3405
   the value passed to us by mips_function_arg.  SIBCALL_P is true
3406
   if we are expanding a sibling call, false if we're expanding
3407
   a normal call.  */
3408
 
3409
void
3410
mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3411
{
3412
  rtx orig_addr, pattern, insn;
3413
 
3414
  orig_addr = addr;
3415
  if (!call_insn_operand (addr, VOIDmode))
3416
    {
3417
      addr = gen_reg_rtx (Pmode);
3418
      mips_load_call_address (addr, orig_addr, sibcall_p);
3419
    }
3420
 
3421
  if (TARGET_MIPS16
3422
      && mips16_hard_float
3423
      && build_mips16_call_stub (result, addr, args_size,
3424
                                 aux == 0 ? 0 : (int) GET_MODE (aux)))
3425
    return;
3426
 
3427
  if (result == 0)
3428
    pattern = (sibcall_p
3429
               ? gen_sibcall_internal (addr, args_size)
3430
               : gen_call_internal (addr, args_size));
3431
  else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3432
    {
3433
      rtx reg1, reg2;
3434
 
3435
      reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3436
      reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3437
      pattern =
3438
        (sibcall_p
3439
         ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3440
         : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3441
    }
3442
  else
3443
    pattern = (sibcall_p
3444
               ? gen_sibcall_value_internal (result, addr, args_size)
3445
               : gen_call_value_internal (result, addr, args_size));
3446
 
3447
  insn = emit_call_insn (pattern);
3448
 
3449
  /* Lazy-binding stubs require $gp to be valid on entry.  */
3450
  if (global_got_operand (orig_addr, VOIDmode))
3451
    use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3452
}
3453
 
3454
 
3455
/* We can handle any sibcall when TARGET_SIBCALLS is true.  */
3456
 
3457
static bool
3458
mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3459
                              tree exp ATTRIBUTE_UNUSED)
3460
{
3461
  return TARGET_SIBCALLS;
3462
}
3463
 
3464
/* Emit code to move general operand SRC into condition-code
3465
   register DEST.  SCRATCH is a scratch TFmode float register.
3466
   The sequence is:
3467
 
3468
        FP1 = SRC
3469
        FP2 = 0.0f
3470
        DEST = FP2 < FP1
3471
 
3472
   where FP1 and FP2 are single-precision float registers
3473
   taken from SCRATCH.  */
3474
 
3475
void
3476
mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3477
{
3478
  rtx fp1, fp2;
3479
 
3480
  /* Change the source to SFmode.  */
3481
  if (MEM_P (src))
3482
    src = adjust_address (src, SFmode, 0);
3483
  else if (REG_P (src) || GET_CODE (src) == SUBREG)
3484
    src = gen_rtx_REG (SFmode, true_regnum (src));
3485
 
3486
  fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3487
  fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3488
 
3489
  emit_move_insn (copy_rtx (fp1), src);
3490
  emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3491
  emit_insn (gen_slt_sf (dest, fp2, fp1));
3492
}
3493
 
3494
/* Emit code to change the current function's return address to
3495
   ADDRESS.  SCRATCH is available as a scratch register, if needed.
3496
   ADDRESS and SCRATCH are both word-mode GPRs.  */
3497
 
3498
void
3499
mips_set_return_address (rtx address, rtx scratch)
3500
{
3501
  rtx slot_address;
3502
 
3503
  compute_frame_size (get_frame_size ());
3504
  gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3505
  slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3506
                                  cfun->machine->frame.gp_sp_offset);
3507
 
3508
  emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3509
}
3510
 
3511
/* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3512
   Assume that the areas do not overlap.  */
3513
 
3514
static void
3515
mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3516
{
3517
  HOST_WIDE_INT offset, delta;
3518
  unsigned HOST_WIDE_INT bits;
3519
  int i;
3520
  enum machine_mode mode;
3521
  rtx *regs;
3522
 
3523
  /* Work out how many bits to move at a time.  If both operands have
3524
     half-word alignment, it is usually better to move in half words.
3525
     For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3526
     and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3527
     Otherwise move word-sized chunks.  */
3528
  if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3529
      && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3530
    bits = BITS_PER_WORD / 2;
3531
  else
3532
    bits = BITS_PER_WORD;
3533
 
3534
  mode = mode_for_size (bits, MODE_INT, 0);
3535
  delta = bits / BITS_PER_UNIT;
3536
 
3537
  /* Allocate a buffer for the temporary registers.  */
3538
  regs = alloca (sizeof (rtx) * length / delta);
3539
 
3540
  /* Load as many BITS-sized chunks as possible.  Use a normal load if
3541
     the source has enough alignment, otherwise use left/right pairs.  */
3542
  for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3543
    {
3544
      regs[i] = gen_reg_rtx (mode);
3545
      if (MEM_ALIGN (src) >= bits)
3546
        emit_move_insn (regs[i], adjust_address (src, mode, offset));
3547
      else
3548
        {
3549
          rtx part = adjust_address (src, BLKmode, offset);
3550
          if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3551
            gcc_unreachable ();
3552
        }
3553
    }
3554
 
3555
  /* Copy the chunks to the destination.  */
3556
  for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3557
    if (MEM_ALIGN (dest) >= bits)
3558
      emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3559
    else
3560
      {
3561
        rtx part = adjust_address (dest, BLKmode, offset);
3562
        if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3563
          gcc_unreachable ();
3564
      }
3565
 
3566
  /* Mop up any left-over bytes.  */
3567
  if (offset < length)
3568
    {
3569
      src = adjust_address (src, BLKmode, offset);
3570
      dest = adjust_address (dest, BLKmode, offset);
3571
      move_by_pieces (dest, src, length - offset,
3572
                      MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3573
    }
3574
}
3575
 
3576
#define MAX_MOVE_REGS 4
3577
#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3578
 
3579
 
3580
/* Helper function for doing a loop-based block operation on memory
3581
   reference MEM.  Each iteration of the loop will operate on LENGTH
3582
   bytes of MEM.
3583
 
3584
   Create a new base register for use within the loop and point it to
3585
   the start of MEM.  Create a new memory reference that uses this
3586
   register.  Store them in *LOOP_REG and *LOOP_MEM respectively.  */
3587
 
3588
static void
3589
mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3590
                       rtx *loop_reg, rtx *loop_mem)
3591
{
3592
  *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3593
 
3594
  /* Although the new mem does not refer to a known location,
3595
     it does keep up to LENGTH bytes of alignment.  */
3596
  *loop_mem = change_address (mem, BLKmode, *loop_reg);
3597
  set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3598
}
3599
 
3600
 
3601
/* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3602
   per iteration.  LENGTH must be at least MAX_MOVE_BYTES.  Assume that the
3603
   memory regions do not overlap.  */
3604
 
3605
static void
3606
mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3607
{
3608
  rtx label, src_reg, dest_reg, final_src;
3609
  HOST_WIDE_INT leftover;
3610
 
3611
  leftover = length % MAX_MOVE_BYTES;
3612
  length -= leftover;
3613
 
3614
  /* Create registers and memory references for use within the loop.  */
3615
  mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3616
  mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3617
 
3618
  /* Calculate the value that SRC_REG should have after the last iteration
3619
     of the loop.  */
3620
  final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3621
                                   0, 0, OPTAB_WIDEN);
3622
 
3623
  /* Emit the start of the loop.  */
3624
  label = gen_label_rtx ();
3625
  emit_label (label);
3626
 
3627
  /* Emit the loop body.  */
3628
  mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3629
 
3630
  /* Move on to the next block.  */
3631
  emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3632
  emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3633
 
3634
  /* Emit the loop condition.  */
3635
  if (Pmode == DImode)
3636
    emit_insn (gen_cmpdi (src_reg, final_src));
3637
  else
3638
    emit_insn (gen_cmpsi (src_reg, final_src));
3639
  emit_jump_insn (gen_bne (label));
3640
 
3641
  /* Mop up any left-over bytes.  */
3642
  if (leftover)
3643
    mips_block_move_straight (dest, src, leftover);
3644
}
3645
 
3646
/* Expand a movmemsi instruction.  */
3647
 
3648
bool
3649
mips_expand_block_move (rtx dest, rtx src, rtx length)
3650
{
3651
  if (GET_CODE (length) == CONST_INT)
3652
    {
3653
      if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3654
        {
3655
          mips_block_move_straight (dest, src, INTVAL (length));
3656
          return true;
3657
        }
3658
      else if (optimize)
3659
        {
3660
          mips_block_move_loop (dest, src, INTVAL (length));
3661
          return true;
3662
        }
3663
    }
3664
  return false;
3665
}
3666
 
3667
/* Argument support functions.  */
3668
 
3669
/* Initialize CUMULATIVE_ARGS for a function.  */
3670
 
3671
void
3672
init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3673
                      rtx libname ATTRIBUTE_UNUSED)
3674
{
3675
  static CUMULATIVE_ARGS zero_cum;
3676
  tree param, next_param;
3677
 
3678
  *cum = zero_cum;
3679
  cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3680
 
3681
  /* Determine if this function has variable arguments.  This is
3682
     indicated by the last argument being 'void_type_mode' if there
3683
     are no variable arguments.  The standard MIPS calling sequence
3684
     passes all arguments in the general purpose registers in this case.  */
3685
 
3686
  for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3687
       param != 0; param = next_param)
3688
    {
3689
      next_param = TREE_CHAIN (param);
3690
      if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3691
        cum->gp_reg_found = 1;
3692
    }
3693
}
3694
 
3695
 
3696
/* Fill INFO with information about a single argument.  CUM is the
3697
   cumulative state for earlier arguments.  MODE is the mode of this
3698
   argument and TYPE is its type (if known).  NAMED is true if this
3699
   is a named (fixed) argument rather than a variable one.  */
3700
 
3701
static void
3702
mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3703
               tree type, int named, struct mips_arg_info *info)
3704
{
3705
  bool doubleword_aligned_p;
3706
  unsigned int num_bytes, num_words, max_regs;
3707
 
3708
  /* Work out the size of the argument.  */
3709
  num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3710
  num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3711
 
3712
  /* Decide whether it should go in a floating-point register, assuming
3713
     one is free.  Later code checks for availability.
3714
 
3715
     The checks against UNITS_PER_FPVALUE handle the soft-float and
3716
     single-float cases.  */
3717
  switch (mips_abi)
3718
    {
3719
    case ABI_EABI:
3720
      /* The EABI conventions have traditionally been defined in terms
3721
         of TYPE_MODE, regardless of the actual type.  */
3722
      info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3723
                      || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3724
                     && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3725
      break;
3726
 
3727
    case ABI_32:
3728
    case ABI_O64:
3729
      /* Only leading floating-point scalars are passed in
3730
         floating-point registers.  We also handle vector floats the same
3731
         say, which is OK because they are not covered by the standard ABI.  */
3732
      info->fpr_p = (!cum->gp_reg_found
3733
                     && cum->arg_number < 2
3734
                     && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3735
                         || VECTOR_FLOAT_TYPE_P (type))
3736
                     && (GET_MODE_CLASS (mode) == MODE_FLOAT
3737
                         || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3738
                     && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3739
      break;
3740
 
3741
    case ABI_N32:
3742
    case ABI_64:
3743
      /* Scalar and complex floating-point types are passed in
3744
         floating-point registers.  */
3745
      info->fpr_p = (named
3746
                     && (type == 0 || FLOAT_TYPE_P (type))
3747
                     && (GET_MODE_CLASS (mode) == MODE_FLOAT
3748
                         || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3749
                         || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3750
                     && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3751
 
3752
      /* ??? According to the ABI documentation, the real and imaginary
3753
         parts of complex floats should be passed in individual registers.
3754
         The real and imaginary parts of stack arguments are supposed
3755
         to be contiguous and there should be an extra word of padding
3756
         at the end.
3757
 
3758
         This has two problems.  First, it makes it impossible to use a
3759
         single "void *" va_list type, since register and stack arguments
3760
         are passed differently.  (At the time of writing, MIPSpro cannot
3761
         handle complex float varargs correctly.)  Second, it's unclear
3762
         what should happen when there is only one register free.
3763
 
3764
         For now, we assume that named complex floats should go into FPRs
3765
         if there are two FPRs free, otherwise they should be passed in the
3766
         same way as a struct containing two floats.  */
3767
      if (info->fpr_p
3768
          && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3769
          && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3770
        {
3771
          if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3772
            info->fpr_p = false;
3773
          else
3774
            num_words = 2;
3775
        }
3776
      break;
3777
 
3778
    default:
3779
      gcc_unreachable ();
3780
    }
3781
 
3782
  /* See whether the argument has doubleword alignment.  */
3783
  doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3784
 
3785
  /* Set REG_OFFSET to the register count we're interested in.
3786
     The EABI allocates the floating-point registers separately,
3787
     but the other ABIs allocate them like integer registers.  */
3788
  info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3789
                      ? cum->num_fprs
3790
                      : cum->num_gprs);
3791
 
3792
  /* Advance to an even register if the argument is doubleword-aligned.  */
3793
  if (doubleword_aligned_p)
3794
    info->reg_offset += info->reg_offset & 1;
3795
 
3796
  /* Work out the offset of a stack argument.  */
3797
  info->stack_offset = cum->stack_words;
3798
  if (doubleword_aligned_p)
3799
    info->stack_offset += info->stack_offset & 1;
3800
 
3801
  max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3802
 
3803
  /* Partition the argument between registers and stack.  */
3804
  info->reg_words = MIN (num_words, max_regs);
3805
  info->stack_words = num_words - info->reg_words;
3806
}
3807
 
3808
 
3809
/* Implement FUNCTION_ARG_ADVANCE.  */
3810
 
3811
void
3812
function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3813
                      tree type, int named)
3814
{
3815
  struct mips_arg_info info;
3816
 
3817
  mips_arg_info (cum, mode, type, named, &info);
3818
 
3819
  if (!info.fpr_p)
3820
    cum->gp_reg_found = true;
3821
 
3822
  /* See the comment above the cumulative args structure in mips.h
3823
     for an explanation of what this code does.  It assumes the O32
3824
     ABI, which passes at most 2 arguments in float registers.  */
3825
  if (cum->arg_number < 2 && info.fpr_p)
3826
    cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3827
 
3828
  if (mips_abi != ABI_EABI || !info.fpr_p)
3829
    cum->num_gprs = info.reg_offset + info.reg_words;
3830
  else if (info.reg_words > 0)
3831
    cum->num_fprs += FP_INC;
3832
 
3833
  if (info.stack_words > 0)
3834
    cum->stack_words = info.stack_offset + info.stack_words;
3835
 
3836
  cum->arg_number++;
3837
}
3838
 
3839
/* Implement FUNCTION_ARG.  */
3840
 
3841
struct rtx_def *
3842
function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3843
              tree type, int named)
3844
{
3845
  struct mips_arg_info info;
3846
 
3847
  /* We will be called with a mode of VOIDmode after the last argument
3848
     has been seen.  Whatever we return will be passed to the call
3849
     insn.  If we need a mips16 fp_code, return a REG with the code
3850
     stored as the mode.  */
3851
  if (mode == VOIDmode)
3852
    {
3853
      if (TARGET_MIPS16 && cum->fp_code != 0)
3854
        return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3855
 
3856
      else
3857
        return 0;
3858
    }
3859
 
3860
  mips_arg_info (cum, mode, type, named, &info);
3861
 
3862
  /* Return straight away if the whole argument is passed on the stack.  */
3863
  if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3864
    return 0;
3865
 
3866
  if (type != 0
3867
      && TREE_CODE (type) == RECORD_TYPE
3868
      && TARGET_NEWABI
3869
      && TYPE_SIZE_UNIT (type)
3870
      && host_integerp (TYPE_SIZE_UNIT (type), 1)
3871
      && named)
3872
    {
3873
      /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3874
         structure contains a double in its entirety, then that 64 bit
3875
         chunk is passed in a floating point register.  */
3876
      tree field;
3877
 
3878
      /* First check to see if there is any such field.  */
3879
      for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3880
        if (TREE_CODE (field) == FIELD_DECL
3881
            && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3882
            && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3883
            && host_integerp (bit_position (field), 0)
3884
            && int_bit_position (field) % BITS_PER_WORD == 0)
3885
          break;
3886
 
3887
      if (field != 0)
3888
        {
3889
          /* Now handle the special case by returning a PARALLEL
3890
             indicating where each 64 bit chunk goes.  INFO.REG_WORDS
3891
             chunks are passed in registers.  */
3892
          unsigned int i;
3893
          HOST_WIDE_INT bitpos;
3894
          rtx ret;
3895
 
3896
          /* assign_parms checks the mode of ENTRY_PARM, so we must
3897
             use the actual mode here.  */
3898
          ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3899
 
3900
          bitpos = 0;
3901
          field = TYPE_FIELDS (type);
3902
          for (i = 0; i < info.reg_words; i++)
3903
            {
3904
              rtx reg;
3905
 
3906
              for (; field; field = TREE_CHAIN (field))
3907
                if (TREE_CODE (field) == FIELD_DECL
3908
                    && int_bit_position (field) >= bitpos)
3909
                  break;
3910
 
3911
              if (field
3912
                  && int_bit_position (field) == bitpos
3913
                  && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3914
                  && !TARGET_SOFT_FLOAT
3915
                  && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3916
                reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3917
              else
3918
                reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3919
 
3920
              XVECEXP (ret, 0, i)
3921
                = gen_rtx_EXPR_LIST (VOIDmode, reg,
3922
                                     GEN_INT (bitpos / BITS_PER_UNIT));
3923
 
3924
              bitpos += BITS_PER_WORD;
3925
            }
3926
          return ret;
3927
        }
3928
    }
3929
 
3930
  /* Handle the n32/n64 conventions for passing complex floating-point
3931
     arguments in FPR pairs.  The real part goes in the lower register
3932
     and the imaginary part goes in the upper register.  */
3933
  if (TARGET_NEWABI
3934
      && info.fpr_p
3935
      && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3936
    {
3937
      rtx real, imag;
3938
      enum machine_mode inner;
3939
      int reg;
3940
 
3941
      inner = GET_MODE_INNER (mode);
3942
      reg = FP_ARG_FIRST + info.reg_offset;
3943
      if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
3944
        {
3945
          /* Real part in registers, imaginary part on stack.  */
3946
          gcc_assert (info.stack_words == info.reg_words);
3947
          return gen_rtx_REG (inner, reg);
3948
        }
3949
      else
3950
        {
3951
          gcc_assert (info.stack_words == 0);
3952
          real = gen_rtx_EXPR_LIST (VOIDmode,
3953
                                    gen_rtx_REG (inner, reg),
3954
                                    const0_rtx);
3955
          imag = gen_rtx_EXPR_LIST (VOIDmode,
3956
                                    gen_rtx_REG (inner,
3957
                                                 reg + info.reg_words / 2),
3958
                                    GEN_INT (GET_MODE_SIZE (inner)));
3959
          return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3960
        }
3961
    }
3962
 
3963
  if (!info.fpr_p)
3964
    return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3965
  else if (info.reg_offset == 1)
3966
    /* This code handles the special o32 case in which the second word
3967
       of the argument structure is passed in floating-point registers.  */
3968
    return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3969
  else
3970
    return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3971
}
3972
 
3973
 
3974
/* Implement TARGET_ARG_PARTIAL_BYTES.  */
3975
 
3976
static int
3977
mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3978
                        enum machine_mode mode, tree type, bool named)
3979
{
3980
  struct mips_arg_info info;
3981
 
3982
  mips_arg_info (cum, mode, type, named, &info);
3983
  return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3984
}
3985
 
3986
 
3987
/* Implement FUNCTION_ARG_BOUNDARY.  Every parameter gets at least
3988
   PARM_BOUNDARY bits of alignment, but will be given anything up
3989
   to STACK_BOUNDARY bits if the type requires it.  */
3990
 
3991
int
3992
function_arg_boundary (enum machine_mode mode, tree type)
3993
{
3994
  unsigned int alignment;
3995
 
3996
  alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3997
  if (alignment < PARM_BOUNDARY)
3998
    alignment = PARM_BOUNDARY;
3999
  if (alignment > STACK_BOUNDARY)
4000
    alignment = STACK_BOUNDARY;
4001
  return alignment;
4002
}
4003
 
4004
/* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4005
   upward rather than downward.  In other words, return true if the
4006
   first byte of the stack slot has useful data, false if the last
4007
   byte does.  */
4008
 
4009
bool
4010
mips_pad_arg_upward (enum machine_mode mode, tree type)
4011
{
4012
  /* On little-endian targets, the first byte of every stack argument
4013
     is passed in the first byte of the stack slot.  */
4014
  if (!BYTES_BIG_ENDIAN)
4015
    return true;
4016
 
4017
  /* Otherwise, integral types are padded downward: the last byte of a
4018
     stack argument is passed in the last byte of the stack slot.  */
4019
  if (type != 0
4020
      ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
4021
      : GET_MODE_CLASS (mode) == MODE_INT)
4022
    return false;
4023
 
4024
  /* Big-endian o64 pads floating-point arguments downward.  */
4025
  if (mips_abi == ABI_O64)
4026
    if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4027
      return false;
4028
 
4029
  /* Other types are padded upward for o32, o64, n32 and n64.  */
4030
  if (mips_abi != ABI_EABI)
4031
    return true;
4032
 
4033
  /* Arguments smaller than a stack slot are padded downward.  */
4034
  if (mode != BLKmode)
4035
    return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4036
  else
4037
    return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4038
}
4039
 
4040
 
4041
/* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...).  Return !BYTES_BIG_ENDIAN
4042
   if the least significant byte of the register has useful data.  Return
4043
   the opposite if the most significant byte does.  */
4044
 
4045
bool
4046
mips_pad_reg_upward (enum machine_mode mode, tree type)
4047
{
4048
  /* No shifting is required for floating-point arguments.  */
4049
  if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4050
    return !BYTES_BIG_ENDIAN;
4051
 
4052
  /* Otherwise, apply the same padding to register arguments as we do
4053
     to stack arguments.  */
4054
  return mips_pad_arg_upward (mode, type);
4055
}
4056
 
4057
static void
4058
mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4059
                             tree type, int *pretend_size ATTRIBUTE_UNUSED,
4060
                             int no_rtl)
4061
{
4062
  CUMULATIVE_ARGS local_cum;
4063
  int gp_saved, fp_saved;
4064
 
4065
  /* The caller has advanced CUM up to, but not beyond, the last named
4066
     argument.  Advance a local copy of CUM past the last "real" named
4067
     argument, to find out how many registers are left over.  */
4068
 
4069
  local_cum = *cum;
4070
  FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4071
 
4072
  /* Found out how many registers we need to save.  */
4073
  gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4074
  fp_saved = (EABI_FLOAT_VARARGS_P
4075
              ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4076
              : 0);
4077
 
4078
  if (!no_rtl)
4079
    {
4080
      if (gp_saved > 0)
4081
        {
4082
          rtx ptr, mem;
4083
 
4084
          ptr = plus_constant (virtual_incoming_args_rtx,
4085
                               REG_PARM_STACK_SPACE (cfun->decl)
4086
                               - gp_saved * UNITS_PER_WORD);
4087
          mem = gen_rtx_MEM (BLKmode, ptr);
4088
          set_mem_alias_set (mem, get_varargs_alias_set ());
4089
 
4090
          move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4091
                               mem, gp_saved);
4092
        }
4093
      if (fp_saved > 0)
4094
        {
4095
          /* We can't use move_block_from_reg, because it will use
4096
             the wrong mode.  */
4097
          enum machine_mode mode;
4098
          int off, i;
4099
 
4100
          /* Set OFF to the offset from virtual_incoming_args_rtx of
4101
             the first float register.  The FP save area lies below
4102
             the integer one, and is aligned to UNITS_PER_FPVALUE bytes.  */
4103
          off = -gp_saved * UNITS_PER_WORD;
4104
          off &= ~(UNITS_PER_FPVALUE - 1);
4105
          off -= fp_saved * UNITS_PER_FPREG;
4106
 
4107
          mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4108
 
4109
          for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4110
            {
4111
              rtx ptr, mem;
4112
 
4113
              ptr = plus_constant (virtual_incoming_args_rtx, off);
4114
              mem = gen_rtx_MEM (mode, ptr);
4115
              set_mem_alias_set (mem, get_varargs_alias_set ());
4116
              emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4117
              off += UNITS_PER_HWFPVALUE;
4118
            }
4119
        }
4120
    }
4121
  if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4122
    cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4123
                                   + fp_saved * UNITS_PER_FPREG);
4124
}
4125
 
4126
/* Create the va_list data type.
4127
   We keep 3 pointers, and two offsets.
4128
   Two pointers are to the overflow area, which starts at the CFA.
4129
     One of these is constant, for addressing into the GPR save area below it.
4130
     The other is advanced up the stack through the overflow region.
4131
   The third pointer is to the GPR save area.  Since the FPR save area
4132
     is just below it, we can address FPR slots off this pointer.
4133
   We also keep two one-byte offsets, which are to be subtracted from the
4134
     constant pointers to yield addresses in the GPR and FPR save areas.
4135
     These are downcounted as float or non-float arguments are used,
4136
     and when they get to zero, the argument must be obtained from the
4137
     overflow region.
4138
   If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4139
     pointer is enough.  It's started at the GPR save area, and is
4140
     advanced, period.
4141
   Note that the GPR save area is not constant size, due to optimization
4142
     in the prologue.  Hence, we can't use a design with two pointers
4143
     and two offsets, although we could have designed this with two pointers
4144
     and three offsets.  */
4145
 
4146
static tree
4147
mips_build_builtin_va_list (void)
4148
{
4149
  if (EABI_FLOAT_VARARGS_P)
4150
    {
4151
      tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4152
      tree array, index;
4153
 
4154
      record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4155
 
4156
      f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4157
                          ptr_type_node);
4158
      f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4159
                          ptr_type_node);
4160
      f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4161
                          ptr_type_node);
4162
      f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4163
                          unsigned_char_type_node);
4164
      f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4165
                          unsigned_char_type_node);
4166
      /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4167
         warn on every user file.  */
4168
      index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4169
      array = build_array_type (unsigned_char_type_node,
4170
                                build_index_type (index));
4171
      f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4172
 
4173
      DECL_FIELD_CONTEXT (f_ovfl) = record;
4174
      DECL_FIELD_CONTEXT (f_gtop) = record;
4175
      DECL_FIELD_CONTEXT (f_ftop) = record;
4176
      DECL_FIELD_CONTEXT (f_goff) = record;
4177
      DECL_FIELD_CONTEXT (f_foff) = record;
4178
      DECL_FIELD_CONTEXT (f_res) = record;
4179
 
4180
      TYPE_FIELDS (record) = f_ovfl;
4181
      TREE_CHAIN (f_ovfl) = f_gtop;
4182
      TREE_CHAIN (f_gtop) = f_ftop;
4183
      TREE_CHAIN (f_ftop) = f_goff;
4184
      TREE_CHAIN (f_goff) = f_foff;
4185
      TREE_CHAIN (f_foff) = f_res;
4186
 
4187
      layout_type (record);
4188
      return record;
4189
    }
4190
  else if (TARGET_IRIX && TARGET_IRIX6)
4191
    /* On IRIX 6, this type is 'char *'.  */
4192
    return build_pointer_type (char_type_node);
4193
  else
4194
    /* Otherwise, we use 'void *'.  */
4195
    return ptr_type_node;
4196
}
4197
 
4198
/* Implement va_start.  */
4199
 
4200
void
4201
mips_va_start (tree valist, rtx nextarg)
4202
{
4203
  if (EABI_FLOAT_VARARGS_P)
4204
    {
4205
      const CUMULATIVE_ARGS *cum;
4206
      tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4207
      tree ovfl, gtop, ftop, goff, foff;
4208
      tree t;
4209
      int gpr_save_area_size;
4210
      int fpr_save_area_size;
4211
      int fpr_offset;
4212
 
4213
      cum = &current_function_args_info;
4214
      gpr_save_area_size
4215
        = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4216
      fpr_save_area_size
4217
        = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4218
 
4219
      f_ovfl = TYPE_FIELDS (va_list_type_node);
4220
      f_gtop = TREE_CHAIN (f_ovfl);
4221
      f_ftop = TREE_CHAIN (f_gtop);
4222
      f_goff = TREE_CHAIN (f_ftop);
4223
      f_foff = TREE_CHAIN (f_goff);
4224
 
4225
      ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4226
                     NULL_TREE);
4227
      gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4228
                     NULL_TREE);
4229
      ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4230
                     NULL_TREE);
4231
      goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4232
                     NULL_TREE);
4233
      foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4234
                     NULL_TREE);
4235
 
4236
      /* Emit code to initialize OVFL, which points to the next varargs
4237
         stack argument.  CUM->STACK_WORDS gives the number of stack
4238
         words used by named arguments.  */
4239
      t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4240
      if (cum->stack_words > 0)
4241
        t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
4242
                    build_int_cst (NULL_TREE,
4243
                                   cum->stack_words * UNITS_PER_WORD));
4244
      t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4245
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4246
 
4247
      /* Emit code to initialize GTOP, the top of the GPR save area.  */
4248
      t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4249
      t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4250
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4251
 
4252
      /* Emit code to initialize FTOP, the top of the FPR save area.
4253
         This address is gpr_save_area_bytes below GTOP, rounded
4254
         down to the next fp-aligned boundary.  */
4255
      t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4256
      fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4257
      fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4258
      if (fpr_offset)
4259
        t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
4260
                    build_int_cst (NULL_TREE, -fpr_offset));
4261
      t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4262
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4263
 
4264
      /* Emit code to initialize GOFF, the offset from GTOP of the
4265
         next GPR argument.  */
4266
      t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
4267
                  build_int_cst (NULL_TREE, gpr_save_area_size));
4268
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4269
 
4270
      /* Likewise emit code to initialize FOFF, the offset from FTOP
4271
         of the next FPR argument.  */
4272
      t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
4273
                  build_int_cst (NULL_TREE, fpr_save_area_size));
4274
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4275
    }
4276
  else
4277
    {
4278
      nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4279
      std_expand_builtin_va_start (valist, nextarg);
4280
    }
4281
}
4282
 
4283
/* Implement va_arg.  */
4284
 
4285
static tree
4286
mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4287
{
4288
  HOST_WIDE_INT size, rsize;
4289
  tree addr;
4290
  bool indirect;
4291
 
4292
  indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4293
 
4294
  if (indirect)
4295
    type = build_pointer_type (type);
4296
 
4297
  size = int_size_in_bytes (type);
4298
  rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4299
 
4300
  if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4301
    addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4302
  else
4303
    {
4304
      /* Not a simple merged stack.      */
4305
 
4306
      tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4307
      tree ovfl, top, off, align;
4308
      HOST_WIDE_INT osize;
4309
      tree t, u;
4310
 
4311
      f_ovfl = TYPE_FIELDS (va_list_type_node);
4312
      f_gtop = TREE_CHAIN (f_ovfl);
4313
      f_ftop = TREE_CHAIN (f_gtop);
4314
      f_goff = TREE_CHAIN (f_ftop);
4315
      f_foff = TREE_CHAIN (f_goff);
4316
 
4317
      /* We maintain separate pointers and offsets for floating-point
4318
         and integer arguments, but we need similar code in both cases.
4319
         Let:
4320
 
4321
         TOP be the top of the register save area;
4322
         OFF be the offset from TOP of the next register;
4323
         ADDR_RTX be the address of the argument;
4324
         RSIZE be the number of bytes used to store the argument
4325
         when it's in the register save area;
4326
         OSIZE be the number of bytes used to store it when it's
4327
         in the stack overflow area; and
4328
         PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4329
 
4330
         The code we want is:
4331
 
4332
         1: off &= -rsize;        // round down
4333
         2: if (off != 0)
4334
         3:   {
4335
         4:      addr_rtx = top - off;
4336
         5:      off -= rsize;
4337
         6:   }
4338
         7: else
4339
         8:   {
4340
         9:      ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4341
         10:     addr_rtx = ovfl + PADDING;
4342
         11:     ovfl += osize;
4343
         14:   }
4344
 
4345
         [1] and [9] can sometimes be optimized away.  */
4346
 
4347
      ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4348
                     NULL_TREE);
4349
 
4350
      if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4351
          && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4352
        {
4353
          top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4354
                        NULL_TREE);
4355
          off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4356
                        NULL_TREE);
4357
 
4358
          /* When floating-point registers are saved to the stack,
4359
             each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4360
             of the float's precision.  */
4361
          rsize = UNITS_PER_HWFPVALUE;
4362
 
4363
          /* Overflow arguments are padded to UNITS_PER_WORD bytes
4364
             (= PARM_BOUNDARY bits).  This can be different from RSIZE
4365
             in two cases:
4366
 
4367
             (1) On 32-bit targets when TYPE is a structure such as:
4368
 
4369
             struct s { float f; };
4370
 
4371
             Such structures are passed in paired FPRs, so RSIZE
4372
             will be 8 bytes.  However, the structure only takes
4373
             up 4 bytes of memory, so OSIZE will only be 4.
4374
 
4375
             (2) In combinations such as -mgp64 -msingle-float
4376
             -fshort-double.  Doubles passed in registers
4377
             will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4378
             but those passed on the stack take up
4379
             UNITS_PER_WORD bytes.  */
4380
          osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4381
        }
4382
      else
4383
        {
4384
          top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4385
                        NULL_TREE);
4386
          off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4387
                        NULL_TREE);
4388
          if (rsize > UNITS_PER_WORD)
4389
            {
4390
              /* [1] Emit code for: off &= -rsize.      */
4391
              t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4392
                          build_int_cst (NULL_TREE, -rsize));
4393
              t = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t);
4394
              gimplify_and_add (t, pre_p);
4395
            }
4396
          osize = rsize;
4397
        }
4398
 
4399
      /* [2] Emit code to branch if off == 0.  */
4400
      t = build2 (NE_EXPR, boolean_type_node, off,
4401
                  build_int_cst (TREE_TYPE (off), 0));
4402
      addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4403
 
4404
      /* [5] Emit code for: off -= rsize.  We do this as a form of
4405
         post-increment not available to C.  Also widen for the
4406
         coming pointer arithmetic.  */
4407
      t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4408
      t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4409
      t = fold_convert (sizetype, t);
4410
      t = fold_convert (TREE_TYPE (top), t);
4411
 
4412
      /* [4] Emit code for: addr_rtx = top - off.  On big endian machines,
4413
         the argument has RSIZE - SIZE bytes of leading padding.  */
4414
      t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t);
4415
      if (BYTES_BIG_ENDIAN && rsize > size)
4416
        {
4417
          u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4418
                                                          rsize - size));
4419
          t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4420
        }
4421
      COND_EXPR_THEN (addr) = t;
4422
 
4423
      if (osize > UNITS_PER_WORD)
4424
        {
4425
          /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize.  */
4426
          u = fold_convert (TREE_TYPE (ovfl),
4427
                            build_int_cst (NULL_TREE, osize - 1));
4428
          t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4429
          u = fold_convert (TREE_TYPE (ovfl),
4430
                            build_int_cst (NULL_TREE, -osize));
4431
          t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4432
          align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4433
        }
4434
      else
4435
        align = NULL;
4436
 
4437
      /* [10, 11].      Emit code to store ovfl in addr_rtx, then
4438
         post-increment ovfl by osize.  On big-endian machines,
4439
         the argument has OSIZE - SIZE bytes of leading padding.  */
4440
      u = fold_convert (TREE_TYPE (ovfl),
4441
                        build_int_cst (NULL_TREE, osize));
4442
      t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4443
      if (BYTES_BIG_ENDIAN && osize > size)
4444
        {
4445
          u = fold_convert (TREE_TYPE (t),
4446
                            build_int_cst (NULL_TREE, osize - size));
4447
          t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4448
        }
4449
 
4450
      /* String [9] and [10,11] together.  */
4451
      if (align)
4452
        t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4453
      COND_EXPR_ELSE (addr) = t;
4454
 
4455
      addr = fold_convert (build_pointer_type (type), addr);
4456
      addr = build_va_arg_indirect_ref (addr);
4457
    }
4458
 
4459
  if (indirect)
4460
    addr = build_va_arg_indirect_ref (addr);
4461
 
4462
  return addr;
4463
}
4464
 
4465
/* Return true if it is possible to use left/right accesses for a
4466
   bitfield of WIDTH bits starting BITPOS bits into *OP.  When
4467
   returning true, update *OP, *LEFT and *RIGHT as follows:
4468
 
4469
   *OP is a BLKmode reference to the whole field.
4470
 
4471
   *LEFT is a QImode reference to the first byte if big endian or
4472
   the last byte if little endian.  This address can be used in the
4473
   left-side instructions (lwl, swl, ldl, sdl).
4474
 
4475
   *RIGHT is a QImode reference to the opposite end of the field and
4476
   can be used in the patterning right-side instruction.  */
4477
 
4478
static bool
4479
mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4480
                        rtx *left, rtx *right)
4481
{
4482
  rtx first, last;
4483
 
4484
  /* Check that the operand really is a MEM.  Not all the extv and
4485
     extzv predicates are checked.  */
4486
  if (!MEM_P (*op))
4487
    return false;
4488
 
4489
  /* Check that the size is valid.  */
4490
  if (width != 32 && (!TARGET_64BIT || width != 64))
4491
    return false;
4492
 
4493
  /* We can only access byte-aligned values.  Since we are always passed
4494
     a reference to the first byte of the field, it is not necessary to
4495
     do anything with BITPOS after this check.  */
4496
  if (bitpos % BITS_PER_UNIT != 0)
4497
    return false;
4498
 
4499
  /* Reject aligned bitfields: we want to use a normal load or store
4500
     instead of a left/right pair.  */
4501
  if (MEM_ALIGN (*op) >= width)
4502
    return false;
4503
 
4504
  /* Adjust *OP to refer to the whole field.  This also has the effect
4505
     of legitimizing *OP's address for BLKmode, possibly simplifying it.  */
4506
  *op = adjust_address (*op, BLKmode, 0);
4507
  set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4508
 
4509
  /* Get references to both ends of the field.  We deliberately don't
4510
     use the original QImode *OP for FIRST since the new BLKmode one
4511
     might have a simpler address.  */
4512
  first = adjust_address (*op, QImode, 0);
4513
  last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4514
 
4515
  /* Allocate to LEFT and RIGHT according to endianness.  LEFT should
4516
     be the upper word and RIGHT the lower word.  */
4517
  if (TARGET_BIG_ENDIAN)
4518
    *left = first, *right = last;
4519
  else
4520
    *left = last, *right = first;
4521
 
4522
  return true;
4523
}
4524
 
4525
 
4526
/* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4527
   Return true on success.  We only handle cases where zero_extract is
4528
   equivalent to sign_extract.  */
4529
 
4530
bool
4531
mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4532
{
4533
  rtx left, right, temp;
4534
 
4535
  /* If TARGET_64BIT, the destination of a 32-bit load will be a
4536
     paradoxical word_mode subreg.  This is the only case in which
4537
     we allow the destination to be larger than the source.  */
4538
  if (GET_CODE (dest) == SUBREG
4539
      && GET_MODE (dest) == DImode
4540
      && SUBREG_BYTE (dest) == 0
4541
      && GET_MODE (SUBREG_REG (dest)) == SImode)
4542
    dest = SUBREG_REG (dest);
4543
 
4544
  /* After the above adjustment, the destination must be the same
4545
     width as the source.  */
4546
  if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4547
    return false;
4548
 
4549
  if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4550
    return false;
4551
 
4552
  temp = gen_reg_rtx (GET_MODE (dest));
4553
  if (GET_MODE (dest) == DImode)
4554
    {
4555
      emit_insn (gen_mov_ldl (temp, src, left));
4556
      emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4557
    }
4558
  else
4559
    {
4560
      emit_insn (gen_mov_lwl (temp, src, left));
4561
      emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4562
    }
4563
  return true;
4564
}
4565
 
4566
 
4567
/* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC).  Return
4568
   true on success.  */
4569
 
4570
bool
4571
mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4572
{
4573
  rtx left, right;
4574
  enum machine_mode mode;
4575
 
4576
  if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4577
    return false;
4578
 
4579
  mode = mode_for_size (width, MODE_INT, 0);
4580
  src = gen_lowpart (mode, src);
4581
 
4582
  if (mode == DImode)
4583
    {
4584
      emit_insn (gen_mov_sdl (dest, src, left));
4585
      emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4586
    }
4587
  else
4588
    {
4589
      emit_insn (gen_mov_swl (dest, src, left));
4590
      emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4591
    }
4592
  return true;
4593
}
4594
 
4595
/* Return true if X is a MEM with the same size as MODE.  */
4596
 
4597
bool
4598
mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4599
{
4600
  rtx size;
4601
 
4602
  if (!MEM_P (x))
4603
    return false;
4604
 
4605
  size = MEM_SIZE (x);
4606
  return size && INTVAL (size) == GET_MODE_SIZE (mode);
4607
}
4608
 
4609
/* Return true if (zero_extract OP SIZE POSITION) can be used as the
4610
   source of an "ext" instruction or the destination of an "ins"
4611
   instruction.  OP must be a register operand and the following
4612
   conditions must hold:
4613
 
4614
 
4615
 
4616
 
4617
 
4618
   Also reject lengths equal to a word as they are better handled
4619
   by the move patterns.  */
4620
 
4621
bool
4622
mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4623
{
4624
  HOST_WIDE_INT len, pos;
4625
 
4626
  if (!ISA_HAS_EXT_INS
4627
      || !register_operand (op, VOIDmode)
4628
      || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4629
    return false;
4630
 
4631
  len = INTVAL (size);
4632
  pos = INTVAL (position);
4633
 
4634
  if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4635
      || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4636
    return false;
4637
 
4638
  return true;
4639
}
4640
 
4641
/* Set up globals to generate code for the ISA or processor
4642
   described by INFO.  */
4643
 
4644
static void
4645
mips_set_architecture (const struct mips_cpu_info *info)
4646
{
4647
  if (info != 0)
4648
    {
4649
      mips_arch_info = info;
4650
      mips_arch = info->cpu;
4651
      mips_isa = info->isa;
4652
    }
4653
}
4654
 
4655
 
4656
/* Likewise for tuning.  */
4657
 
4658
static void
4659
mips_set_tune (const struct mips_cpu_info *info)
4660
{
4661
  if (info != 0)
4662
    {
4663
      mips_tune_info = info;
4664
      mips_tune = info->cpu;
4665
    }
4666
}
4667
 
4668
/* Implement TARGET_HANDLE_OPTION.  */
4669
 
4670
static bool
4671
mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4672
{
4673
  switch (code)
4674
    {
4675
    case OPT_mabi_:
4676
      if (strcmp (arg, "32") == 0)
4677
        mips_abi = ABI_32;
4678
      else if (strcmp (arg, "o64") == 0)
4679
        mips_abi = ABI_O64;
4680
      else if (strcmp (arg, "n32") == 0)
4681
        mips_abi = ABI_N32;
4682
      else if (strcmp (arg, "64") == 0)
4683
        mips_abi = ABI_64;
4684
      else if (strcmp (arg, "eabi") == 0)
4685
        mips_abi = ABI_EABI;
4686
      else
4687
        return false;
4688
      return true;
4689
 
4690
    case OPT_march_:
4691
    case OPT_mtune_:
4692
      return mips_parse_cpu (arg) != 0;
4693
 
4694
    case OPT_mips:
4695
      mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4696
      return mips_isa_info != 0;
4697
 
4698
    case OPT_mno_flush_func:
4699
      mips_cache_flush_func = NULL;
4700
      return true;
4701
 
4702
    default:
4703
      return true;
4704
    }
4705
}
4706
 
4707
/* Set up the threshold for data to go into the small data area, instead
4708
   of the normal data area, and detect any conflicts in the switches.  */
4709
 
4710
void
4711
override_options (void)
4712
{
4713
  int i, start, regno;
4714
  enum machine_mode mode;
4715
 
4716
  mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4717
 
4718
  /* The following code determines the architecture and register size.
4719
     Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4720
     The GAS and GCC code should be kept in sync as much as possible.  */
4721
 
4722
  if (mips_arch_string != 0)
4723
    mips_set_architecture (mips_parse_cpu (mips_arch_string));
4724
 
4725
  if (mips_isa_info != 0)
4726
    {
4727
      if (mips_arch_info == 0)
4728
        mips_set_architecture (mips_isa_info);
4729
      else if (mips_arch_info->isa != mips_isa_info->isa)
4730
        error ("-%s conflicts with the other architecture options, "
4731
               "which specify a %s processor",
4732
               mips_isa_info->name,
4733
               mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4734
    }
4735
 
4736
  if (mips_arch_info == 0)
4737
    {
4738
#ifdef MIPS_CPU_STRING_DEFAULT
4739
      mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4740
#else
4741
      mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4742
#endif
4743
    }
4744
 
4745
  if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4746
    error ("-march=%s is not compatible with the selected ABI",
4747
           mips_arch_info->name);
4748
 
4749
  /* Optimize for mips_arch, unless -mtune selects a different processor.  */
4750
  if (mips_tune_string != 0)
4751
    mips_set_tune (mips_parse_cpu (mips_tune_string));
4752
 
4753
  if (mips_tune_info == 0)
4754
    mips_set_tune (mips_arch_info);
4755
 
4756
  /* Set cost structure for the processor.  */
4757
  mips_cost = &mips_rtx_cost_data[mips_tune];
4758
 
4759
  if ((target_flags_explicit & MASK_64BIT) != 0)
4760
    {
4761
      /* The user specified the size of the integer registers.  Make sure
4762
         it agrees with the ABI and ISA.  */
4763
      if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4764
        error ("-mgp64 used with a 32-bit processor");
4765
      else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4766
        error ("-mgp32 used with a 64-bit ABI");
4767
      else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4768
        error ("-mgp64 used with a 32-bit ABI");
4769
    }
4770
  else
4771
    {
4772
      /* Infer the integer register size from the ABI and processor.
4773
         Restrict ourselves to 32-bit registers if that's all the
4774
         processor has, or if the ABI cannot handle 64-bit registers.  */
4775
      if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4776
        target_flags &= ~MASK_64BIT;
4777
      else
4778
        target_flags |= MASK_64BIT;
4779
    }
4780
 
4781
  if ((target_flags_explicit & MASK_FLOAT64) != 0)
4782
    {
4783
      /* Really, -mfp32 and -mfp64 are ornamental options.  There's
4784
         only one right answer here.  */
4785
      if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4786
        error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4787
      else if (!TARGET_64BIT && TARGET_FLOAT64)
4788
        error ("unsupported combination: %s", "-mgp32 -mfp64");
4789
      else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4790
        error ("unsupported combination: %s", "-mfp64 -msingle-float");
4791
    }
4792
  else
4793
    {
4794
      /* -msingle-float selects 32-bit float registers.  Otherwise the
4795
         float registers should be the same size as the integer ones.  */
4796
      if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4797
        target_flags |= MASK_FLOAT64;
4798
      else
4799
        target_flags &= ~MASK_FLOAT64;
4800
    }
4801
 
4802
  /* End of code shared with GAS.  */
4803
 
4804
  if ((target_flags_explicit & MASK_LONG64) == 0)
4805
    {
4806
      if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4807
        target_flags |= MASK_LONG64;
4808
      else
4809
        target_flags &= ~MASK_LONG64;
4810
    }
4811
 
4812
  if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4813
      && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4814
    {
4815
      /* For some configurations, it is useful to have -march control
4816
         the default setting of MASK_SOFT_FLOAT.  */
4817
      switch ((int) mips_arch)
4818
        {
4819
        case PROCESSOR_R4100:
4820
        case PROCESSOR_R4111:
4821
        case PROCESSOR_R4120:
4822
        case PROCESSOR_R4130:
4823
          target_flags |= MASK_SOFT_FLOAT;
4824
          break;
4825
 
4826
        default:
4827
          target_flags &= ~MASK_SOFT_FLOAT;
4828
          break;
4829
        }
4830
    }
4831
 
4832
  if (!TARGET_OLDABI)
4833
    flag_pcc_struct_return = 0;
4834
 
4835
  if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4836
    {
4837
      /* If neither -mbranch-likely nor -mno-branch-likely was given
4838
         on the command line, set MASK_BRANCHLIKELY based on the target
4839
         architecture.
4840
 
4841
         By default, we enable use of Branch Likely instructions on
4842
         all architectures which support them with the following
4843
         exceptions: when creating MIPS32 or MIPS64 code, and when
4844
         tuning for architectures where their use tends to hurt
4845
         performance.
4846
 
4847
         The MIPS32 and MIPS64 architecture specifications say "Software
4848
         is strongly encouraged to avoid use of Branch Likely
4849
         instructions, as they will be removed from a future revision
4850
         of the [MIPS32 and MIPS64] architecture."  Therefore, we do not
4851
         issue those instructions unless instructed to do so by
4852
         -mbranch-likely.  */
4853
      if (ISA_HAS_BRANCHLIKELY
4854
          && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4855
          && !(TUNE_MIPS5500 || TUNE_SB1))
4856
        target_flags |= MASK_BRANCHLIKELY;
4857
      else
4858
        target_flags &= ~MASK_BRANCHLIKELY;
4859
    }
4860
  if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4861
    warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4862
 
4863
  /* The effect of -mabicalls isn't defined for the EABI.  */
4864
  if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4865
    {
4866
      error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4867
      target_flags &= ~MASK_ABICALLS;
4868
    }
4869
 
4870
  if (TARGET_ABICALLS)
4871
    {
4872
      /* We need to set flag_pic for executables as well as DSOs
4873
         because we may reference symbols that are not defined in
4874
         the final executable.  (MIPS does not use things like
4875
         copy relocs, for example.)
4876
 
4877
         Also, there is a body of code that uses __PIC__ to distinguish
4878
         between -mabicalls and -mno-abicalls code.  */
4879
      flag_pic = 1;
4880
      if (mips_section_threshold > 0)
4881
        warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
4882
    }
4883
 
4884
  /* mips_split_addresses is a half-way house between explicit
4885
     relocations and the traditional assembler macros.  It can
4886
     split absolute 32-bit symbolic constants into a high/lo_sum
4887
     pair but uses macros for other sorts of access.
4888
 
4889
     Like explicit relocation support for REL targets, it relies
4890
     on GNU extensions in the assembler and the linker.
4891
 
4892
     Although this code should work for -O0, it has traditionally
4893
     been treated as an optimization.  */
4894
  if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4895
      && optimize && !flag_pic
4896
      && !ABI_HAS_64BIT_SYMBOLS)
4897
    mips_split_addresses = 1;
4898
  else
4899
    mips_split_addresses = 0;
4900
 
4901
  /* -mvr4130-align is a "speed over size" optimization: it usually produces
4902
     faster code, but at the expense of more nops.  Enable it at -O3 and
4903
     above.  */
4904
  if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4905
    target_flags |= MASK_VR4130_ALIGN;
4906
 
4907
  /* When compiling for the mips16, we cannot use floating point.  We
4908
     record the original hard float value in mips16_hard_float.  */
4909
  if (TARGET_MIPS16)
4910
    {
4911
      if (TARGET_SOFT_FLOAT)
4912
        mips16_hard_float = 0;
4913
      else
4914
        mips16_hard_float = 1;
4915
      target_flags |= MASK_SOFT_FLOAT;
4916
 
4917
      /* Don't run the scheduler before reload, since it tends to
4918
         increase register pressure.  */
4919
      flag_schedule_insns = 0;
4920
 
4921
      /* Don't do hot/cold partitioning.  The constant layout code expects
4922
         the whole function to be in a single section.  */
4923
      flag_reorder_blocks_and_partition = 0;
4924
 
4925
      /* Silently disable -mexplicit-relocs since it doesn't apply
4926
         to mips16 code.  Even so, it would overly pedantic to warn
4927
         about "-mips16 -mexplicit-relocs", especially given that
4928
         we use a %gprel() operator.  */
4929
      target_flags &= ~MASK_EXPLICIT_RELOCS;
4930
    }
4931
 
4932
  /* When using explicit relocs, we call dbr_schedule from within
4933
     mips_reorg.  */
4934
  if (TARGET_EXPLICIT_RELOCS)
4935
    {
4936
      mips_flag_delayed_branch = flag_delayed_branch;
4937
      flag_delayed_branch = 0;
4938
    }
4939
 
4940
#ifdef MIPS_TFMODE_FORMAT
4941
  REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4942
#endif
4943
 
4944
  /* Make sure that the user didn't turn off paired single support when
4945
     MIPS-3D support is requested.  */
4946
  if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4947
      && !TARGET_PAIRED_SINGLE_FLOAT)
4948
    error ("-mips3d requires -mpaired-single");
4949
 
4950
  /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT.  */
4951
  if (TARGET_MIPS3D)
4952
    target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4953
 
4954
  /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4955
     and TARGET_HARD_FLOAT are both true.  */
4956
  if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4957
    error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4958
 
4959
  /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4960
     enabled.  */
4961
  if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4962
    error ("-mips3d/-mpaired-single must be used with -mips64");
4963
 
4964
  if (TARGET_MIPS16 && TARGET_DSP)
4965
    error ("-mips16 and -mdsp cannot be used together");
4966
 
4967
  mips_print_operand_punct['?'] = 1;
4968
  mips_print_operand_punct['#'] = 1;
4969
  mips_print_operand_punct['/'] = 1;
4970
  mips_print_operand_punct['&'] = 1;
4971
  mips_print_operand_punct['!'] = 1;
4972
  mips_print_operand_punct['*'] = 1;
4973
  mips_print_operand_punct['@'] = 1;
4974
  mips_print_operand_punct['.'] = 1;
4975
  mips_print_operand_punct['('] = 1;
4976
  mips_print_operand_punct[')'] = 1;
4977
  mips_print_operand_punct['['] = 1;
4978
  mips_print_operand_punct[']'] = 1;
4979
  mips_print_operand_punct['<'] = 1;
4980
  mips_print_operand_punct['>'] = 1;
4981
  mips_print_operand_punct['{'] = 1;
4982
  mips_print_operand_punct['}'] = 1;
4983
  mips_print_operand_punct['^'] = 1;
4984
  mips_print_operand_punct['$'] = 1;
4985
  mips_print_operand_punct['+'] = 1;
4986
  mips_print_operand_punct['~'] = 1;
4987
 
4988
  /* Set up array to map GCC register number to debug register number.
4989
     Ignore the special purpose register numbers.  */
4990
 
4991
  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4992
    mips_dbx_regno[i] = -1;
4993
 
4994
  start = GP_DBX_FIRST - GP_REG_FIRST;
4995
  for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4996
    mips_dbx_regno[i] = i + start;
4997
 
4998
  start = FP_DBX_FIRST - FP_REG_FIRST;
4999
  for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5000
    mips_dbx_regno[i] = i + start;
5001
 
5002
  mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
5003
  mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
5004
 
5005
  /* Set up array giving whether a given register can hold a given mode.  */
5006
 
5007
  for (mode = VOIDmode;
5008
       mode != MAX_MACHINE_MODE;
5009
       mode = (enum machine_mode) ((int)mode + 1))
5010
    {
5011
      register int size              = GET_MODE_SIZE (mode);
5012
      register enum mode_class class = GET_MODE_CLASS (mode);
5013
 
5014
      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5015
        {
5016
          register int temp;
5017
 
5018
          if (mode == CCV2mode)
5019
            temp = (ISA_HAS_8CC
5020
                    && ST_REG_P (regno)
5021
                    && (regno - ST_REG_FIRST) % 2 == 0);
5022
 
5023
          else if (mode == CCV4mode)
5024
            temp = (ISA_HAS_8CC
5025
                    && ST_REG_P (regno)
5026
                    && (regno - ST_REG_FIRST) % 4 == 0);
5027
 
5028
          else if (mode == CCmode)
5029
            {
5030
              if (! ISA_HAS_8CC)
5031
                temp = (regno == FPSW_REGNUM);
5032
              else
5033
                temp = (ST_REG_P (regno) || GP_REG_P (regno)
5034
                        || FP_REG_P (regno));
5035
            }
5036
 
5037
          else if (GP_REG_P (regno))
5038
            temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5039
 
5040
          else if (FP_REG_P (regno))
5041
            temp = ((regno % FP_INC) == 0)
5042
                    && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5043
                          || class == MODE_VECTOR_FLOAT)
5044
                         && size <= UNITS_PER_FPVALUE)
5045
                        /* Allow integer modes that fit into a single
5046
                           register.  We need to put integers into FPRs
5047
                           when using instructions like cvt and trunc.
5048
                           We can't allow sizes smaller than a word,
5049
                           the FPU has no appropriate load/store
5050
                           instructions for those.  */
5051
                        || (class == MODE_INT
5052
                            && size >= MIN_UNITS_PER_WORD
5053
                            && size <= UNITS_PER_FPREG)
5054
                        /* Allow TFmode for CCmode reloads.  */
5055
                        || (ISA_HAS_8CC && mode == TFmode));
5056
 
5057
          else if (ACC_REG_P (regno))
5058
            temp = (INTEGRAL_MODE_P (mode)
5059
                    && (size <= UNITS_PER_WORD
5060
                        || (ACC_HI_REG_P (regno)
5061
                            && size == 2 * UNITS_PER_WORD)));
5062
 
5063
          else if (ALL_COP_REG_P (regno))
5064
            temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5065
          else
5066
            temp = 0;
5067
 
5068
          mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5069
        }
5070
    }
5071
 
5072
  /* Save GPR registers in word_mode sized hunks.  word_mode hasn't been
5073
     initialized yet, so we can't use that here.  */
5074
  gpr_mode = TARGET_64BIT ? DImode : SImode;
5075
 
5076
  /* Provide default values for align_* for 64-bit targets.  */
5077
  if (TARGET_64BIT && !TARGET_MIPS16)
5078
    {
5079
      if (align_loops == 0)
5080
        align_loops = 8;
5081
      if (align_jumps == 0)
5082
        align_jumps = 8;
5083
      if (align_functions == 0)
5084
        align_functions = 8;
5085
    }
5086
 
5087
  /* Function to allocate machine-dependent function status.  */
5088
  init_machine_status = &mips_init_machine_status;
5089
 
5090
  if (ABI_HAS_64BIT_SYMBOLS)
5091
    {
5092
      if (TARGET_EXPLICIT_RELOCS)
5093
        {
5094
          mips_split_p[SYMBOL_64_HIGH] = true;
5095
          mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5096
          mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5097
 
5098
          mips_split_p[SYMBOL_64_MID] = true;
5099
          mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5100
          mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5101
 
5102
          mips_split_p[SYMBOL_64_LOW] = true;
5103
          mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5104
          mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5105
 
5106
          mips_split_p[SYMBOL_GENERAL] = true;
5107
          mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5108
        }
5109
    }
5110
  else
5111
    {
5112
      if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5113
        {
5114
          mips_split_p[SYMBOL_GENERAL] = true;
5115
          mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5116
          mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5117
        }
5118
    }
5119
 
5120
  if (TARGET_MIPS16)
5121
    {
5122
      /* The high part is provided by a pseudo copy of $gp.  */
5123
      mips_split_p[SYMBOL_SMALL_DATA] = true;
5124
      mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5125
    }
5126
 
5127
  if (TARGET_EXPLICIT_RELOCS)
5128
    {
5129
      /* Small data constants are kept whole until after reload,
5130
         then lowered by mips_rewrite_small_data.  */
5131
      mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5132
 
5133
      mips_split_p[SYMBOL_GOT_LOCAL] = true;
5134
      if (TARGET_NEWABI)
5135
        {
5136
          mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5137
          mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5138
        }
5139
      else
5140
        {
5141
          mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5142
          mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5143
        }
5144
 
5145
      if (TARGET_XGOT)
5146
        {
5147
          /* The HIGH and LO_SUM are matched by special .md patterns.  */
5148
          mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5149
 
5150
          mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5151
          mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5152
          mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5153
 
5154
          mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5155
          mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5156
          mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5157
        }
5158
      else
5159
        {
5160
          if (TARGET_NEWABI)
5161
            mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5162
          else
5163
            mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5164
          mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5165
        }
5166
    }
5167
 
5168
  if (TARGET_NEWABI)
5169
    {
5170
      mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5171
      mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5172
      mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5173
    }
5174
 
5175
  /* Thread-local relocation operators.  */
5176
  mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5177
  mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5178
  mips_split_p[SYMBOL_DTPREL] = 1;
5179
  mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5180
  mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5181
  mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5182
  mips_split_p[SYMBOL_TPREL] = 1;
5183
  mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5184
  mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5185
 
5186
  /* We don't have a thread pointer access instruction on MIPS16, or
5187
     appropriate TLS relocations.  */
5188
  if (TARGET_MIPS16)
5189
    targetm.have_tls = false;
5190
 
5191
  /* Default to working around R4000 errata only if the processor
5192
     was selected explicitly.  */
5193
  if ((target_flags_explicit & MASK_FIX_R4000) == 0
5194
      && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5195
    target_flags |= MASK_FIX_R4000;
5196
 
5197
  /* Default to working around R4400 errata only if the processor
5198
     was selected explicitly.  */
5199
  if ((target_flags_explicit & MASK_FIX_R4400) == 0
5200
      && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5201
    target_flags |= MASK_FIX_R4400;
5202
}
5203
 
5204
/* Implement CONDITIONAL_REGISTER_USAGE.  */
5205
 
5206
void
5207
mips_conditional_register_usage (void)
5208
{
5209
  if (!TARGET_DSP)
5210
    {
5211
      int regno;
5212
 
5213
      for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5214
        fixed_regs[regno] = call_used_regs[regno] = 1;
5215
    }
5216
  if (!TARGET_HARD_FLOAT)
5217
    {
5218
      int regno;
5219
 
5220
      for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5221
        fixed_regs[regno] = call_used_regs[regno] = 1;
5222
      for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5223
        fixed_regs[regno] = call_used_regs[regno] = 1;
5224
    }
5225
  else if (! ISA_HAS_8CC)
5226
    {
5227
      int regno;
5228
 
5229
      /* We only have a single condition code register.  We
5230
         implement this by hiding all the condition code registers,
5231
         and generating RTL that refers directly to ST_REG_FIRST.  */
5232
      for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5233
        fixed_regs[regno] = call_used_regs[regno] = 1;
5234
    }
5235
  /* In mips16 mode, we permit the $t temporary registers to be used
5236
     for reload.  We prohibit the unused $s registers, since they
5237
     are caller saved, and saving them via a mips16 register would
5238
     probably waste more time than just reloading the value.  */
5239
  if (TARGET_MIPS16)
5240
    {
5241
      fixed_regs[18] = call_used_regs[18] = 1;
5242
      fixed_regs[19] = call_used_regs[19] = 1;
5243
      fixed_regs[20] = call_used_regs[20] = 1;
5244
      fixed_regs[21] = call_used_regs[21] = 1;
5245
      fixed_regs[22] = call_used_regs[22] = 1;
5246
      fixed_regs[23] = call_used_regs[23] = 1;
5247
      fixed_regs[26] = call_used_regs[26] = 1;
5248
      fixed_regs[27] = call_used_regs[27] = 1;
5249
      fixed_regs[30] = call_used_regs[30] = 1;
5250
    }
5251
  /* fp20-23 are now caller saved.  */
5252
  if (mips_abi == ABI_64)
5253
    {
5254
      int regno;
5255
      for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5256
        call_really_used_regs[regno] = call_used_regs[regno] = 1;
5257
    }
5258
  /* Odd registers from fp21 to fp31 are now caller saved.  */
5259
  if (mips_abi == ABI_N32)
5260
    {
5261
      int regno;
5262
      for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5263
        call_really_used_regs[regno] = call_used_regs[regno] = 1;
5264
    }
5265
}
5266
 
5267
/* Allocate a chunk of memory for per-function machine-dependent data.  */
5268
static struct machine_function *
5269
mips_init_machine_status (void)
5270
{
5271
  return ((struct machine_function *)
5272
          ggc_alloc_cleared (sizeof (struct machine_function)));
5273
}
5274
 
5275
/* On the mips16, we want to allocate $24 (T_REG) before other
5276
   registers for instructions for which it is possible.  This helps
5277
   avoid shuffling registers around in order to set up for an xor,
5278
   encouraging the compiler to use a cmp instead.  */
5279
 
5280
void
5281
mips_order_regs_for_local_alloc (void)
5282
{
5283
  register int i;
5284
 
5285
  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5286
    reg_alloc_order[i] = i;
5287
 
5288
  if (TARGET_MIPS16)
5289
    {
5290
      /* It really doesn't matter where we put register 0, since it is
5291
         a fixed register anyhow.  */
5292
      reg_alloc_order[0] = 24;
5293
      reg_alloc_order[24] = 0;
5294
    }
5295
}
5296
 
5297
 
5298
/* The MIPS debug format wants all automatic variables and arguments
5299
   to be in terms of the virtual frame pointer (stack pointer before
5300
   any adjustment in the function), while the MIPS 3.0 linker wants
5301
   the frame pointer to be the stack pointer after the initial
5302
   adjustment.  So, we do the adjustment here.  The arg pointer (which
5303
   is eliminated) points to the virtual frame pointer, while the frame
5304
   pointer (which may be eliminated) points to the stack pointer after
5305
   the initial adjustments.  */
5306
 
5307
HOST_WIDE_INT
5308
mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5309
{
5310
  rtx offset2 = const0_rtx;
5311
  rtx reg = eliminate_constant_term (addr, &offset2);
5312
 
5313
  if (offset == 0)
5314
    offset = INTVAL (offset2);
5315
 
5316
  if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5317
      || reg == hard_frame_pointer_rtx)
5318
    {
5319
      HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5320
                                  ? compute_frame_size (get_frame_size ())
5321
                                  : cfun->machine->frame.total_size;
5322
 
5323
      /* MIPS16 frame is smaller */
5324
      if (frame_pointer_needed && TARGET_MIPS16)
5325
        frame_size -= cfun->machine->frame.args_size;
5326
 
5327
      offset = offset - frame_size;
5328
    }
5329
 
5330
  /* sdbout_parms does not want this to crash for unrecognized cases.  */
5331
#if 0
5332
  else if (reg != arg_pointer_rtx)
5333
    fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5334
                addr);
5335
#endif
5336
 
5337
  return offset;
5338
}
5339
 
5340
/* Implement the PRINT_OPERAND macro.  The MIPS-specific operand codes are:
5341
 
5342
   'X'  OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5343
   'x'  OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5344
   'h'  OP is HIGH, prints %hi(X),
5345
   'd'  output integer constant in decimal,
5346
   'z'  if the operand is 0, use $0 instead of normal operand.
5347
   'D'  print second part of double-word register or memory operand.
5348
   'L'  print low-order register of double-word register operand.
5349
   'M'  print high-order register of double-word register operand.
5350
   'C'  print part of opcode for a branch condition.
5351
   'F'  print part of opcode for a floating-point branch condition.
5352
   'N'  print part of opcode for a branch condition, inverted.
5353
   'W'  print part of opcode for a floating-point branch condition, inverted.
5354
   'T'  print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5355
              'z' for (eq:?I ...), 'n' for (ne:?I ...).
5356
   't'  like 'T', but with the EQ/NE cases reversed
5357
   'Y'  for a CONST_INT X, print mips_fp_conditions[X]
5358
   'Z'  print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5359
   'R'  print the reloc associated with LO_SUM
5360
   'q'  print DSP accumulator registers
5361
 
5362
   The punctuation characters are:
5363
 
5364
   '('  Turn on .set noreorder
5365
   ')'  Turn on .set reorder
5366
   '['  Turn on .set noat
5367
   ']'  Turn on .set at
5368
   '<'  Turn on .set nomacro
5369
   '>'  Turn on .set macro
5370
   '{'  Turn on .set volatile (not GAS)
5371
   '}'  Turn on .set novolatile (not GAS)
5372
   '&'  Turn on .set noreorder if filling delay slots
5373
   '*'  Turn on both .set noreorder and .set nomacro if filling delay slots
5374
   '!'  Turn on .set nomacro if filling delay slots
5375
   '#'  Print nop if in a .set noreorder section.
5376
   '/'  Like '#', but does nothing within a delayed branch sequence
5377
   '?'  Print 'l' if we are to use a branch likely instead of normal branch.
5378
   '@'  Print the name of the assembler temporary register (at or $1).
5379
   '.'  Print the name of the register with a hard-wired zero (zero or $0).
5380
   '^'  Print the name of the pic call-through register (t9 or $25).
5381
   '$'  Print the name of the stack pointer register (sp or $29).
5382
   '+'  Print the name of the gp register (usually gp or $28).
5383
   '~'  Output a branch alignment to LABEL_ALIGN(NULL).  */
5384
 
5385
void
5386
print_operand (FILE *file, rtx op, int letter)
5387
{
5388
  register enum rtx_code code;
5389
 
5390
  if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5391
    {
5392
      switch (letter)
5393
        {
5394
        case '?':
5395
          if (mips_branch_likely)
5396
            putc ('l', file);
5397
          break;
5398
 
5399
        case '@':
5400
          fputs (reg_names [GP_REG_FIRST + 1], file);
5401
          break;
5402
 
5403
        case '^':
5404
          fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5405
          break;
5406
 
5407
        case '.':
5408
          fputs (reg_names [GP_REG_FIRST + 0], file);
5409
          break;
5410
 
5411
        case '$':
5412
          fputs (reg_names[STACK_POINTER_REGNUM], file);
5413
          break;
5414
 
5415
        case '+':
5416
          fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5417
          break;
5418
 
5419
        case '&':
5420
          if (final_sequence != 0 && set_noreorder++ == 0)
5421
            fputs (".set\tnoreorder\n\t", file);
5422
          break;
5423
 
5424
        case '*':
5425
          if (final_sequence != 0)
5426
            {
5427
              if (set_noreorder++ == 0)
5428
                fputs (".set\tnoreorder\n\t", file);
5429
 
5430
              if (set_nomacro++ == 0)
5431
                fputs (".set\tnomacro\n\t", file);
5432
            }
5433
          break;
5434
 
5435
        case '!':
5436
          if (final_sequence != 0 && set_nomacro++ == 0)
5437
            fputs ("\n\t.set\tnomacro", file);
5438
          break;
5439
 
5440
        case '#':
5441
          if (set_noreorder != 0)
5442
            fputs ("\n\tnop", file);
5443
          break;
5444
 
5445
        case '/':
5446
          /* Print an extra newline so that the delayed insn is separated
5447
             from the following ones.  This looks neater and is consistent
5448
             with non-nop delayed sequences.  */
5449
          if (set_noreorder != 0 && final_sequence == 0)
5450
            fputs ("\n\tnop\n", file);
5451
          break;
5452
 
5453
        case '(':
5454
          if (set_noreorder++ == 0)
5455
            fputs (".set\tnoreorder\n\t", file);
5456
          break;
5457
 
5458
        case ')':
5459
          if (set_noreorder == 0)
5460
            error ("internal error: %%) found without a %%( in assembler pattern");
5461
 
5462
          else if (--set_noreorder == 0)
5463
            fputs ("\n\t.set\treorder", file);
5464
 
5465
          break;
5466
 
5467
        case '[':
5468
          if (set_noat++ == 0)
5469
            fputs (".set\tnoat\n\t", file);
5470
          break;
5471
 
5472
        case ']':
5473
          if (set_noat == 0)
5474
            error ("internal error: %%] found without a %%[ in assembler pattern");
5475
          else if (--set_noat == 0)
5476
            fputs ("\n\t.set\tat", file);
5477
 
5478
          break;
5479
 
5480
        case '<':
5481
          if (set_nomacro++ == 0)
5482
            fputs (".set\tnomacro\n\t", file);
5483
          break;
5484
 
5485
        case '>':
5486
          if (set_nomacro == 0)
5487
            error ("internal error: %%> found without a %%< in assembler pattern");
5488
          else if (--set_nomacro == 0)
5489
            fputs ("\n\t.set\tmacro", file);
5490
 
5491
          break;
5492
 
5493
        case '{':
5494
          if (set_volatile++ == 0)
5495
            fputs ("#.set\tvolatile\n\t", file);
5496
          break;
5497
 
5498
        case '}':
5499
          if (set_volatile == 0)
5500
            error ("internal error: %%} found without a %%{ in assembler pattern");
5501
          else if (--set_volatile == 0)
5502
            fputs ("\n\t#.set\tnovolatile", file);
5503
 
5504
          break;
5505
 
5506
        case '~':
5507
          {
5508
            if (align_labels_log > 0)
5509
              ASM_OUTPUT_ALIGN (file, align_labels_log);
5510
          }
5511
          break;
5512
 
5513
        default:
5514
          error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5515
          break;
5516
        }
5517
 
5518
      return;
5519
    }
5520
 
5521
  if (! op)
5522
    {
5523
      error ("PRINT_OPERAND null pointer");
5524
      return;
5525
    }
5526
 
5527
  code = GET_CODE (op);
5528
 
5529
  if (letter == 'C')
5530
    switch (code)
5531
      {
5532
      case EQ:  fputs ("eq",  file); break;
5533
      case NE:  fputs ("ne",  file); break;
5534
      case GT:  fputs ("gt",  file); break;
5535
      case GE:  fputs ("ge",  file); break;
5536
      case LT:  fputs ("lt",  file); break;
5537
      case LE:  fputs ("le",  file); break;
5538
      case GTU: fputs ("gtu", file); break;
5539
      case GEU: fputs ("geu", file); break;
5540
      case LTU: fputs ("ltu", file); break;
5541
      case LEU: fputs ("leu", file); break;
5542
      default:
5543
        fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5544
      }
5545
 
5546
  else if (letter == 'N')
5547
    switch (code)
5548
      {
5549
      case EQ:  fputs ("ne",  file); break;
5550
      case NE:  fputs ("eq",  file); break;
5551
      case GT:  fputs ("le",  file); break;
5552
      case GE:  fputs ("lt",  file); break;
5553
      case LT:  fputs ("ge",  file); break;
5554
      case LE:  fputs ("gt",  file); break;
5555
      case GTU: fputs ("leu", file); break;
5556
      case GEU: fputs ("ltu", file); break;
5557
      case LTU: fputs ("geu", file); break;
5558
      case LEU: fputs ("gtu", file); break;
5559
      default:
5560
        fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5561
      }
5562
 
5563
  else if (letter == 'F')
5564
    switch (code)
5565
      {
5566
      case EQ: fputs ("c1f", file); break;
5567
      case NE: fputs ("c1t", file); break;
5568
      default:
5569
        fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5570
      }
5571
 
5572
  else if (letter == 'W')
5573
    switch (code)
5574
      {
5575
      case EQ: fputs ("c1t", file); break;
5576
      case NE: fputs ("c1f", file); break;
5577
      default:
5578
        fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5579
      }
5580
 
5581
  else if (letter == 'h')
5582
    {
5583
      if (GET_CODE (op) == HIGH)
5584
        op = XEXP (op, 0);
5585
 
5586
      print_operand_reloc (file, op, mips_hi_relocs);
5587
    }
5588
 
5589
  else if (letter == 'R')
5590
    print_operand_reloc (file, op, mips_lo_relocs);
5591
 
5592
  else if (letter == 'Y')
5593
    {
5594
      if (GET_CODE (op) == CONST_INT
5595
          && ((unsigned HOST_WIDE_INT) INTVAL (op)
5596
              < ARRAY_SIZE (mips_fp_conditions)))
5597
        fputs (mips_fp_conditions[INTVAL (op)], file);
5598
      else
5599
        output_operand_lossage ("invalid %%Y value");
5600
    }
5601
 
5602
  else if (letter == 'Z')
5603
    {
5604
      if (ISA_HAS_8CC)
5605
        {
5606
          print_operand (file, op, 0);
5607
          fputc (',', file);
5608
        }
5609
    }
5610
 
5611
  else if (letter == 'q')
5612
    {
5613
      int regnum;
5614
 
5615
      if (code != REG)
5616
        fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5617
 
5618
      regnum = REGNO (op);
5619
      if (MD_REG_P (regnum))
5620
        fprintf (file, "$ac0");
5621
      else if (DSP_ACC_REG_P (regnum))
5622
        fprintf (file, "$ac%c", reg_names[regnum][3]);
5623
      else
5624
        fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5625
    }
5626
 
5627
  else if (code == REG || code == SUBREG)
5628
    {
5629
      register int regnum;
5630
 
5631
      if (code == REG)
5632
        regnum = REGNO (op);
5633
      else
5634
        regnum = true_regnum (op);
5635
 
5636
      if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5637
          || (letter == 'L' && WORDS_BIG_ENDIAN)
5638
          || letter == 'D')
5639
        regnum++;
5640
 
5641
      fprintf (file, "%s", reg_names[regnum]);
5642
    }
5643
 
5644
  else if (code == MEM)
5645
    {
5646
      if (letter == 'D')
5647
        output_address (plus_constant (XEXP (op, 0), 4));
5648
      else
5649
        output_address (XEXP (op, 0));
5650
    }
5651
 
5652
  else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5653
    fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5654
 
5655
  else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5656
    fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5657
 
5658
  else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5659
    fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5660
 
5661
  else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5662
    fputs (reg_names[GP_REG_FIRST], file);
5663
 
5664
  else if (letter == 'd' || letter == 'x' || letter == 'X')
5665
    output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5666
 
5667
  else if (letter == 'T' || letter == 't')
5668
    {
5669
      int truth = (code == NE) == (letter == 'T');
5670
      fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5671
    }
5672
 
5673
  else if (CONST_GP_P (op))
5674
    fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5675
 
5676
  else
5677
    output_addr_const (file, op);
5678
}
5679
 
5680
 
5681
/* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5682
   RELOCS is the array of relocations to use.  */
5683
 
5684
static void
5685
print_operand_reloc (FILE *file, rtx op, const char **relocs)
5686
{
5687
  enum mips_symbol_type symbol_type;
5688
  const char *p;
5689
  rtx base;
5690
  HOST_WIDE_INT offset;
5691
 
5692
  symbol_type = mips_classify_symbolic_expression (op);
5693
  if (relocs[symbol_type] == 0)
5694
    fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5695
 
5696
  /* If OP uses an UNSPEC address, we want to print the inner symbol.  */
5697
  mips_split_const (op, &base, &offset);
5698
  if (UNSPEC_ADDRESS_P (base))
5699
    op = plus_constant (UNSPEC_ADDRESS (base), offset);
5700
 
5701
  fputs (relocs[symbol_type], file);
5702
  output_addr_const (file, op);
5703
  for (p = relocs[symbol_type]; *p != 0; p++)
5704
    if (*p == '(')
5705
      fputc (')', file);
5706
}
5707
 
5708
/* Output address operand X to FILE.  */
5709
 
5710
void
5711
print_operand_address (FILE *file, rtx x)
5712
{
5713
  struct mips_address_info addr;
5714
 
5715
  if (mips_classify_address (&addr, x, word_mode, true))
5716
    switch (addr.type)
5717
      {
5718
      case ADDRESS_REG:
5719
        print_operand (file, addr.offset, 0);
5720
        fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5721
        return;
5722
 
5723
      case ADDRESS_LO_SUM:
5724
        print_operand (file, addr.offset, 'R');
5725
        fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5726
        return;
5727
 
5728
      case ADDRESS_CONST_INT:
5729
        output_addr_const (file, x);
5730
        fprintf (file, "(%s)", reg_names[0]);
5731
        return;
5732
 
5733
      case ADDRESS_SYMBOLIC:
5734
        output_addr_const (file, x);
5735
        return;
5736
      }
5737
  gcc_unreachable ();
5738
}
5739
 
5740
/* When using assembler macros, keep track of all of small-data externs
5741
   so that mips_file_end can emit the appropriate declarations for them.
5742
 
5743
   In most cases it would be safe (though pointless) to emit .externs
5744
   for other symbols too.  One exception is when an object is within
5745
   the -G limit but declared by the user to be in a section other
5746
   than .sbss or .sdata.  */
5747
 
5748
int
5749
mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5750
{
5751
  register struct extern_list *p;
5752
 
5753
  if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5754
    {
5755
      p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5756
      p->next = extern_head;
5757
      p->name = name;
5758
      p->size = int_size_in_bytes (TREE_TYPE (decl));
5759
      extern_head = p;
5760
    }
5761
 
5762
  if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5763
    {
5764
      p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5765
      p->next = extern_head;
5766
      p->name = name;
5767
      p->size = -1;
5768
      extern_head = p;
5769
    }
5770
 
5771
  return 0;
5772
}
5773
 
5774
#if TARGET_IRIX
5775
static void
5776
irix_output_external_libcall (rtx fun)
5777
{
5778
  register struct extern_list *p;
5779
 
5780
  if (mips_abi == ABI_32)
5781
    {
5782
      p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5783
      p->next = extern_head;
5784
      p->name = XSTR (fun, 0);
5785
      p->size = -1;
5786
      extern_head = p;
5787
    }
5788
}
5789
#endif
5790
 
5791
/* Emit a new filename to a stream.  If we are smuggling stabs, try to
5792
   put out a MIPS ECOFF file and a stab.  */
5793
 
5794
void
5795
mips_output_filename (FILE *stream, const char *name)
5796
{
5797
 
5798
  /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5799
     directives.  */
5800
  if (write_symbols == DWARF2_DEBUG)
5801
    return;
5802
  else if (mips_output_filename_first_time)
5803
    {
5804
      mips_output_filename_first_time = 0;
5805
      num_source_filenames += 1;
5806
      current_function_file = name;
5807
      fprintf (stream, "\t.file\t%d ", num_source_filenames);
5808
      output_quoted_string (stream, name);
5809
      putc ('\n', stream);
5810
    }
5811
 
5812
  /* If we are emitting stabs, let dbxout.c handle this (except for
5813
     the mips_output_filename_first_time case).  */
5814
  else if (write_symbols == DBX_DEBUG)
5815
    return;
5816
 
5817
  else if (name != current_function_file
5818
           && strcmp (name, current_function_file) != 0)
5819
    {
5820
      num_source_filenames += 1;
5821
      current_function_file = name;
5822
      fprintf (stream, "\t.file\t%d ", num_source_filenames);
5823
      output_quoted_string (stream, name);
5824
      putc ('\n', stream);
5825
    }
5826
}
5827
 
5828
/* Output an ASCII string, in a space-saving way.  PREFIX is the string
5829
   that should be written before the opening quote, such as "\t.ascii\t"
5830
   for real string data or "\t# " for a comment.  */
5831
 
5832
void
5833
mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5834
                   const char *prefix)
5835
{
5836
  size_t i;
5837
  int cur_pos = 17;
5838
  register const unsigned char *string =
5839
    (const unsigned char *)string_param;
5840
 
5841
  fprintf (stream, "%s\"", prefix);
5842
  for (i = 0; i < len; i++)
5843
    {
5844
      register int c = string[i];
5845
 
5846
      if (ISPRINT (c))
5847
        {
5848
          if (c == '\\' || c == '\"')
5849
            {
5850
              putc ('\\', stream);
5851
              cur_pos++;
5852
            }
5853
          putc (c, stream);
5854
          cur_pos++;
5855
        }
5856
      else
5857
        {
5858
          fprintf (stream, "\\%03o", c);
5859
          cur_pos += 4;
5860
        }
5861
 
5862
      if (cur_pos > 72 && i+1 < len)
5863
        {
5864
          cur_pos = 17;
5865
          fprintf (stream, "\"\n%s\"", prefix);
5866
        }
5867
    }
5868
  fprintf (stream, "\"\n");
5869
}
5870
 
5871
/* Implement TARGET_ASM_FILE_START.  */
5872
 
5873
static void
5874
mips_file_start (void)
5875
{
5876
  default_file_start ();
5877
 
5878
  if (!TARGET_IRIX)
5879
    {
5880
      /* Generate a special section to describe the ABI switches used to
5881
         produce the resultant binary.  This used to be done by the assembler
5882
         setting bits in the ELF header's flags field, but we have run out of
5883
         bits.  GDB needs this information in order to be able to correctly
5884
         debug these binaries.  See the function mips_gdbarch_init() in
5885
         gdb/mips-tdep.c.  This is unnecessary for the IRIX 5/6 ABIs and
5886
         causes unnecessary IRIX 6 ld warnings.  */
5887
      const char * abi_string = NULL;
5888
 
5889
      switch (mips_abi)
5890
        {
5891
        case ABI_32:   abi_string = "abi32"; break;
5892
        case ABI_N32:  abi_string = "abiN32"; break;
5893
        case ABI_64:   abi_string = "abi64"; break;
5894
        case ABI_O64:  abi_string = "abiO64"; break;
5895
        case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5896
        default:
5897
          gcc_unreachable ();
5898
        }
5899
      /* Note - we use fprintf directly rather than calling switch_to_section
5900
         because in this way we can avoid creating an allocated section.  We
5901
         do not want this section to take up any space in the running
5902
         executable.  */
5903
      fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5904
 
5905
      /* There is no ELF header flag to distinguish long32 forms of the
5906
         EABI from long64 forms.  Emit a special section to help tools
5907
         such as GDB.  Do the same for o64, which is sometimes used with
5908
         -mlong64.  */
5909
      if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
5910
        fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5911
                 TARGET_LONG64 ? 64 : 32);
5912
 
5913
      /* Restore the default section.  */
5914
      fprintf (asm_out_file, "\t.previous\n");
5915
    }
5916
 
5917
  /* Generate the pseudo ops that System V.4 wants.  */
5918
  if (TARGET_ABICALLS)
5919
    fprintf (asm_out_file, "\t.abicalls\n");
5920
 
5921
  if (TARGET_MIPS16)
5922
    fprintf (asm_out_file, "\t.set\tmips16\n");
5923
 
5924
  if (flag_verbose_asm)
5925
    fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5926
             ASM_COMMENT_START,
5927
             mips_section_threshold, mips_arch_info->name, mips_isa);
5928
}
5929
 
5930
#ifdef BSS_SECTION_ASM_OP
5931
/* Implement ASM_OUTPUT_ALIGNED_BSS.  This differs from the default only
5932
   in the use of sbss.  */
5933
 
5934
void
5935
mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5936
                         unsigned HOST_WIDE_INT size, int align)
5937
{
5938
  extern tree last_assemble_variable_decl;
5939
 
5940
  if (mips_in_small_data_p (decl))
5941
    switch_to_section (get_named_section (NULL, ".sbss", 0));
5942
  else
5943
    switch_to_section (bss_section);
5944
  ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5945
  last_assemble_variable_decl = decl;
5946
  ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5947
  ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5948
}
5949
#endif
5950
 
5951
/* Implement TARGET_ASM_FILE_END.  When using assembler macros, emit
5952
   .externs for any small-data variables that turned out to be external.  */
5953
 
5954
static void
5955
mips_file_end (void)
5956
{
5957
  tree name_tree;
5958
  struct extern_list *p;
5959
 
5960
  if (extern_head)
5961
    {
5962
      fputs ("\n", asm_out_file);
5963
 
5964
      for (p = extern_head; p != 0; p = p->next)
5965
        {
5966
          name_tree = get_identifier (p->name);
5967
 
5968
          /* Positively ensure only one .extern for any given symbol.  */
5969
          if (!TREE_ASM_WRITTEN (name_tree)
5970
              && TREE_SYMBOL_REFERENCED (name_tree))
5971
            {
5972
              TREE_ASM_WRITTEN (name_tree) = 1;
5973
              /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5974
                 `.global name .text' directive for every used but
5975
                 undefined function.  If we don't, the linker may perform
5976
                 an optimization (skipping over the insns that set $gp)
5977
                 when it is unsafe.  */
5978
              if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5979
                {
5980
                  fputs ("\t.globl ", asm_out_file);
5981
                  assemble_name (asm_out_file, p->name);
5982
                  fputs (" .text\n", asm_out_file);
5983
                }
5984
              else
5985
                {
5986
                  fputs ("\t.extern\t", asm_out_file);
5987
                  assemble_name (asm_out_file, p->name);
5988
                  fprintf (asm_out_file, ", %d\n", p->size);
5989
                }
5990
            }
5991
        }
5992
    }
5993
}
5994
 
5995
/* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON.  This is usually the same as the
5996
   elfos.h version, but we also need to handle -muninit-const-in-rodata.  */
5997
 
5998
void
5999
mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
6000
                                 unsigned HOST_WIDE_INT size,
6001
                                 unsigned int align)
6002
{
6003
  /* If the target wants uninitialized const declarations in
6004
     .rdata then don't put them in .comm.  */
6005
  if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
6006
      && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
6007
      && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6008
    {
6009
      if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6010
        targetm.asm_out.globalize_label (stream, name);
6011
 
6012
      switch_to_section (readonly_data_section);
6013
      ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6014
      mips_declare_object (stream, name, "",
6015
                           ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
6016
                           size);
6017
    }
6018
  else
6019
    mips_declare_common_object (stream, name, "\n\t.comm\t",
6020
                                size, align, true);
6021
}
6022
 
6023
/* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6024
   NAME is the name of the object and ALIGN is the required alignment
6025
   in bytes.  TAKES_ALIGNMENT_P is true if the directive takes a third
6026
   alignment argument.  */
6027
 
6028
void
6029
mips_declare_common_object (FILE *stream, const char *name,
6030
                            const char *init_string,
6031
                            unsigned HOST_WIDE_INT size,
6032
                            unsigned int align, bool takes_alignment_p)
6033
{
6034
  if (!takes_alignment_p)
6035
    {
6036
      size += (align / BITS_PER_UNIT) - 1;
6037
      size -= size % (align / BITS_PER_UNIT);
6038
      mips_declare_object (stream, name, init_string,
6039
                           "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6040
    }
6041
  else
6042
    mips_declare_object (stream, name, init_string,
6043
                         "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6044
                         size, align / BITS_PER_UNIT);
6045
}
6046
 
6047
/* Emit either a label, .comm, or .lcomm directive.  When using assembler
6048
   macros, mark the symbol as written so that mips_file_end won't emit an
6049
   .extern for it.  STREAM is the output file, NAME is the name of the
6050
   symbol, INIT_STRING is the string that should be written before the
6051
   symbol and FINAL_STRING is the string that should be written after it.
6052
   FINAL_STRING is a printf() format that consumes the remaining arguments.  */
6053
 
6054
void
6055
mips_declare_object (FILE *stream, const char *name, const char *init_string,
6056
                     const char *final_string, ...)
6057
{
6058
  va_list ap;
6059
 
6060
  fputs (init_string, stream);
6061
  assemble_name (stream, name);
6062
  va_start (ap, final_string);
6063
  vfprintf (stream, final_string, ap);
6064
  va_end (ap);
6065
 
6066
  if (!TARGET_EXPLICIT_RELOCS)
6067
    {
6068
      tree name_tree = get_identifier (name);
6069
      TREE_ASM_WRITTEN (name_tree) = 1;
6070
    }
6071
}
6072
 
6073
#ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6074
extern int size_directive_output;
6075
 
6076
/* Implement ASM_DECLARE_OBJECT_NAME.  This is like most of the standard ELF
6077
   definitions except that it uses mips_declare_object() to emit the label.  */
6078
 
6079
void
6080
mips_declare_object_name (FILE *stream, const char *name,
6081
                          tree decl ATTRIBUTE_UNUSED)
6082
{
6083
#ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6084
  ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6085
#endif
6086
 
6087
  size_directive_output = 0;
6088
  if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6089
    {
6090
      HOST_WIDE_INT size;
6091
 
6092
      size_directive_output = 1;
6093
      size = int_size_in_bytes (TREE_TYPE (decl));
6094
      ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6095
    }
6096
 
6097
  mips_declare_object (stream, name, "", ":\n");
6098
}
6099
 
6100
/* Implement ASM_FINISH_DECLARE_OBJECT.  This is generic ELF stuff.  */
6101
 
6102
void
6103
mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6104
{
6105
  const char *name;
6106
 
6107
  name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6108
  if (!flag_inhibit_size_directive
6109
      && DECL_SIZE (decl) != 0
6110
      && !at_end && top_level
6111
      && DECL_INITIAL (decl) == error_mark_node
6112
      && !size_directive_output)
6113
    {
6114
      HOST_WIDE_INT size;
6115
 
6116
      size_directive_output = 1;
6117
      size = int_size_in_bytes (TREE_TYPE (decl));
6118
      ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6119
    }
6120
}
6121
#endif
6122
 
6123
/* Return true if X is a small data address that can be rewritten
6124
   as a LO_SUM.  */
6125
 
6126
static bool
6127
mips_rewrite_small_data_p (rtx x)
6128
{
6129
  enum mips_symbol_type symbol_type;
6130
 
6131
  return (TARGET_EXPLICIT_RELOCS
6132
          && mips_symbolic_constant_p (x, &symbol_type)
6133
          && symbol_type == SYMBOL_SMALL_DATA);
6134
}
6135
 
6136
 
6137
/* A for_each_rtx callback for mips_small_data_pattern_p.  */
6138
 
6139
static int
6140
mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6141
{
6142
  if (GET_CODE (*loc) == LO_SUM)
6143
    return -1;
6144
 
6145
  return mips_rewrite_small_data_p (*loc);
6146
}
6147
 
6148
/* Return true if OP refers to small data symbols directly, not through
6149
   a LO_SUM.  */
6150
 
6151
bool
6152
mips_small_data_pattern_p (rtx op)
6153
{
6154
  return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6155
}
6156
 
6157
/* A for_each_rtx callback, used by mips_rewrite_small_data.  */
6158
 
6159
static int
6160
mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6161
{
6162
  if (mips_rewrite_small_data_p (*loc))
6163
    *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6164
 
6165
  if (GET_CODE (*loc) == LO_SUM)
6166
    return -1;
6167
 
6168
  return 0;
6169
}
6170
 
6171
/* If possible, rewrite OP so that it refers to small data using
6172
   explicit relocations.  */
6173
 
6174
rtx
6175
mips_rewrite_small_data (rtx op)
6176
{
6177
  op = copy_insn (op);
6178
  for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6179
  return op;
6180
}
6181
 
6182
/* Return true if the current function has an insn that implicitly
6183
   refers to $gp.  */
6184
 
6185
static bool
6186
mips_function_has_gp_insn (void)
6187
{
6188
  /* Don't bother rechecking if we found one last time.  */
6189
  if (!cfun->machine->has_gp_insn_p)
6190
    {
6191
      rtx insn;
6192
 
6193
      push_topmost_sequence ();
6194
      for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6195
        if (INSN_P (insn)
6196
            && GET_CODE (PATTERN (insn)) != USE
6197
            && GET_CODE (PATTERN (insn)) != CLOBBER
6198
            && (get_attr_got (insn) != GOT_UNSET
6199
                || small_data_pattern (PATTERN (insn), VOIDmode)))
6200
          break;
6201
      pop_topmost_sequence ();
6202
 
6203
      cfun->machine->has_gp_insn_p = (insn != 0);
6204
    }
6205
  return cfun->machine->has_gp_insn_p;
6206
}
6207
 
6208
 
6209
/* Return the register that should be used as the global pointer
6210
   within this function.  Return 0 if the function doesn't need
6211
   a global pointer.  */
6212
 
6213
static unsigned int
6214
mips_global_pointer (void)
6215
{
6216
  unsigned int regno;
6217
 
6218
  /* $gp is always available in non-abicalls code.  */
6219
  if (!TARGET_ABICALLS)
6220
    return GLOBAL_POINTER_REGNUM;
6221
 
6222
  /* We must always provide $gp when it is used implicitly.  */
6223
  if (!TARGET_EXPLICIT_RELOCS)
6224
    return GLOBAL_POINTER_REGNUM;
6225
 
6226
  /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6227
     a valid gp.  */
6228
  if (current_function_profile)
6229
    return GLOBAL_POINTER_REGNUM;
6230
 
6231
  /* If the function has a nonlocal goto, $gp must hold the correct
6232
     global pointer for the target function.  */
6233
  if (current_function_has_nonlocal_goto)
6234
    return GLOBAL_POINTER_REGNUM;
6235
 
6236
  /* If the gp is never referenced, there's no need to initialize it.
6237
     Note that reload can sometimes introduce constant pool references
6238
     into a function that otherwise didn't need them.  For example,
6239
     suppose we have an instruction like:
6240
 
6241
          (set (reg:DF R1) (float:DF (reg:SI R2)))
6242
 
6243
     If R2 turns out to be constant such as 1, the instruction may have a
6244
     REG_EQUAL note saying that R1 == 1.0.  Reload then has the option of
6245
     using this constant if R2 doesn't get allocated to a register.
6246
 
6247
     In cases like these, reload will have added the constant to the pool
6248
     but no instruction will yet refer to it.  */
6249
  if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6250
      && !current_function_uses_const_pool
6251
      && !mips_function_has_gp_insn ())
6252
    return 0;
6253
 
6254
  /* We need a global pointer, but perhaps we can use a call-clobbered
6255
     register instead of $gp.  */
6256
  if (TARGET_NEWABI && current_function_is_leaf)
6257
    for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6258
      if (!regs_ever_live[regno]
6259
          && call_used_regs[regno]
6260
          && !fixed_regs[regno]
6261
          && regno != PIC_FUNCTION_ADDR_REGNUM)
6262
        return regno;
6263
 
6264
  return GLOBAL_POINTER_REGNUM;
6265
}
6266
 
6267
 
6268
/* Return true if the current function must save REGNO.  */
6269
 
6270
static bool
6271
mips_save_reg_p (unsigned int regno)
6272
{
6273
  /* We only need to save $gp for NewABI PIC.  */
6274
  if (regno == GLOBAL_POINTER_REGNUM)
6275
    return (TARGET_ABICALLS && TARGET_NEWABI
6276
            && cfun->machine->global_pointer == regno);
6277
 
6278
  /* Check call-saved registers.  */
6279
  if (regs_ever_live[regno] && !call_used_regs[regno])
6280
    return true;
6281
 
6282
  /* We need to save the old frame pointer before setting up a new one.  */
6283
  if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6284
    return true;
6285
 
6286
  /* We need to save the incoming return address if it is ever clobbered
6287
     within the function.  */
6288
  if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6289
    return true;
6290
 
6291
  if (TARGET_MIPS16)
6292
    {
6293
      tree return_type;
6294
 
6295
      return_type = DECL_RESULT (current_function_decl);
6296
 
6297
      /* $18 is a special case in mips16 code.  It may be used to call
6298
         a function which returns a floating point value, but it is
6299
         marked in call_used_regs.  */
6300
      if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6301
        return true;
6302
 
6303
      /* $31 is also a special case.  It will be used to copy a return
6304
         value into the floating point registers if the return value is
6305
         floating point.  */
6306
      if (regno == GP_REG_FIRST + 31
6307
          && mips16_hard_float
6308
          && !aggregate_value_p (return_type, current_function_decl)
6309
          && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6310
          && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6311
        return true;
6312
    }
6313
 
6314
  return false;
6315
}
6316
 
6317
 
6318
/* Return the bytes needed to compute the frame pointer from the current
6319
   stack pointer.  SIZE is the size (in bytes) of the local variables.
6320
 
6321
   MIPS stack frames look like:
6322
 
6323
             Before call                        After call
6324
        +-----------------------+       +-----------------------+
6325
   high |                       |       |                       |
6326
   mem. |                       |       |                       |
6327
        |  caller's temps.      |       |  caller's temps.      |
6328
        |                       |       |                       |
6329
        +-----------------------+       +-----------------------+
6330
        |                       |       |                       |
6331
        |  arguments on stack.  |       |  arguments on stack.  |
6332
        |                       |       |                       |
6333
        +-----------------------+       +-----------------------+
6334
        |  4 words to save      |       |  4 words to save      |
6335
        |  arguments passed     |       |  arguments passed     |
6336
        |  in registers, even   |       |  in registers, even   |
6337
    SP->|  if not passed.       |  VFP->|  if not passed.       |
6338
        +-----------------------+       +-----------------------+
6339
                                        |                       |
6340
                                        |  fp register save     |
6341
                                        |                       |
6342
                                        +-----------------------+
6343
                                        |                       |
6344
                                        |  gp register save     |
6345
                                        |                       |
6346
                                        +-----------------------+
6347
                                        |                       |
6348
                                        |  local variables      |
6349
                                        |                       |
6350
                                        +-----------------------+
6351
                                        |                       |
6352
                                        |  alloca allocations   |
6353
                                        |                       |
6354
                                        +-----------------------+
6355
                                        |                       |
6356
                                        |  GP save for V.4 abi  |
6357
                                        |                       |
6358
                                        +-----------------------+
6359
                                        |                       |
6360
                                        |  arguments on stack   |
6361
                                        |                       |
6362
                                        +-----------------------+
6363
                                        |  4 words to save      |
6364
                                        |  arguments passed     |
6365
                                        |  in registers, even   |
6366
   low                              SP->|  if not passed.       |
6367
   memory                               +-----------------------+
6368
 
6369
*/
6370
 
6371
HOST_WIDE_INT
6372
compute_frame_size (HOST_WIDE_INT size)
6373
{
6374
  unsigned int regno;
6375
  HOST_WIDE_INT total_size;     /* # bytes that the entire frame takes up */
6376
  HOST_WIDE_INT var_size;       /* # bytes that variables take up */
6377
  HOST_WIDE_INT args_size;      /* # bytes that outgoing arguments take up */
6378
  HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6379
  HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6380
  HOST_WIDE_INT gp_reg_size;    /* # bytes needed to store gp regs */
6381
  HOST_WIDE_INT fp_reg_size;    /* # bytes needed to store fp regs */
6382
  unsigned int mask;            /* mask of saved gp registers */
6383
  unsigned int fmask;           /* mask of saved fp registers */
6384
 
6385
  cfun->machine->global_pointer = mips_global_pointer ();
6386
 
6387
  gp_reg_size = 0;
6388
  fp_reg_size = 0;
6389
  mask = 0;
6390
  fmask = 0;
6391
  var_size = MIPS_STACK_ALIGN (size);
6392
  args_size = current_function_outgoing_args_size;
6393
  cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6394
 
6395
  /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6396
     functions.  If the function has local variables, we're committed
6397
     to allocating it anyway.  Otherwise reclaim it here.  */
6398
  if (var_size == 0 && current_function_is_leaf)
6399
    cprestore_size = args_size = 0;
6400
 
6401
  /* The MIPS 3.0 linker does not like functions that dynamically
6402
     allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6403
     looks like we are trying to create a second frame pointer to the
6404
     function, so allocate some stack space to make it happy.  */
6405
 
6406
  if (args_size == 0 && current_function_calls_alloca)
6407
    args_size = 4 * UNITS_PER_WORD;
6408
 
6409
  total_size = var_size + args_size + cprestore_size;
6410
 
6411
  /* Calculate space needed for gp registers.  */
6412
  for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6413
    if (mips_save_reg_p (regno))
6414
      {
6415
        gp_reg_size += GET_MODE_SIZE (gpr_mode);
6416
        mask |= 1 << (regno - GP_REG_FIRST);
6417
      }
6418
 
6419
  /* We need to restore these for the handler.  */
6420
  if (current_function_calls_eh_return)
6421
    {
6422
      unsigned int i;
6423
      for (i = 0; ; ++i)
6424
        {
6425
          regno = EH_RETURN_DATA_REGNO (i);
6426
          if (regno == INVALID_REGNUM)
6427
            break;
6428
          gp_reg_size += GET_MODE_SIZE (gpr_mode);
6429
          mask |= 1 << (regno - GP_REG_FIRST);
6430
        }
6431
    }
6432
 
6433
  /* This loop must iterate over the same space as its companion in
6434
     save_restore_insns.  */
6435
  for (regno = (FP_REG_LAST - FP_INC + 1);
6436
       regno >= FP_REG_FIRST;
6437
       regno -= FP_INC)
6438
    {
6439
      if (mips_save_reg_p (regno))
6440
        {
6441
          fp_reg_size += FP_INC * UNITS_PER_FPREG;
6442
          fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6443
        }
6444
    }
6445
 
6446
  gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6447
  total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6448
 
6449
  /* Add in the space required for saving incoming register arguments.  */
6450
  total_size += current_function_pretend_args_size;
6451
  total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6452
 
6453
  /* Save other computed information.  */
6454
  cfun->machine->frame.total_size = total_size;
6455
  cfun->machine->frame.var_size = var_size;
6456
  cfun->machine->frame.args_size = args_size;
6457
  cfun->machine->frame.cprestore_size = cprestore_size;
6458
  cfun->machine->frame.gp_reg_size = gp_reg_size;
6459
  cfun->machine->frame.fp_reg_size = fp_reg_size;
6460
  cfun->machine->frame.mask = mask;
6461
  cfun->machine->frame.fmask = fmask;
6462
  cfun->machine->frame.initialized = reload_completed;
6463
  cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6464
  cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6465
 
6466
  if (mask)
6467
    {
6468
      HOST_WIDE_INT offset;
6469
 
6470
      offset = (args_size + cprestore_size + var_size
6471
                + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6472
      cfun->machine->frame.gp_sp_offset = offset;
6473
      cfun->machine->frame.gp_save_offset = offset - total_size;
6474
    }
6475
  else
6476
    {
6477
      cfun->machine->frame.gp_sp_offset = 0;
6478
      cfun->machine->frame.gp_save_offset = 0;
6479
    }
6480
 
6481
  if (fmask)
6482
    {
6483
      HOST_WIDE_INT offset;
6484
 
6485
      offset = (args_size + cprestore_size + var_size
6486
                + gp_reg_rounded + fp_reg_size
6487
                - FP_INC * UNITS_PER_FPREG);
6488
      cfun->machine->frame.fp_sp_offset = offset;
6489
      cfun->machine->frame.fp_save_offset = offset - total_size;
6490
    }
6491
  else
6492
    {
6493
      cfun->machine->frame.fp_sp_offset = 0;
6494
      cfun->machine->frame.fp_save_offset = 0;
6495
    }
6496
 
6497
  /* Ok, we're done.  */
6498
  return total_size;
6499
}
6500
 
6501
/* Implement INITIAL_ELIMINATION_OFFSET.  FROM is either the frame
6502
   pointer or argument pointer.  TO is either the stack pointer or
6503
   hard frame pointer.  */
6504
 
6505
HOST_WIDE_INT
6506
mips_initial_elimination_offset (int from, int to)
6507
{
6508
  HOST_WIDE_INT offset;
6509
 
6510
  compute_frame_size (get_frame_size ());
6511
 
6512
  /* Set OFFSET to the offset from the stack pointer.  */
6513
  switch (from)
6514
    {
6515
    case FRAME_POINTER_REGNUM:
6516
      offset = 0;
6517
      break;
6518
 
6519
    case ARG_POINTER_REGNUM:
6520
      offset = (cfun->machine->frame.total_size
6521
                - current_function_pretend_args_size);
6522
      break;
6523
 
6524
    default:
6525
      gcc_unreachable ();
6526
    }
6527
 
6528
  if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6529
    offset -= cfun->machine->frame.args_size;
6530
 
6531
  return offset;
6532
}
6533
 
6534
/* Implement RETURN_ADDR_RTX.  Note, we do not support moving
6535
   back to a previous frame.  */
6536
rtx
6537
mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6538
{
6539
  if (count != 0)
6540
    return const0_rtx;
6541
 
6542
  return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6543
}
6544
 
6545
/* Use FN to save or restore register REGNO.  MODE is the register's
6546
   mode and OFFSET is the offset of its save slot from the current
6547
   stack pointer.  */
6548
 
6549
static void
6550
mips_save_restore_reg (enum machine_mode mode, int regno,
6551
                       HOST_WIDE_INT offset, mips_save_restore_fn fn)
6552
{
6553
  rtx mem;
6554
 
6555
  mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
6556
 
6557
  fn (gen_rtx_REG (mode, regno), mem);
6558
}
6559
 
6560
 
6561
/* Call FN for each register that is saved by the current function.
6562
   SP_OFFSET is the offset of the current stack pointer from the start
6563
   of the frame.  */
6564
 
6565
static void
6566
mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6567
{
6568
#define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6569
 
6570
  enum machine_mode fpr_mode;
6571
  HOST_WIDE_INT offset;
6572
  int regno;
6573
 
6574
  /* Save registers starting from high to low.  The debuggers prefer at least
6575
     the return register be stored at func+4, and also it allows us not to
6576
     need a nop in the epilog if at least one register is reloaded in
6577
     addition to return address.  */
6578
  offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6579
  for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6580
    if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6581
      {
6582
        mips_save_restore_reg (gpr_mode, regno, offset, fn);
6583
        offset -= GET_MODE_SIZE (gpr_mode);
6584
      }
6585
 
6586
  /* This loop must iterate over the same space as its companion in
6587
     compute_frame_size.  */
6588
  offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6589
  fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6590
  for (regno = (FP_REG_LAST - FP_INC + 1);
6591
       regno >= FP_REG_FIRST;
6592
       regno -= FP_INC)
6593
    if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6594
      {
6595
        mips_save_restore_reg (fpr_mode, regno, offset, fn);
6596
        offset -= GET_MODE_SIZE (fpr_mode);
6597
      }
6598
#undef BITSET_P
6599
}
6600
 
6601
/* If we're generating n32 or n64 abicalls, and the current function
6602
   does not use $28 as its global pointer, emit a cplocal directive.
6603
   Use pic_offset_table_rtx as the argument to the directive.  */
6604
 
6605
static void
6606
mips_output_cplocal (void)
6607
{
6608
  if (!TARGET_EXPLICIT_RELOCS
6609
      && cfun->machine->global_pointer > 0
6610
      && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6611
    output_asm_insn (".cplocal %+", 0);
6612
}
6613
 
6614
/* Return the style of GP load sequence that is being used for the
6615
   current function.  */
6616
 
6617
enum mips_loadgp_style
6618
mips_current_loadgp_style (void)
6619
{
6620
  if (!TARGET_ABICALLS || cfun->machine->global_pointer == 0)
6621
    return LOADGP_NONE;
6622
 
6623
  if (TARGET_ABSOLUTE_ABICALLS)
6624
    return LOADGP_ABSOLUTE;
6625
 
6626
  return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6627
}
6628
 
6629
/* The __gnu_local_gp symbol.  */
6630
 
6631
static GTY(()) rtx mips_gnu_local_gp;
6632
 
6633
/* If we're generating n32 or n64 abicalls, emit instructions
6634
   to set up the global pointer.  */
6635
 
6636
static void
6637
mips_emit_loadgp (void)
6638
{
6639
  rtx addr, offset, incoming_address;
6640
 
6641
  switch (mips_current_loadgp_style ())
6642
    {
6643
    case LOADGP_ABSOLUTE:
6644
      if (mips_gnu_local_gp == NULL)
6645
        {
6646
          mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6647
          SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6648
        }
6649
      emit_insn (gen_loadgp_noshared (mips_gnu_local_gp));
6650
      break;
6651
 
6652
    case LOADGP_NEWABI:
6653
      addr = XEXP (DECL_RTL (current_function_decl), 0);
6654
      offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6655
      incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6656
      emit_insn (gen_loadgp (offset, incoming_address));
6657
      if (!TARGET_EXPLICIT_RELOCS)
6658
        emit_insn (gen_loadgp_blockage ());
6659
      break;
6660
 
6661
    default:
6662
      break;
6663
    }
6664
}
6665
 
6666
/* Set up the stack and frame (if desired) for the function.  */
6667
 
6668
static void
6669
mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6670
{
6671
  const char *fnname;
6672
  HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6673
 
6674
#ifdef SDB_DEBUGGING_INFO
6675
  if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6676
    SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6677
#endif
6678
 
6679
  /* In mips16 mode, we may need to generate a 32 bit to handle
6680
     floating point arguments.  The linker will arrange for any 32 bit
6681
     functions to call this stub, which will then jump to the 16 bit
6682
     function proper.  */
6683
  if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6684
      && current_function_args_info.fp_code != 0)
6685
    build_mips16_function_stub (file);
6686
 
6687
  if (!FUNCTION_NAME_ALREADY_DECLARED)
6688
    {
6689
      /* Get the function name the same way that toplev.c does before calling
6690
         assemble_start_function.  This is needed so that the name used here
6691
         exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
6692
      fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6693
 
6694
      if (!flag_inhibit_size_directive)
6695
        {
6696
          fputs ("\t.ent\t", file);
6697
          assemble_name (file, fnname);
6698
          fputs ("\n", file);
6699
        }
6700
 
6701
      assemble_name (file, fnname);
6702
      fputs (":\n", file);
6703
    }
6704
 
6705
  /* Stop mips_file_end from treating this function as external.  */
6706
  if (TARGET_IRIX && mips_abi == ABI_32)
6707
    TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6708
 
6709
  if (!flag_inhibit_size_directive)
6710
    {
6711
      /* .frame FRAMEREG, FRAMESIZE, RETREG */
6712
      fprintf (file,
6713
               "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6714
               "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6715
               ", args= " HOST_WIDE_INT_PRINT_DEC
6716
               ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6717
               (reg_names[(frame_pointer_needed)
6718
                          ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6719
               ((frame_pointer_needed && TARGET_MIPS16)
6720
                ? tsize - cfun->machine->frame.args_size
6721
                : tsize),
6722
               reg_names[GP_REG_FIRST + 31],
6723
               cfun->machine->frame.var_size,
6724
               cfun->machine->frame.num_gp,
6725
               cfun->machine->frame.num_fp,
6726
               cfun->machine->frame.args_size,
6727
               cfun->machine->frame.cprestore_size);
6728
 
6729
      /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6730
      fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6731
               cfun->machine->frame.mask,
6732
               cfun->machine->frame.gp_save_offset);
6733
      fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6734
               cfun->machine->frame.fmask,
6735
               cfun->machine->frame.fp_save_offset);
6736
 
6737
      /* Require:
6738
         OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6739
         HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs.  */
6740
    }
6741
 
6742
  if (mips_current_loadgp_style () == LOADGP_OLDABI)
6743
    {
6744
      /* Handle the initialization of $gp for SVR4 PIC.  */
6745
      if (!cfun->machine->all_noreorder_p)
6746
        output_asm_insn ("%(.cpload\t%^%)", 0);
6747
      else
6748
        output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6749
    }
6750
  else if (cfun->machine->all_noreorder_p)
6751
    output_asm_insn ("%(%<", 0);
6752
 
6753
  /* Tell the assembler which register we're using as the global
6754
     pointer.  This is needed for thunks, since they can use either
6755
     explicit relocs or assembler macros.  */
6756
  mips_output_cplocal ();
6757
}
6758
 
6759
/* Make the last instruction frame related and note that it performs
6760
   the operation described by FRAME_PATTERN.  */
6761
 
6762
static void
6763
mips_set_frame_expr (rtx frame_pattern)
6764
{
6765
  rtx insn;
6766
 
6767
  insn = get_last_insn ();
6768
  RTX_FRAME_RELATED_P (insn) = 1;
6769
  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6770
                                      frame_pattern,
6771
                                      REG_NOTES (insn));
6772
}
6773
 
6774
 
6775
/* Return a frame-related rtx that stores REG at MEM.
6776
   REG must be a single register.  */
6777
 
6778
static rtx
6779
mips_frame_set (rtx mem, rtx reg)
6780
{
6781
  rtx set;
6782
 
6783
  /* If we're saving the return address register and the dwarf return
6784
     address column differs from the hard register number, adjust the
6785
     note reg to refer to the former.  */
6786
  if (REGNO (reg) == GP_REG_FIRST + 31
6787
      && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6788
    reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6789
 
6790
  set = gen_rtx_SET (VOIDmode, mem, reg);
6791
  RTX_FRAME_RELATED_P (set) = 1;
6792
 
6793
  return set;
6794
}
6795
 
6796
 
6797
/* Save register REG to MEM.  Make the instruction frame-related.  */
6798
 
6799
static void
6800
mips_save_reg (rtx reg, rtx mem)
6801
{
6802
  if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6803
    {
6804
      rtx x1, x2;
6805
 
6806
      if (mips_split_64bit_move_p (mem, reg))
6807
        mips_split_64bit_move (mem, reg);
6808
      else
6809
        emit_move_insn (mem, reg);
6810
 
6811
      x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6812
      x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6813
      mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6814
    }
6815
  else
6816
    {
6817
      if (TARGET_MIPS16
6818
          && REGNO (reg) != GP_REG_FIRST + 31
6819
          && !M16_REG_P (REGNO (reg)))
6820
        {
6821
          /* Save a non-mips16 register by moving it through a temporary.
6822
             We don't need to do this for $31 since there's a special
6823
             instruction for it.  */
6824
          emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6825
          emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6826
        }
6827
      else
6828
        emit_move_insn (mem, reg);
6829
 
6830
      mips_set_frame_expr (mips_frame_set (mem, reg));
6831
    }
6832
}
6833
 
6834
 
6835
/* Expand the prologue into a bunch of separate insns.  */
6836
 
6837
void
6838
mips_expand_prologue (void)
6839
{
6840
  HOST_WIDE_INT size;
6841
 
6842
  if (cfun->machine->global_pointer > 0)
6843
    REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6844
 
6845
  size = compute_frame_size (get_frame_size ());
6846
 
6847
  /* Save the registers.  Allocate up to MIPS_MAX_FIRST_STACK_STEP
6848
     bytes beforehand; this is enough to cover the register save area
6849
     without going out of range.  */
6850
  if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6851
    {
6852
      HOST_WIDE_INT step1;
6853
 
6854
      step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6855
      RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6856
                                                     stack_pointer_rtx,
6857
                                                     GEN_INT (-step1)))) = 1;
6858
      size -= step1;
6859
      mips_for_each_saved_reg (size, mips_save_reg);
6860
    }
6861
 
6862
  /* Allocate the rest of the frame.  */
6863
  if (size > 0)
6864
    {
6865
      if (SMALL_OPERAND (-size))
6866
        RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6867
                                                       stack_pointer_rtx,
6868
                                                       GEN_INT (-size)))) = 1;
6869
      else
6870
        {
6871
          emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6872
          if (TARGET_MIPS16)
6873
            {
6874
              /* There are no instructions to add or subtract registers
6875
                 from the stack pointer, so use the frame pointer as a
6876
                 temporary.  We should always be using a frame pointer
6877
                 in this case anyway.  */
6878
              gcc_assert (frame_pointer_needed);
6879
              emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6880
              emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6881
                                        hard_frame_pointer_rtx,
6882
                                        MIPS_PROLOGUE_TEMP (Pmode)));
6883
              emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6884
            }
6885
          else
6886
            emit_insn (gen_sub3_insn (stack_pointer_rtx,
6887
                                      stack_pointer_rtx,
6888
                                      MIPS_PROLOGUE_TEMP (Pmode)));
6889
 
6890
          /* Describe the combined effect of the previous instructions.  */
6891
          mips_set_frame_expr
6892
            (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6893
                          plus_constant (stack_pointer_rtx, -size)));
6894
        }
6895
    }
6896
 
6897
  /* Set up the frame pointer, if we're using one.  In mips16 code,
6898
     we point the frame pointer ahead of the outgoing argument area.
6899
     This should allow more variables & incoming arguments to be
6900
     accessed with unextended instructions.  */
6901
  if (frame_pointer_needed)
6902
    {
6903
      if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6904
        {
6905
          rtx offset = GEN_INT (cfun->machine->frame.args_size);
6906
          if (SMALL_OPERAND (cfun->machine->frame.args_size))
6907
            RTX_FRAME_RELATED_P
6908
              (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6909
                                         stack_pointer_rtx,
6910
                                         offset))) = 1;
6911
          else
6912
            {
6913
              emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
6914
              emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6915
              emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6916
                                        hard_frame_pointer_rtx,
6917
                                        MIPS_PROLOGUE_TEMP (Pmode)));
6918
              mips_set_frame_expr
6919
                (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
6920
                              plus_constant (stack_pointer_rtx,
6921
                                             cfun->machine->frame.args_size)));
6922
            }
6923
        }
6924
      else
6925
        RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6926
                                             stack_pointer_rtx)) = 1;
6927
    }
6928
 
6929
  mips_emit_loadgp ();
6930
 
6931
  /* If generating o32/o64 abicalls, save $gp on the stack.  */
6932
  if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6933
    emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6934
 
6935
  /* If we are profiling, make sure no instructions are scheduled before
6936
     the call to mcount.  */
6937
 
6938
  if (current_function_profile)
6939
    emit_insn (gen_blockage ());
6940
}
6941
 
6942
/* Do any necessary cleanup after a function to restore stack, frame,
6943
   and regs.  */
6944
 
6945
#define RA_MASK BITMASK_HIGH    /* 1 << 31 */
6946
 
6947
static void
6948
mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6949
                               HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6950
{
6951
  /* Reinstate the normal $gp.  */
6952
  REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6953
  mips_output_cplocal ();
6954
 
6955
  if (cfun->machine->all_noreorder_p)
6956
    {
6957
      /* Avoid using %>%) since it adds excess whitespace.  */
6958
      output_asm_insn (".set\tmacro", 0);
6959
      output_asm_insn (".set\treorder", 0);
6960
      set_noreorder = set_nomacro = 0;
6961
    }
6962
 
6963
  if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6964
    {
6965
      const char *fnname;
6966
 
6967
      /* Get the function name the same way that toplev.c does before calling
6968
         assemble_start_function.  This is needed so that the name used here
6969
         exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
6970
      fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6971
      fputs ("\t.end\t", file);
6972
      assemble_name (file, fnname);
6973
      fputs ("\n", file);
6974
    }
6975
}
6976
 
6977
/* Emit instructions to restore register REG from slot MEM.  */
6978
 
6979
static void
6980
mips_restore_reg (rtx reg, rtx mem)
6981
{
6982
  /* There's no mips16 instruction to load $31 directly.  Load into
6983
     $7 instead and adjust the return insn appropriately.  */
6984
  if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6985
    reg = gen_rtx_REG (GET_MODE (reg), 7);
6986
 
6987
  if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6988
    {
6989
      /* Can't restore directly; move through a temporary.  */
6990
      emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6991
      emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6992
    }
6993
  else
6994
    emit_move_insn (reg, mem);
6995
}
6996
 
6997
 
6998
/* Expand the epilogue into a bunch of separate insns.  SIBCALL_P is true
6999
   if this epilogue precedes a sibling call, false if it is for a normal
7000
   "epilogue" pattern.  */
7001
 
7002
void
7003
mips_expand_epilogue (int sibcall_p)
7004
{
7005
  HOST_WIDE_INT step1, step2;
7006
  rtx base, target;
7007
 
7008
  if (!sibcall_p && mips_can_use_return_insn ())
7009
    {
7010
      emit_jump_insn (gen_return ());
7011
      return;
7012
    }
7013
 
7014
  /* Split the frame into two.  STEP1 is the amount of stack we should
7015
     deallocate before restoring the registers.  STEP2 is the amount we
7016
     should deallocate afterwards.
7017
 
7018
     Start off by assuming that no registers need to be restored.  */
7019
  step1 = cfun->machine->frame.total_size;
7020
  step2 = 0;
7021
 
7022
  /* Work out which register holds the frame address.  Account for the
7023
     frame pointer offset used by mips16 code.  */
7024
  if (!frame_pointer_needed)
7025
    base = stack_pointer_rtx;
7026
  else
7027
    {
7028
      base = hard_frame_pointer_rtx;
7029
      if (TARGET_MIPS16)
7030
        step1 -= cfun->machine->frame.args_size;
7031
    }
7032
 
7033
  /* If we need to restore registers, deallocate as much stack as
7034
     possible in the second step without going out of range.  */
7035
  if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7036
    {
7037
      step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7038
      step1 -= step2;
7039
    }
7040
 
7041
  /* Set TARGET to BASE + STEP1.  */
7042
  target = base;
7043
  if (step1 > 0)
7044
    {
7045
      rtx adjust;
7046
 
7047
      /* Get an rtx for STEP1 that we can add to BASE.  */
7048
      adjust = GEN_INT (step1);
7049
      if (!SMALL_OPERAND (step1))
7050
        {
7051
          emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7052
          adjust = MIPS_EPILOGUE_TEMP (Pmode);
7053
        }
7054
 
7055
      /* Normal mode code can copy the result straight into $sp.  */
7056
      if (!TARGET_MIPS16)
7057
        target = stack_pointer_rtx;
7058
 
7059
      emit_insn (gen_add3_insn (target, base, adjust));
7060
    }
7061
 
7062
  /* Copy TARGET into the stack pointer.  */
7063
  if (target != stack_pointer_rtx)
7064
    emit_move_insn (stack_pointer_rtx, target);
7065
 
7066
  /* If we're using addressing macros for n32/n64 abicalls, $gp is
7067
     implicitly used by all SYMBOL_REFs.  We must emit a blockage
7068
     insn before restoring it.  */
7069
  if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
7070
    emit_insn (gen_blockage ());
7071
 
7072
  /* Restore the registers.  */
7073
  mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7074
                           mips_restore_reg);
7075
 
7076
  /* Deallocate the final bit of the frame.  */
7077
  if (step2 > 0)
7078
    emit_insn (gen_add3_insn (stack_pointer_rtx,
7079
                              stack_pointer_rtx,
7080
                              GEN_INT (step2)));
7081
 
7082
  /* Add in the __builtin_eh_return stack adjustment.  We need to
7083
     use a temporary in mips16 code.  */
7084
  if (current_function_calls_eh_return)
7085
    {
7086
      if (TARGET_MIPS16)
7087
        {
7088
          emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7089
          emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7090
                                    MIPS_EPILOGUE_TEMP (Pmode),
7091
                                    EH_RETURN_STACKADJ_RTX));
7092
          emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7093
        }
7094
      else
7095
        emit_insn (gen_add3_insn (stack_pointer_rtx,
7096
                                  stack_pointer_rtx,
7097
                                  EH_RETURN_STACKADJ_RTX));
7098
    }
7099
 
7100
  if (!sibcall_p)
7101
    {
7102
      /* The mips16 loads the return address into $7, not $31.  */
7103
      if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7104
        emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7105
                                                          GP_REG_FIRST + 7)));
7106
      else
7107
        emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7108
                                                          GP_REG_FIRST + 31)));
7109
    }
7110
}
7111
 
7112
/* Return nonzero if this function is known to have a null epilogue.
7113
   This allows the optimizer to omit jumps to jumps if no stack
7114
   was created.  */
7115
 
7116
int
7117
mips_can_use_return_insn (void)
7118
{
7119
  tree return_type;
7120
 
7121
  if (! reload_completed)
7122
    return 0;
7123
 
7124
  if (regs_ever_live[31] || current_function_profile)
7125
    return 0;
7126
 
7127
  return_type = DECL_RESULT (current_function_decl);
7128
 
7129
  /* In mips16 mode, a function which returns a floating point value
7130
     needs to arrange to copy the return value into the floating point
7131
     registers.  */
7132
  if (TARGET_MIPS16
7133
      && mips16_hard_float
7134
      && ! aggregate_value_p (return_type, current_function_decl)
7135
      && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7136
      && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7137
    return 0;
7138
 
7139
  if (cfun->machine->frame.initialized)
7140
    return cfun->machine->frame.total_size == 0;
7141
 
7142
  return compute_frame_size (get_frame_size ()) == 0;
7143
}
7144
 
7145
/* Implement TARGET_ASM_OUTPUT_MI_THUNK.  Generate rtl rather than asm text
7146
   in order to avoid duplicating too much logic from elsewhere.  */
7147
 
7148
static void
7149
mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7150
                      HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7151
                      tree function)
7152
{
7153
  rtx this, temp1, temp2, insn, fnaddr;
7154
 
7155
  /* Pretend to be a post-reload pass while generating rtl.  */
7156
  no_new_pseudos = 1;
7157
  reload_completed = 1;
7158
  reset_block_changes ();
7159
 
7160
  /* Pick a global pointer for -mabicalls.  Use $15 rather than $28
7161
     for TARGET_NEWABI since the latter is a call-saved register.  */
7162
  if (TARGET_ABICALLS)
7163
    cfun->machine->global_pointer
7164
      = REGNO (pic_offset_table_rtx)
7165
      = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7166
 
7167
  /* Set up the global pointer for n32 or n64 abicalls.  */
7168
  mips_emit_loadgp ();
7169
 
7170
  /* We need two temporary registers in some cases.  */
7171
  temp1 = gen_rtx_REG (Pmode, 2);
7172
  temp2 = gen_rtx_REG (Pmode, 3);
7173
 
7174
  /* Find out which register contains the "this" pointer.  */
7175
  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7176
    this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7177
  else
7178
    this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7179
 
7180
  /* Add DELTA to THIS.  */
7181
  if (delta != 0)
7182
    {
7183
      rtx offset = GEN_INT (delta);
7184
      if (!SMALL_OPERAND (delta))
7185
        {
7186
          emit_move_insn (temp1, offset);
7187
          offset = temp1;
7188
        }
7189
      emit_insn (gen_add3_insn (this, this, offset));
7190
    }
7191
 
7192
  /* If needed, add *(*THIS + VCALL_OFFSET) to THIS.  */
7193
  if (vcall_offset != 0)
7194
    {
7195
      rtx addr;
7196
 
7197
      /* Set TEMP1 to *THIS.  */
7198
      emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7199
 
7200
      /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET.  */
7201
      addr = mips_add_offset (temp2, temp1, vcall_offset);
7202
 
7203
      /* Load the offset and add it to THIS.  */
7204
      emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7205
      emit_insn (gen_add3_insn (this, this, temp1));
7206
    }
7207
 
7208
  /* Jump to the target function.  Use a sibcall if direct jumps are
7209
     allowed, otherwise load the address into a register first.  */
7210
  fnaddr = XEXP (DECL_RTL (function), 0);
7211
  if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7212
    {
7213
      /* This is messy.  gas treats "la $25,foo" as part of a call
7214
         sequence and may allow a global "foo" to be lazily bound.
7215
         The general move patterns therefore reject this combination.
7216
 
7217
         In this context, lazy binding would actually be OK for o32 and o64,
7218
         but it's still wrong for n32 and n64; see mips_load_call_address.
7219
         We must therefore load the address via a temporary register if
7220
         mips_dangerous_for_la25_p.
7221
 
7222
         If we jump to the temporary register rather than $25, the assembler
7223
         can use the move insn to fill the jump's delay slot.  */
7224
      if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7225
        temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7226
      mips_load_call_address (temp1, fnaddr, true);
7227
 
7228
      if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7229
        emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7230
      emit_jump_insn (gen_indirect_jump (temp1));
7231
    }
7232
  else
7233
    {
7234
      insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7235
      SIBLING_CALL_P (insn) = 1;
7236
    }
7237
 
7238
  /* Run just enough of rest_of_compilation.  This sequence was
7239
     "borrowed" from alpha.c.  */
7240
  insn = get_insns ();
7241
  insn_locators_initialize ();
7242
  split_all_insns_noflow ();
7243
  if (TARGET_MIPS16)
7244
    mips16_lay_out_constants ();
7245
  shorten_branches (insn);
7246
  final_start_function (insn, file, 1);
7247
  final (insn, file, 1);
7248
  final_end_function ();
7249
 
7250
  /* Clean up the vars set above.  Note that final_end_function resets
7251
     the global pointer for us.  */
7252
  reload_completed = 0;
7253
  no_new_pseudos = 0;
7254
}
7255
 
7256
/* Returns nonzero if X contains a SYMBOL_REF.  */
7257
 
7258
static int
7259
symbolic_expression_p (rtx x)
7260
{
7261
  if (GET_CODE (x) == SYMBOL_REF)
7262
    return 1;
7263
 
7264
  if (GET_CODE (x) == CONST)
7265
    return symbolic_expression_p (XEXP (x, 0));
7266
 
7267
  if (UNARY_P (x))
7268
    return symbolic_expression_p (XEXP (x, 0));
7269
 
7270
  if (ARITHMETIC_P (x))
7271
    return (symbolic_expression_p (XEXP (x, 0))
7272
            || symbolic_expression_p (XEXP (x, 1)));
7273
 
7274
  return 0;
7275
}
7276
 
7277
/* Choose the section to use for the constant rtx expression X that has
7278
   mode MODE.  */
7279
 
7280
static section *
7281
mips_select_rtx_section (enum machine_mode mode, rtx x,
7282
                         unsigned HOST_WIDE_INT align)
7283
{
7284
  if (TARGET_MIPS16)
7285
    {
7286
      /* In mips16 mode, the constant table always goes in the same section
7287
         as the function, so that constants can be loaded using PC relative
7288
         addressing.  */
7289
      return function_section (current_function_decl);
7290
    }
7291
  else if (TARGET_EMBEDDED_DATA)
7292
    {
7293
      /* For embedded applications, always put constants in read-only data,
7294
         in order to reduce RAM usage.  */
7295
      return mergeable_constant_section (mode, align, 0);
7296
    }
7297
  else
7298
    {
7299
      /* For hosted applications, always put constants in small data if
7300
         possible, as this gives the best performance.  */
7301
      /* ??? Consider using mergeable small data sections.  */
7302
 
7303
      if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7304
          && mips_section_threshold > 0)
7305
        return get_named_section (NULL, ".sdata", 0);
7306
      else if (flag_pic && symbolic_expression_p (x))
7307
        return get_named_section (NULL, ".data.rel.ro", 3);
7308
      else
7309
        return mergeable_constant_section (mode, align, 0);
7310
    }
7311
}
7312
 
7313
/* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7314
 
7315
   The complication here is that, with the combination TARGET_ABICALLS
7316
   && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7317
   therefore not be included in the read-only part of a DSO.  Handle such
7318
   cases by selecting a normal data section instead of a read-only one.
7319
   The logic apes that in default_function_rodata_section.  */
7320
 
7321
static section *
7322
mips_function_rodata_section (tree decl)
7323
{
7324
  if (!TARGET_ABICALLS || TARGET_GPWORD)
7325
    return default_function_rodata_section (decl);
7326
 
7327
  if (decl && DECL_SECTION_NAME (decl))
7328
    {
7329
      const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7330
      if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7331
        {
7332
          char *rname = ASTRDUP (name);
7333
          rname[14] = 'd';
7334
          return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7335
        }
7336
      else if (flag_function_sections && flag_data_sections
7337
               && strncmp (name, ".text.", 6) == 0)
7338
        {
7339
          char *rname = ASTRDUP (name);
7340
          memcpy (rname + 1, "data", 4);
7341
          return get_section (rname, SECTION_WRITE, decl);
7342
        }
7343
    }
7344
  return data_section;
7345
}
7346
 
7347
/* Implement TARGET_IN_SMALL_DATA_P.  This function controls whether
7348
   locally-defined objects go in a small data section.  It also controls
7349
   the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
7350
   mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses.  */
7351
 
7352
static bool
7353
mips_in_small_data_p (tree decl)
7354
{
7355
  HOST_WIDE_INT size;
7356
 
7357
  if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7358
    return false;
7359
 
7360
  /* We don't yet generate small-data references for -mabicalls.  See related
7361
     -G handling in override_options.  */
7362
  if (TARGET_ABICALLS)
7363
    return false;
7364
 
7365
  if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7366
    {
7367
      const char *name;
7368
 
7369
      /* Reject anything that isn't in a known small-data section.  */
7370
      name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7371
      if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7372
        return false;
7373
 
7374
      /* If a symbol is defined externally, the assembler will use the
7375
         usual -G rules when deciding how to implement macros.  */
7376
      if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7377
        return true;
7378
    }
7379
  else if (TARGET_EMBEDDED_DATA)
7380
    {
7381
      /* Don't put constants into the small data section: we want them
7382
         to be in ROM rather than RAM.  */
7383
      if (TREE_CODE (decl) != VAR_DECL)
7384
        return false;
7385
 
7386
      if (TREE_READONLY (decl)
7387
          && !TREE_SIDE_EFFECTS (decl)
7388
          && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7389
        return false;
7390
    }
7391
 
7392
  size = int_size_in_bytes (TREE_TYPE (decl));
7393
  return (size > 0 && size <= mips_section_threshold);
7394
}
7395
 
7396
/* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P.  We don't want to use
7397
   anchors for small data: the GP register acts as an anchor in that
7398
   case.  We also don't want to use them for PC-relative accesses,
7399
   where the PC acts as an anchor.  */
7400
 
7401
static bool
7402
mips_use_anchors_for_symbol_p (rtx symbol)
7403
{
7404
  switch (mips_classify_symbol (symbol))
7405
    {
7406
    case SYMBOL_CONSTANT_POOL:
7407
    case SYMBOL_SMALL_DATA:
7408
      return false;
7409
 
7410
    default:
7411
      return true;
7412
    }
7413
}
7414
 
7415
/* See whether VALTYPE is a record whose fields should be returned in
7416
   floating-point registers.  If so, return the number of fields and
7417
   list them in FIELDS (which should have two elements).  Return 0
7418
   otherwise.
7419
 
7420
   For n32 & n64, a structure with one or two fields is returned in
7421
   floating-point registers as long as every field has a floating-point
7422
   type.  */
7423
 
7424
static int
7425
mips_fpr_return_fields (tree valtype, tree *fields)
7426
{
7427
  tree field;
7428
  int i;
7429
 
7430
  if (!TARGET_NEWABI)
7431
    return 0;
7432
 
7433
  if (TREE_CODE (valtype) != RECORD_TYPE)
7434
    return 0;
7435
 
7436
  i = 0;
7437
  for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7438
    {
7439
      if (TREE_CODE (field) != FIELD_DECL)
7440
        continue;
7441
 
7442
      if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7443
        return 0;
7444
 
7445
      if (i == 2)
7446
        return 0;
7447
 
7448
      fields[i++] = field;
7449
    }
7450
  return i;
7451
}
7452
 
7453
 
7454
/* Implement TARGET_RETURN_IN_MSB.  For n32 & n64, we should return
7455
   a value in the most significant part of $2/$3 if:
7456
 
7457
      - the target is big-endian;
7458
 
7459
      - the value has a structure or union type (we generalize this to
7460
        cover aggregates from other languages too); and
7461
 
7462
      - the structure is not returned in floating-point registers.  */
7463
 
7464
static bool
7465
mips_return_in_msb (tree valtype)
7466
{
7467
  tree fields[2];
7468
 
7469
  return (TARGET_NEWABI
7470
          && TARGET_BIG_ENDIAN
7471
          && AGGREGATE_TYPE_P (valtype)
7472
          && mips_fpr_return_fields (valtype, fields) == 0);
7473
}
7474
 
7475
 
7476
/* Return a composite value in a pair of floating-point registers.
7477
   MODE1 and OFFSET1 are the mode and byte offset for the first value,
7478
   likewise MODE2 and OFFSET2 for the second.  MODE is the mode of the
7479
   complete value.
7480
 
7481
   For n32 & n64, $f0 always holds the first value and $f2 the second.
7482
   Otherwise the values are packed together as closely as possible.  */
7483
 
7484
static rtx
7485
mips_return_fpr_pair (enum machine_mode mode,
7486
                      enum machine_mode mode1, HOST_WIDE_INT offset1,
7487
                      enum machine_mode mode2, HOST_WIDE_INT offset2)
7488
{
7489
  int inc;
7490
 
7491
  inc = (TARGET_NEWABI ? 2 : FP_INC);
7492
  return gen_rtx_PARALLEL
7493
    (mode,
7494
     gen_rtvec (2,
7495
                gen_rtx_EXPR_LIST (VOIDmode,
7496
                                   gen_rtx_REG (mode1, FP_RETURN),
7497
                                   GEN_INT (offset1)),
7498
                gen_rtx_EXPR_LIST (VOIDmode,
7499
                                   gen_rtx_REG (mode2, FP_RETURN + inc),
7500
                                   GEN_INT (offset2))));
7501
 
7502
}
7503
 
7504
 
7505
/* Implement FUNCTION_VALUE and LIBCALL_VALUE.  For normal calls,
7506
   VALTYPE is the return type and MODE is VOIDmode.  For libcalls,
7507
   VALTYPE is null and MODE is the mode of the return value.  */
7508
 
7509
rtx
7510
mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7511
                     enum machine_mode mode)
7512
{
7513
  if (valtype)
7514
    {
7515
      tree fields[2];
7516
      int unsignedp;
7517
 
7518
      mode = TYPE_MODE (valtype);
7519
      unsignedp = TYPE_UNSIGNED (valtype);
7520
 
7521
      /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7522
         true, we must promote the mode just as PROMOTE_MODE does.  */
7523
      mode = promote_mode (valtype, mode, &unsignedp, 1);
7524
 
7525
      /* Handle structures whose fields are returned in $f0/$f2.  */
7526
      switch (mips_fpr_return_fields (valtype, fields))
7527
        {
7528
        case 1:
7529
          return gen_rtx_REG (mode, FP_RETURN);
7530
 
7531
        case 2:
7532
          return mips_return_fpr_pair (mode,
7533
                                       TYPE_MODE (TREE_TYPE (fields[0])),
7534
                                       int_byte_position (fields[0]),
7535
                                       TYPE_MODE (TREE_TYPE (fields[1])),
7536
                                       int_byte_position (fields[1]));
7537
        }
7538
 
7539
      /* If a value is passed in the most significant part of a register, see
7540
         whether we have to round the mode up to a whole number of words.  */
7541
      if (mips_return_in_msb (valtype))
7542
        {
7543
          HOST_WIDE_INT size = int_size_in_bytes (valtype);
7544
          if (size % UNITS_PER_WORD != 0)
7545
            {
7546
              size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7547
              mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7548
            }
7549
        }
7550
 
7551
      /* For EABI, the class of return register depends entirely on MODE.
7552
         For example, "struct { some_type x; }" and "union { some_type x; }"
7553
         are returned in the same way as a bare "some_type" would be.
7554
         Other ABIs only use FPRs for scalar, complex or vector types.  */
7555
      if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7556
        return gen_rtx_REG (mode, GP_RETURN);
7557
    }
7558
 
7559
  if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7560
       || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7561
      && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7562
    return gen_rtx_REG (mode, FP_RETURN);
7563
 
7564
  /* Handle long doubles for n32 & n64.  */
7565
  if (mode == TFmode)
7566
    return mips_return_fpr_pair (mode,
7567
                                 DImode, 0,
7568
                                 DImode, GET_MODE_SIZE (mode) / 2);
7569
 
7570
  if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7571
      && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7572
    return mips_return_fpr_pair (mode,
7573
                                 GET_MODE_INNER (mode), 0,
7574
                                 GET_MODE_INNER (mode),
7575
                                 GET_MODE_SIZE (mode) / 2);
7576
 
7577
  return gen_rtx_REG (mode, GP_RETURN);
7578
}
7579
 
7580
/* Return nonzero when an argument must be passed by reference.  */
7581
 
7582
static bool
7583
mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7584
                        enum machine_mode mode, tree type,
7585
                        bool named ATTRIBUTE_UNUSED)
7586
{
7587
  if (mips_abi == ABI_EABI)
7588
    {
7589
      int size;
7590
 
7591
      /* ??? How should SCmode be handled?  */
7592
      if (mode == DImode || mode == DFmode)
7593
        return 0;
7594
 
7595
      size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
7596
      return size == -1 || size > UNITS_PER_WORD;
7597
    }
7598
  else
7599
    {
7600
      /* If we have a variable-sized parameter, we have no choice.  */
7601
      return targetm.calls.must_pass_in_stack (mode, type);
7602
    }
7603
}
7604
 
7605
static bool
7606
mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7607
                    enum machine_mode mode ATTRIBUTE_UNUSED,
7608
                    tree type ATTRIBUTE_UNUSED, bool named)
7609
{
7610
  return mips_abi == ABI_EABI && named;
7611
}
7612
 
7613
/* Return true if registers of class CLASS cannot change from mode FROM
7614
   to mode TO.  */
7615
 
7616
bool
7617
mips_cannot_change_mode_class (enum machine_mode from,
7618
                               enum machine_mode to, enum reg_class class)
7619
{
7620
  if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7621
      && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7622
    {
7623
      if (TARGET_BIG_ENDIAN)
7624
        {
7625
          /* When a multi-word value is stored in paired floating-point
7626
             registers, the first register always holds the low word.
7627
             We therefore can't allow FPRs to change between single-word
7628
             and multi-word modes.  */
7629
          if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7630
            return true;
7631
        }
7632
      else
7633
        {
7634
          /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7635
             in LO and HI, the high word always comes first.  We therefore
7636
             can't allow values stored in HI to change between single-word
7637
             and multi-word modes.
7638
             This rule applies to both the original HI/LO pair and the new
7639
             DSP accumulators.  */
7640
          if (reg_classes_intersect_p (ACC_REGS, class))
7641
            return true;
7642
        }
7643
    }
7644
  /* Loading a 32-bit value into a 64-bit floating-point register
7645
     will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7646
     We can't allow 64-bit float registers to change from SImode to
7647
     to a wider mode.  */
7648
  if (TARGET_FLOAT64
7649
      && from == SImode
7650
      && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7651
      && reg_classes_intersect_p (FP_REGS, class))
7652
    return true;
7653
  return false;
7654
}
7655
 
7656
/* Return true if X should not be moved directly into register $25.
7657
   We need this because many versions of GAS will treat "la $25,foo" as
7658
   part of a call sequence and so allow a global "foo" to be lazily bound.  */
7659
 
7660
bool
7661
mips_dangerous_for_la25_p (rtx x)
7662
{
7663
  HOST_WIDE_INT offset;
7664
 
7665
  if (TARGET_EXPLICIT_RELOCS)
7666
    return false;
7667
 
7668
  mips_split_const (x, &x, &offset);
7669
  return global_got_operand (x, VOIDmode);
7670
}
7671
 
7672
/* Implement PREFERRED_RELOAD_CLASS.  */
7673
 
7674
enum reg_class
7675
mips_preferred_reload_class (rtx x, enum reg_class class)
7676
{
7677
  if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7678
    return LEA_REGS;
7679
 
7680
  if (TARGET_HARD_FLOAT
7681
      && FLOAT_MODE_P (GET_MODE (x))
7682
      && reg_class_subset_p (FP_REGS, class))
7683
    return FP_REGS;
7684
 
7685
  if (reg_class_subset_p (GR_REGS, class))
7686
    class = GR_REGS;
7687
 
7688
  if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7689
    class = M16_REGS;
7690
 
7691
  return class;
7692
}
7693
 
7694
/* This function returns the register class required for a secondary
7695
   register when copying between one of the registers in CLASS, and X,
7696
   using MODE.  If IN_P is nonzero, the copy is going from X to the
7697
   register, otherwise the register is the source.  A return value of
7698
   NO_REGS means that no secondary register is required.  */
7699
 
7700
enum reg_class
7701
mips_secondary_reload_class (enum reg_class class,
7702
                             enum machine_mode mode, rtx x, int in_p)
7703
{
7704
  enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7705
  int regno = -1;
7706
  int gp_reg_p;
7707
 
7708
  if (REG_P (x)|| GET_CODE (x) == SUBREG)
7709
    regno = true_regnum (x);
7710
 
7711
  gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7712
 
7713
  if (mips_dangerous_for_la25_p (x))
7714
    {
7715
      gr_regs = LEA_REGS;
7716
      if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7717
        return gr_regs;
7718
    }
7719
 
7720
  /* Copying from HI or LO to anywhere other than a general register
7721
     requires a general register.
7722
     This rule applies to both the original HI/LO pair and the new
7723
     DSP accumulators.  */
7724
  if (reg_class_subset_p (class, ACC_REGS))
7725
    {
7726
      if (TARGET_MIPS16 && in_p)
7727
        {
7728
          /* We can't really copy to HI or LO at all in mips16 mode.  */
7729
          return M16_REGS;
7730
        }
7731
      return gp_reg_p ? NO_REGS : gr_regs;
7732
    }
7733
  if (ACC_REG_P (regno))
7734
    {
7735
      if (TARGET_MIPS16 && ! in_p)
7736
        {
7737
          /* We can't really copy to HI or LO at all in mips16 mode.  */
7738
          return M16_REGS;
7739
        }
7740
      return class == gr_regs ? NO_REGS : gr_regs;
7741
    }
7742
 
7743
  /* We can only copy a value to a condition code register from a
7744
     floating point register, and even then we require a scratch
7745
     floating point register.  We can only copy a value out of a
7746
     condition code register into a general register.  */
7747
  if (class == ST_REGS)
7748
    {
7749
      if (in_p)
7750
        return FP_REGS;
7751
      return gp_reg_p ? NO_REGS : gr_regs;
7752
    }
7753
  if (ST_REG_P (regno))
7754
    {
7755
      if (! in_p)
7756
        return FP_REGS;
7757
      return class == gr_regs ? NO_REGS : gr_regs;
7758
    }
7759
 
7760
  if (class == FP_REGS)
7761
    {
7762
      if (MEM_P (x))
7763
        {
7764
          /* In this case we can use lwc1, swc1, ldc1 or sdc1.  */
7765
          return NO_REGS;
7766
        }
7767
      else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7768
        {
7769
          /* We can use the l.s and l.d macros to load floating-point
7770
             constants.  ??? For l.s, we could probably get better
7771
             code by returning GR_REGS here.  */
7772
          return NO_REGS;
7773
        }
7774
      else if (gp_reg_p || x == CONST0_RTX (mode))
7775
        {
7776
          /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1.  */
7777
          return NO_REGS;
7778
        }
7779
      else if (FP_REG_P (regno))
7780
        {
7781
          /* In this case we can use mov.s or mov.d.  */
7782
          return NO_REGS;
7783
        }
7784
      else
7785
        {
7786
          /* Otherwise, we need to reload through an integer register.  */
7787
          return gr_regs;
7788
        }
7789
    }
7790
 
7791
  /* In mips16 mode, going between memory and anything but M16_REGS
7792
     requires an M16_REG.  */
7793
  if (TARGET_MIPS16)
7794
    {
7795
      if (class != M16_REGS && class != M16_NA_REGS)
7796
        {
7797
          if (gp_reg_p)
7798
            return NO_REGS;
7799
          return M16_REGS;
7800
        }
7801
      if (! gp_reg_p)
7802
        {
7803
          if (class == M16_REGS || class == M16_NA_REGS)
7804
            return NO_REGS;
7805
          return M16_REGS;
7806
        }
7807
    }
7808
 
7809
  return NO_REGS;
7810
}
7811
 
7812
/* Implement CLASS_MAX_NREGS.
7813
 
7814
   Usually all registers are word-sized.  The only supported exception
7815
   is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7816
   registers.  A word-based calculation is correct even in that case,
7817
   since -msingle-float disallows multi-FPR values.
7818
 
7819
   The FP status registers are an exception to this rule.  They are always
7820
   4 bytes wide as they only hold condition code modes, and CCmode is always
7821
   considered to be 4 bytes wide.  */
7822
 
7823
int
7824
mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7825
                      enum machine_mode mode)
7826
{
7827
  if (class == ST_REGS)
7828
    return (GET_MODE_SIZE (mode) + 3) / 4;
7829
  else
7830
    return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7831
}
7832
 
7833
static bool
7834
mips_valid_pointer_mode (enum machine_mode mode)
7835
{
7836
  return (mode == SImode || (TARGET_64BIT && mode == DImode));
7837
}
7838
 
7839
/* Target hook for vector_mode_supported_p.  */
7840
 
7841
static bool
7842
mips_vector_mode_supported_p (enum machine_mode mode)
7843
{
7844
  switch (mode)
7845
    {
7846
    case V2SFmode:
7847
      return TARGET_PAIRED_SINGLE_FLOAT;
7848
 
7849
    case V2HImode:
7850
    case V4QImode:
7851
      return TARGET_DSP;
7852
 
7853
    default:
7854
      return false;
7855
    }
7856
}
7857
 
7858
/* If we can access small data directly (using gp-relative relocation
7859
   operators) return the small data pointer, otherwise return null.
7860
 
7861
   For each mips16 function which refers to GP relative symbols, we
7862
   use a pseudo register, initialized at the start of the function, to
7863
   hold the $gp value.  */
7864
 
7865
static rtx
7866
mips16_gp_pseudo_reg (void)
7867
{
7868
  if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7869
    {
7870
      rtx unspec;
7871
      rtx insn, scan;
7872
 
7873
      cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7874
 
7875
      /* We want to initialize this to a value which gcc will believe
7876
         is constant.  */
7877
      start_sequence ();
7878
      unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7879
      emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7880
                      gen_rtx_CONST (Pmode, unspec));
7881
      insn = get_insns ();
7882
      end_sequence ();
7883
 
7884
      push_topmost_sequence ();
7885
      /* We need to emit the initialization after the FUNCTION_BEG
7886
         note, so that it will be integrated.  */
7887
      for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7888
        if (NOTE_P (scan)
7889
            && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7890
          break;
7891
      if (scan == NULL_RTX)
7892
        scan = get_insns ();
7893
      insn = emit_insn_after (insn, scan);
7894
      pop_topmost_sequence ();
7895
    }
7896
 
7897
  return cfun->machine->mips16_gp_pseudo_rtx;
7898
}
7899
 
7900
/* Write out code to move floating point arguments in or out of
7901
   general registers.  Output the instructions to FILE.  FP_CODE is
7902
   the code describing which arguments are present (see the comment at
7903
   the definition of CUMULATIVE_ARGS in mips.h).  FROM_FP_P is nonzero if
7904
   we are copying from the floating point registers.  */
7905
 
7906
static void
7907
mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7908
{
7909
  const char *s;
7910
  int gparg, fparg;
7911
  unsigned int f;
7912
 
7913
  /* This code only works for the original 32 bit ABI and the O64 ABI.  */
7914
  gcc_assert (TARGET_OLDABI);
7915
 
7916
  if (from_fp_p)
7917
    s = "mfc1";
7918
  else
7919
    s = "mtc1";
7920
  gparg = GP_ARG_FIRST;
7921
  fparg = FP_ARG_FIRST;
7922
  for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7923
    {
7924
      if ((f & 3) == 1)
7925
        {
7926
          if ((fparg & 1) != 0)
7927
            ++fparg;
7928
          fprintf (file, "\t%s\t%s,%s\n", s,
7929
                   reg_names[gparg], reg_names[fparg]);
7930
        }
7931
      else if ((f & 3) == 2)
7932
        {
7933
          if (TARGET_64BIT)
7934
            fprintf (file, "\td%s\t%s,%s\n", s,
7935
                     reg_names[gparg], reg_names[fparg]);
7936
          else
7937
            {
7938
              if ((fparg & 1) != 0)
7939
                ++fparg;
7940
              if (TARGET_BIG_ENDIAN)
7941
                fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7942
                         reg_names[gparg], reg_names[fparg + 1], s,
7943
                         reg_names[gparg + 1], reg_names[fparg]);
7944
              else
7945
                fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7946
                         reg_names[gparg], reg_names[fparg], s,
7947
                         reg_names[gparg + 1], reg_names[fparg + 1]);
7948
              ++gparg;
7949
              ++fparg;
7950
            }
7951
        }
7952
      else
7953
        gcc_unreachable ();
7954
 
7955
      ++gparg;
7956
      ++fparg;
7957
    }
7958
}
7959
 
7960
/* Build a mips16 function stub.  This is used for functions which
7961
   take arguments in the floating point registers.  It is 32 bit code
7962
   that moves the floating point args into the general registers, and
7963
   then jumps to the 16 bit code.  */
7964
 
7965
static void
7966
build_mips16_function_stub (FILE *file)
7967
{
7968
  const char *fnname;
7969
  char *secname, *stubname;
7970
  tree stubid, stubdecl;
7971
  int need_comma;
7972
  unsigned int f;
7973
 
7974
  fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7975
  secname = (char *) alloca (strlen (fnname) + 20);
7976
  sprintf (secname, ".mips16.fn.%s", fnname);
7977
  stubname = (char *) alloca (strlen (fnname) + 20);
7978
  sprintf (stubname, "__fn_stub_%s", fnname);
7979
  stubid = get_identifier (stubname);
7980
  stubdecl = build_decl (FUNCTION_DECL, stubid,
7981
                         build_function_type (void_type_node, NULL_TREE));
7982
  DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7983
 
7984
  fprintf (file, "\t# Stub function for %s (", current_function_name ());
7985
  need_comma = 0;
7986
  for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7987
    {
7988
      fprintf (file, "%s%s",
7989
               need_comma ? ", " : "",
7990
               (f & 3) == 1 ? "float" : "double");
7991
      need_comma = 1;
7992
    }
7993
  fprintf (file, ")\n");
7994
 
7995
  fprintf (file, "\t.set\tnomips16\n");
7996
  switch_to_section (function_section (stubdecl));
7997
  ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7998
 
7999
  /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8000
     within a .ent, and we cannot emit another .ent.  */
8001
  if (!FUNCTION_NAME_ALREADY_DECLARED)
8002
    {
8003
      fputs ("\t.ent\t", file);
8004
      assemble_name (file, stubname);
8005
      fputs ("\n", file);
8006
    }
8007
 
8008
  assemble_name (file, stubname);
8009
  fputs (":\n", file);
8010
 
8011
  /* We don't want the assembler to insert any nops here.  */
8012
  fprintf (file, "\t.set\tnoreorder\n");
8013
 
8014
  mips16_fp_args (file, current_function_args_info.fp_code, 1);
8015
 
8016
  fprintf (asm_out_file, "\t.set\tnoat\n");
8017
  fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8018
  assemble_name (file, fnname);
8019
  fprintf (file, "\n");
8020
  fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8021
  fprintf (asm_out_file, "\t.set\tat\n");
8022
 
8023
  /* Unfortunately, we can't fill the jump delay slot.  We can't fill
8024
     with one of the mfc1 instructions, because the result is not
8025
     available for one instruction, so if the very first instruction
8026
     in the function refers to the register, it will see the wrong
8027
     value.  */
8028
  fprintf (file, "\tnop\n");
8029
 
8030
  fprintf (file, "\t.set\treorder\n");
8031
 
8032
  if (!FUNCTION_NAME_ALREADY_DECLARED)
8033
    {
8034
      fputs ("\t.end\t", file);
8035
      assemble_name (file, stubname);
8036
      fputs ("\n", file);
8037
    }
8038
 
8039
  fprintf (file, "\t.set\tmips16\n");
8040
 
8041
  switch_to_section (function_section (current_function_decl));
8042
}
8043
 
8044
/* We keep a list of functions for which we have already built stubs
8045
   in build_mips16_call_stub.  */
8046
 
8047
struct mips16_stub
8048
{
8049
  struct mips16_stub *next;
8050
  char *name;
8051
  int fpret;
8052
};
8053
 
8054
static struct mips16_stub *mips16_stubs;
8055
 
8056
/* Build a call stub for a mips16 call.  A stub is needed if we are
8057
   passing any floating point values which should go into the floating
8058
   point registers.  If we are, and the call turns out to be to a 32
8059
   bit function, the stub will be used to move the values into the
8060
   floating point registers before calling the 32 bit function.  The
8061
   linker will magically adjust the function call to either the 16 bit
8062
   function or the 32 bit stub, depending upon where the function call
8063
   is actually defined.
8064
 
8065
   Similarly, we need a stub if the return value might come back in a
8066
   floating point register.
8067
 
8068
   RETVAL is the location of the return value, or null if this is
8069
   a call rather than a call_value.  FN is the address of the
8070
   function and ARG_SIZE is the size of the arguments.  FP_CODE
8071
   is the code built by function_arg.  This function returns a nonzero
8072
   value if it builds the call instruction itself.  */
8073
 
8074
int
8075
build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8076
{
8077
  int fpret;
8078
  const char *fnname;
8079
  char *secname, *stubname;
8080
  struct mips16_stub *l;
8081
  tree stubid, stubdecl;
8082
  int need_comma;
8083
  unsigned int f;
8084
 
8085
  /* We don't need to do anything if we aren't in mips16 mode, or if
8086
     we were invoked with the -msoft-float option.  */
8087
  if (! TARGET_MIPS16 || ! mips16_hard_float)
8088
    return 0;
8089
 
8090
  /* Figure out whether the value might come back in a floating point
8091
     register.  */
8092
  fpret = (retval != 0
8093
           && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8094
           && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8095
 
8096
  /* We don't need to do anything if there were no floating point
8097
     arguments and the value will not be returned in a floating point
8098
     register.  */
8099
  if (fp_code == 0 && ! fpret)
8100
    return 0;
8101
 
8102
  /* We don't need to do anything if this is a call to a special
8103
     mips16 support function.  */
8104
  if (GET_CODE (fn) == SYMBOL_REF
8105
      && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8106
    return 0;
8107
 
8108
  /* This code will only work for o32 and o64 abis.  The other ABI's
8109
     require more sophisticated support.  */
8110
  gcc_assert (TARGET_OLDABI);
8111
 
8112
  /* We can only handle SFmode and DFmode floating point return
8113
     values.  */
8114
  if (fpret)
8115
    gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
8116
 
8117
  /* If we're calling via a function pointer, then we must always call
8118
     via a stub.  There are magic stubs provided in libgcc.a for each
8119
     of the required cases.  Each of them expects the function address
8120
     to arrive in register $2.  */
8121
 
8122
  if (GET_CODE (fn) != SYMBOL_REF)
8123
    {
8124
      char buf[30];
8125
      tree id;
8126
      rtx stub_fn, insn;
8127
 
8128
      /* ??? If this code is modified to support other ABI's, we need
8129
         to handle PARALLEL return values here.  */
8130
 
8131
      sprintf (buf, "__mips16_call_stub_%s%d",
8132
               (fpret
8133
                ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8134
                : ""),
8135
               fp_code);
8136
      id = get_identifier (buf);
8137
      stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8138
 
8139
      emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8140
 
8141
      if (retval == NULL_RTX)
8142
        insn = gen_call_internal (stub_fn, arg_size);
8143
      else
8144
        insn = gen_call_value_internal (retval, stub_fn, arg_size);
8145
      insn = emit_call_insn (insn);
8146
 
8147
      /* Put the register usage information on the CALL.  */
8148
      CALL_INSN_FUNCTION_USAGE (insn) =
8149
        gen_rtx_EXPR_LIST (VOIDmode,
8150
                           gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8151
                           CALL_INSN_FUNCTION_USAGE (insn));
8152
 
8153
      /* If we are handling a floating point return value, we need to
8154
         save $18 in the function prologue.  Putting a note on the
8155
         call will mean that regs_ever_live[$18] will be true if the
8156
         call is not eliminated, and we can check that in the prologue
8157
         code.  */
8158
      if (fpret)
8159
        CALL_INSN_FUNCTION_USAGE (insn) =
8160
          gen_rtx_EXPR_LIST (VOIDmode,
8161
                             gen_rtx_USE (VOIDmode,
8162
                                          gen_rtx_REG (word_mode, 18)),
8163
                             CALL_INSN_FUNCTION_USAGE (insn));
8164
 
8165
      /* Return 1 to tell the caller that we've generated the call
8166
         insn.  */
8167
      return 1;
8168
    }
8169
 
8170
  /* We know the function we are going to call.  If we have already
8171
     built a stub, we don't need to do anything further.  */
8172
 
8173
  fnname = XSTR (fn, 0);
8174
  for (l = mips16_stubs; l != NULL; l = l->next)
8175
    if (strcmp (l->name, fnname) == 0)
8176
      break;
8177
 
8178
  if (l == NULL)
8179
    {
8180
      /* Build a special purpose stub.  When the linker sees a
8181
         function call in mips16 code, it will check where the target
8182
         is defined.  If the target is a 32 bit call, the linker will
8183
         search for the section defined here.  It can tell which
8184
         symbol this section is associated with by looking at the
8185
         relocation information (the name is unreliable, since this
8186
         might be a static function).  If such a section is found, the
8187
         linker will redirect the call to the start of the magic
8188
         section.
8189
 
8190
         If the function does not return a floating point value, the
8191
         special stub section is named
8192
             .mips16.call.FNNAME
8193
 
8194
         If the function does return a floating point value, the stub
8195
         section is named
8196
             .mips16.call.fp.FNNAME
8197
         */
8198
 
8199
      secname = (char *) alloca (strlen (fnname) + 40);
8200
      sprintf (secname, ".mips16.call.%s%s",
8201
               fpret ? "fp." : "",
8202
               fnname);
8203
      stubname = (char *) alloca (strlen (fnname) + 20);
8204
      sprintf (stubname, "__call_stub_%s%s",
8205
               fpret ? "fp_" : "",
8206
               fnname);
8207
      stubid = get_identifier (stubname);
8208
      stubdecl = build_decl (FUNCTION_DECL, stubid,
8209
                             build_function_type (void_type_node, NULL_TREE));
8210
      DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8211
 
8212
      fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8213
               (fpret
8214
                ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8215
                : ""),
8216
               fnname);
8217
      need_comma = 0;
8218
      for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8219
        {
8220
          fprintf (asm_out_file, "%s%s",
8221
                   need_comma ? ", " : "",
8222
                   (f & 3) == 1 ? "float" : "double");
8223
          need_comma = 1;
8224
        }
8225
      fprintf (asm_out_file, ")\n");
8226
 
8227
      fprintf (asm_out_file, "\t.set\tnomips16\n");
8228
      assemble_start_function (stubdecl, stubname);
8229
 
8230
      if (!FUNCTION_NAME_ALREADY_DECLARED)
8231
        {
8232
          fputs ("\t.ent\t", asm_out_file);
8233
          assemble_name (asm_out_file, stubname);
8234
          fputs ("\n", asm_out_file);
8235
 
8236
          assemble_name (asm_out_file, stubname);
8237
          fputs (":\n", asm_out_file);
8238
        }
8239
 
8240
      /* We build the stub code by hand.  That's the only way we can
8241
         do it, since we can't generate 32 bit code during a 16 bit
8242
         compilation.  */
8243
 
8244
      /* We don't want the assembler to insert any nops here.  */
8245
      fprintf (asm_out_file, "\t.set\tnoreorder\n");
8246
 
8247
      mips16_fp_args (asm_out_file, fp_code, 0);
8248
 
8249
      if (! fpret)
8250
        {
8251
          fprintf (asm_out_file, "\t.set\tnoat\n");
8252
          fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8253
                   fnname);
8254
          fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8255
          fprintf (asm_out_file, "\t.set\tat\n");
8256
          /* Unfortunately, we can't fill the jump delay slot.  We
8257
             can't fill with one of the mtc1 instructions, because the
8258
             result is not available for one instruction, so if the
8259
             very first instruction in the function refers to the
8260
             register, it will see the wrong value.  */
8261
          fprintf (asm_out_file, "\tnop\n");
8262
        }
8263
      else
8264
        {
8265
          fprintf (asm_out_file, "\tmove\t%s,%s\n",
8266
                   reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8267
          fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8268
          /* As above, we can't fill the delay slot.  */
8269
          fprintf (asm_out_file, "\tnop\n");
8270
          if (GET_MODE (retval) == SFmode)
8271
            fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8272
                     reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8273
          else
8274
            {
8275
              if (TARGET_BIG_ENDIAN)
8276
                {
8277
                  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8278
                           reg_names[GP_REG_FIRST + 2],
8279
                           reg_names[FP_REG_FIRST + 1]);
8280
                  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8281
                           reg_names[GP_REG_FIRST + 3],
8282
                           reg_names[FP_REG_FIRST + 0]);
8283
                }
8284
              else
8285
                {
8286
                  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8287
                           reg_names[GP_REG_FIRST + 2],
8288
                           reg_names[FP_REG_FIRST + 0]);
8289
                  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8290
                           reg_names[GP_REG_FIRST + 3],
8291
                           reg_names[FP_REG_FIRST + 1]);
8292
                }
8293
            }
8294
          fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8295
          /* As above, we can't fill the delay slot.  */
8296
          fprintf (asm_out_file, "\tnop\n");
8297
        }
8298
 
8299
      fprintf (asm_out_file, "\t.set\treorder\n");
8300
 
8301
#ifdef ASM_DECLARE_FUNCTION_SIZE
8302
      ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8303
#endif
8304
 
8305
      if (!FUNCTION_NAME_ALREADY_DECLARED)
8306
        {
8307
          fputs ("\t.end\t", asm_out_file);
8308
          assemble_name (asm_out_file, stubname);
8309
          fputs ("\n", asm_out_file);
8310
        }
8311
 
8312
      fprintf (asm_out_file, "\t.set\tmips16\n");
8313
 
8314
      /* Record this stub.  */
8315
      l = (struct mips16_stub *) xmalloc (sizeof *l);
8316
      l->name = xstrdup (fnname);
8317
      l->fpret = fpret;
8318
      l->next = mips16_stubs;
8319
      mips16_stubs = l;
8320
    }
8321
 
8322
  /* If we expect a floating point return value, but we've built a
8323
     stub which does not expect one, then we're in trouble.  We can't
8324
     use the existing stub, because it won't handle the floating point
8325
     value.  We can't build a new stub, because the linker won't know
8326
     which stub to use for the various calls in this object file.
8327
     Fortunately, this case is illegal, since it means that a function
8328
     was declared in two different ways in a single compilation.  */
8329
  if (fpret && ! l->fpret)
8330
    error ("cannot handle inconsistent calls to %qs", fnname);
8331
 
8332
  /* If we are calling a stub which handles a floating point return
8333
     value, we need to arrange to save $18 in the prologue.  We do
8334
     this by marking the function call as using the register.  The
8335
     prologue will later see that it is used, and emit code to save
8336
     it.  */
8337
 
8338
  if (l->fpret)
8339
    {
8340
      rtx insn;
8341
 
8342
      if (retval == NULL_RTX)
8343
        insn = gen_call_internal (fn, arg_size);
8344
      else
8345
        insn = gen_call_value_internal (retval, fn, arg_size);
8346
      insn = emit_call_insn (insn);
8347
 
8348
      CALL_INSN_FUNCTION_USAGE (insn) =
8349
        gen_rtx_EXPR_LIST (VOIDmode,
8350
                           gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8351
                           CALL_INSN_FUNCTION_USAGE (insn));
8352
 
8353
      /* Return 1 to tell the caller that we've generated the call
8354
         insn.  */
8355
      return 1;
8356
    }
8357
 
8358
  /* Return 0 to let the caller generate the call insn.  */
8359
  return 0;
8360
}
8361
 
8362
/* An entry in the mips16 constant pool.  VALUE is the pool constant,
8363
   MODE is its mode, and LABEL is the CODE_LABEL associated with it.  */
8364
 
8365
struct mips16_constant {
8366
  struct mips16_constant *next;
8367
  rtx value;
8368
  rtx label;
8369
  enum machine_mode mode;
8370
};
8371
 
8372
/* Information about an incomplete mips16 constant pool.  FIRST is the
8373
   first constant, HIGHEST_ADDRESS is the highest address that the first
8374
   byte of the pool can have, and INSN_ADDRESS is the current instruction
8375
   address.  */
8376
 
8377
struct mips16_constant_pool {
8378
  struct mips16_constant *first;
8379
  int highest_address;
8380
  int insn_address;
8381
};
8382
 
8383
/* Add constant VALUE to POOL and return its label.  MODE is the
8384
   value's mode (used for CONST_INTs, etc.).  */
8385
 
8386
static rtx
8387
add_constant (struct mips16_constant_pool *pool,
8388
              rtx value, enum machine_mode mode)
8389
{
8390
  struct mips16_constant **p, *c;
8391
  bool first_of_size_p;
8392
 
8393
  /* See whether the constant is already in the pool.  If so, return the
8394
     existing label, otherwise leave P pointing to the place where the
8395
     constant should be added.
8396
 
8397
     Keep the pool sorted in increasing order of mode size so that we can
8398
     reduce the number of alignments needed.  */
8399
  first_of_size_p = true;
8400
  for (p = &pool->first; *p != 0; p = &(*p)->next)
8401
    {
8402
      if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8403
        return (*p)->label;
8404
      if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8405
        break;
8406
      if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8407
        first_of_size_p = false;
8408
    }
8409
 
8410
  /* In the worst case, the constant needed by the earliest instruction
8411
     will end up at the end of the pool.  The entire pool must then be
8412
     accessible from that instruction.
8413
 
8414
     When adding the first constant, set the pool's highest address to
8415
     the address of the first out-of-range byte.  Adjust this address
8416
     downwards each time a new constant is added.  */
8417
  if (pool->first == 0)
8418
    /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8419
       is the address of the instruction with the lowest two bits clear.
8420
       The base PC value for ld has the lowest three bits clear.  Assume
8421
       the worst case here.  */
8422
    pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8423
  pool->highest_address -= GET_MODE_SIZE (mode);
8424
  if (first_of_size_p)
8425
    /* Take into account the worst possible padding due to alignment.  */
8426
    pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8427
 
8428
  /* Create a new entry.  */
8429
  c = (struct mips16_constant *) xmalloc (sizeof *c);
8430
  c->value = value;
8431
  c->mode = mode;
8432
  c->label = gen_label_rtx ();
8433
  c->next = *p;
8434
  *p = c;
8435
 
8436
  return c->label;
8437
}
8438
 
8439
/* Output constant VALUE after instruction INSN and return the last
8440
   instruction emitted.  MODE is the mode of the constant.  */
8441
 
8442
static rtx
8443
dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8444
{
8445
  switch (GET_MODE_CLASS (mode))
8446
    {
8447
    case MODE_INT:
8448
      {
8449
        rtx size = GEN_INT (GET_MODE_SIZE (mode));
8450
        return emit_insn_after (gen_consttable_int (value, size), insn);
8451
      }
8452
 
8453
    case MODE_FLOAT:
8454
      return emit_insn_after (gen_consttable_float (value), insn);
8455
 
8456
    case MODE_VECTOR_FLOAT:
8457
    case MODE_VECTOR_INT:
8458
      {
8459
        int i;
8460
        for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8461
          insn = dump_constants_1 (GET_MODE_INNER (mode),
8462
                                   CONST_VECTOR_ELT (value, i), insn);
8463
        return insn;
8464
      }
8465
 
8466
    default:
8467
      gcc_unreachable ();
8468
    }
8469
}
8470
 
8471
 
8472
/* Dump out the constants in CONSTANTS after INSN.  */
8473
 
8474
static void
8475
dump_constants (struct mips16_constant *constants, rtx insn)
8476
{
8477
  struct mips16_constant *c, *next;
8478
  int align;
8479
 
8480
  align = 0;
8481
  for (c = constants; c != NULL; c = next)
8482
    {
8483
      /* If necessary, increase the alignment of PC.  */
8484
      if (align < GET_MODE_SIZE (c->mode))
8485
        {
8486
          int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8487
          insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8488
        }
8489
      align = GET_MODE_SIZE (c->mode);
8490
 
8491
      insn = emit_label_after (c->label, insn);
8492
      insn = dump_constants_1 (c->mode, c->value, insn);
8493
 
8494
      next = c->next;
8495
      free (c);
8496
    }
8497
 
8498
  emit_barrier_after (insn);
8499
}
8500
 
8501
/* Return the length of instruction INSN.  */
8502
 
8503
static int
8504
mips16_insn_length (rtx insn)
8505
{
8506
  if (JUMP_P (insn))
8507
    {
8508
      rtx body = PATTERN (insn);
8509
      if (GET_CODE (body) == ADDR_VEC)
8510
        return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8511
      if (GET_CODE (body) == ADDR_DIFF_VEC)
8512
        return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8513
    }
8514
  return get_attr_length (insn);
8515
}
8516
 
8517
/* Rewrite *X so that constant pool references refer to the constant's
8518
   label instead.  DATA points to the constant pool structure.  */
8519
 
8520
static int
8521
mips16_rewrite_pool_refs (rtx *x, void *data)
8522
{
8523
  struct mips16_constant_pool *pool = data;
8524
  if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8525
    *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8526
                                                 get_pool_constant (*x),
8527
                                                 get_pool_mode (*x)));
8528
  return 0;
8529
}
8530
 
8531
/* Build MIPS16 constant pools.  */
8532
 
8533
static void
8534
mips16_lay_out_constants (void)
8535
{
8536
  struct mips16_constant_pool pool;
8537
  rtx insn, barrier;
8538
 
8539
  barrier = 0;
8540
  memset (&pool, 0, sizeof (pool));
8541
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8542
    {
8543
      /* Rewrite constant pool references in INSN.  */
8544
      if (INSN_P (insn))
8545
        for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8546
 
8547
      pool.insn_address += mips16_insn_length (insn);
8548
 
8549
      if (pool.first != NULL)
8550
        {
8551
          /* If there are no natural barriers between the first user of
8552
             the pool and the highest acceptable address, we'll need to
8553
             create a new instruction to jump around the constant pool.
8554
             In the worst case, this instruction will be 4 bytes long.
8555
 
8556
             If it's too late to do this transformation after INSN,
8557
             do it immediately before INSN.  */
8558
          if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8559
            {
8560
              rtx label, jump;
8561
 
8562
              label = gen_label_rtx ();
8563
 
8564
              jump = emit_jump_insn_before (gen_jump (label), insn);
8565
              JUMP_LABEL (jump) = label;
8566
              LABEL_NUSES (label) = 1;
8567
              barrier = emit_barrier_after (jump);
8568
 
8569
              emit_label_after (label, barrier);
8570
              pool.insn_address += 4;
8571
            }
8572
 
8573
          /* See whether the constant pool is now out of range of the first
8574
             user.  If so, output the constants after the previous barrier.
8575
             Note that any instructions between BARRIER and INSN (inclusive)
8576
             will use negative offsets to refer to the pool.  */
8577
          if (pool.insn_address > pool.highest_address)
8578
            {
8579
              dump_constants (pool.first, barrier);
8580
              pool.first = NULL;
8581
              barrier = 0;
8582
            }
8583
          else if (BARRIER_P (insn))
8584
            barrier = insn;
8585
        }
8586
    }
8587
  dump_constants (pool.first, get_last_insn ());
8588
}
8589
 
8590
/* A temporary variable used by for_each_rtx callbacks, etc.  */
8591
static rtx mips_sim_insn;
8592
 
8593
/* A structure representing the state of the processor pipeline.
8594
   Used by the mips_sim_* family of functions.  */
8595
struct mips_sim {
8596
  /* The maximum number of instructions that can be issued in a cycle.
8597
     (Caches mips_issue_rate.)  */
8598
  unsigned int issue_rate;
8599
 
8600
  /* The current simulation time.  */
8601
  unsigned int time;
8602
 
8603
  /* How many more instructions can be issued in the current cycle.  */
8604
  unsigned int insns_left;
8605
 
8606
  /* LAST_SET[X].INSN is the last instruction to set register X.
8607
     LAST_SET[X].TIME is the time at which that instruction was issued.
8608
     INSN is null if no instruction has yet set register X.  */
8609
  struct {
8610
    rtx insn;
8611
    unsigned int time;
8612
  } last_set[FIRST_PSEUDO_REGISTER];
8613
 
8614
  /* The pipeline's current DFA state.  */
8615
  state_t dfa_state;
8616
};
8617
 
8618
/* Reset STATE to the initial simulation state.  */
8619
 
8620
static void
8621
mips_sim_reset (struct mips_sim *state)
8622
{
8623
  state->time = 0;
8624
  state->insns_left = state->issue_rate;
8625
  memset (&state->last_set, 0, sizeof (state->last_set));
8626
  state_reset (state->dfa_state);
8627
}
8628
 
8629
/* Initialize STATE before its first use.  DFA_STATE points to an
8630
   allocated but uninitialized DFA state.  */
8631
 
8632
static void
8633
mips_sim_init (struct mips_sim *state, state_t dfa_state)
8634
{
8635
  state->issue_rate = mips_issue_rate ();
8636
  state->dfa_state = dfa_state;
8637
  mips_sim_reset (state);
8638
}
8639
 
8640
/* Advance STATE by one clock cycle.  */
8641
 
8642
static void
8643
mips_sim_next_cycle (struct mips_sim *state)
8644
{
8645
  state->time++;
8646
  state->insns_left = state->issue_rate;
8647
  state_transition (state->dfa_state, 0);
8648
}
8649
 
8650
/* Advance simulation state STATE until instruction INSN can read
8651
   register REG.  */
8652
 
8653
static void
8654
mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8655
{
8656
  unsigned int i;
8657
 
8658
  for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8659
    if (state->last_set[REGNO (reg) + i].insn != 0)
8660
      {
8661
        unsigned int t;
8662
 
8663
        t = state->last_set[REGNO (reg) + i].time;
8664
        t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8665
        while (state->time < t)
8666
          mips_sim_next_cycle (state);
8667
    }
8668
}
8669
 
8670
/* A for_each_rtx callback.  If *X is a register, advance simulation state
8671
   DATA until mips_sim_insn can read the register's value.  */
8672
 
8673
static int
8674
mips_sim_wait_regs_2 (rtx *x, void *data)
8675
{
8676
  if (REG_P (*x))
8677
    mips_sim_wait_reg (data, mips_sim_insn, *x);
8678
  return 0;
8679
}
8680
 
8681
/* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X.  */
8682
 
8683
static void
8684
mips_sim_wait_regs_1 (rtx *x, void *data)
8685
{
8686
  for_each_rtx (x, mips_sim_wait_regs_2, data);
8687
}
8688
 
8689
/* Advance simulation state STATE until all of INSN's register
8690
   dependencies are satisfied.  */
8691
 
8692
static void
8693
mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8694
{
8695
  mips_sim_insn = insn;
8696
  note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8697
}
8698
 
8699
/* Advance simulation state STATE until the units required by
8700
   instruction INSN are available.  */
8701
 
8702
static void
8703
mips_sim_wait_units (struct mips_sim *state, rtx insn)
8704
{
8705
  state_t tmp_state;
8706
 
8707
  tmp_state = alloca (state_size ());
8708
  while (state->insns_left == 0
8709
         || (memcpy (tmp_state, state->dfa_state, state_size ()),
8710
             state_transition (tmp_state, insn) >= 0))
8711
    mips_sim_next_cycle (state);
8712
}
8713
 
8714
/* Advance simulation state STATE until INSN is ready to issue.  */
8715
 
8716
static void
8717
mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8718
{
8719
  mips_sim_wait_regs (state, insn);
8720
  mips_sim_wait_units (state, insn);
8721
}
8722
 
8723
/* mips_sim_insn has just set X.  Update the LAST_SET array
8724
   in simulation state DATA.  */
8725
 
8726
static void
8727
mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8728
{
8729
  struct mips_sim *state;
8730
  unsigned int i;
8731
 
8732
  state = data;
8733
  if (REG_P (x))
8734
    for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8735
      {
8736
        state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8737
        state->last_set[REGNO (x) + i].time = state->time;
8738
      }
8739
}
8740
 
8741
/* Issue instruction INSN in scheduler state STATE.  Assume that INSN
8742
   can issue immediately (i.e., that mips_sim_wait_insn has already
8743
   been called).  */
8744
 
8745
static void
8746
mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8747
{
8748
  state_transition (state->dfa_state, insn);
8749
  state->insns_left--;
8750
 
8751
  mips_sim_insn = insn;
8752
  note_stores (PATTERN (insn), mips_sim_record_set, state);
8753
}
8754
 
8755
/* Simulate issuing a NOP in state STATE.  */
8756
 
8757
static void
8758
mips_sim_issue_nop (struct mips_sim *state)
8759
{
8760
  if (state->insns_left == 0)
8761
    mips_sim_next_cycle (state);
8762
  state->insns_left--;
8763
}
8764
 
8765
/* Update simulation state STATE so that it's ready to accept the instruction
8766
   after INSN.  INSN should be part of the main rtl chain, not a member of a
8767
   SEQUENCE.  */
8768
 
8769
static void
8770
mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8771
{
8772
  /* If INSN is a jump with an implicit delay slot, simulate a nop.  */
8773
  if (JUMP_P (insn))
8774
    mips_sim_issue_nop (state);
8775
 
8776
  switch (GET_CODE (SEQ_BEGIN (insn)))
8777
    {
8778
    case CODE_LABEL:
8779
    case CALL_INSN:
8780
      /* We can't predict the processor state after a call or label.  */
8781
      mips_sim_reset (state);
8782
      break;
8783
 
8784
    case JUMP_INSN:
8785
      /* The delay slots of branch likely instructions are only executed
8786
         when the branch is taken.  Therefore, if the caller has simulated
8787
         the delay slot instruction, STATE does not really reflect the state
8788
         of the pipeline for the instruction after the delay slot.  Also,
8789
         branch likely instructions tend to incur a penalty when not taken,
8790
         so there will probably be an extra delay between the branch and
8791
         the instruction after the delay slot.  */
8792
      if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8793
        mips_sim_reset (state);
8794
      break;
8795
 
8796
    default:
8797
      break;
8798
    }
8799
}
8800
 
8801
/* The VR4130 pipeline issues aligned pairs of instructions together,
8802
   but it stalls the second instruction if it depends on the first.
8803
   In order to cut down the amount of logic required, this dependence
8804
   check is not based on a full instruction decode.  Instead, any non-SPECIAL
8805
   instruction is assumed to modify the register specified by bits 20-16
8806
   (which is usually the "rt" field).
8807
 
8808
   In beq, beql, bne and bnel instructions, the rt field is actually an
8809
   input, so we can end up with a false dependence between the branch
8810
   and its delay slot.  If this situation occurs in instruction INSN,
8811
   try to avoid it by swapping rs and rt.  */
8812
 
8813
static void
8814
vr4130_avoid_branch_rt_conflict (rtx insn)
8815
{
8816
  rtx first, second;
8817
 
8818
  first = SEQ_BEGIN (insn);
8819
  second = SEQ_END (insn);
8820
  if (JUMP_P (first)
8821
      && NONJUMP_INSN_P (second)
8822
      && GET_CODE (PATTERN (first)) == SET
8823
      && GET_CODE (SET_DEST (PATTERN (first))) == PC
8824
      && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8825
    {
8826
      /* Check for the right kind of condition.  */
8827
      rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8828
      if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8829
          && REG_P (XEXP (cond, 0))
8830
          && REG_P (XEXP (cond, 1))
8831
          && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8832
          && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8833
        {
8834
          /* SECOND mentions the rt register but not the rs register.  */
8835
          rtx tmp = XEXP (cond, 0);
8836
          XEXP (cond, 0) = XEXP (cond, 1);
8837
          XEXP (cond, 1) = tmp;
8838
        }
8839
    }
8840
}
8841
 
8842
/* Implement -mvr4130-align.  Go through each basic block and simulate the
8843
   processor pipeline.  If we find that a pair of instructions could execute
8844
   in parallel, and the first of those instruction is not 8-byte aligned,
8845
   insert a nop to make it aligned.  */
8846
 
8847
static void
8848
vr4130_align_insns (void)
8849
{
8850
  struct mips_sim state;
8851
  rtx insn, subinsn, last, last2, next;
8852
  bool aligned_p;
8853
 
8854
  dfa_start ();
8855
 
8856
  /* LAST is the last instruction before INSN to have a nonzero length.
8857
     LAST2 is the last such instruction before LAST.  */
8858
  last = 0;
8859
  last2 = 0;
8860
 
8861
  /* ALIGNED_P is true if INSN is known to be at an aligned address.  */
8862
  aligned_p = true;
8863
 
8864
  mips_sim_init (&state, alloca (state_size ()));
8865
  for (insn = get_insns (); insn != 0; insn = next)
8866
    {
8867
      unsigned int length;
8868
 
8869
      next = NEXT_INSN (insn);
8870
 
8871
      /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8872
         This isn't really related to the alignment pass, but we do it on
8873
         the fly to avoid a separate instruction walk.  */
8874
      vr4130_avoid_branch_rt_conflict (insn);
8875
 
8876
      if (USEFUL_INSN_P (insn))
8877
        FOR_EACH_SUBINSN (subinsn, insn)
8878
          {
8879
            mips_sim_wait_insn (&state, subinsn);
8880
 
8881
            /* If we want this instruction to issue in parallel with the
8882
               previous one, make sure that the previous instruction is
8883
               aligned.  There are several reasons why this isn't worthwhile
8884
               when the second instruction is a call:
8885
 
8886
                  - Calls are less likely to be performance critical,
8887
                  - There's a good chance that the delay slot can execute
8888
                    in parallel with the call.
8889
                  - The return address would then be unaligned.
8890
 
8891
               In general, if we're going to insert a nop between instructions
8892
               X and Y, it's better to insert it immediately after X.  That
8893
               way, if the nop makes Y aligned, it will also align any labels
8894
               between X and Y.  */
8895
            if (state.insns_left != state.issue_rate
8896
                && !CALL_P (subinsn))
8897
              {
8898
                if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8899
                  {
8900
                    /* SUBINSN is the first instruction in INSN and INSN is
8901
                       aligned.  We want to align the previous instruction
8902
                       instead, so insert a nop between LAST2 and LAST.
8903
 
8904
                       Note that LAST could be either a single instruction
8905
                       or a branch with a delay slot.  In the latter case,
8906
                       LAST, like INSN, is already aligned, but the delay
8907
                       slot must have some extra delay that stops it from
8908
                       issuing at the same time as the branch.  We therefore
8909
                       insert a nop before the branch in order to align its
8910
                       delay slot.  */
8911
                    emit_insn_after (gen_nop (), last2);
8912
                    aligned_p = false;
8913
                  }
8914
                else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8915
                  {
8916
                    /* SUBINSN is the delay slot of INSN, but INSN is
8917
                       currently unaligned.  Insert a nop between
8918
                       LAST and INSN to align it.  */
8919
                    emit_insn_after (gen_nop (), last);
8920
                    aligned_p = true;
8921
                  }
8922
              }
8923
            mips_sim_issue_insn (&state, subinsn);
8924
          }
8925
      mips_sim_finish_insn (&state, insn);
8926
 
8927
      /* Update LAST, LAST2 and ALIGNED_P for the next instruction.  */
8928
      length = get_attr_length (insn);
8929
      if (length > 0)
8930
        {
8931
          /* If the instruction is an asm statement or multi-instruction
8932
             mips.md patern, the length is only an estimate.  Insert an
8933
             8 byte alignment after it so that the following instructions
8934
             can be handled correctly.  */
8935
          if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8936
              && (recog_memoized (insn) < 0 || length >= 8))
8937
            {
8938
              next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8939
              next = NEXT_INSN (next);
8940
              mips_sim_next_cycle (&state);
8941
              aligned_p = true;
8942
            }
8943
          else if (length & 4)
8944
            aligned_p = !aligned_p;
8945
          last2 = last;
8946
          last = insn;
8947
        }
8948
 
8949
      /* See whether INSN is an aligned label.  */
8950
      if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8951
        aligned_p = true;
8952
    }
8953
  dfa_finish ();
8954
}
8955
 
8956
/* Subroutine of mips_reorg.  If there is a hazard between INSN
8957
   and a previous instruction, avoid it by inserting nops after
8958
   instruction AFTER.
8959
 
8960
   *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8961
   this point.  If *DELAYED_REG is non-null, INSN must wait a cycle
8962
   before using the value of that register.  *HILO_DELAY counts the
8963
   number of instructions since the last hilo hazard (that is,
8964
   the number of instructions since the last mflo or mfhi).
8965
 
8966
   After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8967
   for the next instruction.
8968
 
8969
   LO_REG is an rtx for the LO register, used in dependence checking.  */
8970
 
8971
static void
8972
mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8973
                   rtx *delayed_reg, rtx lo_reg)
8974
{
8975
  rtx pattern, set;
8976
  int nops, ninsns;
8977
 
8978
  if (!INSN_P (insn))
8979
    return;
8980
 
8981
  pattern = PATTERN (insn);
8982
 
8983
  /* Do not put the whole function in .set noreorder if it contains
8984
     an asm statement.  We don't know whether there will be hazards
8985
     between the asm statement and the gcc-generated code.  */
8986
  if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8987
    cfun->machine->all_noreorder_p = false;
8988
 
8989
  /* Ignore zero-length instructions (barriers and the like).  */
8990
  ninsns = get_attr_length (insn) / 4;
8991
  if (ninsns == 0)
8992
    return;
8993
 
8994
  /* Work out how many nops are needed.  Note that we only care about
8995
     registers that are explicitly mentioned in the instruction's pattern.
8996
     It doesn't matter that calls use the argument registers or that they
8997
     clobber hi and lo.  */
8998
  if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8999
    nops = 2 - *hilo_delay;
9000
  else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
9001
    nops = 1;
9002
  else
9003
    nops = 0;
9004
 
9005
  /* Insert the nops between this instruction and the previous one.
9006
     Each new nop takes us further from the last hilo hazard.  */
9007
  *hilo_delay += nops;
9008
  while (nops-- > 0)
9009
    emit_insn_after (gen_hazard_nop (), after);
9010
 
9011
  /* Set up the state for the next instruction.  */
9012
  *hilo_delay += ninsns;
9013
  *delayed_reg = 0;
9014
  if (INSN_CODE (insn) >= 0)
9015
    switch (get_attr_hazard (insn))
9016
      {
9017
      case HAZARD_NONE:
9018
        break;
9019
 
9020
      case HAZARD_HILO:
9021
        *hilo_delay = 0;
9022
        break;
9023
 
9024
      case HAZARD_DELAY:
9025
        set = single_set (insn);
9026
        gcc_assert (set != 0);
9027
        *delayed_reg = SET_DEST (set);
9028
        break;
9029
      }
9030
}
9031
 
9032
 
9033
/* Go through the instruction stream and insert nops where necessary.
9034
   See if the whole function can then be put into .set noreorder &
9035
   .set nomacro.  */
9036
 
9037
static void
9038
mips_avoid_hazards (void)
9039
{
9040
  rtx insn, last_insn, lo_reg, delayed_reg;
9041
  int hilo_delay, i;
9042
 
9043
  /* Force all instructions to be split into their final form.  */
9044
  split_all_insns_noflow ();
9045
 
9046
  /* Recalculate instruction lengths without taking nops into account.  */
9047
  cfun->machine->ignore_hazard_length_p = true;
9048
  shorten_branches (get_insns ());
9049
 
9050
  cfun->machine->all_noreorder_p = true;
9051
 
9052
  /* Profiled functions can't be all noreorder because the profiler
9053
     support uses assembler macros.  */
9054
  if (current_function_profile)
9055
    cfun->machine->all_noreorder_p = false;
9056
 
9057
  /* Code compiled with -mfix-vr4120 can't be all noreorder because
9058
     we rely on the assembler to work around some errata.  */
9059
  if (TARGET_FIX_VR4120)
9060
    cfun->machine->all_noreorder_p = false;
9061
 
9062
  /* The same is true for -mfix-vr4130 if we might generate mflo or
9063
     mfhi instructions.  Note that we avoid using mflo and mfhi if
9064
     the VR4130 macc and dmacc instructions are available instead;
9065
     see the *mfhilo_{si,di}_macc patterns.  */
9066
  if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
9067
    cfun->machine->all_noreorder_p = false;
9068
 
9069
  last_insn = 0;
9070
  hilo_delay = 2;
9071
  delayed_reg = 0;
9072
  lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
9073
 
9074
  for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9075
    if (INSN_P (insn))
9076
      {
9077
        if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9078
          for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9079
            mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
9080
                               &hilo_delay, &delayed_reg, lo_reg);
9081
        else
9082
          mips_avoid_hazard (last_insn, insn, &hilo_delay,
9083
                             &delayed_reg, lo_reg);
9084
 
9085
        last_insn = insn;
9086
      }
9087
}
9088
 
9089
 
9090
/* Implement TARGET_MACHINE_DEPENDENT_REORG.  */
9091
 
9092
static void
9093
mips_reorg (void)
9094
{
9095
  if (TARGET_MIPS16)
9096
    mips16_lay_out_constants ();
9097
  else if (TARGET_EXPLICIT_RELOCS)
9098
    {
9099
      if (mips_flag_delayed_branch)
9100
        dbr_schedule (get_insns ());
9101
      mips_avoid_hazards ();
9102
      if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
9103
        vr4130_align_insns ();
9104
    }
9105
}
9106
 
9107
/* This function does three things:
9108
 
9109
   - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9110
   - Register the mips16 hardware floating point stubs.
9111
   - Register the gofast functions if selected using --enable-gofast.  */
9112
 
9113
#include "config/gofast.h"
9114
 
9115
static void
9116
mips_init_libfuncs (void)
9117
{
9118
  if (TARGET_FIX_VR4120)
9119
    {
9120
      set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9121
      set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9122
    }
9123
 
9124
  if (TARGET_MIPS16 && mips16_hard_float)
9125
    {
9126
      set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9127
      set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9128
      set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9129
      set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9130
 
9131
      set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9132
      set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9133
      set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9134
      set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9135
      set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9136
      set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9137
 
9138
      set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9139
      set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9140
 
9141
      if (TARGET_DOUBLE_FLOAT)
9142
        {
9143
          set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9144
          set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9145
          set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9146
          set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9147
 
9148
          set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9149
          set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9150
          set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9151
          set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9152
          set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9153
          set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9154
 
9155
          set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9156
          set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9157
 
9158
          set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9159
          set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9160
        }
9161
    }
9162
  else
9163
    gofast_maybe_init_libfuncs ();
9164
}
9165
 
9166
/* Return a number assessing the cost of moving a register in class
9167
   FROM to class TO.  The classes are expressed using the enumeration
9168
   values such as `GENERAL_REGS'.  A value of 2 is the default; other
9169
   values are interpreted relative to that.
9170
 
9171
   It is not required that the cost always equal 2 when FROM is the
9172
   same as TO; on some machines it is expensive to move between
9173
   registers if they are not general registers.
9174
 
9175
   If reload sees an insn consisting of a single `set' between two
9176
   hard registers, and if `REGISTER_MOVE_COST' applied to their
9177
   classes returns a value of 2, reload does not check to ensure that
9178
   the constraints of the insn are met.  Setting a cost of other than
9179
   2 will allow reload to verify that the constraints are met.  You
9180
   should do this if the `movM' pattern's constraints do not allow
9181
   such copying.
9182
 
9183
   ??? We make the cost of moving from HI/LO into general
9184
   registers the same as for one of moving general registers to
9185
   HI/LO for TARGET_MIPS16 in order to prevent allocating a
9186
   pseudo to HI/LO.  This might hurt optimizations though, it
9187
   isn't clear if it is wise.  And it might not work in all cases.  We
9188
   could solve the DImode LO reg problem by using a multiply, just
9189
   like reload_{in,out}si.  We could solve the SImode/HImode HI reg
9190
   problem by using divide instructions.  divu puts the remainder in
9191
   the HI reg, so doing a divide by -1 will move the value in the HI
9192
   reg for all values except -1.  We could handle that case by using a
9193
   signed divide, e.g.  -1 / 2 (or maybe 1 / -2?).  We'd have to emit
9194
   a compare/branch to test the input value to see which instruction
9195
   we need to use.  This gets pretty messy, but it is feasible.  */
9196
 
9197
int
9198
mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9199
                         enum reg_class to, enum reg_class from)
9200
{
9201
  if (from == M16_REGS && GR_REG_CLASS_P (to))
9202
    return 2;
9203
  else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9204
    return 2;
9205
  else if (GR_REG_CLASS_P (from))
9206
    {
9207
      if (to == M16_REGS)
9208
        return 2;
9209
      else if (to == M16_NA_REGS)
9210
        return 2;
9211
      else if (GR_REG_CLASS_P (to))
9212
        {
9213
          if (TARGET_MIPS16)
9214
            return 4;
9215
          else
9216
            return 2;
9217
        }
9218
      else if (to == FP_REGS)
9219
        return 4;
9220
      else if (reg_class_subset_p (to, ACC_REGS))
9221
        {
9222
          if (TARGET_MIPS16)
9223
            return 12;
9224
          else
9225
            return 6;
9226
        }
9227
      else if (COP_REG_CLASS_P (to))
9228
        {
9229
          return 5;
9230
        }
9231
    }
9232
  else if (from == FP_REGS)
9233
    {
9234
      if (GR_REG_CLASS_P (to))
9235
        return 4;
9236
      else if (to == FP_REGS)
9237
        return 2;
9238
      else if (to == ST_REGS)
9239
        return 8;
9240
    }
9241
  else if (reg_class_subset_p (from, ACC_REGS))
9242
    {
9243
      if (GR_REG_CLASS_P (to))
9244
        {
9245
          if (TARGET_MIPS16)
9246
            return 12;
9247
          else
9248
            return 6;
9249
        }
9250
    }
9251
  else if (from == ST_REGS && GR_REG_CLASS_P (to))
9252
    return 4;
9253
  else if (COP_REG_CLASS_P (from))
9254
    {
9255
      return 5;
9256
    }
9257
 
9258
  /* Fall through.
9259
     ??? What cases are these? Shouldn't we return 2 here?  */
9260
 
9261
  return 12;
9262
}
9263
 
9264
/* Return the length of INSN.  LENGTH is the initial length computed by
9265
   attributes in the machine-description file.  */
9266
 
9267
int
9268
mips_adjust_insn_length (rtx insn, int length)
9269
{
9270
  /* A unconditional jump has an unfilled delay slot if it is not part
9271
     of a sequence.  A conditional jump normally has a delay slot, but
9272
     does not on MIPS16.  */
9273
  if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9274
    length += 4;
9275
 
9276
  /* See how many nops might be needed to avoid hardware hazards.  */
9277
  if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9278
    switch (get_attr_hazard (insn))
9279
      {
9280
      case HAZARD_NONE:
9281
        break;
9282
 
9283
      case HAZARD_DELAY:
9284
        length += 4;
9285
        break;
9286
 
9287
      case HAZARD_HILO:
9288
        length += 8;
9289
        break;
9290
      }
9291
 
9292
  /* All MIPS16 instructions are a measly two bytes.  */
9293
  if (TARGET_MIPS16)
9294
    length /= 2;
9295
 
9296
  return length;
9297
}
9298
 
9299
 
9300
/* Return an asm sequence to start a noat block and load the address
9301
   of a label into $1.  */
9302
 
9303
const char *
9304
mips_output_load_label (void)
9305
{
9306
  if (TARGET_EXPLICIT_RELOCS)
9307
    switch (mips_abi)
9308
      {
9309
      case ABI_N32:
9310
        return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9311
 
9312
      case ABI_64:
9313
        return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9314
 
9315
      default:
9316
        if (ISA_HAS_LOAD_DELAY)
9317
          return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9318
        return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9319
      }
9320
  else
9321
    {
9322
      if (Pmode == DImode)
9323
        return "%[dla\t%@,%0";
9324
      else
9325
        return "%[la\t%@,%0";
9326
    }
9327
}
9328
 
9329
/* Return the assembly code for INSN, which has the operands given by
9330
   OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9331
   BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9332
   is in range of a direct branch.  BRANCH_IF_FALSE is an inverted
9333
   version of BRANCH_IF_TRUE.  */
9334
 
9335
const char *
9336
mips_output_conditional_branch (rtx insn, rtx *operands,
9337
                                const char *branch_if_true,
9338
                                const char *branch_if_false)
9339
{
9340
  unsigned int length;
9341
  rtx taken, not_taken;
9342
 
9343
  length = get_attr_length (insn);
9344
  if (length <= 8)
9345
    {
9346
      /* Just a simple conditional branch.  */
9347
      mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9348
      return branch_if_true;
9349
    }
9350
 
9351
  /* Generate a reversed branch around a direct jump.  This fallback does
9352
     not use branch-likely instructions.  */
9353
  mips_branch_likely = false;
9354
  not_taken = gen_label_rtx ();
9355
  taken = operands[1];
9356
 
9357
  /* Generate the reversed branch to NOT_TAKEN.  */
9358
  operands[1] = not_taken;
9359
  output_asm_insn (branch_if_false, operands);
9360
 
9361
  /* If INSN has a delay slot, we must provide delay slots for both the
9362
     branch to NOT_TAKEN and the conditional jump.  We must also ensure
9363
     that INSN's delay slot is executed in the appropriate cases.  */
9364
  if (final_sequence)
9365
    {
9366
      /* This first delay slot will always be executed, so use INSN's
9367
         delay slot if is not annulled.  */
9368
      if (!INSN_ANNULLED_BRANCH_P (insn))
9369
        {
9370
          final_scan_insn (XVECEXP (final_sequence, 0, 1),
9371
                           asm_out_file, optimize, 1, NULL);
9372
          INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9373
        }
9374
      else
9375
        output_asm_insn ("nop", 0);
9376
      fprintf (asm_out_file, "\n");
9377
    }
9378
 
9379
  /* Output the unconditional branch to TAKEN.  */
9380
  if (length <= 16)
9381
    output_asm_insn ("j\t%0%/", &taken);
9382
  else
9383
    {
9384
      output_asm_insn (mips_output_load_label (), &taken);
9385
      output_asm_insn ("jr\t%@%]%/", 0);
9386
    }
9387
 
9388
  /* Now deal with its delay slot; see above.  */
9389
  if (final_sequence)
9390
    {
9391
      /* This delay slot will only be executed if the branch is taken.
9392
         Use INSN's delay slot if is annulled.  */
9393
      if (INSN_ANNULLED_BRANCH_P (insn))
9394
        {
9395
          final_scan_insn (XVECEXP (final_sequence, 0, 1),
9396
                           asm_out_file, optimize, 1, NULL);
9397
          INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9398
        }
9399
      else
9400
        output_asm_insn ("nop", 0);
9401
      fprintf (asm_out_file, "\n");
9402
    }
9403
 
9404
  /* Output NOT_TAKEN.  */
9405
  (*targetm.asm_out.internal_label) (asm_out_file, "L",
9406
                                     CODE_LABEL_NUMBER (not_taken));
9407
  return "";
9408
}
9409
 
9410
/* Return the assembly code for INSN, which branches to OPERANDS[1]
9411
   if some ordered condition is true.  The condition is given by
9412
   OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9413
   OPERANDS[0].  OPERANDS[2] is the comparison's first operand;
9414
   its second is always zero.  */
9415
 
9416
const char *
9417
mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9418
{
9419
  const char *branch[2];
9420
 
9421
  /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9422
     Make BRANCH[0] branch on the inverse condition.  */
9423
  switch (GET_CODE (operands[0]))
9424
    {
9425
      /* These cases are equivalent to comparisons against zero.  */
9426
    case LEU:
9427
      inverted_p = !inverted_p;
9428
      /* Fall through.  */
9429
    case GTU:
9430
      branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9431
      branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9432
      break;
9433
 
9434
      /* These cases are always true or always false.  */
9435
    case LTU:
9436
      inverted_p = !inverted_p;
9437
      /* Fall through.  */
9438
    case GEU:
9439
      branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9440
      branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9441
      break;
9442
 
9443
    default:
9444
      branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9445
      branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9446
      break;
9447
    }
9448
  return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9449
}
9450
 
9451
/* Used to output div or ddiv instruction DIVISION, which has the operands
9452
   given by OPERANDS.  Add in a divide-by-zero check if needed.
9453
 
9454
   When working around R4000 and R4400 errata, we need to make sure that
9455
   the division is not immediately followed by a shift[1][2].  We also
9456
   need to stop the division from being put into a branch delay slot[3].
9457
   The easiest way to avoid both problems is to add a nop after the
9458
   division.  When a divide-by-zero check is needed, this nop can be
9459
   used to fill the branch delay slot.
9460
 
9461
   [1] If a double-word or a variable shift executes immediately
9462
       after starting an integer division, the shift may give an
9463
       incorrect result.  See quotations of errata #16 and #28 from
9464
       "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9465
       in mips.md for details.
9466
 
9467
   [2] A similar bug to [1] exists for all revisions of the
9468
       R4000 and the R4400 when run in an MC configuration.
9469
       From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9470
 
9471
       "19. In this following sequence:
9472
 
9473
                    ddiv                (or ddivu or div or divu)
9474
                    dsll32              (or dsrl32, dsra32)
9475
 
9476
            if an MPT stall occurs, while the divide is slipping the cpu
9477
            pipeline, then the following double shift would end up with an
9478
            incorrect result.
9479
 
9480
            Workaround: The compiler needs to avoid generating any
9481
            sequence with divide followed by extended double shift."
9482
 
9483
       This erratum is also present in "MIPS R4400MC Errata, Processor
9484
       Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9485
       & 3.0" as errata #10 and #4, respectively.
9486
 
9487
   [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9488
       (also valid for MIPS R4000MC processors):
9489
 
9490
       "52. R4000SC: This bug does not apply for the R4000PC.
9491
 
9492
            There are two flavors of this bug:
9493
 
9494
            1) If the instruction just after divide takes an RF exception
9495
               (tlb-refill, tlb-invalid) and gets an instruction cache
9496
               miss (both primary and secondary) and the line which is
9497
               currently in secondary cache at this index had the first
9498
               data word, where the bits 5..2 are set, then R4000 would
9499
               get a wrong result for the div.
9500
 
9501
            ##1
9502
                    nop
9503
                    div r8, r9
9504
                    -------------------         # end-of page. -tlb-refill
9505
                    nop
9506
            ##2
9507
                    nop
9508
                    div r8, r9
9509
                    -------------------         # end-of page. -tlb-invalid
9510
                    nop
9511
 
9512
            2) If the divide is in the taken branch delay slot, where the
9513
               target takes RF exception and gets an I-cache miss for the
9514
               exception vector or where I-cache miss occurs for the
9515
               target address, under the above mentioned scenarios, the
9516
               div would get wrong results.
9517
 
9518
            ##1
9519
                    j   r2              # to next page mapped or unmapped
9520
                    div r8,r9           # this bug would be there as long
9521
                                        # as there is an ICache miss and
9522
                    nop                 # the "data pattern" is present
9523
 
9524
            ##2
9525
                    beq r0, r0, NextPage        # to Next page
9526
                    div r8,r9
9527
                    nop
9528
 
9529
            This bug is present for div, divu, ddiv, and ddivu
9530
            instructions.
9531
 
9532
            Workaround: For item 1), OS could make sure that the next page
9533
            after the divide instruction is also mapped.  For item 2), the
9534
            compiler could make sure that the divide instruction is not in
9535
            the branch delay slot."
9536
 
9537
       These processors have PRId values of 0x00004220 and 0x00004300 for
9538
       the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400.  */
9539
 
9540
const char *
9541
mips_output_division (const char *division, rtx *operands)
9542
{
9543
  const char *s;
9544
 
9545
  s = division;
9546
  if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9547
    {
9548
      output_asm_insn (s, operands);
9549
      s = "nop";
9550
    }
9551
  if (TARGET_CHECK_ZERO_DIV)
9552
    {
9553
      if (TARGET_MIPS16)
9554
        {
9555
          output_asm_insn (s, operands);
9556
          s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9557
        }
9558
      else if (GENERATE_DIVIDE_TRAPS)
9559
        {
9560
          output_asm_insn (s, operands);
9561
          s = "teq\t%2,%.,7";
9562
        }
9563
      else
9564
        {
9565
          output_asm_insn ("%(bne\t%2,%.,1f", operands);
9566
          output_asm_insn (s, operands);
9567
          s = "break\t7%)\n1:";
9568
        }
9569
    }
9570
  return s;
9571
}
9572
 
9573
/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9574
   with a final "000" replaced by "k".  Ignore case.
9575
 
9576
   Note: this function is shared between GCC and GAS.  */
9577
 
9578
static bool
9579
mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9580
{
9581
  while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9582
    given++, canonical++;
9583
 
9584
  return ((*given == 0 && *canonical == 0)
9585
          || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9586
}
9587
 
9588
 
9589
/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9590
   CPU name.  We've traditionally allowed a lot of variation here.
9591
 
9592
   Note: this function is shared between GCC and GAS.  */
9593
 
9594
static bool
9595
mips_matching_cpu_name_p (const char *canonical, const char *given)
9596
{
9597
  /* First see if the name matches exactly, or with a final "000"
9598
     turned into "k".  */
9599
  if (mips_strict_matching_cpu_name_p (canonical, given))
9600
    return true;
9601
 
9602
  /* If not, try comparing based on numerical designation alone.
9603
     See if GIVEN is an unadorned number, or 'r' followed by a number.  */
9604
  if (TOLOWER (*given) == 'r')
9605
    given++;
9606
  if (!ISDIGIT (*given))
9607
    return false;
9608
 
9609
  /* Skip over some well-known prefixes in the canonical name,
9610
     hoping to find a number there too.  */
9611
  if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9612
    canonical += 2;
9613
  else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9614
    canonical += 2;
9615
  else if (TOLOWER (canonical[0]) == 'r')
9616
    canonical += 1;
9617
 
9618
  return mips_strict_matching_cpu_name_p (canonical, given);
9619
}
9620
 
9621
 
9622
/* Return the mips_cpu_info entry for the processor or ISA given
9623
   by CPU_STRING.  Return null if the string isn't recognized.
9624
 
9625
   A similar function exists in GAS.  */
9626
 
9627
static const struct mips_cpu_info *
9628
mips_parse_cpu (const char *cpu_string)
9629
{
9630
  const struct mips_cpu_info *p;
9631
  const char *s;
9632
 
9633
  /* In the past, we allowed upper-case CPU names, but it doesn't
9634
     work well with the multilib machinery.  */
9635
  for (s = cpu_string; *s != 0; s++)
9636
    if (ISUPPER (*s))
9637
      {
9638
        warning (0, "the cpu name must be lower case");
9639
        break;
9640
      }
9641
 
9642
  /* 'from-abi' selects the most compatible architecture for the given
9643
     ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs.  For the
9644
     EABIs, we have to decide whether we're using the 32-bit or 64-bit
9645
     version.  Look first at the -mgp options, if given, otherwise base
9646
     the choice on MASK_64BIT in TARGET_DEFAULT.  */
9647
  if (strcasecmp (cpu_string, "from-abi") == 0)
9648
    return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9649
                                   : ABI_NEEDS_64BIT_REGS ? 3
9650
                                   : (TARGET_64BIT ? 3 : 1));
9651
 
9652
  /* 'default' has traditionally been a no-op.  Probably not very useful.  */
9653
  if (strcasecmp (cpu_string, "default") == 0)
9654
    return 0;
9655
 
9656
  for (p = mips_cpu_info_table; p->name != 0; p++)
9657
    if (mips_matching_cpu_name_p (p->name, cpu_string))
9658
      return p;
9659
 
9660
  return 0;
9661
}
9662
 
9663
 
9664
/* Return the processor associated with the given ISA level, or null
9665
   if the ISA isn't valid.  */
9666
 
9667
static const struct mips_cpu_info *
9668
mips_cpu_info_from_isa (int isa)
9669
{
9670
  const struct mips_cpu_info *p;
9671
 
9672
  for (p = mips_cpu_info_table; p->name != 0; p++)
9673
    if (p->isa == isa)
9674
      return p;
9675
 
9676
  return 0;
9677
}
9678
 
9679
/* Implement HARD_REGNO_NREGS.  The size of FP registers is controlled
9680
   by UNITS_PER_FPREG.  The size of FP status registers is always 4, because
9681
   they only hold condition code modes, and CCmode is always considered to
9682
   be 4 bytes wide.  All other registers are word sized.  */
9683
 
9684
unsigned int
9685
mips_hard_regno_nregs (int regno, enum machine_mode mode)
9686
{
9687
  if (ST_REG_P (regno))
9688
    return ((GET_MODE_SIZE (mode) + 3) / 4);
9689
  else if (! FP_REG_P (regno))
9690
    return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9691
  else
9692
    return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9693
}
9694
 
9695
/* Implement TARGET_RETURN_IN_MEMORY.  Under the old (i.e., 32 and O64 ABIs)
9696
   all BLKmode objects are returned in memory.  Under the new (N32 and
9697
   64-bit MIPS ABIs) small structures are returned in a register.
9698
   Objects with varying size must still be returned in memory, of
9699
   course.  */
9700
 
9701
static bool
9702
mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9703
{
9704
  if (TARGET_OLDABI)
9705
    return (TYPE_MODE (type) == BLKmode);
9706
  else
9707
    return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9708
            || (int_size_in_bytes (type) == -1));
9709
}
9710
 
9711
static bool
9712
mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9713
{
9714
  return !TARGET_OLDABI;
9715
}
9716
 
9717
/* Return true if INSN is a multiply-add or multiply-subtract
9718
   instruction and PREV assigns to the accumulator operand.  */
9719
 
9720
bool
9721
mips_linked_madd_p (rtx prev, rtx insn)
9722
{
9723
  rtx x;
9724
 
9725
  x = single_set (insn);
9726
  if (x == 0)
9727
    return false;
9728
 
9729
  x = SET_SRC (x);
9730
 
9731
  if (GET_CODE (x) == PLUS
9732
      && GET_CODE (XEXP (x, 0)) == MULT
9733
      && reg_set_p (XEXP (x, 1), prev))
9734
    return true;
9735
 
9736
  if (GET_CODE (x) == MINUS
9737
      && GET_CODE (XEXP (x, 1)) == MULT
9738
      && reg_set_p (XEXP (x, 0), prev))
9739
    return true;
9740
 
9741
  return false;
9742
}
9743
 
9744
/* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9745
   that may clobber hi or lo.  */
9746
 
9747
static rtx mips_macc_chains_last_hilo;
9748
 
9749
/* A TUNE_MACC_CHAINS helper function.  Record that instruction INSN has
9750
   been scheduled, updating mips_macc_chains_last_hilo appropriately.  */
9751
 
9752
static void
9753
mips_macc_chains_record (rtx insn)
9754
{
9755
  if (get_attr_may_clobber_hilo (insn))
9756
    mips_macc_chains_last_hilo = insn;
9757
}
9758
 
9759
/* A TUNE_MACC_CHAINS helper function.  Search ready queue READY, which
9760
   has NREADY elements, looking for a multiply-add or multiply-subtract
9761
   instruction that is cumulative with mips_macc_chains_last_hilo.
9762
   If there is one, promote it ahead of anything else that might
9763
   clobber hi or lo.  */
9764
 
9765
static void
9766
mips_macc_chains_reorder (rtx *ready, int nready)
9767
{
9768
  int i, j;
9769
 
9770
  if (mips_macc_chains_last_hilo != 0)
9771
    for (i = nready - 1; i >= 0; i--)
9772
      if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9773
        {
9774
          for (j = nready - 1; j > i; j--)
9775
            if (recog_memoized (ready[j]) >= 0
9776
                && get_attr_may_clobber_hilo (ready[j]))
9777
              {
9778
                mips_promote_ready (ready, i, j);
9779
                break;
9780
              }
9781
          break;
9782
        }
9783
}
9784
 
9785
/* The last instruction to be scheduled.  */
9786
 
9787
static rtx vr4130_last_insn;
9788
 
9789
/* A note_stores callback used by vr4130_true_reg_dependence_p.  DATA
9790
   points to an rtx that is initially an instruction.  Nullify the rtx
9791
   if the instruction uses the value of register X.  */
9792
 
9793
static void
9794
vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9795
{
9796
  rtx *insn_ptr = data;
9797
  if (REG_P (x)
9798
      && *insn_ptr != 0
9799
      && reg_referenced_p (x, PATTERN (*insn_ptr)))
9800
    *insn_ptr = 0;
9801
}
9802
 
9803
/* Return true if there is true register dependence between vr4130_last_insn
9804
   and INSN.  */
9805
 
9806
static bool
9807
vr4130_true_reg_dependence_p (rtx insn)
9808
{
9809
  note_stores (PATTERN (vr4130_last_insn),
9810
               vr4130_true_reg_dependence_p_1, &insn);
9811
  return insn == 0;
9812
}
9813
 
9814
/* A TUNE_MIPS4130 helper function.  Given that INSN1 is at the head of
9815
   the ready queue and that INSN2 is the instruction after it, return
9816
   true if it is worth promoting INSN2 ahead of INSN1.  Look for cases
9817
   in which INSN1 and INSN2 can probably issue in parallel, but for
9818
   which (INSN2, INSN1) should be less sensitive to instruction
9819
   alignment than (INSN1, INSN2).  See 4130.md for more details.  */
9820
 
9821
static bool
9822
vr4130_swap_insns_p (rtx insn1, rtx insn2)
9823
{
9824
  rtx dep;
9825
 
9826
  /* Check for the following case:
9827
 
9828
     1) there is some other instruction X with an anti dependence on INSN1;
9829
     2) X has a higher priority than INSN2; and
9830
     3) X is an arithmetic instruction (and thus has no unit restrictions).
9831
 
9832
     If INSN1 is the last instruction blocking X, it would better to
9833
     choose (INSN1, X) over (INSN2, INSN1).  */
9834
  for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9835
    if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9836
        && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9837
        && recog_memoized (XEXP (dep, 0)) >= 0
9838
        && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9839
      return false;
9840
 
9841
  if (vr4130_last_insn != 0
9842
      && recog_memoized (insn1) >= 0
9843
      && recog_memoized (insn2) >= 0)
9844
    {
9845
      /* See whether INSN1 and INSN2 use different execution units,
9846
         or if they are both ALU-type instructions.  If so, they can
9847
         probably execute in parallel.  */
9848
      enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9849
      enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9850
      if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9851
        {
9852
          /* If only one of the instructions has a dependence on
9853
             vr4130_last_insn, prefer to schedule the other one first.  */
9854
          bool dep1 = vr4130_true_reg_dependence_p (insn1);
9855
          bool dep2 = vr4130_true_reg_dependence_p (insn2);
9856
          if (dep1 != dep2)
9857
            return dep1;
9858
 
9859
          /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9860
             is not an ALU-type instruction and if INSN1 uses the same
9861
             execution unit.  (Note that if this condition holds, we already
9862
             know that INSN2 uses a different execution unit.)  */
9863
          if (class1 != VR4130_CLASS_ALU
9864
              && recog_memoized (vr4130_last_insn) >= 0
9865
              && class1 == get_attr_vr4130_class (vr4130_last_insn))
9866
            return true;
9867
        }
9868
    }
9869
  return false;
9870
}
9871
 
9872
/* A TUNE_MIPS4130 helper function.  (READY, NREADY) describes a ready
9873
   queue with at least two instructions.  Swap the first two if
9874
   vr4130_swap_insns_p says that it could be worthwhile.  */
9875
 
9876
static void
9877
vr4130_reorder (rtx *ready, int nready)
9878
{
9879
  if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9880
    mips_promote_ready (ready, nready - 2, nready - 1);
9881
}
9882
 
9883
/* Remove the instruction at index LOWER from ready queue READY and
9884
   reinsert it in front of the instruction at index HIGHER.  LOWER must
9885
   be <= HIGHER.  */
9886
 
9887
static void
9888
mips_promote_ready (rtx *ready, int lower, int higher)
9889
{
9890
  rtx new_head;
9891
  int i;
9892
 
9893
  new_head = ready[lower];
9894
  for (i = lower; i < higher; i++)
9895
    ready[i] = ready[i + 1];
9896
  ready[i] = new_head;
9897
}
9898
 
9899
/* Implement TARGET_SCHED_REORDER.  */
9900
 
9901
static int
9902
mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9903
                    rtx *ready, int *nreadyp, int cycle)
9904
{
9905
  if (!reload_completed && TUNE_MACC_CHAINS)
9906
    {
9907
      if (cycle == 0)
9908
        mips_macc_chains_last_hilo = 0;
9909
      if (*nreadyp > 0)
9910
        mips_macc_chains_reorder (ready, *nreadyp);
9911
    }
9912
  if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9913
    {
9914
      if (cycle == 0)
9915
        vr4130_last_insn = 0;
9916
      if (*nreadyp > 1)
9917
        vr4130_reorder (ready, *nreadyp);
9918
    }
9919
  return mips_issue_rate ();
9920
}
9921
 
9922
/* Implement TARGET_SCHED_VARIABLE_ISSUE.  */
9923
 
9924
static int
9925
mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9926
                     rtx insn, int more)
9927
{
9928
  switch (GET_CODE (PATTERN (insn)))
9929
    {
9930
    case USE:
9931
    case CLOBBER:
9932
      /* Don't count USEs and CLOBBERs against the issue rate.  */
9933
      break;
9934
 
9935
    default:
9936
      more--;
9937
      if (!reload_completed && TUNE_MACC_CHAINS)
9938
        mips_macc_chains_record (insn);
9939
      vr4130_last_insn = insn;
9940
      break;
9941
    }
9942
  return more;
9943
}
9944
 
9945
/* Implement TARGET_SCHED_ADJUST_COST.  We assume that anti and output
9946
   dependencies have no cost.  */
9947
 
9948
static int
9949
mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9950
                  rtx dep ATTRIBUTE_UNUSED, int cost)
9951
{
9952
  if (REG_NOTE_KIND (link) != 0)
9953
    return 0;
9954
  return cost;
9955
}
9956
 
9957
/* Return the number of instructions that can be issued per cycle.  */
9958
 
9959
static int
9960
mips_issue_rate (void)
9961
{
9962
  switch (mips_tune)
9963
    {
9964
    case PROCESSOR_R4130:
9965
    case PROCESSOR_R5400:
9966
    case PROCESSOR_R5500:
9967
    case PROCESSOR_R7000:
9968
    case PROCESSOR_R9000:
9969
      return 2;
9970
 
9971
    case PROCESSOR_SB1:
9972
    case PROCESSOR_SB1A:
9973
      /* This is actually 4, but we get better performance if we claim 3.
9974
         This is partly because of unwanted speculative code motion with the
9975
         larger number, and partly because in most common cases we can't
9976
         reach the theoretical max of 4.  */
9977
      return 3;
9978
 
9979
    default:
9980
      return 1;
9981
    }
9982
}
9983
 
9984
/* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD.  This should
9985
   be as wide as the scheduling freedom in the DFA.  */
9986
 
9987
static int
9988
mips_multipass_dfa_lookahead (void)
9989
{
9990
  /* Can schedule up to 4 of the 6 function units in any one cycle.  */
9991
  if (TUNE_SB1)
9992
    return 4;
9993
 
9994
  return 0;
9995
}
9996
 
9997
/* Implements a store data bypass check.  We need this because the cprestore
9998
   pattern is type store, but defined using an UNSPEC.  This UNSPEC causes the
9999
   default routine to abort.  We just return false for that case.  */
10000
/* ??? Should try to give a better result here than assuming false.  */
10001
 
10002
int
10003
mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10004
{
10005
  if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10006
    return false;
10007
 
10008
  return ! store_data_bypass_p (out_insn, in_insn);
10009
}
10010
 
10011
/* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10012
   return the first operand of the associated "pref" or "prefx" insn.  */
10013
 
10014
rtx
10015
mips_prefetch_cookie (rtx write, rtx locality)
10016
{
10017
  /* store_streamed / load_streamed.  */
10018
  if (INTVAL (locality) <= 0)
10019
    return GEN_INT (INTVAL (write) + 4);
10020
 
10021
  /* store / load.  */
10022
  if (INTVAL (locality) <= 2)
10023
    return write;
10024
 
10025
  /* store_retained / load_retained.  */
10026
  return GEN_INT (INTVAL (write) + 6);
10027
}
10028
 
10029
/* MIPS builtin function support. */
10030
 
10031
struct builtin_description
10032
{
10033
  /* The code of the main .md file instruction.  See mips_builtin_type
10034
     for more information.  */
10035
  enum insn_code icode;
10036
 
10037
  /* The floating-point comparison code to use with ICODE, if any.  */
10038
  enum mips_fp_condition cond;
10039
 
10040
  /* The name of the builtin function.  */
10041
  const char *name;
10042
 
10043
  /* Specifies how the function should be expanded.  */
10044
  enum mips_builtin_type builtin_type;
10045
 
10046
  /* The function's prototype.  */
10047
  enum mips_function_type function_type;
10048
 
10049
  /* The target flags required for this function.  */
10050
  int target_flags;
10051
};
10052
 
10053
/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10054
   FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields.  */
10055
#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS)               \
10056
  { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN,                 \
10057
    MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10058
 
10059
/* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
10060
   TARGET_FLAGS.  */
10061
#define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS)                   \
10062
  { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND,           \
10063
    "__builtin_mips_" #INSN "_" #COND "_s",                             \
10064
    MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS },      \
10065
  { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND,           \
10066
    "__builtin_mips_" #INSN "_" #COND "_d",                             \
10067
    MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10068
 
10069
/* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10070
   The lower and upper forms require TARGET_FLAGS while the any and all
10071
   forms require MASK_MIPS3D.  */
10072
#define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS)                       \
10073
  { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND,          \
10074
    "__builtin_mips_any_" #INSN "_" #COND "_ps",                        \
10075
    MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D },      \
10076
  { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND,          \
10077
    "__builtin_mips_all_" #INSN "_" #COND "_ps",                        \
10078
    MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D },      \
10079
  { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND,          \
10080
    "__builtin_mips_lower_" #INSN "_" #COND "_ps",                      \
10081
    MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS },   \
10082
  { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND,          \
10083
    "__builtin_mips_upper_" #INSN "_" #COND "_ps",                      \
10084
    MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10085
 
10086
/* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s.  The functions
10087
   require MASK_MIPS3D.  */
10088
#define CMP_4S_BUILTINS(INSN, COND)                                     \
10089
  { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND,          \
10090
    "__builtin_mips_any_" #INSN "_" #COND "_4s",                        \
10091
    MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,           \
10092
    MASK_MIPS3D },                                                      \
10093
  { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND,          \
10094
    "__builtin_mips_all_" #INSN "_" #COND "_4s",                        \
10095
    MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,           \
10096
    MASK_MIPS3D }
10097
 
10098
/* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps.  The comparison
10099
   instruction requires TARGET_FLAGS.  */
10100
#define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS)                        \
10101
  { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND,          \
10102
    "__builtin_mips_movt_" #INSN "_" #COND "_ps",                       \
10103
    MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,             \
10104
    TARGET_FLAGS },                                                     \
10105
  { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND,          \
10106
    "__builtin_mips_movf_" #INSN "_" #COND "_ps",                       \
10107
    MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,             \
10108
    TARGET_FLAGS }
10109
 
10110
/* Define all the builtins related to c.cond.fmt condition COND.  */
10111
#define CMP_BUILTINS(COND)                                              \
10112
  MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT),                   \
10113
  MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D),                             \
10114
  CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D),                        \
10115
  CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT),                  \
10116
  CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D),                            \
10117
  CMP_4S_BUILTINS (c, COND),                                            \
10118
  CMP_4S_BUILTINS (cabs, COND)
10119
 
10120
static const struct builtin_description mips_bdesc[] =
10121
{
10122
  DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10123
  DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10124
  DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10125
  DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10126
  DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10127
  DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10128
  DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10129
  DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10130
 
10131
  DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10132
                  MASK_PAIRED_SINGLE_FLOAT),
10133
  DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10134
  DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10135
  DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10136
  DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10137
 
10138
  DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10139
  DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10140
  DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10141
  DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10142
  DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10143
  DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10144
 
10145
  DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10146
  DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10147
  DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10148
  DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10149
  DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10150
  DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10151
 
10152
  MIPS_FP_CONDITIONS (CMP_BUILTINS)
10153
};
10154
 
10155
/* Builtin functions for the SB-1 processor.  */
10156
 
10157
#define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10158
 
10159
static const struct builtin_description sb1_bdesc[] =
10160
{
10161
  DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10162
};
10163
 
10164
/* Builtin functions for DSP ASE.  */
10165
 
10166
#define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10167
#define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10168
#define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10169
#define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10170
 
10171
/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10172
   CODE_FOR_mips_<INSN>.  FUNCTION_TYPE and TARGET_FLAGS are
10173
   builtin_description fields.  */
10174
#define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS)     \
10175
  { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN,                 \
10176
    MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10177
 
10178
/* Define __builtin_mips_bposge<VALUE>.  <VALUE> is 32 for the MIPS32 DSP
10179
   branch instruction.  TARGET_FLAGS is a builtin_description field.  */
10180
#define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS)                             \
10181
  { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE,             \
10182
    MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10183
 
10184
static const struct builtin_description dsp_bdesc[] =
10185
{
10186
  DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10187
  DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10188
  DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10189
  DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10190
  DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10191
  DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10192
  DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10193
  DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10194
  DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10195
  DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10196
  DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10197
  DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10198
  DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10199
  DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10200
  DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10201
  DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10202
  DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10203
  DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10204
  DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10205
  DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10206
  DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10207
  DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10208
  DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10209
  DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10210
  DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10211
  DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10212
  DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10213
  DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10214
  DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10215
  DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10216
  DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10217
  DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10218
  DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10219
  DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10220
  DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10221
  DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10222
  DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10223
  DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10224
  DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10225
  DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10226
  DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10227
  DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10228
  DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10229
  DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10230
  DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10231
  DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10232
  DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10233
  DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10234
  DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10235
  DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10236
  DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10237
  DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10238
  DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10239
  DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10240
  DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10241
  DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10242
  DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10243
  DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10244
  DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10245
  DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10246
  DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10247
  DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10248
  DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10249
  DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10250
  DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10251
  DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10252
  DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10253
  DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10254
  DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10255
  DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10256
  DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10257
  DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10258
  DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10259
  DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10260
  DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10261
  DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10262
  DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10263
  DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10264
  DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10265
  DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10266
  DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10267
  DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10268
  DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10269
  DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10270
  DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10271
  BPOSGE_BUILTIN (32, MASK_DSP)
10272
};
10273
 
10274
/* This helps provide a mapping from builtin function codes to bdesc
10275
   arrays.  */
10276
 
10277
struct bdesc_map
10278
{
10279
  /* The builtin function table that this entry describes.  */
10280
  const struct builtin_description *bdesc;
10281
 
10282
  /* The number of entries in the builtin function table.  */
10283
  unsigned int size;
10284
 
10285
  /* The target processor that supports these builtin functions.
10286
     PROCESSOR_MAX means we enable them for all processors.  */
10287
  enum processor_type proc;
10288
};
10289
 
10290
static const struct bdesc_map bdesc_arrays[] =
10291
{
10292
  { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10293
  { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10294
  { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10295
};
10296
 
10297
/* Take the head of argument list *ARGLIST and convert it into a form
10298
   suitable for input operand OP of instruction ICODE.  Return the value
10299
   and point *ARGLIST at the next element of the list.  */
10300
 
10301
static rtx
10302
mips_prepare_builtin_arg (enum insn_code icode,
10303
                          unsigned int op, tree *arglist)
10304
{
10305
  rtx value;
10306
  enum machine_mode mode;
10307
 
10308
  value = expand_normal (TREE_VALUE (*arglist));
10309
  mode = insn_data[icode].operand[op].mode;
10310
  if (!insn_data[icode].operand[op].predicate (value, mode))
10311
    {
10312
      value = copy_to_mode_reg (mode, value);
10313
      /* Check the predicate again.  */
10314
      if (!insn_data[icode].operand[op].predicate (value, mode))
10315
        {
10316
          error ("invalid argument to builtin function");
10317
          return const0_rtx;
10318
        }
10319
    }
10320
 
10321
  *arglist = TREE_CHAIN (*arglist);
10322
  return value;
10323
}
10324
 
10325
/* Return an rtx suitable for output operand OP of instruction ICODE.
10326
   If TARGET is non-null, try to use it where possible.  */
10327
 
10328
static rtx
10329
mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10330
{
10331
  enum machine_mode mode;
10332
 
10333
  mode = insn_data[icode].operand[op].mode;
10334
  if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10335
    target = gen_reg_rtx (mode);
10336
 
10337
  return target;
10338
}
10339
 
10340
/* Expand builtin functions.  This is called from TARGET_EXPAND_BUILTIN.  */
10341
 
10342
rtx
10343
mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10344
                     enum machine_mode mode ATTRIBUTE_UNUSED,
10345
                     int ignore ATTRIBUTE_UNUSED)
10346
{
10347
  enum insn_code icode;
10348
  enum mips_builtin_type type;
10349
  tree fndecl, arglist;
10350
  unsigned int fcode;
10351
  const struct builtin_description *bdesc;
10352
  const struct bdesc_map *m;
10353
 
10354
  fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10355
  arglist = TREE_OPERAND (exp, 1);
10356
  fcode = DECL_FUNCTION_CODE (fndecl);
10357
 
10358
  bdesc = NULL;
10359
  for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10360
    {
10361
      if (fcode < m->size)
10362
        {
10363
          bdesc = m->bdesc;
10364
          icode = bdesc[fcode].icode;
10365
          type = bdesc[fcode].builtin_type;
10366
          break;
10367
        }
10368
      fcode -= m->size;
10369
    }
10370
  if (bdesc == NULL)
10371
    return 0;
10372
 
10373
  switch (type)
10374
    {
10375
    case MIPS_BUILTIN_DIRECT:
10376
      return mips_expand_builtin_direct (icode, target, arglist, true);
10377
 
10378
    case MIPS_BUILTIN_DIRECT_NO_TARGET:
10379
      return mips_expand_builtin_direct (icode, target, arglist, false);
10380
 
10381
    case MIPS_BUILTIN_MOVT:
10382
    case MIPS_BUILTIN_MOVF:
10383
      return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10384
                                        target, arglist);
10385
 
10386
    case MIPS_BUILTIN_CMP_ANY:
10387
    case MIPS_BUILTIN_CMP_ALL:
10388
    case MIPS_BUILTIN_CMP_UPPER:
10389
    case MIPS_BUILTIN_CMP_LOWER:
10390
    case MIPS_BUILTIN_CMP_SINGLE:
10391
      return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10392
                                          target, arglist);
10393
 
10394
    case MIPS_BUILTIN_BPOSGE32:
10395
      return mips_expand_builtin_bposge (type, target);
10396
 
10397
    default:
10398
      return 0;
10399
    }
10400
}
10401
 
10402
/* Init builtin functions.  This is called from TARGET_INIT_BUILTIN.  */
10403
 
10404
void
10405
mips_init_builtins (void)
10406
{
10407
  const struct builtin_description *d;
10408
  const struct bdesc_map *m;
10409
  tree types[(int) MIPS_MAX_FTYPE_MAX];
10410
  tree V2SF_type_node;
10411
  tree V2HI_type_node;
10412
  tree V4QI_type_node;
10413
  unsigned int offset;
10414
 
10415
  /* We have only builtins for -mpaired-single, -mips3d and -mdsp.  */
10416
  if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10417
    return;
10418
 
10419
  if (TARGET_PAIRED_SINGLE_FLOAT)
10420
    {
10421
      V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10422
 
10423
      types[MIPS_V2SF_FTYPE_V2SF]
10424
        = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10425
 
10426
      types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10427
        = build_function_type_list (V2SF_type_node,
10428
                                    V2SF_type_node, V2SF_type_node, NULL_TREE);
10429
 
10430
      types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10431
        = build_function_type_list (V2SF_type_node,
10432
                                    V2SF_type_node, V2SF_type_node,
10433
                                    integer_type_node, NULL_TREE);
10434
 
10435
      types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10436
        = build_function_type_list (V2SF_type_node,
10437
                                    V2SF_type_node, V2SF_type_node,
10438
                                    V2SF_type_node, V2SF_type_node, NULL_TREE);
10439
 
10440
      types[MIPS_V2SF_FTYPE_SF_SF]
10441
        = build_function_type_list (V2SF_type_node,
10442
                                    float_type_node, float_type_node, NULL_TREE);
10443
 
10444
      types[MIPS_INT_FTYPE_V2SF_V2SF]
10445
        = build_function_type_list (integer_type_node,
10446
                                    V2SF_type_node, V2SF_type_node, NULL_TREE);
10447
 
10448
      types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10449
        = build_function_type_list (integer_type_node,
10450
                                    V2SF_type_node, V2SF_type_node,
10451
                                    V2SF_type_node, V2SF_type_node, NULL_TREE);
10452
 
10453
      types[MIPS_INT_FTYPE_SF_SF]
10454
        = build_function_type_list (integer_type_node,
10455
                                    float_type_node, float_type_node, NULL_TREE);
10456
 
10457
      types[MIPS_INT_FTYPE_DF_DF]
10458
        = build_function_type_list (integer_type_node,
10459
                                    double_type_node, double_type_node, NULL_TREE);
10460
 
10461
      types[MIPS_SF_FTYPE_V2SF]
10462
        = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10463
 
10464
      types[MIPS_SF_FTYPE_SF]
10465
        = build_function_type_list (float_type_node,
10466
                                    float_type_node, NULL_TREE);
10467
 
10468
      types[MIPS_SF_FTYPE_SF_SF]
10469
        = build_function_type_list (float_type_node,
10470
                                    float_type_node, float_type_node, NULL_TREE);
10471
 
10472
      types[MIPS_DF_FTYPE_DF]
10473
        = build_function_type_list (double_type_node,
10474
                                    double_type_node, NULL_TREE);
10475
 
10476
      types[MIPS_DF_FTYPE_DF_DF]
10477
        = build_function_type_list (double_type_node,
10478
                                    double_type_node, double_type_node, NULL_TREE);
10479
    }
10480
 
10481
  if (TARGET_DSP)
10482
    {
10483
      V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10484
      V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10485
 
10486
      types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10487
        = build_function_type_list (V2HI_type_node,
10488
                                    V2HI_type_node, V2HI_type_node,
10489
                                    NULL_TREE);
10490
 
10491
      types[MIPS_SI_FTYPE_SI_SI]
10492
        = build_function_type_list (intSI_type_node,
10493
                                    intSI_type_node, intSI_type_node,
10494
                                    NULL_TREE);
10495
 
10496
      types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10497
        = build_function_type_list (V4QI_type_node,
10498
                                    V4QI_type_node, V4QI_type_node,
10499
                                    NULL_TREE);
10500
 
10501
      types[MIPS_SI_FTYPE_V4QI]
10502
        = build_function_type_list (intSI_type_node,
10503
                                    V4QI_type_node,
10504
                                    NULL_TREE);
10505
 
10506
      types[MIPS_V2HI_FTYPE_V2HI]
10507
        = build_function_type_list (V2HI_type_node,
10508
                                    V2HI_type_node,
10509
                                    NULL_TREE);
10510
 
10511
      types[MIPS_SI_FTYPE_SI]
10512
        = build_function_type_list (intSI_type_node,
10513
                                    intSI_type_node,
10514
                                    NULL_TREE);
10515
 
10516
      types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10517
        = build_function_type_list (V4QI_type_node,
10518
                                    V2HI_type_node, V2HI_type_node,
10519
                                    NULL_TREE);
10520
 
10521
      types[MIPS_V2HI_FTYPE_SI_SI]
10522
        = build_function_type_list (V2HI_type_node,
10523
                                    intSI_type_node, intSI_type_node,
10524
                                    NULL_TREE);
10525
 
10526
      types[MIPS_SI_FTYPE_V2HI]
10527
        = build_function_type_list (intSI_type_node,
10528
                                    V2HI_type_node,
10529
                                    NULL_TREE);
10530
 
10531
      types[MIPS_V2HI_FTYPE_V4QI]
10532
        = build_function_type_list (V2HI_type_node,
10533
                                    V4QI_type_node,
10534
                                    NULL_TREE);
10535
 
10536
      types[MIPS_V4QI_FTYPE_V4QI_SI]
10537
        = build_function_type_list (V4QI_type_node,
10538
                                    V4QI_type_node, intSI_type_node,
10539
                                    NULL_TREE);
10540
 
10541
      types[MIPS_V2HI_FTYPE_V2HI_SI]
10542
        = build_function_type_list (V2HI_type_node,
10543
                                    V2HI_type_node, intSI_type_node,
10544
                                    NULL_TREE);
10545
 
10546
      types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10547
        = build_function_type_list (V2HI_type_node,
10548
                                    V4QI_type_node, V2HI_type_node,
10549
                                    NULL_TREE);
10550
 
10551
      types[MIPS_SI_FTYPE_V2HI_V2HI]
10552
        = build_function_type_list (intSI_type_node,
10553
                                    V2HI_type_node, V2HI_type_node,
10554
                                    NULL_TREE);
10555
 
10556
      types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10557
        = build_function_type_list (intDI_type_node,
10558
                                    intDI_type_node, V4QI_type_node, V4QI_type_node,
10559
                                    NULL_TREE);
10560
 
10561
      types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10562
        = build_function_type_list (intDI_type_node,
10563
                                    intDI_type_node, V2HI_type_node, V2HI_type_node,
10564
                                    NULL_TREE);
10565
 
10566
      types[MIPS_DI_FTYPE_DI_SI_SI]
10567
        = build_function_type_list (intDI_type_node,
10568
                                    intDI_type_node, intSI_type_node, intSI_type_node,
10569
                                    NULL_TREE);
10570
 
10571
      types[MIPS_V4QI_FTYPE_SI]
10572
        = build_function_type_list (V4QI_type_node,
10573
                                    intSI_type_node,
10574
                                    NULL_TREE);
10575
 
10576
      types[MIPS_V2HI_FTYPE_SI]
10577
        = build_function_type_list (V2HI_type_node,
10578
                                    intSI_type_node,
10579
                                    NULL_TREE);
10580
 
10581
      types[MIPS_VOID_FTYPE_V4QI_V4QI]
10582
        = build_function_type_list (void_type_node,
10583
                                    V4QI_type_node, V4QI_type_node,
10584
                                    NULL_TREE);
10585
 
10586
      types[MIPS_SI_FTYPE_V4QI_V4QI]
10587
        = build_function_type_list (intSI_type_node,
10588
                                    V4QI_type_node, V4QI_type_node,
10589
                                    NULL_TREE);
10590
 
10591
      types[MIPS_VOID_FTYPE_V2HI_V2HI]
10592
        = build_function_type_list (void_type_node,
10593
                                    V2HI_type_node, V2HI_type_node,
10594
                                    NULL_TREE);
10595
 
10596
      types[MIPS_SI_FTYPE_DI_SI]
10597
        = build_function_type_list (intSI_type_node,
10598
                                    intDI_type_node, intSI_type_node,
10599
                                    NULL_TREE);
10600
 
10601
      types[MIPS_DI_FTYPE_DI_SI]
10602
        = build_function_type_list (intDI_type_node,
10603
                                    intDI_type_node, intSI_type_node,
10604
                                    NULL_TREE);
10605
 
10606
      types[MIPS_VOID_FTYPE_SI_SI]
10607
        = build_function_type_list (void_type_node,
10608
                                    intSI_type_node, intSI_type_node,
10609
                                    NULL_TREE);
10610
 
10611
      types[MIPS_SI_FTYPE_PTR_SI]
10612
        = build_function_type_list (intSI_type_node,
10613
                                    ptr_type_node, intSI_type_node,
10614
                                    NULL_TREE);
10615
 
10616
      types[MIPS_SI_FTYPE_VOID]
10617
        = build_function_type (intSI_type_node, void_list_node);
10618
    }
10619
 
10620
  /* Iterate through all of the bdesc arrays, initializing all of the
10621
     builtin functions.  */
10622
 
10623
  offset = 0;
10624
  for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10625
    {
10626
      if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10627
        for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10628
          if ((d->target_flags & target_flags) == d->target_flags)
10629
            lang_hooks.builtin_function (d->name, types[d->function_type],
10630
                                         d - m->bdesc + offset,
10631
                                         BUILT_IN_MD, NULL, NULL);
10632
      offset += m->size;
10633
    }
10634
}
10635
 
10636
/* Expand a MIPS_BUILTIN_DIRECT function.  ICODE is the code of the
10637
   .md pattern and ARGLIST is the list of function arguments.  TARGET,
10638
   if nonnull, suggests a good place to put the result.
10639
   HAS_TARGET indicates the function must return something.  */
10640
 
10641
static rtx
10642
mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
10643
                            bool has_target)
10644
{
10645
  rtx ops[MAX_RECOG_OPERANDS];
10646
  int i = 0;
10647
 
10648
  if (has_target)
10649
    {
10650
      /* We save target to ops[0].  */
10651
      ops[0] = mips_prepare_builtin_target (icode, 0, target);
10652
      i = 1;
10653
    }
10654
 
10655
  /* We need to test if arglist is not zero.  Some instructions have extra
10656
     clobber registers.  */
10657
  for (; i < insn_data[icode].n_operands && arglist != 0; i++)
10658
    ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10659
 
10660
  switch (i)
10661
    {
10662
    case 2:
10663
      emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10664
      break;
10665
 
10666
    case 3:
10667
      emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10668
      break;
10669
 
10670
    case 4:
10671
      emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10672
      break;
10673
 
10674
    default:
10675
      gcc_unreachable ();
10676
    }
10677
  return target;
10678
}
10679
 
10680
/* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10681
   function (TYPE says which).  ARGLIST is the list of arguments to the
10682
   function, ICODE is the instruction that should be used to compare
10683
   the first two arguments, and COND is the condition it should test.
10684
   TARGET, if nonnull, suggests a good place to put the result.  */
10685
 
10686
static rtx
10687
mips_expand_builtin_movtf (enum mips_builtin_type type,
10688
                           enum insn_code icode, enum mips_fp_condition cond,
10689
                           rtx target, tree arglist)
10690
{
10691
  rtx cmp_result, op0, op1;
10692
 
10693
  cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10694
  op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10695
  op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10696
  emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10697
 
10698
  icode = CODE_FOR_mips_cond_move_tf_ps;
10699
  target = mips_prepare_builtin_target (icode, 0, target);
10700
  if (type == MIPS_BUILTIN_MOVT)
10701
    {
10702
      op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10703
      op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10704
    }
10705
  else
10706
    {
10707
      op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10708
      op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10709
    }
10710
  emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10711
  return target;
10712
}
10713
 
10714
/* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10715
   into TARGET otherwise.  Return TARGET.  */
10716
 
10717
static rtx
10718
mips_builtin_branch_and_move (rtx condition, rtx target,
10719
                              rtx value_if_true, rtx value_if_false)
10720
{
10721
  rtx true_label, done_label;
10722
 
10723
  true_label = gen_label_rtx ();
10724
  done_label = gen_label_rtx ();
10725
 
10726
  /* First assume that CONDITION is false.  */
10727
  emit_move_insn (target, value_if_false);
10728
 
10729
  /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise.  */
10730
  emit_jump_insn (gen_condjump (condition, true_label));
10731
  emit_jump_insn (gen_jump (done_label));
10732
  emit_barrier ();
10733
 
10734
  /* Fix TARGET if CONDITION is true.  */
10735
  emit_label (true_label);
10736
  emit_move_insn (target, value_if_true);
10737
 
10738
  emit_label (done_label);
10739
  return target;
10740
}
10741
 
10742
/* Expand a comparison builtin of type BUILTIN_TYPE.  ICODE is the code
10743
   of the comparison instruction and COND is the condition it should test.
10744
   ARGLIST is the list of function arguments and TARGET, if nonnull,
10745
   suggests a good place to put the boolean result.  */
10746
 
10747
static rtx
10748
mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10749
                             enum insn_code icode, enum mips_fp_condition cond,
10750
                             rtx target, tree arglist)
10751
{
10752
  rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10753
  int i;
10754
 
10755
  if (target == 0 || GET_MODE (target) != SImode)
10756
    target = gen_reg_rtx (SImode);
10757
 
10758
  /* Prepare the operands to the comparison.  */
10759
  cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10760
  for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10761
    ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10762
 
10763
  switch (insn_data[icode].n_operands)
10764
    {
10765
    case 4:
10766
      emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10767
      break;
10768
 
10769
    case 6:
10770
      emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10771
                                  ops[3], ops[4], GEN_INT (cond)));
10772
      break;
10773
 
10774
    default:
10775
      gcc_unreachable ();
10776
    }
10777
 
10778
  /* If the comparison sets more than one register, we define the result
10779
     to be 0 if all registers are false and -1 if all registers are true.
10780
     The value of the complete result is indeterminate otherwise.  */
10781
  switch (builtin_type)
10782
    {
10783
    case MIPS_BUILTIN_CMP_ALL:
10784
      condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10785
      return mips_builtin_branch_and_move (condition, target,
10786
                                           const0_rtx, const1_rtx);
10787
 
10788
    case MIPS_BUILTIN_CMP_UPPER:
10789
    case MIPS_BUILTIN_CMP_LOWER:
10790
      offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10791
      condition = gen_single_cc (cmp_result, offset);
10792
      return mips_builtin_branch_and_move (condition, target,
10793
                                           const1_rtx, const0_rtx);
10794
 
10795
    default:
10796
      condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10797
      return mips_builtin_branch_and_move (condition, target,
10798
                                           const1_rtx, const0_rtx);
10799
    }
10800
}
10801
 
10802
/* Expand a bposge builtin of type BUILTIN_TYPE.  TARGET, if nonnull,
10803
   suggests a good place to put the boolean result.  */
10804
 
10805
static rtx
10806
mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10807
{
10808
  rtx condition, cmp_result;
10809
  int cmp_value;
10810
 
10811
  if (target == 0 || GET_MODE (target) != SImode)
10812
    target = gen_reg_rtx (SImode);
10813
 
10814
  cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10815
 
10816
  if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10817
    cmp_value = 32;
10818
  else
10819
    gcc_assert (0);
10820
 
10821
  condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10822
  return mips_builtin_branch_and_move (condition, target,
10823
                                       const1_rtx, const0_rtx);
10824
}
10825
 
10826
/* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10827
   FIRST is true if this is the first time handling this decl.  */
10828
 
10829
static void
10830
mips_encode_section_info (tree decl, rtx rtl, int first)
10831
{
10832
  default_encode_section_info (decl, rtl, first);
10833
 
10834
  if (TREE_CODE (decl) == FUNCTION_DECL
10835
      && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10836
    {
10837
      rtx symbol = XEXP (rtl, 0);
10838
      SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10839
    }
10840
}
10841
 
10842
/* Implement TARGET_EXTRA_LIVE_ON_ENTRY.  PIC_FUNCTION_ADDR_REGNUM is live
10843
   on entry to a function when generating -mshared abicalls code.  */
10844
 
10845
static void
10846
mips_extra_live_on_entry (bitmap regs)
10847
{
10848
  if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
10849
    bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10850
}
10851
 
10852
/* SImode values are represented as sign-extended to DImode.  */
10853
 
10854
int
10855
mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10856
{
10857
  if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10858
    return SIGN_EXTEND;
10859
 
10860
  return UNKNOWN;
10861
}
10862
 
10863
#include "gt-mips.h"

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