1 |
38 |
julius |
;; Machine description for GNU compiler, OpenRISC 1000 family, OR32 ISA
|
2 |
|
|
;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
|
3 |
|
|
;; Contributed by Damjan Lampret in 1999.
|
4 |
|
|
;; Major optimizations by Matjaz Breskvar in 2005.
|
5 |
|
|
|
6 |
|
|
;; This file is part of GNU CC.
|
7 |
|
|
|
8 |
|
|
;; GNU CC is free software; you can redistribute it and/or modify
|
9 |
|
|
;; it under the terms of the GNU General Public License as published by
|
10 |
|
|
;; the Free Software Foundation; either version 1, or (at your option)
|
11 |
|
|
;; any later version.
|
12 |
|
|
|
13 |
|
|
;; GNU CC is distributed in the hope that it will be useful,
|
14 |
|
|
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
15 |
|
|
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
16 |
|
|
;; GNU General Public License for more details.
|
17 |
|
|
|
18 |
|
|
;; You should have received a copy of the GNU General Public License
|
19 |
|
|
;; along with GNU CC; see the file COPYING. If not, write to
|
20 |
|
|
;; the Free Software Foundation, 59 Temple Place - Suite 330,
|
21 |
|
|
;; Boston, MA 02111-1307, USA.
|
22 |
|
|
|
23 |
|
|
(include "predicates.md")
|
24 |
|
|
|
25 |
|
|
(define_attr "type"
|
26 |
|
|
"unknown,load,store,move,extend,logic,add,mul,shift,compare,branch,jump,fp"
|
27 |
|
|
(const_string "unknown"))
|
28 |
|
|
|
29 |
|
|
;; Number of instructions
|
30 |
|
|
(define_attr "length" "" (const_int 1))
|
31 |
|
|
|
32 |
|
|
(define_delay (eq_attr "type" "branch,jump")
|
33 |
|
|
[(and (eq_attr "type" "!branch,jump")
|
34 |
|
|
(eq_attr "length" "1")) (nil) (nil)])
|
35 |
|
|
|
36 |
|
|
;; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
|
37 |
|
|
;; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
|
38 |
|
|
;; MULTIPLICITY - Number of functional units of this type
|
39 |
|
|
;; SIMULTANEITY - Zero for pipelined functional unit
|
40 |
|
|
;; READY-DELAY - Number of cycles before result is available
|
41 |
|
|
;; ISSUE-DELAY - Number of cycles before unit can accept new instruction
|
42 |
|
|
;;
|
43 |
|
|
;(define_function_unit "bit_unit" 1 0 (eq_attr "type" "shift") 3 1)
|
44 |
|
|
;(define_function_unit "lsu" 1 0 (eq_attr "type" "load") 3 3)
|
45 |
|
|
;(define_function_unit "lsu" 1 0 (eq_attr "type" "store") 2 1)
|
46 |
|
|
;(define_function_unit "alu" 1 0 (eq_attr "type" "add,logic,extend,move,compare") 2 1)
|
47 |
|
|
;(define_function_unit "mul_unit" 1 0 (eq_attr "type" "mul") 16 16)
|
48 |
|
|
(define_cpu_unit "or32_alu")
|
49 |
|
|
(define_insn_reservation "bit_unit" 3 (eq_attr "type" "shift") "or32_alu")
|
50 |
|
|
(define_insn_reservation "lsu_load" 3 (eq_attr "type" "load") "or32_alu*3")
|
51 |
|
|
(define_insn_reservation "lsu_store" 2 (eq_attr "type" "store") "or32_alu")
|
52 |
|
|
(define_insn_reservation "alu_unit" 2 (eq_attr "type" "add,logic,extend,move,compare") "or32_alu")
|
53 |
|
|
(define_insn_reservation "mul_unit" 16 (eq_attr "type" "mul") "or32_alu*16")
|
54 |
|
|
|
55 |
|
|
|
56 |
|
|
;; Called after register allocation to add any instructions needed for the
|
57 |
|
|
;; prologue. Using a prologue insn is favored compared to putting all of the
|
58 |
|
|
;; instructions in output_function_prologue(), since it allows the scheduler
|
59 |
|
|
;; to intermix instructions with the saves of the caller saved registers. In
|
60 |
|
|
;; some cases, it might be necessary to emit a barrier instruction as the last
|
61 |
|
|
;; insn to prevent such scheduling.
|
62 |
|
|
|
63 |
|
|
(define_expand "prologue"
|
64 |
|
|
[(use (const_int 1))]
|
65 |
|
|
"TARGET_MASK_SCHED_LOGUE"
|
66 |
|
|
{
|
67 |
|
|
or32_expand_prologue ();
|
68 |
|
|
DONE;
|
69 |
|
|
})
|
70 |
|
|
|
71 |
|
|
;; Called after register allocation to add any instructions needed for the
|
72 |
|
|
;; epilogue. Using an epilogue insn is favored compared to putting all of the
|
73 |
|
|
;; instructions in output_function_epilogue(), since it allows the scheduler
|
74 |
|
|
;; to intermix instructions with the restores of the caller saved registers.
|
75 |
|
|
;; In some cases, it might be necessary to emit a barrier instruction as the
|
76 |
|
|
;; first insn to prevent such scheduling.
|
77 |
|
|
(define_expand "epilogue"
|
78 |
|
|
[(use (const_int 2))]
|
79 |
|
|
"TARGET_MASK_SCHED_LOGUE"
|
80 |
|
|
{
|
81 |
|
|
or32_expand_epilogue (false);
|
82 |
|
|
DONE;
|
83 |
|
|
})
|
84 |
|
|
|
85 |
|
|
(define_expand "sibcall_epilogue"
|
86 |
|
|
[(use (const_int 2))]
|
87 |
|
|
"TARGET_MASK_SCHED_LOGUE"
|
88 |
|
|
{
|
89 |
|
|
or32_expand_epilogue (true);
|
90 |
|
|
DONE;
|
91 |
|
|
})
|
92 |
|
|
|
93 |
|
|
(define_insn "return_internal"
|
94 |
|
|
[(return)
|
95 |
|
|
(use (match_operand 0 "pmode_register_operand" ""))]
|
96 |
|
|
"TARGET_MASK_SCHED_LOGUE"
|
97 |
|
|
"l.jr \t%0%("
|
98 |
|
|
[(set_attr "type" "jump")
|
99 |
|
|
(set_attr "length" "1")])
|
100 |
|
|
|
101 |
|
|
;;
|
102 |
|
|
;; Sibcalls
|
103 |
|
|
;;
|
104 |
|
|
|
105 |
|
|
(define_expand "sibcall"
|
106 |
|
|
[(parallel [(call (match_operand 0 "" "")
|
107 |
|
|
(match_operand 1 "" ""))
|
108 |
|
|
(use (match_operand 2 "" "")) ;; next_arg_reg
|
109 |
|
|
(use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
|
110 |
|
|
"TARGET_MASK_SIBCALL"
|
111 |
|
|
"
|
112 |
|
|
{
|
113 |
|
|
or32_expand_sibcall (0, XEXP (operands[0], 0), operands[1]);
|
114 |
|
|
DONE;
|
115 |
|
|
}")
|
116 |
|
|
|
117 |
|
|
(define_expand "sibcall_value"
|
118 |
|
|
[(set (match_operand 0 "" "")
|
119 |
|
|
(call (match_operand:SI 1 "" "")
|
120 |
|
|
(match_operand 2 "" "")))]
|
121 |
|
|
"TARGET_MASK_SIBCALL"
|
122 |
|
|
"
|
123 |
|
|
{
|
124 |
|
|
or32_expand_sibcall (operands[0], XEXP (operands[1], 0), operands[2]);
|
125 |
|
|
DONE;
|
126 |
|
|
}")
|
127 |
|
|
|
128 |
|
|
(define_insn "sibcall_internal"
|
129 |
|
|
[(call (mem:SI (match_operand:SI 0 "sibcall_insn_operand" "s,r"))
|
130 |
|
|
(match_operand 1 "" ""))
|
131 |
|
|
(use (reg:SI 9))]
|
132 |
|
|
"TARGET_MASK_SIBCALL"
|
133 |
|
|
"@
|
134 |
|
|
l.j \t%S0%(\t # sibcall s
|
135 |
|
|
l.jr \t%0%(\t # sibcall r"
|
136 |
|
|
[(set_attr "type" "jump,jump")])
|
137 |
|
|
|
138 |
|
|
|
139 |
|
|
|
140 |
|
|
;;
|
141 |
|
|
;; movQI
|
142 |
|
|
;;
|
143 |
|
|
|
144 |
|
|
(define_expand "movqi"
|
145 |
|
|
[(set (match_operand:QI 0 "general_operand" "")
|
146 |
|
|
(match_operand:QI 1 "general_operand" ""))]
|
147 |
|
|
""
|
148 |
|
|
"
|
149 |
|
|
if (!no_new_pseudos)
|
150 |
|
|
{
|
151 |
|
|
if (GET_CODE (operands[1]) == CONST_INT)
|
152 |
|
|
{
|
153 |
|
|
rtx reg = gen_reg_rtx (SImode);
|
154 |
|
|
|
155 |
|
|
emit_insn (gen_movsi (reg, operands[1]));
|
156 |
|
|
operands[1] = gen_lowpart (QImode, reg);
|
157 |
|
|
}
|
158 |
|
|
if (GET_CODE (operands[1]) == MEM && optimize > 0)
|
159 |
|
|
{
|
160 |
|
|
rtx reg = gen_reg_rtx (SImode);
|
161 |
|
|
|
162 |
|
|
emit_insn (gen_rtx_SET (SImode, reg,
|
163 |
|
|
gen_rtx_ZERO_EXTEND (SImode,
|
164 |
|
|
operands[1])));
|
165 |
|
|
|
166 |
|
|
operands[1] = gen_lowpart (QImode, reg);
|
167 |
|
|
}
|
168 |
|
|
if (GET_CODE (operands[0]) != REG)
|
169 |
|
|
operands[1] = force_reg (QImode, operands[1]);
|
170 |
|
|
}
|
171 |
|
|
")
|
172 |
|
|
|
173 |
|
|
(define_insn "*movqi_internal"
|
174 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,r,r,r,r")
|
175 |
|
|
(match_operand:QI 1 "general_operand" "r,r,I,K,m"))]
|
176 |
|
|
""
|
177 |
|
|
"@
|
178 |
|
|
l.sb \t%0,%1\t # movqi
|
179 |
|
|
l.ori \t%0,%1,0\t # movqi: move reg to reg
|
180 |
|
|
l.addi \t%0,r0,%1\t # movqi: move immediate
|
181 |
|
|
l.ori \t%0,r0,%1\t # movqi: move immediate
|
182 |
|
|
l.lbz \t%0,%1\t # movqi"
|
183 |
|
|
[(set_attr "type" "store,add,add,logic,load")])
|
184 |
|
|
|
185 |
|
|
|
186 |
|
|
;;
|
187 |
|
|
;; movHI
|
188 |
|
|
;;
|
189 |
|
|
|
190 |
|
|
(define_expand "movhi"
|
191 |
|
|
[(set (match_operand:HI 0 "general_operand" "")
|
192 |
|
|
(match_operand:HI 1 "general_operand" ""))]
|
193 |
|
|
""
|
194 |
|
|
"
|
195 |
|
|
if (!no_new_pseudos)
|
196 |
|
|
{
|
197 |
|
|
if (GET_CODE (operands[1]) == CONST_INT)
|
198 |
|
|
{
|
199 |
|
|
rtx reg = gen_reg_rtx (SImode);
|
200 |
|
|
|
201 |
|
|
emit_insn (gen_movsi (reg, operands[1]));
|
202 |
|
|
operands[1] = gen_lowpart (HImode, reg);
|
203 |
|
|
}
|
204 |
|
|
if (GET_CODE (operands[1]) == MEM && optimize > 0)
|
205 |
|
|
{
|
206 |
|
|
rtx reg = gen_reg_rtx (SImode);
|
207 |
|
|
|
208 |
|
|
emit_insn (gen_rtx_SET (SImode, reg,
|
209 |
|
|
gen_rtx_ZERO_EXTEND (SImode,
|
210 |
|
|
operands[1])));
|
211 |
|
|
operands[1] = gen_lowpart (HImode, reg);
|
212 |
|
|
}
|
213 |
|
|
if (GET_CODE (operands[0]) != REG)
|
214 |
|
|
operands[1] = force_reg (HImode, operands[1]);
|
215 |
|
|
}
|
216 |
|
|
")
|
217 |
|
|
|
218 |
|
|
(define_insn "*movhi_internal"
|
219 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,r,r,r,r")
|
220 |
|
|
(match_operand:HI 1 "general_operand" "r,r,I,K,m"))]
|
221 |
|
|
""
|
222 |
|
|
"@
|
223 |
|
|
l.sh \t%0,%1\t # movhi
|
224 |
|
|
l.ori \t%0,%1,0\t # movhi: move reg to reg
|
225 |
|
|
l.addi \t%0,r0,%1\t # movhi: move immediate
|
226 |
|
|
l.ori \t%0,r0,%1\t # movhi: move immediate
|
227 |
|
|
l.lhz \t%0,%1\t # movhi"
|
228 |
|
|
[(set_attr "type" "store,add,add,logic,load")])
|
229 |
|
|
|
230 |
|
|
(define_expand "movsi"
|
231 |
|
|
[(set (match_operand:SI 0 "general_operand" "")
|
232 |
|
|
(match_operand:SI 1 "general_operand" ""))]
|
233 |
|
|
""
|
234 |
|
|
{
|
235 |
|
|
/* Working with CONST_INTs is easier, so convert
|
236 |
|
|
a double if needed. */
|
237 |
|
|
|
238 |
|
|
if (GET_CODE (operands[1]) == CONST_DOUBLE) {
|
239 |
|
|
operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
|
240 |
|
|
}
|
241 |
|
|
|
242 |
|
|
/* Handle sets of MEM first. */
|
243 |
|
|
if (GET_CODE (operands[0]) == MEM)
|
244 |
|
|
{
|
245 |
|
|
if (register_operand(operands[1], SImode)
|
246 |
|
|
|| (operands[1] == const0_rtx))
|
247 |
|
|
goto movsi_is_ok;
|
248 |
|
|
|
249 |
|
|
if (! reload_in_progress)
|
250 |
|
|
{
|
251 |
|
|
operands[0] = validize_mem (operands[0]);
|
252 |
|
|
operands[1] = force_reg (SImode, operands[1]);
|
253 |
|
|
}
|
254 |
|
|
}
|
255 |
|
|
|
256 |
|
|
/* This makes sure we will not get rematched due to splittage. */
|
257 |
|
|
if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
|
258 |
|
|
;
|
259 |
|
|
else if (CONSTANT_P (operands[1])
|
260 |
|
|
&& GET_CODE (operands[1]) != HIGH
|
261 |
|
|
&& GET_CODE (operands[1]) != LO_SUM)
|
262 |
|
|
{
|
263 |
|
|
or32_emit_set_const32 (operands[0], operands[1]);
|
264 |
|
|
DONE;
|
265 |
|
|
}
|
266 |
|
|
movsi_is_ok:
|
267 |
|
|
;
|
268 |
|
|
})
|
269 |
|
|
|
270 |
|
|
;;
|
271 |
|
|
;; movSI
|
272 |
|
|
;;
|
273 |
|
|
|
274 |
|
|
(define_insn "*movsi_insn"
|
275 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
|
276 |
|
|
(match_operand:SI 1 "input_operand" "I,K,M,r,m,r"))]
|
277 |
|
|
"(register_operand (operands[0], SImode)
|
278 |
|
|
|| register_operand (operands[1], SImode)
|
279 |
|
|
|| (operands[1] == const0_rtx))"
|
280 |
|
|
"@
|
281 |
|
|
l.addi \t%0,r0,%1\t # move immediate I
|
282 |
|
|
l.ori \t%0,r0,%1\t # move immediate K
|
283 |
|
|
l.movhi \t%0,hi(%1)\t # move immediate M
|
284 |
|
|
l.ori \t%0,%1,0\t # move reg to reg
|
285 |
|
|
l.lwz \t%0,%1\t # SI load
|
286 |
|
|
l.sw \t%0,%1\t # SI store"
|
287 |
|
|
[(set_attr "type" "add,load,store,add,logic,move")
|
288 |
|
|
(set_attr "length" "1,1,1,1,1,1")])
|
289 |
|
|
|
290 |
|
|
(define_insn "*movsi_lo_sum"
|
291 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
292 |
|
|
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
|
293 |
|
|
(match_operand:SI 2 "immediate_operand" "i")))]
|
294 |
|
|
""
|
295 |
|
|
"l.ori \t%0,%1,lo(%2)"
|
296 |
|
|
[(set_attr "type" "logic")
|
297 |
|
|
(set_attr "length" "1")])
|
298 |
|
|
|
299 |
|
|
(define_insn "*movsi_high"
|
300 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
301 |
|
|
(high:SI (match_operand:SI 1 "immediate_operand" "i")))]
|
302 |
|
|
""
|
303 |
|
|
"l.movhi \t%0,hi(%1)"
|
304 |
|
|
[(set_attr "type" "move")
|
305 |
|
|
(set_attr "length" "1")])
|
306 |
|
|
|
307 |
|
|
(define_insn "movsi_insn_big"
|
308 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
|
309 |
|
|
(match_operand:SI 1 "immediate_operand" "i"))]
|
310 |
|
|
"GET_CODE(operands[1]) != CONST_INT"
|
311 |
|
|
"l.movhi \t%0,hi(%1)\;l.ori \t%0,%0,lo(%1)"
|
312 |
|
|
[(set_attr "type" "move")
|
313 |
|
|
(set_attr "length" "2")])
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
;;
|
317 |
|
|
;; Conditional Branches & Moves
|
318 |
|
|
;;
|
319 |
|
|
|
320 |
|
|
(define_expand "addsicc"
|
321 |
|
|
[(match_operand:SI 0 "register_operand" "")
|
322 |
|
|
(match_operand 1 "comparison_operator" "")
|
323 |
|
|
(match_operand:SI 2 "register_operand" "")
|
324 |
|
|
(match_operand:SI 3 "register_operand" "")]
|
325 |
|
|
""
|
326 |
|
|
"FAIL;")
|
327 |
|
|
|
328 |
|
|
(define_expand "addhicc"
|
329 |
|
|
[(match_operand:HI 0 "register_operand" "")
|
330 |
|
|
(match_operand 1 "comparison_operator" "")
|
331 |
|
|
(match_operand:HI 2 "register_operand" "")
|
332 |
|
|
(match_operand:HI 3 "register_operand" "")]
|
333 |
|
|
""
|
334 |
|
|
"FAIL;")
|
335 |
|
|
|
336 |
|
|
(define_expand "addqicc"
|
337 |
|
|
[(match_operand:QI 0 "register_operand" "")
|
338 |
|
|
(match_operand 1 "comparison_operator" "")
|
339 |
|
|
(match_operand:QI 2 "register_operand" "")
|
340 |
|
|
(match_operand:QI 3 "register_operand" "")]
|
341 |
|
|
""
|
342 |
|
|
"FAIL;")
|
343 |
|
|
|
344 |
|
|
|
345 |
|
|
;;
|
346 |
|
|
;; conditional moves
|
347 |
|
|
;;
|
348 |
|
|
|
349 |
|
|
(define_expand "movsicc"
|
350 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
351 |
|
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
352 |
|
|
(match_operand:SI 2 "register_operand" "")
|
353 |
|
|
(match_operand:SI 3 "register_operand" "")))]
|
354 |
|
|
"TARGET_MASK_CMOV"
|
355 |
|
|
"
|
356 |
|
|
{
|
357 |
|
|
if (or32_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
|
358 |
|
|
DONE;
|
359 |
|
|
}")
|
360 |
|
|
|
361 |
|
|
(define_expand "movhicc"
|
362 |
|
|
[(set (match_operand:HI 0 "register_operand" "")
|
363 |
|
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
364 |
|
|
(match_operand:HI 2 "register_operand" "")
|
365 |
|
|
(match_operand:HI 3 "register_operand" "")))]
|
366 |
|
|
""
|
367 |
|
|
"
|
368 |
|
|
{
|
369 |
|
|
FAIL;
|
370 |
|
|
}")
|
371 |
|
|
|
372 |
|
|
(define_expand "movqicc"
|
373 |
|
|
[(set (match_operand:QI 0 "register_operand" "")
|
374 |
|
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
375 |
|
|
(match_operand:QI 2 "register_operand" "")
|
376 |
|
|
(match_operand:QI 3 "register_operand" "")))]
|
377 |
|
|
""
|
378 |
|
|
"
|
379 |
|
|
{
|
380 |
|
|
FAIL;
|
381 |
|
|
}")
|
382 |
|
|
|
383 |
|
|
|
384 |
|
|
;; We use the BASE_REGS for the cmov input operands because, if rA is
|
385 |
|
|
;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
|
386 |
|
|
;; because we may switch the operands and rB may end up being rA.
|
387 |
|
|
|
388 |
|
|
(define_insn "cmov"
|
389 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
390 |
|
|
(if_then_else:SI
|
391 |
|
|
(match_operator 1 "comparison_operator"
|
392 |
|
|
[(match_operand 4 "cc_reg_operand" "")
|
393 |
|
|
(const_int 0)])
|
394 |
|
|
(match_operand:SI 2 "register_operand" "r")
|
395 |
|
|
(match_operand:SI 3 "register_operand" "r")))]
|
396 |
|
|
"TARGET_MASK_CMOV"
|
397 |
|
|
"*
|
398 |
|
|
return or32_output_cmov(operands);
|
399 |
|
|
")
|
400 |
|
|
|
401 |
|
|
;;
|
402 |
|
|
;; ....................
|
403 |
|
|
;;
|
404 |
|
|
;; COMPARISONS
|
405 |
|
|
;;
|
406 |
|
|
;; ....................
|
407 |
|
|
|
408 |
|
|
;; Flow here is rather complex:
|
409 |
|
|
;;
|
410 |
|
|
;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
|
411 |
|
|
;; arguments into the branch_cmp array, and the type into
|
412 |
|
|
;; branch_type. No RTL is generated.
|
413 |
|
|
;;
|
414 |
|
|
;; 2) The appropriate branch define_expand is called, which then
|
415 |
|
|
;; creates the appropriate RTL for the comparison and branch.
|
416 |
|
|
;; Different CC modes are used, based on what type of branch is
|
417 |
|
|
;; done, so that we can constrain things appropriately. There
|
418 |
|
|
;; are assumptions in the rest of GCC that break if we fold the
|
419 |
|
|
;; operands into the branches for integer operations, and use cc0
|
420 |
|
|
;; for floating point, so we use the fp status register instead.
|
421 |
|
|
;; If needed, an appropriate temporary is created to hold the
|
422 |
|
|
;; of the integer compare.
|
423 |
|
|
|
424 |
|
|
;; Compare insns are next. Note that the RS/6000 has two types of compares,
|
425 |
|
|
;; signed & unsigned, and one type of branch.
|
426 |
|
|
;;
|
427 |
|
|
;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
|
428 |
|
|
;; insns, and branches. We store the operands of compares until we see
|
429 |
|
|
;; how it is used.
|
430 |
|
|
|
431 |
|
|
(define_expand "cmpsi"
|
432 |
|
|
[(set (reg:CC 32)
|
433 |
|
|
(compare:CC (match_operand:SI 0 "register_operand" "")
|
434 |
|
|
(match_operand:SI 1 "nonmemory_operand" "")))]
|
435 |
|
|
""
|
436 |
|
|
{
|
437 |
|
|
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
438 |
|
|
operands[0] = force_reg (SImode, operands[0]);
|
439 |
|
|
or32_compare_op0 = operands[0];
|
440 |
|
|
or32_compare_op1 = operands[1];
|
441 |
|
|
DONE;
|
442 |
|
|
})
|
443 |
|
|
|
444 |
|
|
|
445 |
|
|
|
446 |
|
|
;;
|
447 |
|
|
;; Conditional branches
|
448 |
|
|
;;
|
449 |
|
|
|
450 |
|
|
(define_expand "beq"
|
451 |
|
|
[(use (match_operand 0 "" ""))]
|
452 |
|
|
""
|
453 |
|
|
"or32_expand_branch (EQ, operands[0]); DONE;")
|
454 |
|
|
|
455 |
|
|
(define_expand "bne"
|
456 |
|
|
[(use (match_operand 0 "" ""))]
|
457 |
|
|
""
|
458 |
|
|
"or32_expand_branch (NE, operands[0]); DONE;")
|
459 |
|
|
|
460 |
|
|
(define_expand "bgt"
|
461 |
|
|
[(use (match_operand 0 "" ""))]
|
462 |
|
|
""
|
463 |
|
|
"or32_expand_branch (GT, operands[0]); DONE;")
|
464 |
|
|
|
465 |
|
|
(define_expand "bgtu"
|
466 |
|
|
[(use (match_operand 0 "" ""))]
|
467 |
|
|
""
|
468 |
|
|
"or32_expand_branch (GTU, operands[0]); DONE;")
|
469 |
|
|
|
470 |
|
|
(define_expand "blt"
|
471 |
|
|
[(use (match_operand 0 "" ""))]
|
472 |
|
|
""
|
473 |
|
|
"or32_expand_branch (LT, operands[0]); DONE;")
|
474 |
|
|
|
475 |
|
|
(define_expand "bltu"
|
476 |
|
|
[(use (match_operand 0 "" ""))]
|
477 |
|
|
""
|
478 |
|
|
"or32_expand_branch (LTU, operands[0]); DONE;")
|
479 |
|
|
|
480 |
|
|
(define_expand "bge"
|
481 |
|
|
[(use (match_operand 0 "" ""))]
|
482 |
|
|
""
|
483 |
|
|
"or32_expand_branch (GE, operands[0]); DONE;")
|
484 |
|
|
|
485 |
|
|
(define_expand "bgeu"
|
486 |
|
|
[(use (match_operand 0 "" ""))]
|
487 |
|
|
""
|
488 |
|
|
"or32_expand_branch (GEU, operands[0]); DONE;")
|
489 |
|
|
|
490 |
|
|
(define_expand "ble"
|
491 |
|
|
[(use (match_operand 0 "" ""))]
|
492 |
|
|
""
|
493 |
|
|
"or32_expand_branch (LE, operands[0]); DONE;")
|
494 |
|
|
|
495 |
|
|
(define_expand "bleu"
|
496 |
|
|
[(use (match_operand 0 "" ""))]
|
497 |
|
|
""
|
498 |
|
|
"or32_expand_branch (LEU, operands[0]); DONE;")
|
499 |
|
|
|
500 |
|
|
|
501 |
|
|
|
502 |
|
|
;;
|
503 |
|
|
;; Setting a CCxx registers from comparision
|
504 |
|
|
;;
|
505 |
|
|
|
506 |
|
|
|
507 |
|
|
|
508 |
|
|
;; Here are the actual compare insns.
|
509 |
|
|
(define_insn "*cmpsi_eq"
|
510 |
|
|
[(set (reg:CCEQ 32)
|
511 |
|
|
(compare:CCEQ (match_operand:SI 0 "register_operand" "r,r")
|
512 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
513 |
|
|
""
|
514 |
|
|
"@
|
515 |
|
|
l.sfeqi\t%0,%1
|
516 |
|
|
l.sfeq \t%0,%1")
|
517 |
|
|
|
518 |
|
|
(define_insn "*cmpsi_ne"
|
519 |
|
|
[(set (reg:CCNE 32)
|
520 |
|
|
(compare:CCNE (match_operand:SI 0 "register_operand" "r,r")
|
521 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
522 |
|
|
""
|
523 |
|
|
"@
|
524 |
|
|
l.sfnei\t%0,%1
|
525 |
|
|
l.sfne \t%0,%1")
|
526 |
|
|
|
527 |
|
|
(define_insn "*cmpsi_gt"
|
528 |
|
|
[(set (reg:CCGT 32)
|
529 |
|
|
(compare:CCGT (match_operand:SI 0 "register_operand" "r,r")
|
530 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
531 |
|
|
""
|
532 |
|
|
"@
|
533 |
|
|
l.sfgtsi\t%0,%1
|
534 |
|
|
l.sfgts \t%0,%1")
|
535 |
|
|
|
536 |
|
|
(define_insn "*cmpsi_gtu"
|
537 |
|
|
[(set (reg:CCGTU 32)
|
538 |
|
|
(compare:CCGTU (match_operand:SI 0 "register_operand" "r,r")
|
539 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
540 |
|
|
""
|
541 |
|
|
"@
|
542 |
|
|
l.sfgtui\t%0,%1
|
543 |
|
|
l.sfgtu \t%0,%1")
|
544 |
|
|
|
545 |
|
|
(define_insn "*cmpsi_lt"
|
546 |
|
|
[(set (reg:CCLT 32)
|
547 |
|
|
(compare:CCLT (match_operand:SI 0 "register_operand" "r,r")
|
548 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
549 |
|
|
""
|
550 |
|
|
"@
|
551 |
|
|
l.sfltsi\t%0,%1
|
552 |
|
|
l.sflts \t%0,%1")
|
553 |
|
|
|
554 |
|
|
(define_insn "*cmpsi_ltu"
|
555 |
|
|
[(set (reg:CCLTU 32)
|
556 |
|
|
(compare:CCLTU (match_operand:SI 0 "register_operand" "r,r")
|
557 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
558 |
|
|
""
|
559 |
|
|
"@
|
560 |
|
|
l.sfltui\t%0,%1
|
561 |
|
|
l.sfltu \t%0,%1")
|
562 |
|
|
|
563 |
|
|
(define_insn "*cmpsi_ge"
|
564 |
|
|
[(set (reg:CCGE 32)
|
565 |
|
|
(compare:CCGE (match_operand:SI 0 "register_operand" "r,r")
|
566 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
567 |
|
|
""
|
568 |
|
|
"@
|
569 |
|
|
l.sfgesi\t%0,%1
|
570 |
|
|
l.sfges \t%0,%1")
|
571 |
|
|
|
572 |
|
|
|
573 |
|
|
(define_insn "*cmpsi_geu"
|
574 |
|
|
[(set (reg:CCGEU 32)
|
575 |
|
|
(compare:CCGEU (match_operand:SI 0 "register_operand" "r,r")
|
576 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
577 |
|
|
""
|
578 |
|
|
"@
|
579 |
|
|
l.sfgeui\t%0,%1
|
580 |
|
|
l.sfgeu \t%0,%1")
|
581 |
|
|
|
582 |
|
|
|
583 |
|
|
(define_insn "*cmpsi_le"
|
584 |
|
|
[(set (reg:CCLE 32)
|
585 |
|
|
(compare:CCLE (match_operand:SI 0 "register_operand" "r,r")
|
586 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
587 |
|
|
""
|
588 |
|
|
"@
|
589 |
|
|
l.sflesi\t%0,%1
|
590 |
|
|
l.sfles \t%0,%1")
|
591 |
|
|
|
592 |
|
|
(define_insn "*cmpsi_leu"
|
593 |
|
|
[(set (reg:CCLEU 32)
|
594 |
|
|
(compare:CCLEU (match_operand:SI 0 "register_operand" "r,r")
|
595 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
596 |
|
|
""
|
597 |
|
|
"@
|
598 |
|
|
l.sfleui\t%0,%1
|
599 |
|
|
l.sfleu \t%0,%1")
|
600 |
|
|
|
601 |
|
|
(define_insn "*bf"
|
602 |
|
|
[(set (pc)
|
603 |
|
|
(if_then_else (match_operator 1 "comparison_operator"
|
604 |
|
|
[(match_operand 2
|
605 |
|
|
"cc_reg_operand" "")
|
606 |
|
|
(const_int 0)])
|
607 |
|
|
(label_ref (match_operand 0 "" ""))
|
608 |
|
|
(pc)))]
|
609 |
|
|
""
|
610 |
|
|
"*
|
611 |
|
|
return or32_output_bf(operands);
|
612 |
|
|
"
|
613 |
|
|
[(set_attr "type" "branch")
|
614 |
|
|
(set_attr "length" "1")])
|
615 |
|
|
|
616 |
|
|
;;
|
617 |
|
|
;;
|
618 |
|
|
;;
|
619 |
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
620 |
|
|
;;
|
621 |
|
|
;;
|
622 |
|
|
|
623 |
|
|
|
624 |
|
|
(define_insn "movdi"
|
625 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=r, r, m, r")
|
626 |
|
|
(match_operand:DI 1 "general_operand" " r, m, r, i"))]
|
627 |
|
|
""
|
628 |
|
|
"*
|
629 |
|
|
return or32_output_move_double (operands);
|
630 |
|
|
"
|
631 |
|
|
[(set_attr "length" "2,2,2,3")])
|
632 |
|
|
|
633 |
|
|
(define_insn "movdf"
|
634 |
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=r, r, m, r")
|
635 |
|
|
(match_operand:DF 1 "general_operand" " r, m, r, i"))]
|
636 |
|
|
""
|
637 |
|
|
"*
|
638 |
|
|
return or32_output_move_double (operands);
|
639 |
|
|
"
|
640 |
|
|
[(set_attr "length" "2,2,2,3")])
|
641 |
|
|
|
642 |
|
|
|
643 |
|
|
(define_insn "movsf"
|
644 |
|
|
[(set (match_operand:SF 0 "general_operand" "=r,r,m")
|
645 |
|
|
(match_operand:SF 1 "general_operand" "r,m,r"))]
|
646 |
|
|
""
|
647 |
|
|
"@
|
648 |
|
|
l.ori \t%0,%1,0\t # movsf
|
649 |
|
|
l.lwz \t%0,%1\t # movsf
|
650 |
|
|
l.sw \t%0,%1\t # movsf"
|
651 |
|
|
[(set_attr "type" "move,load,store")
|
652 |
|
|
(set_attr "length" "1,1,1")])
|
653 |
|
|
|
654 |
|
|
;;
|
655 |
|
|
;; extendqisi2
|
656 |
|
|
;;
|
657 |
|
|
|
658 |
|
|
(define_expand "extendqisi2"
|
659 |
|
|
[(use (match_operand:SI 0 "register_operand" ""))
|
660 |
|
|
(use (match_operand:QI 1 "nonimmediate_operand" ""))]
|
661 |
|
|
""
|
662 |
|
|
"
|
663 |
|
|
{
|
664 |
|
|
if (TARGET_MASK_SEXT)
|
665 |
|
|
emit_insn (gen_extendqisi2_sext(operands[0], operands[1]));
|
666 |
|
|
else {
|
667 |
|
|
if ( GET_CODE(operands[1]) == MEM ) {
|
668 |
|
|
emit_insn (gen_extendqisi2_no_sext_mem(operands[0], operands[1]));
|
669 |
|
|
}
|
670 |
|
|
else {
|
671 |
|
|
emit_insn (gen_extendqisi2_no_sext_reg(operands[0], operands[1]));
|
672 |
|
|
}
|
673 |
|
|
}
|
674 |
|
|
DONE;
|
675 |
|
|
}")
|
676 |
|
|
|
677 |
|
|
(define_insn "extendqisi2_sext"
|
678 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
679 |
|
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
|
680 |
|
|
"TARGET_MASK_SEXT"
|
681 |
|
|
"@
|
682 |
|
|
l.extbs \t%0,%1\t # extendqisi2_has_signed_extend
|
683 |
|
|
l.lbs \t%0,%1\t # extendqisi2_has_signed_extend"
|
684 |
|
|
[(set_attr "length" "1,1")
|
685 |
|
|
(set_attr "type" "extend,load")])
|
686 |
|
|
|
687 |
|
|
(define_insn "extendqisi2_no_sext_mem"
|
688 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
689 |
|
|
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
|
690 |
|
|
"!TARGET_MASK_SEXT"
|
691 |
|
|
"l.lbs \t%0,%1\t # extendqisi2_no_sext_mem"
|
692 |
|
|
[(set_attr "length" "1")
|
693 |
|
|
(set_attr "type" "load")])
|
694 |
|
|
|
695 |
|
|
(define_expand "extendqisi2_no_sext_reg"
|
696 |
|
|
[(set (match_dup 2)
|
697 |
|
|
(ashift:SI (match_operand:QI 1 "register_operand" "")
|
698 |
|
|
(const_int 24)))
|
699 |
|
|
(set (match_operand:SI 0 "register_operand" "")
|
700 |
|
|
(ashiftrt:SI (match_dup 2)
|
701 |
|
|
(const_int 24)))]
|
702 |
|
|
"!TARGET_MASK_SEXT"
|
703 |
|
|
"
|
704 |
|
|
{
|
705 |
|
|
operands[1] = gen_lowpart (SImode, operands[1]);
|
706 |
|
|
operands[2] = gen_reg_rtx (SImode); }")
|
707 |
|
|
|
708 |
|
|
;;
|
709 |
|
|
;; extendhisi2
|
710 |
|
|
;;
|
711 |
|
|
|
712 |
|
|
(define_expand "extendhisi2"
|
713 |
|
|
[(use (match_operand:SI 0 "register_operand" ""))
|
714 |
|
|
(use (match_operand:HI 1 "nonimmediate_operand" ""))]
|
715 |
|
|
""
|
716 |
|
|
"
|
717 |
|
|
{
|
718 |
|
|
if (TARGET_MASK_SEXT)
|
719 |
|
|
emit_insn (gen_extendhisi2_sext(operands[0], operands[1]));
|
720 |
|
|
else {
|
721 |
|
|
if ( GET_CODE(operands[1]) == MEM ) {
|
722 |
|
|
emit_insn (gen_extendhisi2_no_sext_mem(operands[0], operands[1]));
|
723 |
|
|
}
|
724 |
|
|
else {
|
725 |
|
|
emit_insn (gen_extendhisi2_no_sext_reg(operands[0], operands[1]));
|
726 |
|
|
}
|
727 |
|
|
}
|
728 |
|
|
DONE;
|
729 |
|
|
}")
|
730 |
|
|
|
731 |
|
|
(define_insn "extendhisi2_sext"
|
732 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
733 |
|
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
|
734 |
|
|
"TARGET_MASK_SEXT"
|
735 |
|
|
"@
|
736 |
|
|
l.exths \t%0,%1\t # extendhisi2_has_signed_extend
|
737 |
|
|
l.lhs \t%0,%1\t # extendhisi2_has_signed_extend"
|
738 |
|
|
[(set_attr "length" "1,1")
|
739 |
|
|
(set_attr "type" "extend,load")])
|
740 |
|
|
|
741 |
|
|
(define_insn "extendhisi2_no_sext_mem"
|
742 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
743 |
|
|
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
|
744 |
|
|
"!TARGET_MASK_SEXT"
|
745 |
|
|
"l.lhs \t%0,%1\t # extendhisi2_no_sext_mem"
|
746 |
|
|
[(set_attr "length" "1")
|
747 |
|
|
(set_attr "type" "load")])
|
748 |
|
|
|
749 |
|
|
(define_expand "extendhisi2_no_sext_reg"
|
750 |
|
|
[(set (match_dup 2)
|
751 |
|
|
(ashift:SI (match_operand:HI 1 "register_operand" "")
|
752 |
|
|
(const_int 16)))
|
753 |
|
|
(set (match_operand:SI 0 "register_operand" "")
|
754 |
|
|
(ashiftrt:SI (match_dup 2)
|
755 |
|
|
(const_int 16)))]
|
756 |
|
|
"!TARGET_MASK_SEXT"
|
757 |
|
|
"
|
758 |
|
|
{
|
759 |
|
|
operands[1] = gen_lowpart (SImode, operands[1]);
|
760 |
|
|
operands[2] = gen_reg_rtx (SImode); }")
|
761 |
|
|
|
762 |
|
|
|
763 |
|
|
;;
|
764 |
|
|
;; zero_extend2
|
765 |
|
|
;;
|
766 |
|
|
|
767 |
|
|
(define_insn "zero_extendqisi2"
|
768 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
769 |
|
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
|
770 |
|
|
""
|
771 |
|
|
"@
|
772 |
|
|
l.andi \t%0,%1,0xff\t # zero_extendqisi2
|
773 |
|
|
l.lbz \t%0,%1\t # zero_extendqisi2"
|
774 |
|
|
[(set_attr "type" "logic,load")
|
775 |
|
|
(set_attr "length" "1,1")])
|
776 |
|
|
|
777 |
|
|
|
778 |
|
|
(define_insn "zero_extendhisi2"
|
779 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
780 |
|
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
|
781 |
|
|
""
|
782 |
|
|
"@
|
783 |
|
|
l.andi \t%0,%1,0xffff\t # zero_extendqisi2
|
784 |
|
|
l.lhz \t%0,%1\t # zero_extendqisi2"
|
785 |
|
|
[(set_attr "type" "logic,load")
|
786 |
|
|
(set_attr "length" "1,1")])
|
787 |
|
|
|
788 |
|
|
;;
|
789 |
|
|
;; Shift/rotate operations
|
790 |
|
|
;;
|
791 |
|
|
|
792 |
|
|
(define_insn "ashlsi3"
|
793 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
794 |
|
|
(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
|
795 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
796 |
|
|
""
|
797 |
|
|
"@
|
798 |
|
|
l.sll \t%0,%1,%2
|
799 |
|
|
l.slli \t%0,%1,%2"
|
800 |
|
|
[(set_attr "type" "shift,shift")
|
801 |
|
|
(set_attr "length" "1,1")])
|
802 |
|
|
|
803 |
|
|
(define_insn "ashrsi3"
|
804 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
805 |
|
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
|
806 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
807 |
|
|
""
|
808 |
|
|
"@
|
809 |
|
|
l.sra \t%0,%1,%2
|
810 |
|
|
l.srai \t%0,%1,%2"
|
811 |
|
|
[(set_attr "type" "shift,shift")
|
812 |
|
|
(set_attr "length" "1,1")])
|
813 |
|
|
|
814 |
|
|
(define_insn "lshrsi3"
|
815 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
816 |
|
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
|
817 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
818 |
|
|
""
|
819 |
|
|
"@
|
820 |
|
|
l.srl \t%0,%1,%2
|
821 |
|
|
l.srli \t%0,%1,%2"
|
822 |
|
|
[(set_attr "type" "shift,shift")
|
823 |
|
|
(set_attr "length" "1,1")])
|
824 |
|
|
|
825 |
|
|
(define_insn "rotrsi3"
|
826 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
827 |
|
|
(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
|
828 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
829 |
|
|
"TARGET_MASK_ROR"
|
830 |
|
|
"@
|
831 |
|
|
l.ror \t%0,%1,%2
|
832 |
|
|
l.rori \t%0,%1,%2"
|
833 |
|
|
[(set_attr "type" "shift,shift")
|
834 |
|
|
(set_attr "length" "1,1")])
|
835 |
|
|
|
836 |
|
|
;;
|
837 |
|
|
;; Logical bitwise operations
|
838 |
|
|
;;
|
839 |
|
|
|
840 |
|
|
(define_insn "andsi3"
|
841 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
842 |
|
|
(and:SI (match_operand:SI 1 "register_operand" "%r,r")
|
843 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,K")))]
|
844 |
|
|
""
|
845 |
|
|
"@
|
846 |
|
|
l.and \t%0,%1,%2
|
847 |
|
|
l.andi \t%0,%1,%2"
|
848 |
|
|
[(set_attr "type" "logic,logic")
|
849 |
|
|
(set_attr "length" "1,1")])
|
850 |
|
|
|
851 |
|
|
(define_insn "iorsi3"
|
852 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
853 |
|
|
(ior:SI (match_operand:SI 1 "register_operand" "%r,r")
|
854 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,K")))]
|
855 |
|
|
""
|
856 |
|
|
"@
|
857 |
|
|
l.or \t%0,%1,%2
|
858 |
|
|
l.ori \t%0,%1,%2"
|
859 |
|
|
[(set_attr "type" "logic,logic")
|
860 |
|
|
(set_attr "length" "1,1")])
|
861 |
|
|
|
862 |
|
|
(define_insn "xorsi3"
|
863 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
864 |
|
|
(xor:SI (match_operand:SI 1 "register_operand" "%r,r")
|
865 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
866 |
|
|
""
|
867 |
|
|
"@
|
868 |
|
|
l.xor \t%0,%1,%2
|
869 |
|
|
l.xori \t%0,%1,%2"
|
870 |
|
|
[(set_attr "type" "logic,logic")
|
871 |
|
|
(set_attr "length" "1,1")])
|
872 |
|
|
|
873 |
|
|
(define_insn "one_cmplqi2"
|
874 |
|
|
[(set (match_operand:QI 0 "register_operand" "=r")
|
875 |
|
|
(not:QI (match_operand:QI 1 "register_operand" "r")))]
|
876 |
|
|
""
|
877 |
|
|
"l.xori \t%0,%1,0x00ff"
|
878 |
|
|
[(set_attr "type" "logic")
|
879 |
|
|
(set_attr "length" "1")])
|
880 |
|
|
|
881 |
|
|
(define_insn "one_cmplsi2"
|
882 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
883 |
|
|
(not:SI (match_operand:SI 1 "register_operand" "r")))]
|
884 |
|
|
""
|
885 |
|
|
"l.xori \t%0,%1,0xffff"
|
886 |
|
|
[(set_attr "type" "logic")
|
887 |
|
|
(set_attr "length" "1")])
|
888 |
|
|
|
889 |
|
|
;;
|
890 |
|
|
;; Arithmetic operations
|
891 |
|
|
;;
|
892 |
|
|
|
893 |
|
|
(define_insn "negsi2"
|
894 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
895 |
|
|
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
|
896 |
|
|
""
|
897 |
|
|
"l.sub \t%0,r0,%1"
|
898 |
|
|
[(set_attr "type" "add")
|
899 |
|
|
(set_attr "length" "1")])
|
900 |
|
|
|
901 |
|
|
(define_insn "addsi3"
|
902 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
903 |
|
|
(plus:SI (match_operand:SI 1 "register_operand" "%r,r")
|
904 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
905 |
|
|
""
|
906 |
|
|
"@
|
907 |
|
|
l.add \t%0,%1,%2
|
908 |
|
|
l.addi \t%0,%1,%2"
|
909 |
|
|
[(set_attr "type" "add,add")
|
910 |
|
|
(set_attr "length" "1,1")])
|
911 |
|
|
|
912 |
|
|
(define_insn "subsi3"
|
913 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
914 |
|
|
(minus:SI (match_operand:SI 1 "register_operand" "r,r")
|
915 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
916 |
|
|
""
|
917 |
|
|
"@
|
918 |
|
|
l.sub \t%0,%1,%2
|
919 |
|
|
l.addi \t%0,%1,%n2"
|
920 |
|
|
[(set_attr "type" "add,add")]
|
921 |
|
|
)
|
922 |
|
|
|
923 |
|
|
;;
|
924 |
|
|
;; mul and div
|
925 |
|
|
;;
|
926 |
|
|
|
927 |
|
|
(define_insn "mulsi3"
|
928 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
929 |
|
|
(mult:SI (match_operand:SI 1 "register_operand" "r")
|
930 |
|
|
(match_operand:SI 2 "register_operand" "r")))]
|
931 |
|
|
"TARGET_HARD_MUL"
|
932 |
|
|
"l.mul \t%0,%1,%2"
|
933 |
|
|
[(set_attr "type" "mul")
|
934 |
|
|
(set_attr "length" "1")])
|
935 |
|
|
|
936 |
|
|
(define_insn "divsi3"
|
937 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
938 |
|
|
(div:SI (match_operand:SI 1 "register_operand" "r")
|
939 |
|
|
(match_operand:SI 2 "register_operand" "r")))]
|
940 |
|
|
"TARGET_HARD_DIV"
|
941 |
|
|
"l.div \t%0,%1,%2"
|
942 |
|
|
[(set_attr "type" "mul")
|
943 |
|
|
(set_attr "length" "1")])
|
944 |
|
|
|
945 |
|
|
(define_insn "udivsi3"
|
946 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
947 |
|
|
(udiv:SI (match_operand:SI 1 "register_operand" "r")
|
948 |
|
|
(match_operand:SI 2 "register_operand" "r")))]
|
949 |
|
|
"TARGET_HARD_DIV"
|
950 |
|
|
"l.divu \t%0,%1,%2"
|
951 |
|
|
[(set_attr "type" "mul")
|
952 |
|
|
(set_attr "length" "1")])
|
953 |
|
|
|
954 |
|
|
;;
|
955 |
|
|
;; jumps
|
956 |
|
|
;;
|
957 |
|
|
|
958 |
|
|
;; jump
|
959 |
|
|
|
960 |
|
|
(define_expand "jump"
|
961 |
|
|
[(set (pc)
|
962 |
|
|
(label_ref (match_operand 0 "" "")))]
|
963 |
|
|
""
|
964 |
|
|
"
|
965 |
|
|
{
|
966 |
|
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
967 |
|
|
emit_jump_insn (gen_jump_internal (operands[0]));
|
968 |
|
|
else
|
969 |
|
|
emit_jump_insn (gen_jump_aligned (operands[0]));
|
970 |
|
|
DONE;
|
971 |
|
|
}")
|
972 |
|
|
|
973 |
|
|
(define_insn "jump_internal"
|
974 |
|
|
[(set (pc)
|
975 |
|
|
(label_ref (match_operand 0 "" "")))]
|
976 |
|
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
977 |
|
|
"l.j \t%l0%("
|
978 |
|
|
[(set_attr "type" "jump")
|
979 |
|
|
(set_attr "length" "1")])
|
980 |
|
|
|
981 |
|
|
(define_insn "jump_aligned"
|
982 |
|
|
[(set (pc)
|
983 |
|
|
(label_ref (match_operand 0 "" "")))]
|
984 |
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
985 |
|
|
".balignl 0x8,0x15000015,0x4\;l.j \t%l0%("
|
986 |
|
|
[(set_attr "type" "jump")
|
987 |
|
|
(set_attr "length" "1")])
|
988 |
|
|
|
989 |
|
|
;; indirect jump
|
990 |
|
|
|
991 |
|
|
(define_expand "indirect_jump"
|
992 |
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
993 |
|
|
""
|
994 |
|
|
"
|
995 |
|
|
{
|
996 |
|
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
997 |
|
|
emit_jump_insn (gen_indirect_jump_internal (operands[0]));
|
998 |
|
|
else
|
999 |
|
|
emit_jump_insn (gen_indirect_jump_aligned (operands[0]));
|
1000 |
|
|
DONE;
|
1001 |
|
|
|
1002 |
|
|
}")
|
1003 |
|
|
|
1004 |
|
|
(define_insn "indirect_jump_internal"
|
1005 |
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
1006 |
|
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
1007 |
|
|
"l.jr \t%0%("
|
1008 |
|
|
[(set_attr "type" "jump")
|
1009 |
|
|
(set_attr "length" "1")])
|
1010 |
|
|
|
1011 |
|
|
(define_insn "indirect_jump_aligned"
|
1012 |
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
1013 |
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
1014 |
|
|
".balignl 0x8,0x15000015,0x4\;l.jr \t%0%("
|
1015 |
|
|
[(set_attr "type" "jump")
|
1016 |
|
|
(set_attr "length" "1")])
|
1017 |
|
|
|
1018 |
|
|
;;
|
1019 |
|
|
;; calls
|
1020 |
|
|
;;
|
1021 |
|
|
|
1022 |
|
|
;; call
|
1023 |
|
|
|
1024 |
|
|
(define_expand "call"
|
1025 |
|
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
1026 |
|
|
(match_operand 1 "" "i"))
|
1027 |
|
|
(clobber (reg:SI 9))])]
|
1028 |
|
|
""
|
1029 |
|
|
"
|
1030 |
|
|
{
|
1031 |
|
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
1032 |
|
|
emit_call_insn (gen_call_internal (operands[0], operands[1]));
|
1033 |
|
|
else
|
1034 |
|
|
emit_call_insn (gen_call_aligned (operands[0], operands[1]));
|
1035 |
|
|
DONE;
|
1036 |
|
|
}")
|
1037 |
|
|
|
1038 |
|
|
(define_insn "call_internal"
|
1039 |
|
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
1040 |
|
|
(match_operand 1 "" "i"))
|
1041 |
|
|
(clobber (reg:SI 9))])]
|
1042 |
|
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
1043 |
|
|
"l.jal \t%S0%("
|
1044 |
|
|
[(set_attr "type" "jump")
|
1045 |
|
|
(set_attr "length" "1")])
|
1046 |
|
|
|
1047 |
|
|
(define_insn "call_aligned"
|
1048 |
|
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
1049 |
|
|
(match_operand 1 "" "i"))
|
1050 |
|
|
(clobber (reg:SI 9))])]
|
1051 |
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
1052 |
|
|
".balignl 0x8,0x15000015,0x4\;l.jal \t%S0%("
|
1053 |
|
|
[(set_attr "type" "jump")
|
1054 |
|
|
(set_attr "length" "1")])
|
1055 |
|
|
|
1056 |
|
|
;; call value
|
1057 |
|
|
|
1058 |
|
|
(define_expand "call_value"
|
1059 |
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
1060 |
|
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
1061 |
|
|
(match_operand 2 "" "i")))
|
1062 |
|
|
(clobber (reg:SI 9))])]
|
1063 |
|
|
""
|
1064 |
|
|
"
|
1065 |
|
|
{
|
1066 |
|
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
1067 |
|
|
emit_call_insn (gen_call_value_internal (operands[0], operands[1], operands[2]));
|
1068 |
|
|
else
|
1069 |
|
|
emit_call_insn (gen_call_value_aligned (operands[0], operands[1], operands[2]));
|
1070 |
|
|
DONE;
|
1071 |
|
|
}")
|
1072 |
|
|
|
1073 |
|
|
(define_insn "call_value_internal"
|
1074 |
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
1075 |
|
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
1076 |
|
|
(match_operand 2 "" "i")))
|
1077 |
|
|
(clobber (reg:SI 9))])]
|
1078 |
|
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
1079 |
|
|
"l.jal \t%S1%("
|
1080 |
|
|
[(set_attr "type" "jump")
|
1081 |
|
|
(set_attr "length" "1")])
|
1082 |
|
|
|
1083 |
|
|
(define_insn "call_value_aligned"
|
1084 |
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
1085 |
|
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
1086 |
|
|
(match_operand 2 "" "i")))
|
1087 |
|
|
(clobber (reg:SI 9))])]
|
1088 |
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
1089 |
|
|
".balignl 0x8,0x15000015,0x4\;l.jal \t%S1%("
|
1090 |
|
|
[(set_attr "type" "jump")
|
1091 |
|
|
(set_attr "length" "1")])
|
1092 |
|
|
|
1093 |
|
|
;; indirect call value
|
1094 |
|
|
|
1095 |
|
|
(define_expand "call_value_indirect"
|
1096 |
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
1097 |
|
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
1098 |
|
|
(match_operand 2 "" "i")))
|
1099 |
|
|
(clobber (reg:SI 9))])]
|
1100 |
|
|
""
|
1101 |
|
|
"
|
1102 |
|
|
{
|
1103 |
|
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
1104 |
|
|
emit_call_insn (gen_call_value_indirect_internal (operands[0], operands[1], operands[2]));
|
1105 |
|
|
else
|
1106 |
|
|
emit_call_insn (gen_call_value_indirect_aligned (operands[0], operands[1], operands[2]));
|
1107 |
|
|
DONE;
|
1108 |
|
|
}")
|
1109 |
|
|
|
1110 |
|
|
(define_insn "call_value_indirect_internal"
|
1111 |
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
1112 |
|
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
1113 |
|
|
(match_operand 2 "" "i")))
|
1114 |
|
|
(clobber (reg:SI 9))])]
|
1115 |
|
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
1116 |
|
|
"l.jalr \t%1%("
|
1117 |
|
|
[(set_attr "type" "jump")
|
1118 |
|
|
(set_attr "length" "1")])
|
1119 |
|
|
|
1120 |
|
|
(define_insn "call_value_indirect_aligned"
|
1121 |
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
1122 |
|
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
1123 |
|
|
(match_operand 2 "" "i")))
|
1124 |
|
|
(clobber (reg:SI 9))])]
|
1125 |
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
1126 |
|
|
".balignl 0x8,0x15000015,0x4\;l.jalr \t%1%("
|
1127 |
|
|
[(set_attr "type" "jump")
|
1128 |
|
|
(set_attr "length" "1")])
|
1129 |
|
|
|
1130 |
|
|
;; indirect call
|
1131 |
|
|
|
1132 |
|
|
(define_expand "call_indirect"
|
1133 |
|
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
1134 |
|
|
(match_operand 1 "" "i"))
|
1135 |
|
|
(clobber (reg:SI 9))])]
|
1136 |
|
|
""
|
1137 |
|
|
"
|
1138 |
|
|
{
|
1139 |
|
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
1140 |
|
|
emit_call_insn (gen_call_indirect_internal (operands[0], operands[1]));
|
1141 |
|
|
else
|
1142 |
|
|
emit_call_insn (gen_call_indirect_aligned (operands[0], operands[1]));
|
1143 |
|
|
DONE;
|
1144 |
|
|
}")
|
1145 |
|
|
|
1146 |
|
|
(define_insn "call_indirect_internal"
|
1147 |
|
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
1148 |
|
|
(match_operand 1 "" "i"))
|
1149 |
|
|
(clobber (reg:SI 9))])]
|
1150 |
|
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
1151 |
|
|
"l.jalr \t%0%("
|
1152 |
|
|
[(set_attr "type" "jump")
|
1153 |
|
|
(set_attr "length" "1")])
|
1154 |
|
|
|
1155 |
|
|
(define_insn "call_indirect_aligned"
|
1156 |
|
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
1157 |
|
|
(match_operand 1 "" "i"))
|
1158 |
|
|
(clobber (reg:SI 9))])]
|
1159 |
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
1160 |
|
|
".balignl 0x8,0x15000015,0x4\;l.jalr \t%0%("
|
1161 |
|
|
[(set_attr "type" "jump")
|
1162 |
|
|
(set_attr "length" "1")])
|
1163 |
|
|
|
1164 |
|
|
;; table jump
|
1165 |
|
|
|
1166 |
|
|
(define_expand "tablejump"
|
1167 |
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
1168 |
|
|
(use (label_ref (match_operand 1 "" "")))]
|
1169 |
|
|
""
|
1170 |
|
|
"
|
1171 |
|
|
{
|
1172 |
|
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
1173 |
|
|
emit_jump_insn (gen_tablejump_internal (operands[0], operands[1]));
|
1174 |
|
|
else
|
1175 |
|
|
emit_jump_insn (gen_tablejump_aligned (operands[0], operands[1]));
|
1176 |
|
|
DONE;
|
1177 |
|
|
}")
|
1178 |
|
|
|
1179 |
|
|
(define_insn "tablejump_internal"
|
1180 |
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
1181 |
|
|
(use (label_ref (match_operand 1 "" "")))]
|
1182 |
|
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
1183 |
|
|
"l.jr \t%0%("
|
1184 |
|
|
[(set_attr "type" "jump")
|
1185 |
|
|
(set_attr "length" "1")])
|
1186 |
|
|
|
1187 |
|
|
(define_insn "tablejump_aligned"
|
1188 |
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
1189 |
|
|
(use (label_ref (match_operand 1 "" "")))]
|
1190 |
|
|
"TARGET_MASK_ALIGNED_JUMPS"
|
1191 |
|
|
".balignl 0x8,0x15000015,0x4\;l.jr \t%0%("
|
1192 |
|
|
[(set_attr "type" "jump")
|
1193 |
|
|
(set_attr "length" "1")])
|
1194 |
|
|
|
1195 |
|
|
|
1196 |
|
|
;; no-op
|
1197 |
|
|
|
1198 |
|
|
(define_insn "nop"
|
1199 |
|
|
[(const_int 0)]
|
1200 |
|
|
""
|
1201 |
|
|
"l.nop"
|
1202 |
|
|
[(set_attr "type" "logic")
|
1203 |
|
|
(set_attr "length" "1")])
|
1204 |
|
|
|
1205 |
|
|
;;
|
1206 |
|
|
;; floating point
|
1207 |
|
|
;;
|
1208 |
|
|
|
1209 |
|
|
(define_insn "addsf3"
|
1210 |
|
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
1211 |
|
|
(plus:SF (match_operand:SF 1 "register_operand" "r")
|
1212 |
|
|
(match_operand:SF 2 "register_operand" "r")))]
|
1213 |
|
|
"TARGET_HARD_FLOAT"
|
1214 |
|
|
"lf.add.s\t%0,%1,%2"
|
1215 |
|
|
[(set_attr "type" "fp")
|
1216 |
|
|
(set_attr "length" "1")])
|
1217 |
|
|
|
1218 |
|
|
(define_insn "adddf3"
|
1219 |
|
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
1220 |
|
|
(plus:DF (match_operand:DF 1 "register_operand" "r")
|
1221 |
|
|
(match_operand:DF 2 "register_operand" "r")))]
|
1222 |
|
|
"TARGET_HARD_FLOAT"
|
1223 |
|
|
"lf.add.d\t%0,%1,%2"
|
1224 |
|
|
[(set_attr "type" "fp")
|
1225 |
|
|
(set_attr "length" "1")])
|
1226 |
|
|
|
1227 |
|
|
(define_insn "subsf3"
|
1228 |
|
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
1229 |
|
|
(minus:SF (match_operand:SF 1 "register_operand" "r")
|
1230 |
|
|
(match_operand:SF 2 "register_operand" "r")))]
|
1231 |
|
|
"TARGET_HARD_FLOAT"
|
1232 |
|
|
"lf.sub.s\t%0,%1,%2"
|
1233 |
|
|
[(set_attr "type" "fp")
|
1234 |
|
|
(set_attr "length" "1")])
|
1235 |
|
|
|
1236 |
|
|
(define_insn "subdf3"
|
1237 |
|
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
1238 |
|
|
(minus:DF (match_operand:DF 1 "register_operand" "r")
|
1239 |
|
|
(match_operand:DF 2 "register_operand" "r")))]
|
1240 |
|
|
"TARGET_HARD_FLOAT"
|
1241 |
|
|
"lf.sub.d\t%0,%1,%2"
|
1242 |
|
|
[(set_attr "type" "fp")
|
1243 |
|
|
(set_attr "length" "1")])
|
1244 |
|
|
|
1245 |
|
|
(define_insn "mulsf3"
|
1246 |
|
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
1247 |
|
|
(mult:SF (match_operand:SF 1 "register_operand" "r")
|
1248 |
|
|
(match_operand:SF 2 "register_operand" "r")))]
|
1249 |
|
|
"TARGET_HARD_FLOAT"
|
1250 |
|
|
"lf.mul.s\t%0,%1,%2"
|
1251 |
|
|
[(set_attr "type" "fp")
|
1252 |
|
|
(set_attr "length" "1")])
|
1253 |
|
|
|
1254 |
|
|
(define_insn "muldf3"
|
1255 |
|
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
1256 |
|
|
(mult:DF (match_operand:DF 1 "register_operand" "r")
|
1257 |
|
|
(match_operand:DF 2 "register_operand" "r")))]
|
1258 |
|
|
"TARGET_HARD_FLOAT"
|
1259 |
|
|
"lf.mul.d\t%0,%1,%2"
|
1260 |
|
|
[(set_attr "type" "fp")
|
1261 |
|
|
(set_attr "length" "1")])
|
1262 |
|
|
|
1263 |
|
|
(define_insn "divsf3"
|
1264 |
|
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
1265 |
|
|
(div:SF (match_operand:SF 1 "register_operand" "r")
|
1266 |
|
|
(match_operand:SF 2 "register_operand" "r")))]
|
1267 |
|
|
"TARGET_HARD_FLOAT"
|
1268 |
|
|
"lf.div.s\t%0,%1,%2"
|
1269 |
|
|
[(set_attr "type" "fp")
|
1270 |
|
|
(set_attr "length" "1")])
|
1271 |
|
|
|
1272 |
|
|
(define_insn "divdf3"
|
1273 |
|
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
1274 |
|
|
(div:DF (match_operand:DF 1 "register_operand" "r")
|
1275 |
|
|
(match_operand:DF 2 "register_operand" "r")))]
|
1276 |
|
|
"TARGET_HARD_FLOAT"
|
1277 |
|
|
"lf.div.d\t%0,%1,%2"
|
1278 |
|
|
[(set_attr "type" "fp")
|
1279 |
|
|
(set_attr "length" "1")])
|
1280 |
|
|
|
1281 |
|
|
|
1282 |
|
|
;; Local variables:
|
1283 |
|
|
;; mode:emacs-lisp
|
1284 |
|
|
;; comment-start: ";; "
|
1285 |
|
|
;; eval: (set-syntax-table (copy-sequence (syntax-table)))
|
1286 |
|
|
;; eval: (modify-syntax-entry ?[ "(]")
|
1287 |
|
|
;; eval: (modify-syntax-entry ?] ")[")
|
1288 |
|
|
;; eval: (modify-syntax-entry ?{ "(}")
|
1289 |
|
|
;; eval: (modify-syntax-entry ?} "){")
|
1290 |
|
|
;; eval: (setq indent-tabs-mode t)
|
1291 |
|
|
;; End:
|