OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [or32/] [or32.opt] - Blame information for rev 38

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
; Options for the OR32 port of the compiler
2 
 
3 
mhard-float
4 
Target RejectNegative Mask(HARD_FLOAT)
5 
Use hardware floating point
6 
 
7 
msoft-float
8 
Target RejectNegative InverseMask(HARD_FLOAT)
9 
Do not use hardware floating point
10 
 
11 
mhard-div
12 
Target RejectNegative Mask(HARD_DIV)
13 
Use hardware division
14 
 
15 
msoft-div
16 
Target RejectNegative InverseMask(HARD_DIV)
17 
Do not use hardware division
18 
 
19 
mhard-mul
20 
Target RejectNegative Mask(HARD_MUL)
21 
Use hardware multiplication
22 
 
23 
msoft-mul
24 
Target RejectNegative InverseMask(HARD_MUL)
25 
Do not use hardware multiplication
26 
 
27 
maj
28 
Target Mask(MASK_ALIGNED_JUMPS)
29 
Use aligned jumps
30 
 
31 
msext
32 
Target Mask(MASK_SEXT)
33 
Use sign-extending instructions
34 
 
35 
mcmov
36 
Target Mask(MASK_CMOV)
37 
Use conditional move instructions
38 
 
39 
mlogue
40 
Target Mask(MASK_SCHED_LOGUE)
41 
Schedule prologue/epilogue
42 
 
43 
mror
44 
Target Mask(MASK_ROR)
45 
Emit ROR instructions
46 
 
47 
msibcall
48 
Target Mask(MASK_SIBCALL)
49 
Enable sibcall optimization

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.