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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [pa/] [pa32-regs.h] - Blame information for rev 154

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1 38 julius
/* Standard register usage.  */
2
 
3
/* Number of actual hardware registers.
4
   The hardware registers are assigned numbers for the compiler
5
   from 0 to just below FIRST_PSEUDO_REGISTER.
6
   All registers that the compiler knows about must be given numbers,
7
   even those that are not normally considered general registers.
8
 
9
   HP-PA 1.0 has 32 fullword registers and 16 floating point
10
   registers. The floating point registers hold either word or double
11
   word values.
12
 
13
   16 additional registers are reserved.
14
 
15
   HP-PA 1.1 has 32 fullword registers and 32 floating point
16
   registers. However, the floating point registers behave
17
   differently: the left and right halves of registers are addressable
18
   as 32 bit registers. So, we will set things up like the 68k which
19
   has different fp units: define separate register sets for the 1.0
20
   and 1.1 fp units.  */
21
 
22
#define FIRST_PSEUDO_REGISTER 89  /* 32 general regs + 56 fp regs +
23
                                     + 1 shift reg */
24
 
25
/* 1 for registers that have pervasive standard uses
26
   and are not available for the register allocator.
27
 
28
   On the HP-PA, these are:
29
   Reg 0        = 0 (hardware). However, 0 is used for condition code,
30
                  so is not fixed.
31
   Reg 1        = ADDIL target/Temporary (hardware).
32
   Reg 2        = Return Pointer
33
   Reg 3        = Frame Pointer
34
   Reg 4        = Frame Pointer (>8k varying frame with HP compilers only)
35
   Reg 4-18     = Preserved Registers
36
   Reg 19       = Linkage Table Register in HPUX 8.0 shared library scheme.
37
   Reg 20-22    = Temporary Registers
38
   Reg 23-26    = Temporary/Parameter Registers
39
   Reg 27       = Global Data Pointer (hp)
40
   Reg 28       = Temporary/Return Value register
41
   Reg 29       = Temporary/Static Chain/Return Value register #2
42
   Reg 30       = stack pointer
43
   Reg 31       = Temporary/Millicode Return Pointer (hp)
44
 
45
   Freg 0-3     = Status Registers       -- Not known to the compiler.
46
   Freg 4-7     = Arguments/Return Value
47
   Freg 8-11    = Temporary Registers
48
   Freg 12-15   = Preserved Registers
49
 
50
   Freg 16-31   = Reserved
51
 
52
   On the Snake, fp regs are
53
 
54
   Freg 0-3     = Status Registers      -- Not known to the compiler.
55
   Freg 4L-7R   = Arguments/Return Value
56
   Freg 8L-11R  = Temporary Registers
57
   Freg 12L-21R = Preserved Registers
58
   Freg 22L-31R = Temporary Registers
59
 
60
*/
61
 
62
#define FIXED_REGISTERS  \
63
 {0, 0, 0, 0, 0, 0, 0, 0, \
64
  0, 0, 0, 0, 0, 0, 0, 0, \
65
  0, 0, 0, 0, 0, 0, 0, 0, \
66
  0, 0, 0, 1, 0, 0, 1, 0, \
67
  /* fp registers */      \
68
  0, 0, 0, 0, 0, 0, 0, 0, \
69
  0, 0, 0, 0, 0, 0, 0, 0, \
70
  0, 0, 0, 0, 0, 0, 0, 0, \
71
  0, 0, 0, 0, 0, 0, 0, 0, \
72
  0, 0, 0, 0, 0, 0, 0, 0, \
73
  0, 0, 0, 0, 0, 0, 0, 0, \
74
  0, 0, 0, 0, 0, 0, 0, 0, \
75
  0}
76
 
77
/* 1 for registers not available across function calls.
78
   These must include the FIXED_REGISTERS and also any
79
   registers that can be used without being saved.
80
   The latter must include the registers where values are returned
81
   and the register where structure-value addresses are passed.
82
   Aside from that, you can include as many other registers as you like.  */
83
#define CALL_USED_REGISTERS  \
84
 {1, 1, 1, 0, 0, 0, 0, 0, \
85
  0, 0, 0, 0, 0, 0, 0, 0, \
86
  0, 0, 0, 1, 1, 1, 1, 1, \
87
  1, 1, 1, 1, 1, 1, 1, 1, \
88
  /* fp registers */      \
89
  1, 1, 1, 1, 1, 1, 1, 1, \
90
  1, 1, 1, 1, 1, 1, 1, 1, \
91
  0, 0, 0, 0, 0, 0, 0, 0, \
92
  0, 0, 0, 0, 0, 0, 0, 0, \
93
  0, 0, 0, 0, 1, 1, 1, 1, \
94
  1, 1, 1, 1, 1, 1, 1, 1, \
95
  1, 1, 1, 1, 1, 1, 1, 1, \
96
  1}
97
 
98
#define CONDITIONAL_REGISTER_USAGE \
99
{                                               \
100
  int i;                                        \
101
  if (!TARGET_PA_11)                            \
102
    {                                           \
103
      for (i = 56; i < 88; i++)                 \
104
        fixed_regs[i] = call_used_regs[i] = 1;  \
105
      for (i = 33; i < 88; i += 2)              \
106
        fixed_regs[i] = call_used_regs[i] = 1;  \
107
    }                                           \
108
  if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
109
    {                                           \
110
      for (i = 32; i < 88; i++)                 \
111
        fixed_regs[i] = call_used_regs[i] = 1;  \
112
    }                                           \
113
  if (flag_pic)                                 \
114
    fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;    \
115
}
116
 
117
/* Allocate the call used registers first.  This should minimize
118
   the number of registers that need to be saved (as call used
119
   registers will generally not be allocated across a call).
120
 
121
   Experimentation has shown slightly better results by allocating
122
   FP registers first.  We allocate the caller-saved registers more
123
   or less in reverse order to their allocation as arguments.
124
 
125
   FP registers are ordered so that all L registers are selected before
126
   R registers.  This works around a false dependency interlock on the
127
   PA8000 when accessing the high and low parts of an FP register
128
   independently.  */
129
 
130
#define REG_ALLOC_ORDER \
131
 {                                      \
132
  /* caller-saved fp regs.  */          \
133
  68, 70, 72, 74, 76, 78, 80, 82,       \
134
  84, 86, 40, 42, 44, 46, 38, 36,       \
135
  34, 32,                               \
136
  69, 71, 73, 75, 77, 79, 81, 83,       \
137
  85, 87, 41, 43, 45, 47, 39, 37,       \
138
  35, 33,                               \
139
  /* caller-saved general regs.  */     \
140
  28, 19, 20, 21, 22, 31, 27, 29,       \
141
  23, 24, 25, 26,  2,                   \
142
  /* callee-saved fp regs.  */          \
143
  48, 50, 52, 54, 56, 58, 60, 62,       \
144
  64, 66,                               \
145
  49, 51, 53, 55, 57, 59, 61, 63,       \
146
  65, 67,                               \
147
  /* callee-saved general regs.  */     \
148
   3,  4,  5,  6,  7,  8,  9, 10,       \
149
  11, 12, 13, 14, 15, 16, 17, 18,       \
150
  /* special registers.  */             \
151
   1, 30,  0, 88}
152
 
153
 
154
/* Return number of consecutive hard regs needed starting at reg REGNO
155
   to hold something of mode MODE.
156
   This is ordinarily the length in words of a value of mode MODE
157
   but can be less for certain modes in special long registers.
158
 
159
   On the HP-PA, general registers are 32 bits wide.  The floating
160
   point registers are 64 bits wide.  Snake fp regs are treated as
161
   32 bits wide since the left and right parts are independently
162
   accessible.  */
163
#define HARD_REGNO_NREGS(REGNO, MODE)                                   \
164
  (FP_REGNO_P (REGNO)                                                   \
165
   ? (!TARGET_PA_11                                                     \
166
      ? COMPLEX_MODE_P (MODE) ? 2 : 1                                   \
167
      : (GET_MODE_SIZE (MODE) + 4 - 1) / 4)                             \
168
   : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
169
 
170
/* There are no instructions that use DImode in PA 1.0, so we only
171
   allow it in PA 1.1 and later.  */
172
#define VALID_FP_MODE_P(MODE)                                           \
173
  ((MODE) == SFmode || (MODE) == DFmode                                 \
174
   || (MODE) == SCmode || (MODE) == DCmode                              \
175
   || (MODE) == QImode || (MODE) == HImode || (MODE) == SImode          \
176
   || (TARGET_PA_11 && (MODE) == DImode))
177
 
178
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
179
 
180
   On the HP-PA, the cpu registers can hold any mode that fits in 32 bits.
181
   For the 64-bit modes, we choose a set of non-overlapping general registers
182
   that includes the incoming arguments and the return value.  We specify a
183
   set with no overlaps so that we don't have to specify that the destination
184
   register is an early clobber in patterns using this mode.  Except for the
185
   return value, the starting registers are odd.  For 128 and 256 bit modes,
186
   we similarly specify non-overlapping sets of cpu registers.  However,
187
   there aren't any patterns defined for modes larger than 64 bits at the
188
   moment.
189
 
190
   We limit the modes allowed in the floating point registers to the
191
   set of modes used in the machine definition.  In addition, we allow
192
   the complex modes SCmode and DCmode.  The real and imaginary parts
193
   of complex modes are allocated to separate registers.  This might
194
   allow patterns to be defined in the future to operate on these values.
195
 
196
   The PA 2.0 architecture specifies that quad-precision floating-point
197
   values should start on an even floating point register.  Thus, we
198
   choose non-overlapping sets of registers starting on even register
199
   boundaries for large modes.  However, there is currently no support
200
   in the machine definition for modes larger than 64 bits.  TFmode is
201
   supported under HP-UX using libcalls.  Since TFmode values are passed
202
   by reference, they never need to be loaded into the floating-point
203
   registers.  */
204
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
205
  ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode         \
206
   : !TARGET_PA_11 && FP_REGNO_P (REGNO)                                \
207
     ? (VALID_FP_MODE_P (MODE)                                          \
208
        && (GET_MODE_SIZE (MODE) <= 8                                   \
209
            || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0)))      \
210
   : FP_REGNO_P (REGNO)                                                 \
211
     ? (VALID_FP_MODE_P (MODE)                                          \
212
        && (GET_MODE_SIZE (MODE) <= 4                                   \
213
            || (GET_MODE_SIZE (MODE) == 8 && ((REGNO) & 1) == 0) \
214
            || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0)        \
215
            || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 7) == 0)))      \
216
   : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD                            \
217
      || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD                    \
218
          && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28))  \
219
      || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD                    \
220
          && ((REGNO) & 3) == 3 && (REGNO) <= 23)                       \
221
      || (GET_MODE_SIZE (MODE) == 8 * UNITS_PER_WORD                    \
222
          && ((REGNO) & 7) == 3 && (REGNO) <= 19)))
223
 
224
/* How to renumber registers for dbx and gdb.
225
 
226
   Registers 0  - 31 remain unchanged.
227
 
228
   Registers 32 - 87 are mapped to 72 - 127
229
 
230
   Register 88 is mapped to 32.  */
231
 
232
#define DBX_REGISTER_NUMBER(REGNO) \
233
  ((REGNO) <= 31 ? (REGNO) :                                            \
234
   ((REGNO) <= 87 ? (REGNO) + 40 : 32))
235
 
236
/* We must not use the DBX register numbers for the DWARF 2 CFA column
237
   numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
238
   Instead use the identity mapping.  */
239
#define DWARF_FRAME_REGNUM(REG) REG
240
 
241
/* Define the classes of registers for register constraints in the
242
   machine description.  Also define ranges of constants.
243
 
244
   One of the classes must always be named ALL_REGS and include all hard regs.
245
   If there is more than one class, another class must be named NO_REGS
246
   and contain no registers.
247
 
248
   The name GENERAL_REGS must be the name of a class (or an alias for
249
   another name such as ALL_REGS).  This is the class of registers
250
   that is allowed by "g" or "r" in a register constraint.
251
   Also, registers outside this class are allocated only when
252
   instructions express preferences for them.
253
 
254
   The classes must be numbered in nondecreasing order; that is,
255
   a larger-numbered class must never be contained completely
256
   in a smaller-numbered class.
257
 
258
   For any two classes, it is very desirable that there be another
259
   class that represents their union.  */
260
 
261
  /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
262
     1.1 fp regs, and the high 1.1 fp regs, to which the operands of
263
     fmpyadd and fmpysub are restricted.  */
264
 
265
enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
266
                 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
267
 
268
#define N_REG_CLASSES (int) LIM_REG_CLASSES
269
 
270
/* Give names of register classes as strings for dump file.  */
271
 
272
#define REG_CLASS_NAMES \
273
  {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
274
   "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
275
 
276
/* Define which registers fit in which classes.
277
   This is an initializer for a vector of HARD_REG_SET
278
   of length N_REG_CLASSES. Register 0, the "condition code" register,
279
   is in no class.  */
280
 
281
#define REG_CLASS_CONTENTS      \
282
 {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */                   \
283
  {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */                   \
284
  {0xfffffffe, 0x00000000, 0x00000000}, /* GENERAL_REGS */              \
285
  {0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */              \
286
  {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */                   \
287
  {0xfffffffe, 0xffffffff, 0x00ffffff}, /* GENERAL_OR_FP_REGS */        \
288
  {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */                \
289
  {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */
290
 
291
/* Return the class number of the smallest class containing
292
   reg number REGNO.  This could be a conditional expression
293
   or could index an array.  */
294
 
295
#define REGNO_REG_CLASS(REGNO)                                          \
296
  ((REGNO) == 0 ? NO_REGS                                                \
297
   : (REGNO) == 1 ? R1_REGS                                             \
298
   : (REGNO) < 32 ? GENERAL_REGS                                        \
299
   : (REGNO) < 56 ? FP_REGS                                             \
300
   : (REGNO) < 88 ? FPUPPER_REGS                                        \
301
   : SHIFT_REGS)
302
 
303
/* Get reg_class from a letter such as appears in the machine description.  */
304
/* Keep 'x' for backward compatibility with user asm.  */
305
#define REG_CLASS_FROM_LETTER(C) \
306
  ((C) == 'f' ? FP_REGS :                                       \
307
   (C) == 'y' ? FPUPPER_REGS :                                  \
308
   (C) == 'x' ? FP_REGS :                                       \
309
   (C) == 'q' ? SHIFT_REGS :                                    \
310
   (C) == 'a' ? R1_REGS :                                       \
311
   (C) == 'Z' ? ALL_REGS : NO_REGS)
312
 
313
/* Return the maximum number of consecutive registers
314
   needed to represent mode MODE in a register of class CLASS.  */
315
#define CLASS_MAX_NREGS(CLASS, MODE)                                    \
316
  ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS                        \
317
   ? (!TARGET_PA_11                                                     \
318
      ? COMPLEX_MODE_P (MODE) ? 2 : 1                                   \
319
      : (GET_MODE_SIZE (MODE) + 4 - 1) / 4)                             \
320
   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
321
 
322
/* 1 if N is a possible register number for function argument passing.  */
323
 
324
#define FUNCTION_ARG_REGNO_P(N) \
325
  (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
326
 
327
/* How to refer to registers in assembler output.
328
   This sequence is indexed by compiler's hard-register-number (see above).  */
329
 
330
#define REGISTER_NAMES \
331
{"%r0",   "%r1",    "%r2",   "%r3",    "%r4",   "%r5",    "%r6",   "%r7",    \
332
 "%r8",   "%r9",    "%r10",  "%r11",   "%r12",  "%r13",   "%r14",  "%r15",   \
333
 "%r16",  "%r17",   "%r18",  "%r19",   "%r20",  "%r21",   "%r22",  "%r23",   \
334
 "%r24",  "%r25",   "%r26",  "%r27",   "%r28",  "%r29",   "%r30",  "%r31",   \
335
 "%fr4",  "%fr4R",  "%fr5",  "%fr5R",  "%fr6",  "%fr6R",  "%fr7",  "%fr7R",  \
336
 "%fr8",  "%fr8R",  "%fr9",  "%fr9R",  "%fr10", "%fr10R", "%fr11", "%fr11R", \
337
 "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \
338
 "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \
339
 "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \
340
 "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \
341
 "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \
342
 "SAR"}
343
 
344
#define ADDITIONAL_REGISTER_NAMES \
345
{{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38},                \
346
 {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46},              \
347
 {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54},            \
348
 {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62},            \
349
 {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70},            \
350
 {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78},            \
351
 {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86},            \
352
 {"%cr11",88}}
353
 
354
#define FP_SAVED_REG_LAST 66
355
#define FP_SAVED_REG_FIRST 48
356
#define FP_REG_STEP 2
357
#define FP_REG_FIRST 32
358
#define FP_REG_LAST 87

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