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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [pa/] [pa64-regs.h] - Blame information for rev 154

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/* Configuration for GCC-compiler for PA-RISC.
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   Copyright (C) 1999, 2000, 2003, 2004, 2007 Free Software Foundation, Inc.
3
 
4
This file is part of GCC.
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6
GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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11
GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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16
You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3.  If not see
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<http://www.gnu.org/licenses/>.  */
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20
/* Standard register usage.
21
 
22
   It is safe to refer to actual register numbers in this file.  */
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24
/* Number of actual hardware registers.
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   The hardware registers are assigned numbers for the compiler
26
   from 0 to just below FIRST_PSEUDO_REGISTER.
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   All registers that the compiler knows about must be given numbers,
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   even those that are not normally considered general registers.
29
 
30
   HP-PA 2.0w has 32 fullword registers and 32 floating point
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   registers. However, the floating point registers behave
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   differently: the left and right halves of registers are addressable
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   as 32 bit registers.
34
 
35
   Due to limitations within GCC itself, we do not expose the left/right
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   half addressability when in wide mode.  This is not a major performance
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   issue as using the halves independently triggers false dependency stalls
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   anyway.  */
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#define FIRST_PSEUDO_REGISTER 61  /* 32 general regs + 28 fp regs +
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                                     + 1 shift reg */
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43
/* 1 for registers that have pervasive standard uses
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   and are not available for the register allocator.
45
 
46
   On the HP-PA, these are:
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   Reg 0        = 0 (hardware). However, 0 is used for condition code,
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                  so is not fixed.
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   Reg 1        = ADDIL target/Temporary (hardware).
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   Reg 2        = Return Pointer
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   Reg 3        = Frame Pointer
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   Reg 4        = Frame Pointer (>8k varying frame with HP compilers only)
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   Reg 4-18     = Preserved Registers
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   Reg 19       = Linkage Table Register in HPUX 8.0 shared library scheme.
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   Reg 20-22    = Temporary Registers
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   Reg 23-26    = Temporary/Parameter Registers
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   Reg 27       = Global Data Pointer (hp)
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   Reg 28       = Temporary/Return Value register
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   Reg 29       = Temporary/Static Chain/Return Value register #2
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   Reg 30       = stack pointer
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   Reg 31       = Temporary/Millicode Return Pointer (hp)
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63
   Freg 0-3     = Status Registers      -- Not known to the compiler.
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   Freg 4-7     = Arguments/Return Value
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   Freg 8-11    = Temporary Registers
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   Freg 12-21   = Preserved Registers
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   Freg 22-31 = Temporary Registers
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69
*/
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#define FIXED_REGISTERS  \
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 {0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 1, 0, 0, 1, 0, \
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  /* fp registers */      \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0,                 \
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  /* shift register */    \
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  0}
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84
/* 1 for registers not available across function calls.
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   These must include the FIXED_REGISTERS and also any
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   registers that can be used without being saved.
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   The latter must include the registers where values are returned
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   and the register where structure-value addresses are passed.
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   Aside from that, you can include as many other registers as you like.  */
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#define CALL_USED_REGISTERS  \
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 {1, 1, 1, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 1, 1, 1, 1, 1, \
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  1, 1, 1, 1, 1, 1, 1, 1, \
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  /* fp registers */      \
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  1, 1, 1, 1, 1, 1, 1, 1, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 1, 1, 1, 1, 1, 1, \
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  1, 1, 1, 1,             \
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  /* shift register */    \
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  1}
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#define CONDITIONAL_REGISTER_USAGE \
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{                                               \
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  int i;                                        \
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  if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
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    {                                           \
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      for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)\
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        fixed_regs[i] = call_used_regs[i] = 1;  \
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    }                                           \
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  if (flag_pic)                                 \
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    fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;    \
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}
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115
/* Allocate the call used registers first.  This should minimize
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   the number of registers that need to be saved (as call used
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   registers will generally not be allocated across a call).
118
 
119
   Experimentation has shown slightly better results by allocating
120
   FP registers first.  We allocate the caller-saved registers more
121
   or less in reverse order to their allocation as arguments.  */
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123
#define REG_ALLOC_ORDER \
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 {                                      \
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  /* caller-saved fp regs.  */          \
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  50, 51, 52, 53, 54, 55, 56, 57,       \
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  58, 59, 39, 38, 37, 36, 35, 34,       \
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  33, 32,                               \
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  /* caller-saved general regs.  */     \
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  28, 31, 19, 20, 21, 22, 23, 24,       \
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  25, 26, 29,  2,                       \
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  /* callee-saved fp regs.  */          \
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  40, 41, 42, 43, 44, 45, 46, 47,       \
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  48, 49,                               \
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  /* callee-saved general regs.  */     \
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   3,  4,  5,  6,  7,  8,  9, 10,       \
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  11, 12, 13, 14, 15, 16, 17, 18,       \
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  /* special registers.  */             \
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   1, 27, 30,  0, 60}
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141
 
142
/* Return number of consecutive hard regs needed starting at reg REGNO
143
   to hold something of mode MODE.
144
   This is ordinarily the length in words of a value of mode MODE
145
   but can be less for certain modes in special long registers.
146
 
147
   For PA64, GPRs and FPRs hold 64 bits worth.  We ignore the 32-bit
148
   addressability of the FPRs and pretend each register holds precisely
149
   WORD_SIZE bits.  Note that SCmode values are placed in a single FPR.
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   Thus, any patterns defined to operate on these values would have to
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   use the 32-bit addressability of the FPR registers.  */
152
#define HARD_REGNO_NREGS(REGNO, MODE)                                   \
153
  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
154
 
155
/* These are the valid FP modes.  */
156
#define VALID_FP_MODE_P(MODE)                                           \
157
  ((MODE) == SFmode || (MODE) == DFmode                                 \
158
   || (MODE) == SCmode || (MODE) == DCmode                              \
159
   || (MODE) == QImode || (MODE) == HImode || (MODE) == SImode          \
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   || (MODE) == DImode)
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162
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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   On the HP-PA, the cpu registers can hold any mode.  We
164
   force this to be an even register is it cannot hold the full mode.  */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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  ((REGNO) == 0                                                          \
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   ? (MODE) == CCmode || (MODE) == CCFPmode                             \
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   /* Make wide modes be in aligned registers.  */                      \
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   : FP_REGNO_P (REGNO)                                                 \
170
     ? (VALID_FP_MODE_P (MODE)                                          \
171
        && (GET_MODE_SIZE (MODE) <= 8                                   \
172
            || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0)        \
173
            || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 3) == 0)))      \
174
   : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD                            \
175
      || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD                    \
176
          && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28))  \
177
      || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD                    \
178
          && ((REGNO) & 3) == 3 && (REGNO) <= 23)))
179
 
180
/* How to renumber registers for dbx and gdb.
181
 
182
   Registers 0  - 31 remain unchanged.
183
 
184
   Registers 32 - 59 are mapped to 72, 74, 76 ...
185
 
186
   Register 60 is mapped to 32.  */
187
#define DBX_REGISTER_NUMBER(REGNO) \
188
  ((REGNO) <= 31 ? (REGNO) : ((REGNO) < 60 ? (REGNO - 32) * 2 + 72 : 32))
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190
/* We must not use the DBX register numbers for the DWARF 2 CFA column
191
   numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
192
   Instead use the identity mapping.  */
193
#define DWARF_FRAME_REGNUM(REG) REG
194
 
195
/* Define the classes of registers for register constraints in the
196
   machine description.  Also define ranges of constants.
197
 
198
   One of the classes must always be named ALL_REGS and include all hard regs.
199
   If there is more than one class, another class must be named NO_REGS
200
   and contain no registers.
201
 
202
   The name GENERAL_REGS must be the name of a class (or an alias for
203
   another name such as ALL_REGS).  This is the class of registers
204
   that is allowed by "g" or "r" in a register constraint.
205
   Also, registers outside this class are allocated only when
206
   instructions express preferences for them.
207
 
208
   The classes must be numbered in nondecreasing order; that is,
209
   a larger-numbered class must never be contained completely
210
   in a smaller-numbered class.
211
 
212
   For any two classes, it is very desirable that there be another
213
   class that represents their union.  */
214
 
215
  /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
216
     1.1 fp regs, and the high 1.1 fp regs, to which the operands of
217
     fmpyadd and fmpysub are restricted.  */
218
 
219
enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
220
                 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
221
 
222
#define N_REG_CLASSES (int) LIM_REG_CLASSES
223
 
224
/* Give names of register classes as strings for dump file.  */
225
 
226
#define REG_CLASS_NAMES \
227
  {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
228
   "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
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230
/* Define which registers fit in which classes.
231
   This is an initializer for a vector of HARD_REG_SET
232
   of length N_REG_CLASSES. Register 0, the "condition code" register,
233
   is in no class.  */
234
 
235
#define REG_CLASS_CONTENTS      \
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 {{0x00000000, 0x00000000},     /* NO_REGS */                   \
237
  {0x00000002, 0x00000000},     /* R1_REGS */                   \
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  {0xfffffffe, 0x00000000},     /* GENERAL_REGS */              \
239
  {0x00000000, 0x00000000},     /* FPUPPER_REGS */                      \
240
  {0x00000000, 0x0fffffff},     /* FP_REGS */                   \
241
  {0xfffffffe, 0x0fffffff},     /* GENERAL_OR_FP_REGS */        \
242
  {0x00000000, 0x10000000},     /* SHIFT_REGS */                \
243
  {0xfffffffe, 0x1fffffff}}     /* ALL_REGS */
244
 
245
/* Defines invalid mode changes.
246
 
247
   SImode loads to floating-point registers are not zero-extended.
248
   The definition for LOAD_EXTEND_OP specifies that integer loads
249
   narrower than BITS_PER_WORD will be zero-extended.  As a result,
250
   we inhibit changes from SImode unless they are to a mode that is
251
   identical in size.  */
252
 
253
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)               \
254
  ((FROM) == SImode && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)       \
255
   ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
256
 
257
/* Return the class number of the smallest class containing
258
   reg number REGNO.  This could be a conditional expression
259
   or could index an array.  */
260
 
261
#define REGNO_REG_CLASS(REGNO)                                          \
262
  ((REGNO) == 0 ? NO_REGS                                                \
263
   : (REGNO) == 1 ? R1_REGS                                             \
264
   : (REGNO) < 32 ? GENERAL_REGS                                        \
265
   : (REGNO) < 60 ? FP_REGS                                             \
266
   : SHIFT_REGS)
267
 
268
 
269
/* Get reg_class from a letter such as appears in the machine description.  */
270
/* Keep 'x' for backward compatibility with user asm.  */
271
#define REG_CLASS_FROM_LETTER(C) \
272
  ((C) == 'f' ? FP_REGS :                                       \
273
   (C) == 'y' ? FP_REGS :                                       \
274
   (C) == 'x' ? FP_REGS :                                       \
275
   (C) == 'q' ? SHIFT_REGS :                                    \
276
   (C) == 'a' ? R1_REGS :                                       \
277
   (C) == 'Z' ? ALL_REGS : NO_REGS)
278
 
279
 
280
/* Return the maximum number of consecutive registers
281
   needed to represent mode MODE in a register of class CLASS.  */
282
#define CLASS_MAX_NREGS(CLASS, MODE)                                    \
283
  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
284
 
285
/* 1 if N is a possible register number for function argument passing.  */
286
 
287
#define FUNCTION_ARG_REGNO_P(N) \
288
  ((((N) >= 19) && (N) <= 26) \
289
   || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
290
 
291
/* How to refer to registers in assembler output.
292
   This sequence is indexed by compiler's hard-register-number (see above).  */
293
 
294
#define REGISTER_NAMES \
295
{"%r0",   "%r1",    "%r2",   "%r3",    "%r4",   "%r5",    "%r6",   "%r7",    \
296
 "%r8",   "%r9",    "%r10",  "%r11",   "%r12",  "%r13",   "%r14",  "%r15",   \
297
 "%r16",  "%r17",   "%r18",  "%r19",   "%r20",  "%r21",   "%r22",  "%r23",   \
298
 "%r24",  "%r25",   "%r26",  "%r27",   "%r28",  "%r29",   "%r30",  "%r31",   \
299
 "%fr4",  "%fr5",   "%fr6",  "%fr7",   "%fr8",  "%fr9",   "%fr10", "%fr11",  \
300
 "%fr12", "%fr13",  "%fr14", "%fr15",  "%fr16", "%fr17",  "%fr18", "%fr19",  \
301
 "%fr20", "%fr21",  "%fr22", "%fr23",  "%fr24", "%fr25",  "%fr26", "%fr27",  \
302
 "%fr28", "%fr29",  "%fr30", "%fr31", "SAR"}
303
 
304
#define ADDITIONAL_REGISTER_NAMES \
305
 {{"%cr11",60}}
306
 
307
#define FP_SAVED_REG_LAST 49
308
#define FP_SAVED_REG_FIRST 40
309
#define FP_REG_STEP 1
310
#define FP_REG_FIRST 32
311
#define FP_REG_LAST 59

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