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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [rs6000/] [spe.md] - Blame information for rev 242

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1 38 julius 
;; e500 SPE description
2 
;; Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
3 
;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
4 
 
5 
;; This file is part of GCC.
6 
 
7 
;; GCC is free software; you can redistribute it and/or modify it
8 
;; under the terms of the GNU General Public License as published
9 
;; by the Free Software Foundation; either version 3, or (at your
10 
;; option) any later version.
11 
 
12 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15 
;; License for more details.
16 
 
17 
;; You should have received a copy of the GNU General Public License
18 
;; along with GCC; see the file COPYING3.  If not see
19 
;; .
20 
 
21 
(define_constants
22 
  [(SPE_ACC_REGNO       111)
23 
   (SPEFSCR_REGNO       112)
24 
 
25 
   (CMPDFEQ_GPR         1006)
26 
   (TSTDFEQ_GPR         1007)
27 
   (CMPDFGT_GPR         1008)
28 
   (TSTDFGT_GPR         1009)
29 
   (CMPDFLT_GPR         1010)
30 
   (TSTDFLT_GPR         1011)
31 
   (E500_CR_IOR_COMPARE 1012)
32 
   ])
33 
 
34 
;; Modes using a 64-bit register.
35 
(define_mode_macro SPE64 [DF V4HI V2SF V1DI V2SI])
36 
 
37 
(define_insn "*negsf2_gpr"
38 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
39 
        (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
40 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
41 
  "efsneg %0,%1"
42 
  [(set_attr "type" "fpsimple")])
43 
 
44 
(define_insn "*abssf2_gpr"
45 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
46 
        (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
47 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
48 
  "efsabs %0,%1"
49 
  [(set_attr "type" "fpsimple")])
50 
 
51 
(define_insn "*nabssf2_gpr"
52 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
53 
        (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
54 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
55 
  "efsnabs %0,%1"
56 
  [(set_attr "type" "fpsimple")])
57 
 
58 
(define_insn "*addsf3_gpr"
59 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
60 
        (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
61 
                 (match_operand:SF 2 "gpc_reg_operand" "r")))]
62 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
63 
  "efsadd %0,%1,%2"
64 
  [(set_attr "type" "fp")])
65 
 
66 
(define_insn "*subsf3_gpr"
67 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
68 
        (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
69 
                  (match_operand:SF 2 "gpc_reg_operand" "r")))]
70 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
71 
  "efssub %0,%1,%2"
72 
  [(set_attr "type" "fp")])
73 
 
74 
(define_insn "*mulsf3_gpr"
75 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
76 
        (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
77 
                 (match_operand:SF 2 "gpc_reg_operand" "r")))]
78 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
79 
  "efsmul %0,%1,%2"
80 
  [(set_attr "type" "fp")])
81 
 
82 
(define_insn "*divsf3_gpr"
83 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
84 
        (div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
85 
                (match_operand:SF 2 "gpc_reg_operand" "r")))]
86 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
87 
  "efsdiv %0,%1,%2"
88 
  [(set_attr "type" "vecfdiv")])
89 
 
90 
;; Floating point conversion instructions.
91 
 
92 
(define_insn "fixuns_truncdfsi2"
93 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
94 
        (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
95 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
96 
  "efdctuiz %0,%1"
97 
  [(set_attr "type" "fp")])
98 
 
99 
(define_insn "spe_extendsfdf2"
100 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
101 
        (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
102 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
103 
  "efdcfs %0,%1"
104 
  [(set_attr "type" "fp")])
105 
 
106 
(define_insn "spe_fixuns_truncsfsi2"
107 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
108 
        (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
109 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
110 
  "efsctuiz %0,%1"
111 
  [(set_attr "type" "fp")])
112 
 
113 
(define_insn "spe_fix_truncsfsi2"
114 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
115 
        (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
116 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
117 
  "efsctsiz %0,%1"
118 
  [(set_attr "type" "fp")])
119 
 
120 
(define_insn "spe_fix_truncdfsi2"
121 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
122 
        (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
123 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
124 
  "efdctsiz %0,%1"
125 
  [(set_attr "type" "fp")])
126 
 
127 
(define_insn "spe_floatunssisf2"
128 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
129 
        (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
130 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
131 
  "efscfui %0,%1"
132 
  [(set_attr "type" "fp")])
133 
 
134 
(define_insn "spe_floatunssidf2"
135 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
136 
        (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
137 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
138 
  "efdcfui %0,%1"
139 
  [(set_attr "type" "fp")])
140 
 
141 
(define_insn "spe_floatsisf2"
142 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
143 
        (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
144 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
145 
  "efscfsi %0,%1"
146 
  [(set_attr "type" "fp")])
147 
 
148 
(define_insn "spe_floatsidf2"
149 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
150 
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
151 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
152 
  "efdcfsi %0,%1"
153 
  [(set_attr "type" "fp")])
154 
 
155 
;; SPE SIMD instructions
156 
 
157 
(define_insn "spe_evabs"
158 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
159 
        (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
160 
  "TARGET_SPE"
161 
  "evabs %0,%1"
162 
  [(set_attr "type" "vecsimple")
163 
   (set_attr  "length" "4")])
164 
 
165 
(define_insn "spe_evandc"
166 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
167 
        (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
168 
                  (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
169 
  "TARGET_SPE"
170 
  "evandc %0,%1,%2"
171 
  [(set_attr "type" "vecsimple")
172 
   (set_attr  "length" "4")])
173 
 
174 
(define_insn "spe_evand"
175 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
176 
        (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
177 
                  (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
178 
  "TARGET_SPE"
179 
  "evand %0,%1,%2"
180 
  [(set_attr "type" "vecsimple")
181 
   (set_attr  "length" "4")])
182 
 
183 
;; Vector compare instructions
184 
 
185 
(define_insn "spe_evcmpeq"
186 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
187 
        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
188 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]
189 
  "TARGET_SPE"
190 
  "evcmpeq %0,%1,%2"
191 
  [(set_attr "type" "veccmp")
192 
   (set_attr  "length" "4")])
193 
 
194 
(define_insn "spe_evcmpgts"
195 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
196 
        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
197 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]
198 
  "TARGET_SPE"
199 
  "evcmpgts %0,%1,%2"
200 
  [(set_attr "type" "veccmp")
201 
   (set_attr  "length" "4")])
202 
 
203 
(define_insn "spe_evcmpgtu"
204 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
205 
        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
206 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]
207 
  "TARGET_SPE"
208 
  "evcmpgtu %0,%1,%2"
209 
  [(set_attr "type" "veccmp")
210 
   (set_attr  "length" "4")])
211 
 
212 
(define_insn "spe_evcmplts"
213 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
214 
        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
215 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]
216 
  "TARGET_SPE"
217 
  "evcmplts %0,%1,%2"
218 
  [(set_attr "type" "veccmp")
219 
   (set_attr  "length" "4")])
220 
 
221 
(define_insn "spe_evcmpltu"
222 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
223 
        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
224 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]
225 
  "TARGET_SPE"
226 
  "evcmpltu %0,%1,%2"
227 
  [(set_attr "type" "veccmp")
228 
   (set_attr  "length" "4")])
229 
 
230 
;; Floating point vector compare instructions
231 
 
232 
(define_insn "spe_evfscmpeq"
233 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
234 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
235 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))
236 
   (clobber (reg:SI SPEFSCR_REGNO))]
237 
  "TARGET_SPE"
238 
  "evfscmpeq %0,%1,%2"
239 
  [(set_attr "type" "veccmp")
240 
   (set_attr  "length" "4")])
241 
 
242 
(define_insn "spe_evfscmpgt"
243 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
244 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
245 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))
246 
   (clobber (reg:SI SPEFSCR_REGNO))]
247 
  "TARGET_SPE"
248 
  "evfscmpgt %0,%1,%2"
249 
  [(set_attr "type" "veccmp")
250 
   (set_attr  "length" "4")])
251 
 
252 
(define_insn "spe_evfscmplt"
253 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
254 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
255 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))
256 
   (clobber (reg:SI SPEFSCR_REGNO))]
257 
  "TARGET_SPE"
258 
  "evfscmplt %0,%1,%2"
259 
  [(set_attr "type" "veccmp")
260 
   (set_attr  "length" "4")])
261 
 
262 
(define_insn "spe_evfststeq"
263 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
264 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
265 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]
266 
  "TARGET_SPE"
267 
  "evfststeq %0,%1,%2"
268 
  [(set_attr "type" "veccmp")
269 
   (set_attr  "length" "4")])
270 
 
271 
(define_insn "spe_evfststgt"
272 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
273 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
274 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]
275 
  "TARGET_SPE"
276 
  "evfststgt %0,%1,%2"
277 
  [(set_attr "type" "veccmp")
278 
   (set_attr  "length" "4")])
279 
 
280 
(define_insn "spe_evfststlt"
281 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
282 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
283 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]
284 
  "TARGET_SPE"
285 
  "evfststlt %0,%1,%2"
286 
  [(set_attr "type" "veccmp")
287 
   (set_attr  "length" "4")])
288 
 
289 
;; End of vector compare instructions
290 
 
291 
(define_insn "spe_evcntlsw"
292 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
293 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
294 
  "TARGET_SPE"
295 
  "evcntlsw %0,%1"
296 
  [(set_attr "type" "vecsimple")
297 
   (set_attr  "length" "4")])
298 
 
299 
(define_insn "spe_evcntlzw"
300 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
301 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
302 
  "TARGET_SPE"
303 
  "evcntlzw %0,%1"
304 
  [(set_attr "type" "vecsimple")
305 
   (set_attr  "length" "4")])
306 
 
307 
(define_insn "spe_eveqv"
308 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
309 
        (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
310 
                            (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
311 
  "TARGET_SPE"
312 
  "eveqv %0,%1,%2"
313 
  [(set_attr "type" "vecsimple")
314 
   (set_attr  "length" "4")])
315 
 
316 
(define_insn "spe_evextsb"
317 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
318 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
319 
  "TARGET_SPE"
320 
  "evextsb %0,%1"
321 
  [(set_attr "type" "vecsimple")
322 
   (set_attr  "length" "4")])
323 
 
324 
(define_insn "spe_evextsh"
325 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
326 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
327 
  "TARGET_SPE"
328 
  "evextsh %0,%1"
329 
  [(set_attr "type" "vecsimple")
330 
   (set_attr  "length" "4")])
331 
 
332 
(define_insn "spe_evlhhesplat"
333 
  [(set (match_operand:V2SI 0 "gpc_reg_operand"  "=r")
334 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand"   "b")
335 
                           (match_operand:QI 2 "immediate_operand" "i"))))
336 
   (unspec [(const_int 0)] 509)]
337 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
338 
  "evlhhesplat %0,%2*2(%1)"
339 
  [(set_attr "type" "vecload")
340 
   (set_attr  "length" "4")])
341 
 
342 
(define_insn "spe_evlhhesplatx"
343 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
344 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
345 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
346 
   (unspec [(const_int 0)] 510)]
347 
  "TARGET_SPE"
348 
  "evlhhesplatx %0,%1,%2"
349 
  [(set_attr "type" "vecload")
350 
   (set_attr  "length" "4")])
351 
 
352 
(define_insn "spe_evlhhossplat"
353 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
354 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
355 
                           (match_operand:QI 2 "immediate_operand" "i"))))
356 
   (unspec [(const_int 0)] 511)]
357 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
358 
  "evlhhossplat %0,%2*2(%1)"
359 
  [(set_attr "type" "vecload")
360 
   (set_attr  "length" "4")])
361 
 
362 
(define_insn "spe_evlhhossplatx"
363 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
364 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
365 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
366 
   (unspec [(const_int 0)] 512)]
367 
  "TARGET_SPE"
368 
  "evlhhossplatx %0,%1,%2"
369 
  [(set_attr "type" "vecload")
370 
   (set_attr  "length" "4")])
371 
 
372 
(define_insn "spe_evlhhousplat"
373 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
374 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
375 
                           (match_operand:QI 2 "immediate_operand" "i"))))
376 
   (unspec [(const_int 0)] 513)]
377 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
378 
  "evlhhousplat %0,%2*2(%1)"
379 
  [(set_attr "type" "vecload")
380 
   (set_attr  "length" "4")])
381 
 
382 
(define_insn "spe_evlhhousplatx"
383 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
384 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
385 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
386 
   (unspec [(const_int 0)] 514)]
387 
  "TARGET_SPE"
388 
  "evlhhousplatx %0,%1,%2"
389 
  [(set_attr "type" "vecload")
390 
   (set_attr  "length" "4")])
391 
 
392 
(define_insn "spe_evlwhsplat"
393 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
394 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
395 
                           (match_operand:QI 2 "immediate_operand" "i"))))
396 
   (unspec [(const_int 0)] 515)]
397 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
398 
  "evlwhsplat %0,%2*4(%1)"
399 
  [(set_attr "type" "vecload")
400 
   (set_attr  "length" "4")])
401 
 
402 
(define_insn "spe_evlwhsplatx"
403 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
404 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
405 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
406 
   (unspec [(const_int 0)] 516)]
407 
  "TARGET_SPE"
408 
  "evlwhsplatx %0,%1,%2"
409 
  [(set_attr "type" "vecload")
410 
   (set_attr  "length" "4")])
411 
 
412 
(define_insn "spe_evlwwsplat"
413 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
414 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
415 
                           (match_operand:QI 2 "immediate_operand" "i"))))
416 
   (unspec [(const_int 0)] 517)]
417 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
418 
  "evlwwsplat %0,%2*4(%1)"
419 
  [(set_attr "type" "vecload")
420 
   (set_attr  "length" "4")])
421 
 
422 
(define_insn "spe_evlwwsplatx"
423 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
424 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
425 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
426 
   (unspec [(const_int 0)] 518)]
427 
  "TARGET_SPE"
428 
  "evlwwsplatx %0,%1,%2"
429 
  [(set_attr "type" "vecload")
430 
   (set_attr  "length" "4")])
431 
 
432 
(define_insn "spe_evmergehi"
433 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
434 
        (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
435 
                        (vec_select:V2SI
436 
                         (match_operand:V2SI 2 "gpc_reg_operand" "r")
437 
                         (parallel [(const_int 1)
438 
                                    (const_int 0)]))
439 
                        (const_int 2)))]
440 
  "TARGET_SPE"
441 
  "evmergehi %0,%1,%2"
442 
  [(set_attr "type" "vecsimple")
443 
   (set_attr  "length" "4")])
444 
 
445 
(define_insn "spe_evmergehilo"
446 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
447 
        (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
448 
                        (match_operand:V2SI 2 "gpc_reg_operand" "r")
449 
                        (const_int 2)))]
450 
  "TARGET_SPE"
451 
  "evmergehilo %0,%1,%2"
452 
  [(set_attr "type" "vecsimple")
453 
   (set_attr  "length" "4")])
454 
 
455 
(define_insn "spe_evmergelo"
456 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
457 
        (vec_merge:V2SI (vec_select:V2SI
458 
                         (match_operand:V2SI 1 "gpc_reg_operand" "r")
459 
                         (parallel [(const_int 1)
460 
                                    (const_int 0)]))
461 
                        (match_operand:V2SI 2 "gpc_reg_operand" "r")
462 
                        (const_int 2)))]
463 
  "TARGET_SPE"
464 
  "evmergelo %0,%1,%2"
465 
  [(set_attr "type" "vecsimple")
466 
   (set_attr  "length" "4")])
467 
 
468 
(define_insn "spe_evmergelohi"
469 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
470 
        (vec_merge:V2SI (vec_select:V2SI
471 
                         (match_operand:V2SI 1 "gpc_reg_operand" "r")
472 
                         (parallel [(const_int 1)
473 
                                    (const_int 0)]))
474 
                        (vec_select:V2SI
475 
                         (match_operand:V2SI 2 "gpc_reg_operand" "r")
476 
                         (parallel [(const_int 1)
477 
                                    (const_int 0)]))
478 
                        (const_int 2)))]
479 
  "TARGET_SPE"
480 
  "evmergelohi %0,%1,%2"
481 
  [(set_attr "type" "vecsimple")
482 
   (set_attr  "length" "4")])
483 
 
484 
(define_insn "spe_evnand"
485 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
486 
        (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
487 
                            (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
488 
  "TARGET_SPE"
489 
  "evnand %0,%1,%2"
490 
  [(set_attr "type" "vecsimple")
491 
   (set_attr  "length" "4")])
492 
 
493 
(define_insn "negv2si2"
494 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
495 
        (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
496 
  "TARGET_SPE"
497 
  "evneg %0,%1"
498 
  [(set_attr "type" "vecsimple")
499 
   (set_attr  "length" "4")])
500 
 
501 
(define_insn "spe_evnor"
502 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
503 
        (not:V2SI  (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
504 
                             (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
505 
  "TARGET_SPE"
506 
  "evnor %0,%1,%2"
507 
  [(set_attr "type" "vecsimple")
508 
   (set_attr  "length" "4")])
509 
 
510 
(define_insn "spe_evorc"
511 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
512 
        (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
513 
                  (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
514 
  "TARGET_SPE"
515 
  "evorc %0,%1,%2"
516 
  [(set_attr "type" "vecsimple")
517 
   (set_attr  "length" "4")])
518 
 
519 
(define_insn "spe_evor"
520 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
521 
        (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
522 
                  (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
523 
  "TARGET_SPE"
524 
  "evor %0,%1,%2"
525 
  [(set_attr "type" "vecsimple")
526 
   (set_attr  "length" "4")])
527 
 
528 
(define_insn "spe_evrlwi"
529 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
530 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
531 
                      (match_operand:QI 2 "immediate_operand" "i")] 519))]
532 
  "TARGET_SPE"
533 
  "evrlwi %0,%1,%2"
534 
  [(set_attr "type" "vecsimple")
535 
   (set_attr  "length" "4")])
536 
 
537 
(define_insn "spe_evrlw"
538 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
539 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
540 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))]
541 
  "TARGET_SPE"
542 
  "evrlw %0,%1,%2"
543 
  [(set_attr "type" "veccomplex")
544 
   (set_attr  "length" "4")])
545 
 
546 
(define_insn "spe_evrndw"
547 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
548 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
549 
  "TARGET_SPE"
550 
  "evrndw %0,%1"
551 
  [(set_attr "type" "vecsimple")
552 
   (set_attr  "length" "4")])
553 
 
554 
(define_insn "spe_evsel"
555 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
556 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
557 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
558 
                      (match_operand:CC 3 "cc_reg_operand" "y")] 522))]
559 
  "TARGET_SPE"
560 
  "evsel %0,%1,%2,%3"
561 
  [(set_attr "type" "veccmp")
562 
   (set_attr "length" "4")])
563 
 
564 
(define_insn "spe_evsel_fs"
565 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
566 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
567 
                      (match_operand:V2SF 2 "gpc_reg_operand" "r")
568 
                      (match_operand:CC 3 "cc_reg_operand" "y")] 725))]
569 
  "TARGET_SPE"
570 
  "evsel %0,%1,%2,%3"
571 
  [(set_attr "type" "veccmp")
572 
   (set_attr "length" "4")])
573 
 
574 
(define_insn "spe_evslwi"
575 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
576 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
577 
                      (match_operand:QI 2 "immediate_operand" "i")]
578 
                     523))]
579 
  "TARGET_SPE"
580 
  "evslwi %0,%1,%2"
581 
  [(set_attr "type" "vecsimple")
582 
   (set_attr  "length" "4")])
583 
 
584 
(define_insn "spe_evslw"
585 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
586 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
587 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))]
588 
  "TARGET_SPE"
589 
  "evslw %0,%1,%2"
590 
  [(set_attr "type" "vecsimple")
591 
   (set_attr  "length" "4")])
592 
 
593 
(define_insn "spe_evsrwis"
594 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
595 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
596 
                      (match_operand:QI 2 "immediate_operand" "i")]
597 
                     525))]
598 
  "TARGET_SPE"
599 
  "evsrwis %0,%1,%2"
600 
  [(set_attr "type" "vecsimple")
601 
   (set_attr  "length" "4")])
602 
 
603 
(define_insn "spe_evsrwiu"
604 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
605 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
606 
                      (match_operand:QI 2 "immediate_operand" "i")]
607 
                     526))]
608 
  "TARGET_SPE"
609 
  "evsrwiu %0,%1,%2"
610 
  [(set_attr "type" "vecsimple")
611 
   (set_attr  "length" "4")])
612 
 
613 
(define_insn "spe_evsrws"
614 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
615 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
616 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))]
617 
  "TARGET_SPE"
618 
  "evsrws %0,%1,%2"
619 
  [(set_attr "type" "vecsimple")
620 
   (set_attr  "length" "4")])
621 
 
622 
(define_insn "spe_evsrwu"
623 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
624 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
625 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))]
626 
  "TARGET_SPE"
627 
  "evsrwu %0,%1,%2"
628 
  [(set_attr "type" "vecsimple")
629 
   (set_attr  "length" "4")])
630 
 
631 
;; vector xors
632 
 
633 
(define_insn "xorv2si3"
634 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
635 
        (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
636 
                  (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
637 
  "TARGET_SPE"
638 
  "evxor %0,%1,%2"
639 
  [(set_attr "type" "vecsimple")
640 
   (set_attr  "length" "4")])
641 
 
642 
(define_insn "xorv4hi3"
643 
  [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
644 
        (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
645 
                  (match_operand:V4HI 2 "gpc_reg_operand" "r")))]
646 
  "TARGET_SPE"
647 
  "evxor %0,%1,%2"
648 
  [(set_attr "type" "vecsimple")
649 
   (set_attr  "length" "4")])
650 
 
651 
(define_insn "xorv1di3"
652 
  [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
653 
        (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
654 
                  (match_operand:V1DI 2 "gpc_reg_operand" "r")))]
655 
  "TARGET_SPE"
656 
  "evxor %0,%1,%2"
657 
  [(set_attr "type" "vecsimple")
658 
   (set_attr  "length" "4")])
659 
 
660 
;; end of vector xors
661 
 
662 
(define_insn "spe_evfsabs"
663 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
664 
        (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
665 
  "TARGET_SPE"
666 
  "evfsabs %0,%1"
667 
  [(set_attr "type" "vecsimple")
668 
   (set_attr  "length" "4")])
669 
 
670 
(define_insn "spe_evfsadd"
671 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
672 
        (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
673 
                   (match_operand:V2SF 2 "gpc_reg_operand" "r")))
674 
   (clobber (reg:SI SPEFSCR_REGNO))]
675 
  "TARGET_SPE"
676 
  "evfsadd %0,%1,%2"
677 
  [(set_attr "type" "vecfloat")
678 
   (set_attr  "length" "4")])
679 
 
680 
(define_insn "spe_evfscfsf"
681 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
682 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
683 
  "TARGET_SPE"
684 
  "evfscfsf %0,%1"
685 
  [(set_attr "type" "vecfloat")
686 
   (set_attr  "length" "4")])
687 
 
688 
(define_insn "spe_evfscfsi"
689 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
690 
        (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
691 
  "TARGET_SPE"
692 
  "evfscfsi %0,%1"
693 
  [(set_attr "type" "vecfloat")
694 
   (set_attr  "length" "4")])
695 
 
696 
(define_insn "spe_evfscfuf"
697 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
698 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
699 
  "TARGET_SPE"
700 
  "evfscfuf %0,%1"
701 
  [(set_attr "type" "vecfloat")
702 
   (set_attr  "length" "4")])
703 
 
704 
(define_insn "spe_evfscfui"
705 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
706 
        (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
707 
  "TARGET_SPE"
708 
  "evfscfui %0,%1"
709 
  [(set_attr "type" "vecfloat")
710 
   (set_attr  "length" "4")])
711 
 
712 
(define_insn "spe_evfsctsf"
713 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
714 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
715 
  "TARGET_SPE"
716 
  "evfsctsf %0,%1"
717 
  [(set_attr "type" "vecfloat")
718 
   (set_attr  "length" "4")])
719 
 
720 
(define_insn "spe_evfsctsi"
721 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
722 
        (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
723 
  "TARGET_SPE"
724 
  "evfsctsi %0,%1"
725 
  [(set_attr "type" "vecfloat")
726 
   (set_attr  "length" "4")])
727 
 
728 
(define_insn "spe_evfsctsiz"
729 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
730 
        (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
731 
  "TARGET_SPE"
732 
  "evfsctsiz %0,%1"
733 
  [(set_attr "type" "vecfloat")
734 
   (set_attr  "length" "4")])
735 
 
736 
(define_insn "spe_evfsctuf"
737 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
738 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
739 
  "TARGET_SPE"
740 
  "evfsctuf %0,%1"
741 
  [(set_attr "type" "vecfloat")
742 
   (set_attr  "length" "4")])
743 
 
744 
(define_insn "spe_evfsctui"
745 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
746 
        (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
747 
  "TARGET_SPE"
748 
  "evfsctui %0,%1"
749 
  [(set_attr "type" "vecfloat")
750 
   (set_attr  "length" "4")])
751 
 
752 
(define_insn "spe_evfsctuiz"
753 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
754 
        (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
755 
  "TARGET_SPE"
756 
  "evfsctuiz %0,%1"
757 
  [(set_attr "type" "vecfloat")
758 
   (set_attr  "length" "4")])
759 
 
760 
(define_insn "spe_evfsdiv"
761 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
762 
        (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
763 
                  (match_operand:V2SF 2 "gpc_reg_operand" "r")))
764 
   (clobber (reg:SI SPEFSCR_REGNO))]
765 
  "TARGET_SPE"
766 
  "evfsdiv %0,%1,%2"
767 
  [(set_attr "type" "vecfdiv")
768 
   (set_attr  "length" "4")])
769 
 
770 
(define_insn "spe_evfsmul"
771 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
772 
        (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
773 
                   (match_operand:V2SF 2 "gpc_reg_operand" "r")))
774 
   (clobber (reg:SI SPEFSCR_REGNO))]
775 
  "TARGET_SPE"
776 
  "evfsmul %0,%1,%2"
777 
  [(set_attr "type" "vecfloat")
778 
   (set_attr  "length" "4")])
779 
 
780 
(define_insn "spe_evfsnabs"
781 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
782 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
783 
  "TARGET_SPE"
784 
  "evfsnabs %0,%1"
785 
  [(set_attr "type" "vecsimple")
786 
   (set_attr  "length" "4")])
787 
 
788 
(define_insn "spe_evfsneg"
789 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
790 
        (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
791 
  "TARGET_SPE"
792 
  "evfsneg %0,%1"
793 
  [(set_attr "type" "vecsimple")
794 
   (set_attr  "length" "4")])
795 
 
796 
(define_insn "spe_evfssub"
797 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
798 
        (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
799 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")))
800 
   (clobber (reg:SI SPEFSCR_REGNO))]
801 
  "TARGET_SPE"
802 
  "evfssub %0,%1,%2"
803 
  [(set_attr "type" "vecfloat")
804 
   (set_attr  "length" "4")])
805 
 
806 
;; SPE SIMD load instructions.
807 
 
808 
;; Only the hardware engineer who designed the SPE understands the
809 
;; plethora of load and store instructions ;-).  We have no way of
810 
;; differentiating between them with RTL so use an unspec of const_int 0
811 
;; to avoid identical RTL.
812 
 
813 
(define_insn "spe_evldd"
814 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
815 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
816 
                           (match_operand:QI 2 "immediate_operand" "i"))))
817 
   (unspec [(const_int 0)] 544)]
818 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
819 
  "evldd %0,%2*8(%1)"
820 
  [(set_attr "type" "vecload")
821 
   (set_attr  "length" "4")])
822 
 
823 
(define_insn "spe_evlddx"
824 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
825 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
826 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
827 
   (unspec [(const_int 0)] 545)]
828 
  "TARGET_SPE"
829 
  "evlddx %0,%1,%2"
830 
  [(set_attr "type" "vecload")
831 
   (set_attr  "length" "4")])
832 
 
833 
(define_insn "spe_evldh"
834 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
835 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
836 
                           (match_operand:QI 2 "immediate_operand" "i"))))
837 
   (unspec [(const_int 0)] 546)]
838 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
839 
  "evldh %0,%2*8(%1)"
840 
  [(set_attr "type" "vecload")
841 
   (set_attr  "length" "4")])
842 
 
843 
(define_insn "spe_evldhx"
844 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
845 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
846 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
847 
   (unspec [(const_int 0)] 547)]
848 
  "TARGET_SPE"
849 
  "evldhx %0,%1,%2"
850 
  [(set_attr "type" "vecload")
851 
   (set_attr  "length" "4")])
852 
 
853 
(define_insn "spe_evldw"
854 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
855 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
856 
                           (match_operand:QI 2 "immediate_operand" "i"))))
857 
   (unspec [(const_int 0)] 548)]
858 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
859 
  "evldw %0,%2*8(%1)"
860 
  [(set_attr "type" "vecload")
861 
   (set_attr  "length" "4")])
862 
 
863 
(define_insn "spe_evldwx"
864 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
865 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
866 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
867 
   (unspec [(const_int 0)] 549)]
868 
  "TARGET_SPE"
869 
  "evldwx %0,%1,%2"
870 
  [(set_attr "type" "vecload")
871 
   (set_attr  "length" "4")])
872 
 
873 
(define_insn "spe_evlwhe"
874 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
875 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
876 
                           (match_operand:QI 2 "immediate_operand" "i"))))
877 
   (unspec [(const_int 0)] 550)]
878 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
879 
  "evlwhe %0,%2*4(%1)"
880 
  [(set_attr "type" "vecload")
881 
   (set_attr  "length" "4")])
882 
 
883 
(define_insn "spe_evlwhex"
884 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
885 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
886 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
887 
   (unspec [(const_int 0)] 551)]
888 
  "TARGET_SPE"
889 
  "evlwhex %0,%1,%2"
890 
  [(set_attr "type" "vecload")
891 
   (set_attr  "length" "4")])
892 
 
893 
(define_insn "spe_evlwhos"
894 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
895 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
896 
                           (match_operand:QI 2 "immediate_operand" "i"))))
897 
   (unspec [(const_int 0)] 552)]
898 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
899 
  "evlwhos %0,%2*4(%1)"
900 
  [(set_attr "type" "vecload")
901 
   (set_attr  "length" "4")])
902 
 
903 
(define_insn "spe_evlwhosx"
904 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
905 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
906 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
907 
   (unspec [(const_int 0)] 553)]
908 
  "TARGET_SPE"
909 
  "evlwhosx %0,%1,%2"
910 
  [(set_attr "type" "vecload")
911 
   (set_attr  "length" "4")])
912 
 
913 
(define_insn "spe_evlwhou"
914 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
915 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
916 
                           (match_operand:QI 2 "immediate_operand" "i"))))
917 
   (unspec [(const_int 0)] 554)]
918 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
919 
  "evlwhou %0,%2*4(%1)"
920 
  [(set_attr "type" "vecload")
921 
   (set_attr  "length" "4")])
922 
 
923 
(define_insn "spe_evlwhoux"
924 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
925 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
926 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
927 
   (unspec [(const_int 0)] 555)]
928 
  "TARGET_SPE"
929 
  "evlwhoux %0,%1,%2"
930 
  [(set_attr "type" "vecload")
931 
   (set_attr  "length" "4")])
932 
 
933 
(define_insn "spe_brinc"
934 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
935 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
936 
                    (match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
937 
  "TARGET_SPE"
938 
  "brinc %0,%1,%2"
939 
  [(set_attr "type" "brinc")
940 
   (set_attr  "length" "4")])
941 
 
942 
(define_insn "spe_evmhegsmfaa"
943 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
944 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
945 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
946 
                      (reg:V2SI SPE_ACC_REGNO)] 557))
947 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
948 
  "TARGET_SPE"
949 
  "evmhegsmfaa %0,%1,%2"
950 
  [(set_attr "type" "veccomplex")
951 
   (set_attr  "length" "4")])
952 
 
953 
(define_insn "spe_evmhegsmfan"
954 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
955 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
956 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
957 
                      (reg:V2SI SPE_ACC_REGNO)] 558))
958 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
959 
  "TARGET_SPE"
960 
  "evmhegsmfan %0,%1,%2"
961 
  [(set_attr "type" "veccomplex")
962 
   (set_attr  "length" "4")])
963 
 
964 
(define_insn "spe_evmhegsmiaa"
965 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
966 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
967 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
968 
                      (reg:V2SI SPE_ACC_REGNO)] 559))
969 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
970 
  "TARGET_SPE"
971 
  "evmhegsmiaa %0,%1,%2"
972 
  [(set_attr "type" "veccomplex")
973 
   (set_attr  "length" "4")])
974 
 
975 
(define_insn "spe_evmhegsmian"
976 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
977 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
978 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
979 
                      (reg:V2SI SPE_ACC_REGNO)] 560))
980 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
981 
  "TARGET_SPE"
982 
  "evmhegsmian %0,%1,%2"
983 
  [(set_attr "type" "veccomplex")
984 
   (set_attr  "length" "4")])
985 
 
986 
(define_insn "spe_evmhegumiaa"
987 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
988 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
989 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
990 
                      (reg:V2SI SPE_ACC_REGNO)] 561))
991 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
992 
  "TARGET_SPE"
993 
  "evmhegumiaa %0,%1,%2"
994 
  [(set_attr "type" "veccomplex")
995 
   (set_attr  "length" "4")])
996 
 
997 
(define_insn "spe_evmhegumian"
998 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
999 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1000 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1001 
                      (reg:V2SI SPE_ACC_REGNO)] 562))
1002 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1003 
  "TARGET_SPE"
1004 
  "evmhegumian %0,%1,%2"
1005 
  [(set_attr "type" "veccomplex")
1006 
   (set_attr  "length" "4")])
1007 
 
1008 
(define_insn "spe_evmhesmfaaw"
1009 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1010 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1011 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1012 
                      (reg:V2SI SPE_ACC_REGNO)] 563))
1013 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1014 
  "TARGET_SPE"
1015 
  "evmhesmfaaw %0,%1,%2"
1016 
  [(set_attr "type" "veccomplex")
1017 
   (set_attr  "length" "4")])
1018 
 
1019 
(define_insn "spe_evmhesmfanw"
1020 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1021 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1022 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1023 
                      (reg:V2SI SPE_ACC_REGNO)] 564))
1024 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1025 
  "TARGET_SPE"
1026 
  "evmhesmfanw %0,%1,%2"
1027 
  [(set_attr "type" "veccomplex")
1028 
   (set_attr  "length" "4")])
1029 
 
1030 
(define_insn "spe_evmhesmfa"
1031 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1032 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1033 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565))
1034 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1035 
  "TARGET_SPE"
1036 
  "evmhesmfa %0,%1,%2"
1037 
  [(set_attr "type" "veccomplex")
1038 
   (set_attr  "length" "4")])
1039 
 
1040 
(define_insn "spe_evmhesmf"
1041 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1042 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1043 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))]
1044 
  "TARGET_SPE"
1045 
  "evmhesmf %0,%1,%2"
1046 
  [(set_attr "type" "veccomplex")
1047 
   (set_attr  "length" "4")])
1048 
 
1049 
(define_insn "spe_evmhesmiaaw"
1050 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1051 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1052 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1053 
                      (reg:V2SI SPE_ACC_REGNO)] 567))
1054 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1055 
  "TARGET_SPE"
1056 
  "evmhesmiaaw %0,%1,%2"
1057 
  [(set_attr "type" "veccomplex")
1058 
   (set_attr  "length" "4")])
1059 
 
1060 
(define_insn "spe_evmhesmianw"
1061 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1062 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1063 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1064 
                      (reg:V2SI SPE_ACC_REGNO)] 568))
1065 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1066 
  "TARGET_SPE"
1067 
  "evmhesmianw %0,%1,%2"
1068 
  [(set_attr "type" "veccomplex")
1069 
   (set_attr  "length" "4")])
1070 
 
1071 
(define_insn "spe_evmhesmia"
1072 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1073 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1074 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569))
1075 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1076 
  "TARGET_SPE"
1077 
  "evmhesmia %0,%1,%2"
1078 
  [(set_attr "type" "veccomplex")
1079 
   (set_attr  "length" "4")])
1080 
 
1081 
(define_insn "spe_evmhesmi"
1082 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1083 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1084 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))]
1085 
  "TARGET_SPE"
1086 
  "evmhesmi %0,%1,%2"
1087 
  [(set_attr "type" "veccomplex")
1088 
   (set_attr  "length" "4")])
1089 
 
1090 
(define_insn "spe_evmhessfaaw"
1091 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1092 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1093 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1094 
                      (reg:V2SI SPE_ACC_REGNO)] 571))
1095 
   (clobber (reg:SI SPEFSCR_REGNO))
1096 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1097 
  "TARGET_SPE"
1098 
  "evmhessfaaw %0,%1,%2"
1099 
  [(set_attr "type" "veccomplex")
1100 
   (set_attr  "length" "4")])
1101 
 
1102 
(define_insn "spe_evmhessfanw"
1103 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1104 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1105 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1106 
                      (reg:V2SI SPE_ACC_REGNO)] 572))
1107 
   (clobber (reg:SI SPEFSCR_REGNO))
1108 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1109 
  "TARGET_SPE"
1110 
  "evmhessfanw %0,%1,%2"
1111 
  [(set_attr "type" "veccomplex")
1112 
   (set_attr  "length" "4")])
1113 
 
1114 
(define_insn "spe_evmhessfa"
1115 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1116 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1117 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573))
1118 
   (clobber (reg:SI SPEFSCR_REGNO))
1119 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1120 
  "TARGET_SPE"
1121 
  "evmhessfa %0,%1,%2"
1122 
  [(set_attr "type" "veccomplex")
1123 
   (set_attr  "length" "4")])
1124 
 
1125 
(define_insn "spe_evmhessf"
1126 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1127 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1128 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574))
1129 
   (clobber (reg:SI SPEFSCR_REGNO))]
1130 
  "TARGET_SPE"
1131 
  "evmhessf %0,%1,%2"
1132 
  [(set_attr "type" "veccomplex")
1133 
   (set_attr  "length" "4")])
1134 
 
1135 
(define_insn "spe_evmhessiaaw"
1136 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1137 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1138 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1139 
                      (reg:V2SI SPE_ACC_REGNO)] 575))
1140 
   (clobber (reg:SI SPEFSCR_REGNO))
1141 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1142 
  "TARGET_SPE"
1143 
  "evmhessiaaw %0,%1,%2"
1144 
  [(set_attr "type" "veccomplex")
1145 
   (set_attr  "length" "4")])
1146 
 
1147 
(define_insn "spe_evmhessianw"
1148 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1149 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1150 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1151 
                      (reg:V2SI SPE_ACC_REGNO)] 576))
1152 
   (clobber (reg:SI SPEFSCR_REGNO))
1153 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1154 
  "TARGET_SPE"
1155 
  "evmhessianw %0,%1,%2"
1156 
  [(set_attr "type" "veccomplex")
1157 
   (set_attr  "length" "4")])
1158 
 
1159 
(define_insn "spe_evmheumiaaw"
1160 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1161 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1162 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1163 
                      (reg:V2SI SPE_ACC_REGNO)] 577))
1164 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1165 
  "TARGET_SPE"
1166 
  "evmheumiaaw %0,%1,%2"
1167 
  [(set_attr "type" "veccomplex")
1168 
   (set_attr  "length" "4")])
1169 
 
1170 
(define_insn "spe_evmheumianw"
1171 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1172 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1173 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1174 
                      (reg:V2SI SPE_ACC_REGNO)] 578))
1175 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1176 
  "TARGET_SPE"
1177 
  "evmheumianw %0,%1,%2"
1178 
  [(set_attr "type" "veccomplex")
1179 
   (set_attr  "length" "4")])
1180 
 
1181 
(define_insn "spe_evmheumia"
1182 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1183 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1184 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579))
1185 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1186 
  "TARGET_SPE"
1187 
  "evmheumia %0,%1,%2"
1188 
  [(set_attr "type" "veccomplex")
1189 
   (set_attr  "length" "4")])
1190 
 
1191 
(define_insn "spe_evmheumi"
1192 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1193 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1194 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))]
1195 
  "TARGET_SPE"
1196 
  "evmheumi %0,%1,%2"
1197 
  [(set_attr "type" "veccomplex")
1198 
   (set_attr  "length" "4")])
1199 
 
1200 
(define_insn "spe_evmheusiaaw"
1201 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1202 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1203 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1204 
                      (reg:V2SI SPE_ACC_REGNO)] 581))
1205 
   (clobber (reg:SI SPEFSCR_REGNO))
1206 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1207 
  "TARGET_SPE"
1208 
  "evmheusiaaw %0,%1,%2"
1209 
  [(set_attr "type" "veccomplex")
1210 
   (set_attr  "length" "4")])
1211 
 
1212 
(define_insn "spe_evmheusianw"
1213 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1214 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1215 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1216 
                      (reg:V2SI SPE_ACC_REGNO)] 582))
1217 
   (clobber (reg:SI SPEFSCR_REGNO))
1218 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1219 
  "TARGET_SPE"
1220 
  "evmheusianw %0,%1,%2"
1221 
  [(set_attr "type" "veccomplex")
1222 
   (set_attr  "length" "4")])
1223 
 
1224 
(define_insn "spe_evmhogsmfaa"
1225 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1226 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1227 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1228 
                      (reg:V2SI SPE_ACC_REGNO)] 583))
1229 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1230 
  "TARGET_SPE"
1231 
  "evmhogsmfaa %0,%1,%2"
1232 
  [(set_attr "type" "veccomplex")
1233 
   (set_attr  "length" "4")])
1234 
 
1235 
(define_insn "spe_evmhogsmfan"
1236 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1237 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1238 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1239 
                      (reg:V2SI SPE_ACC_REGNO)] 584))
1240 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1241 
  "TARGET_SPE"
1242 
  "evmhogsmfan %0,%1,%2"
1243 
  [(set_attr "type" "veccomplex")
1244 
   (set_attr  "length" "4")])
1245 
 
1246 
(define_insn "spe_evmhogsmiaa"
1247 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1248 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1249 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1250 
                      (reg:V2SI SPE_ACC_REGNO)] 585))
1251 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1252 
  "TARGET_SPE"
1253 
  "evmhogsmiaa %0,%1,%2"
1254 
  [(set_attr "type" "veccomplex")
1255 
   (set_attr  "length" "4")])
1256 
 
1257 
(define_insn "spe_evmhogsmian"
1258 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1259 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1260 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1261 
                      (reg:V2SI SPE_ACC_REGNO)] 586))
1262 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1263 
  "TARGET_SPE"
1264 
  "evmhogsmian %0,%1,%2"
1265 
  [(set_attr "type" "veccomplex")
1266 
   (set_attr  "length" "4")])
1267 
 
1268 
(define_insn "spe_evmhogumiaa"
1269 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1270 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1271 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1272 
                      (reg:V2SI SPE_ACC_REGNO)] 587))
1273 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1274 
  "TARGET_SPE"
1275 
  "evmhogumiaa %0,%1,%2"
1276 
  [(set_attr "type" "veccomplex")
1277 
   (set_attr  "length" "4")])
1278 
 
1279 
(define_insn "spe_evmhogumian"
1280 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1281 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1282 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1283 
                      (reg:V2SI SPE_ACC_REGNO)] 588))
1284 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1285 
  "TARGET_SPE"
1286 
  "evmhogumian %0,%1,%2"
1287 
  [(set_attr "type" "veccomplex")
1288 
   (set_attr  "length" "4")])
1289 
 
1290 
(define_insn "spe_evmhosmfaaw"
1291 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1292 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1293 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1294 
                      (reg:V2SI SPE_ACC_REGNO)] 589))
1295 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1296 
  "TARGET_SPE"
1297 
  "evmhosmfaaw %0,%1,%2"
1298 
  [(set_attr "type" "veccomplex")
1299 
   (set_attr  "length" "4")])
1300 
 
1301 
(define_insn "spe_evmhosmfanw"
1302 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1303 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1304 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1305 
                      (reg:V2SI SPE_ACC_REGNO)] 590))
1306 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1307 
  "TARGET_SPE"
1308 
  "evmhosmfanw %0,%1,%2"
1309 
  [(set_attr "type" "veccomplex")
1310 
   (set_attr  "length" "4")])
1311 
 
1312 
(define_insn "spe_evmhosmfa"
1313 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1314 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1315 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))]
1316 
  "TARGET_SPE"
1317 
  "evmhosmfa %0,%1,%2"
1318 
  [(set_attr "type" "veccomplex")
1319 
   (set_attr  "length" "4")])
1320 
 
1321 
(define_insn "spe_evmhosmf"
1322 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1323 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1324 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592))
1325 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1326 
  "TARGET_SPE"
1327 
  "evmhosmf %0,%1,%2"
1328 
  [(set_attr "type" "veccomplex")
1329 
   (set_attr  "length" "4")])
1330 
 
1331 
(define_insn "spe_evmhosmiaaw"
1332 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1333 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1334 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1335 
                      (reg:V2SI SPE_ACC_REGNO)] 593))
1336 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1337 
  "TARGET_SPE"
1338 
  "evmhosmiaaw %0,%1,%2"
1339 
  [(set_attr "type" "veccomplex")
1340 
   (set_attr  "length" "4")])
1341 
 
1342 
(define_insn "spe_evmhosmianw"
1343 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1344 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1345 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1346 
                      (reg:V2SI SPE_ACC_REGNO)] 594))
1347 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1348 
  "TARGET_SPE"
1349 
  "evmhosmianw %0,%1,%2"
1350 
  [(set_attr "type" "veccomplex")
1351 
   (set_attr  "length" "4")])
1352 
 
1353 
(define_insn "spe_evmhosmia"
1354 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1355 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1356 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595))
1357 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1358 
  "TARGET_SPE"
1359 
  "evmhosmia %0,%1,%2"
1360 
  [(set_attr "type" "veccomplex")
1361 
   (set_attr  "length" "4")])
1362 
 
1363 
(define_insn "spe_evmhosmi"
1364 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1365 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1366 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))]
1367 
  "TARGET_SPE"
1368 
  "evmhosmi %0,%1,%2"
1369 
  [(set_attr "type" "veccomplex")
1370 
   (set_attr  "length" "4")])
1371 
 
1372 
(define_insn "spe_evmhossfaaw"
1373 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1374 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1375 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1376 
                      (reg:V2SI SPE_ACC_REGNO)] 597))
1377 
   (clobber (reg:SI SPEFSCR_REGNO))
1378 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1379 
  "TARGET_SPE"
1380 
  "evmhossfaaw %0,%1,%2"
1381 
  [(set_attr "type" "veccomplex")
1382 
   (set_attr  "length" "4")])
1383 
 
1384 
(define_insn "spe_evmhossfanw"
1385 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1386 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1387 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1388 
                      (reg:V2SI SPE_ACC_REGNO)] 598))
1389 
   (clobber (reg:SI SPEFSCR_REGNO))
1390 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1391 
  "TARGET_SPE"
1392 
  "evmhossfanw %0,%1,%2"
1393 
  [(set_attr "type" "veccomplex")
1394 
   (set_attr  "length" "4")])
1395 
 
1396 
(define_insn "spe_evmhossfa"
1397 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1398 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1399 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1400 
                      (reg:V2SI SPE_ACC_REGNO)] 599))
1401 
   (clobber (reg:SI SPEFSCR_REGNO))
1402 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1403 
  "TARGET_SPE"
1404 
  "evmhossfa %0,%1,%2"
1405 
  [(set_attr "type" "veccomplex")
1406 
   (set_attr  "length" "4")])
1407 
 
1408 
(define_insn "spe_evmhossf"
1409 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1410 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1411 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600))
1412 
   (clobber (reg:SI SPEFSCR_REGNO))]
1413 
  "TARGET_SPE"
1414 
  "evmhossf %0,%1,%2"
1415 
  [(set_attr "type" "veccomplex")
1416 
   (set_attr  "length" "4")])
1417 
 
1418 
(define_insn "spe_evmhossiaaw"
1419 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1420 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1421 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1422 
                      (reg:V2SI SPE_ACC_REGNO)] 601))
1423 
   (clobber (reg:SI SPEFSCR_REGNO))
1424 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1425 
  "TARGET_SPE"
1426 
  "evmhossiaaw %0,%1,%2"
1427 
  [(set_attr "type" "veccomplex")
1428 
   (set_attr  "length" "4")])
1429 
 
1430 
(define_insn "spe_evmhossianw"
1431 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1432 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1433 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1434 
                      (reg:V2SI SPE_ACC_REGNO)] 602))
1435 
   (clobber (reg:SI SPEFSCR_REGNO))
1436 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1437 
  "TARGET_SPE"
1438 
  "evmhossianw %0,%1,%2"
1439 
  [(set_attr "type" "veccomplex")
1440 
   (set_attr  "length" "4")])
1441 
 
1442 
(define_insn "spe_evmhoumiaaw"
1443 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1444 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1445 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1446 
                      (reg:V2SI SPE_ACC_REGNO)] 603))
1447 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1448 
  "TARGET_SPE"
1449 
  "evmhoumiaaw %0,%1,%2"
1450 
  [(set_attr "type" "veccomplex")
1451 
   (set_attr  "length" "4")])
1452 
 
1453 
(define_insn "spe_evmhoumianw"
1454 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1455 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1456 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1457 
                      (reg:V2SI SPE_ACC_REGNO)] 604))
1458 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1459 
  "TARGET_SPE"
1460 
  "evmhoumianw %0,%1,%2"
1461 
  [(set_attr "type" "veccomplex")
1462 
   (set_attr  "length" "4")])
1463 
 
1464 
(define_insn "spe_evmhoumia"
1465 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1466 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1467 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605))
1468 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1469 
  "TARGET_SPE"
1470 
  "evmhoumia %0,%1,%2"
1471 
  [(set_attr "type" "veccomplex")
1472 
   (set_attr  "length" "4")])
1473 
 
1474 
(define_insn "spe_evmhoumi"
1475 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1476 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1477 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))]
1478 
  "TARGET_SPE"
1479 
  "evmhoumi %0,%1,%2"
1480 
  [(set_attr "type" "veccomplex")
1481 
   (set_attr  "length" "4")])
1482 
 
1483 
(define_insn "spe_evmhousiaaw"
1484 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1485 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1486 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1487 
                      (reg:V2SI SPE_ACC_REGNO)] 607))
1488 
   (clobber (reg:SI SPEFSCR_REGNO))
1489 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1490 
  "TARGET_SPE"
1491 
  "evmhousiaaw %0,%1,%2"
1492 
  [(set_attr "type" "veccomplex")
1493 
   (set_attr  "length" "4")])
1494 
 
1495 
(define_insn "spe_evmhousianw"
1496 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1497 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1498 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1499 
                      (reg:V2SI SPE_ACC_REGNO)] 608))
1500 
   (clobber (reg:SI SPEFSCR_REGNO))
1501 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1502 
  "TARGET_SPE"
1503 
  "evmhousianw %0,%1,%2"
1504 
  [(set_attr "type" "veccomplex")
1505 
   (set_attr  "length" "4")])
1506 
 
1507 
(define_insn "spe_evmmlssfa"
1508 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1509 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1510 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))]
1511 
  "TARGET_SPE"
1512 
  "evmmlssfa %0,%1,%2"
1513 
  [(set_attr "type" "veccomplex")
1514 
   (set_attr  "length" "4")])
1515 
 
1516 
(define_insn "spe_evmmlssf"
1517 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1518 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1519 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))]
1520 
  "TARGET_SPE"
1521 
  "evmmlssf %0,%1,%2"
1522 
  [(set_attr "type" "veccomplex")
1523 
   (set_attr  "length" "4")])
1524 
 
1525 
(define_insn "spe_evmwhsmfa"
1526 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1527 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1528 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611))
1529 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1530 
  "TARGET_SPE"
1531 
  "evmwhsmfa %0,%1,%2"
1532 
  [(set_attr "type" "veccomplex")
1533 
   (set_attr  "length" "4")])
1534 
 
1535 
(define_insn "spe_evmwhsmf"
1536 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1537 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1538 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))]
1539 
  "TARGET_SPE"
1540 
  "evmwhsmf %0,%1,%2"
1541 
  [(set_attr "type" "veccomplex")
1542 
   (set_attr  "length" "4")])
1543 
 
1544 
(define_insn "spe_evmwhsmia"
1545 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1546 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1547 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613))
1548 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1549 
  "TARGET_SPE"
1550 
  "evmwhsmia %0,%1,%2"
1551 
  [(set_attr "type" "veccomplex")
1552 
   (set_attr  "length" "4")])
1553 
 
1554 
(define_insn "spe_evmwhsmi"
1555 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1556 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1557 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))]
1558 
  "TARGET_SPE"
1559 
  "evmwhsmi %0,%1,%2"
1560 
  [(set_attr "type" "veccomplex")
1561 
   (set_attr  "length" "4")])
1562 
 
1563 
(define_insn "spe_evmwhssfa"
1564 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1565 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1566 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615))
1567 
   (clobber (reg:SI SPEFSCR_REGNO))
1568 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1569 
  "TARGET_SPE"
1570 
  "evmwhssfa %0,%1,%2"
1571 
  [(set_attr "type" "veccomplex")
1572 
   (set_attr  "length" "4")])
1573 
 
1574 
(define_insn "spe_evmwhusian"
1575 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1576 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1577 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))]
1578 
  "TARGET_SPE"
1579 
  "evmwhusian %0,%1,%2"
1580 
  [(set_attr "type" "veccomplex")
1581 
   (set_attr  "length" "4")])
1582 
 
1583 
(define_insn "spe_evmwhssf"
1584 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1585 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1586 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628))
1587 
   (clobber (reg:SI SPEFSCR_REGNO))]
1588 
  "TARGET_SPE"
1589 
  "evmwhssf %0,%1,%2"
1590 
  [(set_attr "type" "veccomplex")
1591 
   (set_attr  "length" "4")])
1592 
 
1593 
(define_insn "spe_evmwhumia"
1594 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1595 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1596 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629))
1597 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1598 
  "TARGET_SPE"
1599 
  "evmwhumia %0,%1,%2"
1600 
  [(set_attr "type" "veccomplex")
1601 
   (set_attr  "length" "4")])
1602 
 
1603 
(define_insn "spe_evmwhumi"
1604 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1605 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1606 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))]
1607 
  "TARGET_SPE"
1608 
  "evmwhumi %0,%1,%2"
1609 
  [(set_attr "type" "veccomplex")
1610 
   (set_attr  "length" "4")])
1611 
 
1612 
(define_insn "spe_evmwlsmiaaw"
1613 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1614 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1615 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1616 
                      (reg:V2SI SPE_ACC_REGNO)] 635))
1617 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1618 
  "TARGET_SPE"
1619 
  "evmwlsmiaaw %0,%1,%2"
1620 
  [(set_attr "type" "veccomplex")
1621 
   (set_attr  "length" "4")])
1622 
 
1623 
(define_insn "spe_evmwlsmianw"
1624 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1625 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1626 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1627 
                      (reg:V2SI SPE_ACC_REGNO)] 636))
1628 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1629 
  "TARGET_SPE"
1630 
  "evmwlsmianw %0,%1,%2"
1631 
  [(set_attr "type" "veccomplex")
1632 
   (set_attr  "length" "4")])
1633 
 
1634 
(define_insn "spe_evmwlssiaaw"
1635 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1636 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1637 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1638 
                      (reg:V2SI SPE_ACC_REGNO)] 641))
1639 
   (clobber (reg:SI SPEFSCR_REGNO))
1640 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1641 
  "TARGET_SPE"
1642 
  "evmwlssiaaw %0,%1,%2"
1643 
  [(set_attr "type" "veccomplex")
1644 
   (set_attr  "length" "4")])
1645 
 
1646 
(define_insn "spe_evmwlssianw"
1647 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1648 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1649 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1650 
                      (reg:V2SI SPE_ACC_REGNO)] 642))
1651 
   (clobber (reg:SI SPEFSCR_REGNO))
1652 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1653 
  "TARGET_SPE"
1654 
  "evmwlssianw %0,%1,%2"
1655 
  [(set_attr "type" "veccomplex")
1656 
   (set_attr  "length" "4")])
1657 
 
1658 
(define_insn "spe_evmwlumiaaw"
1659 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1660 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1661 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1662 
                      (reg:V2SI SPE_ACC_REGNO)] 643))
1663 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1664 
  "TARGET_SPE"
1665 
  "evmwlumiaaw %0,%1,%2"
1666 
  [(set_attr "type" "veccomplex")
1667 
   (set_attr  "length" "4")])
1668 
 
1669 
(define_insn "spe_evmwlumianw"
1670 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1671 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1672 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1673 
                      (reg:V2SI SPE_ACC_REGNO)] 644))
1674 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1675 
  "TARGET_SPE"
1676 
  "evmwlumianw %0,%1,%2"
1677 
  [(set_attr "type" "veccomplex")
1678 
   (set_attr  "length" "4")])
1679 
 
1680 
(define_insn "spe_evmwlumia"
1681 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1682 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1683 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645))
1684 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1685 
  "TARGET_SPE"
1686 
  "evmwlumia %0,%1,%2"
1687 
  [(set_attr "type" "veccomplex")
1688 
   (set_attr  "length" "4")])
1689 
 
1690 
(define_insn "spe_evmwlumi"
1691 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1692 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1693 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))]
1694 
  "TARGET_SPE"
1695 
  "evmwlumi %0,%1,%2"
1696 
  [(set_attr "type" "veccomplex")
1697 
   (set_attr  "length" "4")])
1698 
 
1699 
(define_insn "spe_evmwlusiaaw"
1700 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1701 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1702 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1703 
                      (reg:V2SI SPE_ACC_REGNO)] 647))
1704 
   (clobber (reg:SI SPEFSCR_REGNO))
1705 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1706 
  "TARGET_SPE"
1707 
  "evmwlusiaaw %0,%1,%2"
1708 
  [(set_attr "type" "veccomplex")
1709 
   (set_attr  "length" "4")])
1710 
 
1711 
(define_insn "spe_evmwlusianw"
1712 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1713 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1714 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1715 
                      (reg:V2SI SPE_ACC_REGNO)] 648))
1716 
   (clobber (reg:SI SPEFSCR_REGNO))
1717 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1718 
  "TARGET_SPE"
1719 
  "evmwlusianw %0,%1,%2"
1720 
  [(set_attr "type" "veccomplex")
1721 
   (set_attr  "length" "4")])
1722 
 
1723 
(define_insn "spe_evmwsmfaa"
1724 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1725 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1726 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1727 
                      (reg:V2SI SPE_ACC_REGNO)] 649))
1728 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1729 
  "TARGET_SPE"
1730 
  "evmwsmfaa %0,%1,%2"
1731 
  [(set_attr "type" "veccomplex")
1732 
   (set_attr  "length" "4")])
1733 
 
1734 
(define_insn "spe_evmwsmfan"
1735 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1736 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1737 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1738 
                      (reg:V2SI SPE_ACC_REGNO)] 650))
1739 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1740 
  "TARGET_SPE"
1741 
  "evmwsmfan %0,%1,%2"
1742 
  [(set_attr "type" "veccomplex")
1743 
   (set_attr  "length" "4")])
1744 
 
1745 
(define_insn "spe_evmwsmfa"
1746 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1747 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1748 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651))
1749 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1750 
  "TARGET_SPE"
1751 
  "evmwsmfa %0,%1,%2"
1752 
  [(set_attr "type" "veccomplex")
1753 
   (set_attr  "length" "4")])
1754 
 
1755 
(define_insn "spe_evmwsmf"
1756 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1757 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1758 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))]
1759 
  "TARGET_SPE"
1760 
  "evmwsmf %0,%1,%2"
1761 
  [(set_attr "type" "veccomplex")
1762 
   (set_attr  "length" "4")])
1763 
 
1764 
(define_insn "spe_evmwsmiaa"
1765 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1766 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1767 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1768 
                      (reg:V2SI SPE_ACC_REGNO)] 653))
1769 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1770 
  "TARGET_SPE"
1771 
  "evmwsmiaa %0,%1,%2"
1772 
  [(set_attr "type" "veccomplex")
1773 
   (set_attr  "length" "4")])
1774 
 
1775 
(define_insn "spe_evmwsmian"
1776 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1777 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1778 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1779 
                      (reg:V2SI SPE_ACC_REGNO)] 654))
1780 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1781 
  "TARGET_SPE"
1782 
  "evmwsmian %0,%1,%2"
1783 
  [(set_attr "type" "veccomplex")
1784 
   (set_attr  "length" "4")])
1785 
 
1786 
(define_insn "spe_evmwsmia"
1787 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1788 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1789 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655))
1790 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1791 
  "TARGET_SPE"
1792 
  "evmwsmia %0,%1,%2"
1793 
  [(set_attr "type" "veccomplex")
1794 
   (set_attr  "length" "4")])
1795 
 
1796 
(define_insn "spe_evmwsmi"
1797 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1798 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1799 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))]
1800 
  "TARGET_SPE"
1801 
  "evmwsmi %0,%1,%2"
1802 
  [(set_attr "type" "veccomplex")
1803 
   (set_attr  "length" "4")])
1804 
 
1805 
(define_insn "spe_evmwssfaa"
1806 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1807 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1808 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1809 
                      (reg:V2SI SPE_ACC_REGNO)] 657))
1810 
   (clobber (reg:SI SPEFSCR_REGNO))
1811 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1812 
  "TARGET_SPE"
1813 
  "evmwssfaa %0,%1,%2"
1814 
  [(set_attr "type" "veccomplex")
1815 
   (set_attr  "length" "4")])
1816 
 
1817 
(define_insn "spe_evmwssfan"
1818 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1819 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1820 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1821 
                      (reg:V2SI SPE_ACC_REGNO)] 658))
1822 
   (clobber (reg:SI SPEFSCR_REGNO))
1823 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1824 
  "TARGET_SPE"
1825 
  "evmwssfan %0,%1,%2"
1826 
  [(set_attr "type" "veccomplex")
1827 
   (set_attr  "length" "4")])
1828 
 
1829 
(define_insn "spe_evmwssfa"
1830 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1831 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1832 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659))
1833 
   (clobber (reg:SI SPEFSCR_REGNO))
1834 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1835 
  "TARGET_SPE"
1836 
  "evmwssfa %0,%1,%2"
1837 
  [(set_attr "type" "veccomplex")
1838 
   (set_attr  "length" "4")])
1839 
 
1840 
(define_insn "spe_evmwssf"
1841 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1842 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1843 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660))
1844 
   (clobber (reg:SI SPEFSCR_REGNO))]
1845 
  "TARGET_SPE"
1846 
  "evmwssf %0,%1,%2"
1847 
  [(set_attr "type" "veccomplex")
1848 
   (set_attr  "length" "4")])
1849 
 
1850 
(define_insn "spe_evmwumiaa"
1851 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1852 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1853 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1854 
                      (reg:V2SI SPE_ACC_REGNO)] 661))
1855 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1856 
  "TARGET_SPE"
1857 
  "evmwumiaa %0,%1,%2"
1858 
  [(set_attr "type" "veccomplex")
1859 
   (set_attr  "length" "4")])
1860 
 
1861 
(define_insn "spe_evmwumian"
1862 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1863 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1864 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1865 
                      (reg:V2SI SPE_ACC_REGNO)] 662))
1866 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1867 
  "TARGET_SPE"
1868 
  "evmwumian %0,%1,%2"
1869 
  [(set_attr "type" "veccomplex")
1870 
   (set_attr  "length" "4")])
1871 
 
1872 
(define_insn "spe_evmwumia"
1873 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1874 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1875 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663))
1876 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1877 
  "TARGET_SPE"
1878 
  "evmwumia %0,%1,%2"
1879 
  [(set_attr "type" "veccomplex")
1880 
   (set_attr  "length" "4")])
1881 
 
1882 
(define_insn "spe_evmwumi"
1883 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1884 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1885 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))]
1886 
  "TARGET_SPE"
1887 
  "evmwumi %0,%1,%2"
1888 
  [(set_attr "type" "veccomplex")
1889 
   (set_attr  "length" "4")])
1890 
 
1891 
(define_insn "spe_evaddw"
1892 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1893 
        (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1894 
                   (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1895 
  "TARGET_SPE"
1896 
  "evaddw %0,%1,%2"
1897 
  [(set_attr "type" "vecsimple")
1898 
   (set_attr  "length" "4")])
1899 
 
1900 
(define_insn "spe_evaddusiaaw"
1901 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1902 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1903 
                      (reg:V2SI SPE_ACC_REGNO)] 673))
1904 
   (clobber (reg:SI SPEFSCR_REGNO))
1905 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1906 
  "TARGET_SPE"
1907 
  "evaddusiaaw %0,%1"
1908 
  [(set_attr "type" "veccomplex")
1909 
   (set_attr  "length" "4")])
1910 
 
1911 
(define_insn "spe_evaddumiaaw"
1912 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1913 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1914 
                      (reg:V2SI SPE_ACC_REGNO)] 674))
1915 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1916 
  "TARGET_SPE"
1917 
  "evaddumiaaw %0,%1"
1918 
  [(set_attr "type" "veccomplex")
1919 
   (set_attr  "length" "4")])
1920 
 
1921 
(define_insn "spe_evaddssiaaw"
1922 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1923 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1924 
                      (reg:V2SI SPE_ACC_REGNO)] 675))
1925 
   (clobber (reg:SI SPEFSCR_REGNO))
1926 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1927 
  "TARGET_SPE"
1928 
  "evaddssiaaw %0,%1"
1929 
  [(set_attr "type" "veccomplex")
1930 
   (set_attr  "length" "4")])
1931 
 
1932 
(define_insn "spe_evaddsmiaaw"
1933 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1934 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1935 
                      (reg:V2SI SPE_ACC_REGNO)] 676))
1936 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1937 
  "TARGET_SPE"
1938 
  "evaddsmiaaw %0,%1"
1939 
  [(set_attr "type" "veccomplex")
1940 
   (set_attr  "length" "4")])
1941 
 
1942 
(define_insn "spe_evaddiw"
1943 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1944 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1945 
                      (match_operand:QI 2 "immediate_operand" "i")] 677))]
1946 
  "TARGET_SPE"
1947 
  "evaddiw %0,%1,%2"
1948 
  [(set_attr "type" "vecsimple")
1949 
   (set_attr  "length" "4")])
1950 
 
1951 
(define_insn "spe_evsubifw"
1952 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1953 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1954 
                      (match_operand:QI 2 "immediate_operand" "i")] 678))]
1955 
  "TARGET_SPE"
1956 
  "evsubifw %0,%2,%1"
1957 
  [(set_attr "type" "veccomplex")
1958 
   (set_attr  "length" "4")])
1959 
 
1960 
(define_insn "spe_evsubfw"
1961 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1962 
        (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1963 
                    (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1964 
  "TARGET_SPE"
1965 
  "evsubfw %0,%2,%1"
1966 
  [(set_attr "type" "veccomplex")
1967 
   (set_attr  "length" "4")])
1968 
 
1969 
(define_insn "spe_evsubfusiaaw"
1970 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1971 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1972 
                      (reg:V2SI SPE_ACC_REGNO)] 679))
1973 
   (clobber (reg:SI SPEFSCR_REGNO))
1974 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1975 
  "TARGET_SPE"
1976 
  "evsubfusiaaw %0,%1"
1977 
  [(set_attr "type" "veccomplex")
1978 
   (set_attr  "length" "4")])
1979 
 
1980 
(define_insn "spe_evsubfumiaaw"
1981 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1982 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1983 
                      (reg:V2SI SPE_ACC_REGNO)] 680))
1984 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1985 
  "TARGET_SPE"
1986 
  "evsubfumiaaw %0,%1"
1987 
  [(set_attr "type" "veccomplex")
1988 
   (set_attr  "length" "4")])
1989 
 
1990 
(define_insn "spe_evsubfssiaaw"
1991 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1992 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1993 
                      (reg:V2SI SPE_ACC_REGNO)] 681))
1994 
   (clobber (reg:SI SPEFSCR_REGNO))
1995 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1996 
  "TARGET_SPE"
1997 
  "evsubfssiaaw %0,%1"
1998 
  [(set_attr "type" "veccomplex")
1999 
   (set_attr  "length" "4")])
2000 
 
2001 
(define_insn "spe_evsubfsmiaaw"
2002 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2003 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2004 
                      (reg:V2SI SPE_ACC_REGNO)] 682))
2005 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2006 
  "TARGET_SPE"
2007 
  "evsubfsmiaaw %0,%1"
2008 
  [(set_attr "type" "veccomplex")
2009 
   (set_attr  "length" "4")])
2010 
 
2011 
(define_insn "spe_evmra"
2012 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2013 
        (match_operand:V2SI 1 "gpc_reg_operand" "r"))
2014 
   (set (reg:V2SI SPE_ACC_REGNO)
2015 
        (unspec:V2SI [(match_dup 1)] 726))]
2016 
  "TARGET_SPE"
2017 
  "evmra %0,%1"
2018 
  [(set_attr "type" "veccomplex")
2019 
   (set_attr  "length" "4")])
2020 
 
2021 
(define_insn "spe_evdivws"
2022 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2023 
        (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2024 
                  (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2025 
   (clobber (reg:SI SPEFSCR_REGNO))]
2026 
  "TARGET_SPE"
2027 
  "evdivws %0,%1,%2"
2028 
  [(set_attr "type" "vecdiv")
2029 
   (set_attr  "length" "4")])
2030 
 
2031 
(define_insn "spe_evdivwu"
2032 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2033 
        (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2034 
                   (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2035 
      (clobber (reg:SI SPEFSCR_REGNO))]
2036 
  "TARGET_SPE"
2037 
  "evdivwu %0,%1,%2"
2038 
  [(set_attr "type" "vecdiv")
2039 
   (set_attr  "length" "4")])
2040 
 
2041 
(define_insn "spe_evsplatfi"
2042 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2043 
        (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
2044 
  "TARGET_SPE"
2045 
  "evsplatfi %0,%1"
2046 
  [(set_attr "type" "vecperm")
2047 
   (set_attr  "length" "4")])
2048 
 
2049 
(define_insn "spe_evsplati"
2050 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2051 
        (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
2052 
  "TARGET_SPE"
2053 
  "evsplati %0,%1"
2054 
  [(set_attr "type" "vecperm")
2055 
   (set_attr  "length" "4")])
2056 
 
2057 
(define_insn "spe_evstdd"
2058 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2059 
                           (match_operand:QI 1 "immediate_operand" "i")))
2060 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2061 
   (unspec [(const_int 0)] 686)]
2062 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2063 
  "evstdd %2,%1*8(%0)"
2064 
  [(set_attr "type" "vecstore")
2065 
   (set_attr  "length" "4")])
2066 
 
2067 
(define_insn "spe_evstddx"
2068 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2069 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2070 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2071 
   (unspec [(const_int 0)] 687)]
2072 
  "TARGET_SPE"
2073 
  "evstddx %2,%0,%1"
2074 
  [(set_attr "type" "vecstore")
2075 
   (set_attr  "length" "4")])
2076 
 
2077 
(define_insn "spe_evstdh"
2078 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2079 
                           (match_operand:QI 1 "immediate_operand" "i")))
2080 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2081 
   (unspec [(const_int 0)] 688)]
2082 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2083 
  "evstdh %2,%1*8(%0)"
2084 
  [(set_attr "type" "vecstore")
2085 
   (set_attr  "length" "4")])
2086 
 
2087 
(define_insn "spe_evstdhx"
2088 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2089 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2090 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2091 
   (unspec [(const_int 0)] 689)]
2092 
  "TARGET_SPE"
2093 
  "evstdhx %2,%0,%1"
2094 
  [(set_attr "type" "vecstore")
2095 
   (set_attr  "length" "4")])
2096 
 
2097 
(define_insn "spe_evstdw"
2098 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2099 
                           (match_operand:QI 1 "immediate_operand" "i")))
2100 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2101 
   (unspec [(const_int 0)] 690)]
2102 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2103 
  "evstdw %2,%1*8(%0)"
2104 
  [(set_attr "type" "vecstore")
2105 
   (set_attr  "length" "4")])
2106 
 
2107 
(define_insn "spe_evstdwx"
2108 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2109 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2110 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2111 
   (unspec [(const_int 0)] 691)]
2112 
  "TARGET_SPE"
2113 
  "evstdwx %2,%0,%1"
2114 
  [(set_attr "type" "vecstore")
2115 
   (set_attr  "length" "4")])
2116 
 
2117 
(define_insn "spe_evstwhe"
2118 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2119 
                           (match_operand:QI 1 "immediate_operand" "i")))
2120 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2121 
   (unspec [(const_int 0)] 692)]
2122 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2123 
  "evstwhe %2,%1*4(%0)"
2124 
  [(set_attr "type" "vecstore")
2125 
   (set_attr  "length" "4")])
2126 
 
2127 
(define_insn "spe_evstwhex"
2128 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2129 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2130 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2131 
   (unspec [(const_int 0)] 693)]
2132 
  "TARGET_SPE"
2133 
  "evstwhex %2,%0,%1"
2134 
  [(set_attr "type" "vecstore")
2135 
   (set_attr  "length" "4")])
2136 
 
2137 
(define_insn "spe_evstwho"
2138 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2139 
                           (match_operand:QI 1 "immediate_operand" "i")))
2140 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2141 
   (unspec [(const_int 0)] 694)]
2142 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2143 
  "evstwho %2,%1*4(%0)"
2144 
  [(set_attr "type" "vecstore")
2145 
   (set_attr  "length" "4")])
2146 
 
2147 
(define_insn "spe_evstwhox"
2148 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2149 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2150 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2151 
   (unspec [(const_int 0)] 695)]
2152 
  "TARGET_SPE"
2153 
  "evstwhox %2,%0,%1"
2154 
  [(set_attr "type" "vecstore")
2155 
   (set_attr  "length" "4")])
2156 
 
2157 
(define_insn "spe_evstwwe"
2158 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2159 
                           (match_operand:QI 1 "immediate_operand" "i")))
2160 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2161 
   (unspec [(const_int 0)] 696)]
2162 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2163 
  "evstwwe %2,%1*4(%0)"
2164 
  [(set_attr "type" "vecstore")
2165 
   (set_attr  "length" "4")])
2166 
 
2167 
(define_insn "spe_evstwwex"
2168 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2169 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2170 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2171 
   (unspec [(const_int 0)] 697)]
2172 
  "TARGET_SPE"
2173 
  "evstwwex %2,%0,%1"
2174 
  [(set_attr "type" "vecstore")
2175 
   (set_attr  "length" "4")])
2176 
 
2177 
(define_insn "spe_evstwwo"
2178 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2179 
                           (match_operand:QI 1 "immediate_operand" "i")))
2180 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2181 
   (unspec [(const_int 0)] 698)]
2182 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2183 
  "evstwwo %2,%1*4(%0)"
2184 
  [(set_attr "type" "vecstore")
2185 
   (set_attr  "length" "4")])
2186 
 
2187 
(define_insn "spe_evstwwox"
2188 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2189 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2190 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2191 
   (unspec [(const_int 0)] 699)]
2192 
  "TARGET_SPE"
2193 
  "evstwwox %2,%0,%1"
2194 
  [(set_attr "type" "vecstore")
2195 
   (set_attr  "length" "4")])
2196 
 
2197 
;; Double-precision floating point instructions.
2198 
 
2199 
;; FIXME: Add o=r option.
2200 
(define_insn "*frob_df_di"
2201 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r")
2202 
        (subreg:DF (match_operand:DI 1 "input_operand" "r,m") 0))]
2203 
  "TARGET_E500_DOUBLE"
2204 
  "@
2205 
   evmergelo %0,%1,%L1
2206 
   evldd%X1 %0,%y1")
2207 
 
2208 
(define_insn "*frob_di_df"
2209 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
2210 
        (subreg:DI (match_operand:DF 1 "input_operand" "r") 0))]
2211 
  "TARGET_E500_DOUBLE"
2212 
  "evmergehi %0,%1,%1\;mr %L0,%1"
2213 
  [(set_attr "length" "8")])
2214 
 
2215 
(define_insn "*frob_di_df_2"
2216 
  [(set (subreg:DF (match_operand:DI 0 "register_operand" "=&r,r") 0)
2217 
        (match_operand:DF 1 "input_operand" "r,m"))]
2218 
  "TARGET_E500_DOUBLE"
2219 
  "*
2220 
{
2221 
  switch (which_alternative)
2222 
    {
2223 
    default:
2224 
      gcc_unreachable ();
2225 
    case 0:
2226 
      return \"evmergehi %0,%1,%1\;mr %L0,%1\";
2227 
    case 1:
2228 
      /* If the address is not offsettable we need to load the whole
2229 
         doubleword into a 64-bit register and then copy the high word
2230 
         to form the correct output layout.  */
2231 
      if (!offsettable_nonstrict_memref_p (operands[1]))
2232 
        return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\";
2233 
      /* If the low-address word is used in the address, we must load
2234 
        it last.  Otherwise, load it first.  Note that we cannot have
2235 
        auto-increment in that case since the address register is
2236 
        known to be dead.  */
2237 
      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2238 
                             operands[1], 0))
2239 
        return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
2240 
      else
2241 
        return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
2242 
    }
2243 
}"
2244 
  [(set_attr "length" "8,8")])
2245 
 
2246 
(define_insn "*mov_si_e500_subreg0"
2247 
  [(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,&r") 0)
2248 
        (match_operand:SI 1 "input_operand" "r,m"))]
2249 
  "(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
2250 
  "@
2251 
   evmergelo %0,%1,%0
2252 
   evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0")
2253 
 
2254 
;; ??? Could use evstwwe for memory stores in some cases, depending on
2255 
;; the offset.
2256 
(define_insn "*mov_si_e500_subreg0_2"
2257 
  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2258 
        (subreg:SI (match_operand:SPE64 1 "register_operand" "+r,&r") 0))]
2259 
  "(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
2260 
  "@
2261 
   evmergehi %0,%0,%1
2262 
   evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0")
2263 
 
2264 
(define_insn "*mov_si_e500_subreg4"
2265 
  [(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,r") 4)
2266 
        (match_operand:SI 1 "input_operand" "r,m"))]
2267 
  "(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
2268 
  "@
2269 
   mr %0,%1
2270 
   {l%U1%X1|lwz%U1%X1} %0,%1")
2271 
 
2272 
(define_insn "*mov_si_e500_subreg4_2"
2273 
  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2274 
        (subreg:SI (match_operand:SPE64 1 "register_operand" "r,r") 4))]
2275 
  "(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
2276 
  "@
2277 
   mr %0,%1
2278 
   {st%U0%X0|stw%U0%X0} %1,%0")
2279 
 
2280 
;; FIXME: Allow r=CONST0.
2281 
(define_insn "*movdf_e500_double"
2282 
  [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m")
2283 
        (match_operand:DF 1 "input_operand" "r,m,r"))]
2284 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
2285 
    && (gpc_reg_operand (operands[0], DFmode)
2286 
        || gpc_reg_operand (operands[1], DFmode))"
2287 
  "*
2288 
 {
2289 
   switch (which_alternative)
2290 
     {
2291 
     case 0:
2292 
       return \"evor %0,%1,%1\";
2293 
     case 1:
2294 
       return \"evldd%X1 %0,%y1\";
2295 
     case 2:
2296 
       return \"evstdd%X0 %1,%y0\";
2297 
     default:
2298 
       gcc_unreachable ();
2299 
     }
2300 
 }"
2301 
  [(set_attr "type" "*,vecload,vecstore")
2302 
   (set_attr "length" "*,*,*")])
2303 
 
2304 
(define_insn "spe_truncdfsf2"
2305 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
2306 
        (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2307 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2308 
  "efscfd %0,%1")
2309 
 
2310 
(define_insn "spe_absdf2"
2311 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2312 
        (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2313 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2314 
  "efdabs %0,%1")
2315 
 
2316 
(define_insn "spe_nabsdf2"
2317 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2318 
        (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
2319 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2320 
  "efdnabs %0,%1")
2321 
 
2322 
(define_insn "spe_negdf2"
2323 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2324 
        (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2325 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2326 
  "efdneg %0,%1")
2327 
 
2328 
(define_insn "spe_adddf3"
2329 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2330 
        (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2331 
                 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2332 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2333 
  "efdadd %0,%1,%2")
2334 
 
2335 
(define_insn "spe_subdf3"
2336 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2337 
        (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2338 
                  (match_operand:DF 2 "gpc_reg_operand" "r")))]
2339 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2340 
  "efdsub %0,%1,%2")
2341 
 
2342 
(define_insn "spe_muldf3"
2343 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2344 
        (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2345 
                 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2346 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2347 
  "efdmul %0,%1,%2")
2348 
 
2349 
(define_insn "spe_divdf3"
2350 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2351 
        (div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2352 
                (match_operand:DF 2 "gpc_reg_operand" "r")))]
2353 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2354 
  "efddiv %0,%1,%2")
2355 
 
2356 
;; Vector move instructions.
2357 
 
2358 
(define_expand "movv2si"
2359 
  [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
2360 
        (match_operand:V2SI 1 "any_operand" ""))]
2361 
  "TARGET_SPE"
2362 
  "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }")
2363 
 
2364 
(define_insn "*movv2si_internal"
2365 
  [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
2366 
        (match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
2367 
  "TARGET_SPE
2368 
   && (gpc_reg_operand (operands[0], V2SImode)
2369 
       || gpc_reg_operand (operands[1], V2SImode))"
2370 
  "*
2371 
{
2372 
  switch (which_alternative)
2373 
    {
2374 
    case 0: return \"evstdd%X0 %1,%y0\";
2375 
    case 1: return \"evldd%X1 %0,%y1\";
2376 
    case 2: return \"evor %0,%1,%1\";
2377 
    case 3: return output_vec_const_move (operands);
2378 
    default: gcc_unreachable ();
2379 
    }
2380 
}"
2381 
  [(set_attr "type" "vecload,vecstore,*,*")
2382 
   (set_attr "length" "*,*,*,12")])
2383 
 
2384 
(define_split
2385 
  [(set (match_operand:V2SI 0 "register_operand" "")
2386 
        (match_operand:V2SI 1 "zero_constant" ""))]
2387 
  "TARGET_SPE && reload_completed"
2388 
  [(set (match_dup 0)
2389 
        (xor:V2SI (match_dup 0) (match_dup 0)))]
2390 
  "")
2391 
 
2392 
(define_expand "movv1di"
2393 
  [(set (match_operand:V1DI 0 "nonimmediate_operand" "")
2394 
        (match_operand:V1DI 1 "any_operand" ""))]
2395 
  "TARGET_SPE"
2396 
  "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }")
2397 
 
2398 
(define_insn "*movv1di_internal"
2399 
  [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
2400 
        (match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
2401 
  "TARGET_SPE
2402 
   && (gpc_reg_operand (operands[0], V1DImode)
2403 
       || gpc_reg_operand (operands[1], V1DImode))"
2404 
  "@
2405 
   evstdd%X0 %1,%y0
2406 
   evldd%X1 %0,%y1
2407 
   evor %0,%1,%1
2408 
   evxor %0,%0,%0"
2409 
  [(set_attr "type" "vecload,vecstore,*,*")
2410 
   (set_attr "length" "*,*,*,*")])
2411 
 
2412 
(define_expand "movv4hi"
2413 
  [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
2414 
        (match_operand:V4HI 1 "any_operand" ""))]
2415 
  "TARGET_SPE"
2416 
  "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }")
2417 
 
2418 
(define_insn "*movv4hi_internal"
2419 
  [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r")
2420 
        (match_operand:V4HI 1 "input_operand" "r,m,r,W"))]
2421 
  "TARGET_SPE
2422 
   && (gpc_reg_operand (operands[0], V4HImode)
2423 
       || gpc_reg_operand (operands[1], V4HImode))"
2424 
  "@
2425 
   evstdd%X0 %1,%y0
2426 
   evldd%X1 %0,%y1
2427 
   evor %0,%1,%1
2428 
   evxor %0,%0,%0"
2429 
  [(set_attr "type" "vecload")])
2430 
 
2431 
(define_expand "movv2sf"
2432 
  [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
2433 
        (match_operand:V2SF 1 "any_operand" ""))]
2434 
  "TARGET_SPE"
2435 
  "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }")
2436 
 
2437 
(define_insn "*movv2sf_internal"
2438 
  [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
2439 
        (match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
2440 
  "TARGET_SPE
2441 
   && (gpc_reg_operand (operands[0], V2SFmode)
2442 
       || gpc_reg_operand (operands[1], V2SFmode))"
2443 
  "@
2444 
   evstdd%X0 %1,%y0
2445 
   evldd%X1 %0,%y1
2446 
   evor %0,%1,%1
2447 
   evxor %0,%0,%0"
2448 
  [(set_attr "type" "vecload,vecstore,*,*")
2449 
   (set_attr "length" "*,*,*,*")])
2450 
 
2451 
;; End of vector move instructions.
2452 
 
2453 
(define_insn "spe_evmwhssfaa"
2454 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2455 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2456 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702))
2457 
   (clobber (reg:SI SPEFSCR_REGNO))
2458 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2459 
  "TARGET_SPE"
2460 
  "evmwhssfaa %0,%1,%2"
2461 
  [(set_attr "type" "veccomplex")
2462 
   (set_attr  "length" "4")])
2463 
 
2464 
(define_insn "spe_evmwhssmaa"
2465 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2466 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2467 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703))
2468 
   (clobber (reg:SI SPEFSCR_REGNO))
2469 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2470 
  "TARGET_SPE"
2471 
  "evmwhssmaa %0,%1,%2"
2472 
  [(set_attr "type" "veccomplex")
2473 
   (set_attr  "length" "4")])
2474 
 
2475 
(define_insn "spe_evmwhsmfaa"
2476 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2477 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2478 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704))
2479 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2480 
  "TARGET_SPE"
2481 
  "evmwhsmfaa %0,%1,%2"
2482 
  [(set_attr "type" "veccomplex")
2483 
   (set_attr  "length" "4")])
2484 
 
2485 
(define_insn "spe_evmwhsmiaa"
2486 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2487 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2488 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705))
2489 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2490 
  "TARGET_SPE"
2491 
  "evmwhsmiaa %0,%1,%2"
2492 
  [(set_attr "type" "veccomplex")
2493 
   (set_attr  "length" "4")])
2494 
 
2495 
(define_insn "spe_evmwhusiaa"
2496 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2497 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2498 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706))
2499 
   (clobber (reg:SI SPEFSCR_REGNO))
2500 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2501 
  "TARGET_SPE"
2502 
  "evmwhusiaa %0,%1,%2"
2503 
  [(set_attr "type" "veccomplex")
2504 
   (set_attr  "length" "4")])
2505 
 
2506 
(define_insn "spe_evmwhumiaa"
2507 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2508 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2509 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707))
2510 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2511 
  "TARGET_SPE"
2512 
  "evmwhumiaa %0,%1,%2"
2513 
  [(set_attr "type" "veccomplex")
2514 
   (set_attr  "length" "4")])
2515 
 
2516 
(define_insn "spe_evmwhssfan"
2517 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2518 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2519 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708))
2520 
   (clobber (reg:SI SPEFSCR_REGNO))
2521 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2522 
  "TARGET_SPE"
2523 
  "evmwhssfan %0,%1,%2"
2524 
  [(set_attr "type" "veccomplex")
2525 
   (set_attr  "length" "4")])
2526 
 
2527 
(define_insn "spe_evmwhssian"
2528 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2529 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2530 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709))
2531 
   (clobber (reg:SI SPEFSCR_REGNO))
2532 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2533 
  "TARGET_SPE"
2534 
  "evmwhssian %0,%1,%2"
2535 
  [(set_attr "type" "veccomplex")
2536 
   (set_attr  "length" "4")])
2537 
 
2538 
(define_insn "spe_evmwhsmfan"
2539 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2540 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2541 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710))
2542 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2543 
  "TARGET_SPE"
2544 
  "evmwhsmfan %0,%1,%2"
2545 
  [(set_attr "type" "veccomplex")
2546 
   (set_attr  "length" "4")])
2547 
 
2548 
(define_insn "spe_evmwhsmian"
2549 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2550 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2551 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711))
2552 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2553 
  "TARGET_SPE"
2554 
  "evmwhsmian %0,%1,%2"
2555 
  [(set_attr "type" "veccomplex")
2556 
   (set_attr  "length" "4")])
2557 
 
2558 
(define_insn "spe_evmwhumian"
2559 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2560 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2561 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713))
2562 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2563 
  "TARGET_SPE"
2564 
  "evmwhumian %0,%1,%2"
2565 
  [(set_attr "type" "veccomplex")
2566 
   (set_attr  "length" "4")])
2567 
 
2568 
(define_insn "spe_evmwhgssfaa"
2569 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2570 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2571 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714))
2572 
   (clobber (reg:SI SPEFSCR_REGNO))
2573 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2574 
  "TARGET_SPE"
2575 
  "evmwhgssfaa %0,%1,%2"
2576 
  [(set_attr "type" "veccomplex")
2577 
   (set_attr  "length" "4")])
2578 
 
2579 
(define_insn "spe_evmwhgsmfaa"
2580 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2581 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2582 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715))
2583 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2584 
  "TARGET_SPE"
2585 
  "evmwhgsmfaa %0,%1,%2"
2586 
  [(set_attr "type" "veccomplex")
2587 
   (set_attr  "length" "4")])
2588 
 
2589 
(define_insn "spe_evmwhgsmiaa"
2590 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2591 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2592 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716))
2593 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2594 
  "TARGET_SPE"
2595 
  "evmwhgsmiaa %0,%1,%2"
2596 
  [(set_attr "type" "veccomplex")
2597 
   (set_attr  "length" "4")])
2598 
 
2599 
(define_insn "spe_evmwhgumiaa"
2600 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2601 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2602 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717))
2603 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2604 
  "TARGET_SPE"
2605 
  "evmwhgumiaa %0,%1,%2"
2606 
  [(set_attr "type" "veccomplex")
2607 
   (set_attr  "length" "4")])
2608 
 
2609 
(define_insn "spe_evmwhgssfan"
2610 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2611 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2612 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718))
2613 
   (clobber (reg:SI SPEFSCR_REGNO))
2614 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2615 
  "TARGET_SPE"
2616 
  "evmwhgssfan %0,%1,%2"
2617 
  [(set_attr "type" "veccomplex")
2618 
   (set_attr  "length" "4")])
2619 
 
2620 
(define_insn "spe_evmwhgsmfan"
2621 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2622 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2623 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719))
2624 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2625 
  "TARGET_SPE"
2626 
  "evmwhgsmfan %0,%1,%2"
2627 
  [(set_attr "type" "veccomplex")
2628 
   (set_attr  "length" "4")])
2629 
 
2630 
(define_insn "spe_evmwhgsmian"
2631 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2632 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2633 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720))
2634 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2635 
  "TARGET_SPE"
2636 
  "evmwhgsmian %0,%1,%2"
2637 
  [(set_attr "type" "veccomplex")
2638 
   (set_attr  "length" "4")])
2639 
 
2640 
(define_insn "spe_evmwhgumian"
2641 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2642 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2643 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721))
2644 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2645 
  "TARGET_SPE"
2646 
  "evmwhgumian %0,%1,%2"
2647 
  [(set_attr "type" "veccomplex")
2648 
   (set_attr  "length" "4")])
2649 
 
2650 
(define_insn "spe_mtspefscr"
2651 
  [(set (reg:SI SPEFSCR_REGNO)
2652 
        (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2653 
                            722))]
2654 
  "TARGET_SPE"
2655 
  "mtspefscr %0"
2656 
  [(set_attr "type" "vecsimple")])
2657 
 
2658 
(define_insn "spe_mfspefscr"
2659 
  [(set (match_operand:SI 0 "register_operand" "=r")
2660 
        (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))]
2661 
  "TARGET_SPE"
2662 
  "mfspefscr %0"
2663 
  [(set_attr "type" "vecsimple")])
2664 
 
2665 
;; FP comparison stuff.
2666 
 
2667 
;; Flip the GT bit.
2668 
(define_insn "e500_flip_gt_bit"
2669 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2670 
        (unspec:CCFP
2671 
         [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
2672 
  "!TARGET_FPRS && TARGET_HARD_FLOAT"
2673 
  "*
2674 
{
2675 
  return output_e500_flip_gt_bit (operands[0], operands[1]);
2676 
}"
2677 
  [(set_attr "type" "cr_logical")])
2678 
 
2679 
;; MPC8540 single-precision FP instructions on GPRs.
2680 
;; We have 2 variants for each.  One for IEEE compliant math and one
2681 
;; for non IEEE compliant math.
2682 
 
2683 
(define_insn "cmpsfeq_gpr"
2684 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2685 
        (unspec:CCFP
2686 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2687 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2688 
         1000))]
2689 
  "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2690 
  "efscmpeq %0,%1,%2"
2691 
  [(set_attr "type" "veccmp")])
2692 
 
2693 
(define_insn "tstsfeq_gpr"
2694 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2695 
        (unspec:CCFP
2696 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2697 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2698 
         1001))]
2699 
  "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2700 
  "efststeq %0,%1,%2"
2701 
  [(set_attr "type" "veccmpsimple")])
2702 
 
2703 
(define_insn "cmpsfgt_gpr"
2704 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2705 
        (unspec:CCFP
2706 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2707 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2708 
         1002))]
2709 
  "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2710 
  "efscmpgt %0,%1,%2"
2711 
  [(set_attr "type" "veccmp")])
2712 
 
2713 
(define_insn "tstsfgt_gpr"
2714 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2715 
        (unspec:CCFP
2716 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2717 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2718 
         1003))]
2719 
  "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2720 
  "efststgt %0,%1,%2"
2721 
  [(set_attr "type" "veccmpsimple")])
2722 
 
2723 
(define_insn "cmpsflt_gpr"
2724 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2725 
        (unspec:CCFP
2726 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2727 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2728 
         1004))]
2729 
  "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2730 
  "efscmplt %0,%1,%2"
2731 
  [(set_attr "type" "veccmp")])
2732 
 
2733 
(define_insn "tstsflt_gpr"
2734 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2735 
        (unspec:CCFP
2736 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2737 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2738 
         1005))]
2739 
  "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2740 
  "efststlt %0,%1,%2"
2741 
  [(set_attr "type" "veccmpsimple")])
2742 
 
2743 
;; Same thing, but for double-precision.
2744 
 
2745 
(define_insn "cmpdfeq_gpr"
2746 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2747 
        (unspec:CCFP
2748 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2749 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
2750 
         CMPDFEQ_GPR))]
2751 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
2752 
  "efdcmpeq %0,%1,%2"
2753 
  [(set_attr "type" "veccmp")])
2754 
 
2755 
(define_insn "tstdfeq_gpr"
2756 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2757 
        (unspec:CCFP
2758 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2759 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
2760 
         TSTDFEQ_GPR))]
2761 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
2762 
  "efdtsteq %0,%1,%2"
2763 
  [(set_attr "type" "veccmpsimple")])
2764 
 
2765 
(define_insn "cmpdfgt_gpr"
2766 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2767 
        (unspec:CCFP
2768 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2769 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
2770 
         CMPDFGT_GPR))]
2771 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
2772 
  "efdcmpgt %0,%1,%2"
2773 
  [(set_attr "type" "veccmp")])
2774 
 
2775 
(define_insn "tstdfgt_gpr"
2776 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2777 
        (unspec:CCFP
2778 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2779 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
2780 
         TSTDFGT_GPR))]
2781 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
2782 
  "efdtstgt %0,%1,%2"
2783 
  [(set_attr "type" "veccmpsimple")])
2784 
 
2785 
(define_insn "cmpdflt_gpr"
2786 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2787 
        (unspec:CCFP
2788 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2789 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
2790 
         CMPDFLT_GPR))]
2791 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
2792 
  "efdcmplt %0,%1,%2"
2793 
  [(set_attr "type" "veccmp")])
2794 
 
2795 
(define_insn "tstdflt_gpr"
2796 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2797 
        (unspec:CCFP
2798 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2799 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
2800 
         TSTDFLT_GPR))]
2801 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
2802 
  "efdtstlt %0,%1,%2"
2803 
  [(set_attr "type" "veccmpsimple")])
2804 
 
2805 
;; Like cceq_ior_compare, but compare the GT bits.
2806 
(define_insn "e500_cr_ior_compare"
2807 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2808 
        (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
2809 
                      (match_operand 2 "cc_reg_operand" "y")]
2810 
                     E500_CR_IOR_COMPARE))]
2811 
  "TARGET_E500"
2812 
  "cror 4*%0+gt,4*%1+gt,4*%2+gt"
2813 
  [(set_attr "type" "cr_logical")])

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