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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [sh/] [sh.h] - Blame information for rev 199

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1 38 julius
/* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2
   Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3
   2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
   Contributed by Steve Chamberlain (sac@cygnus.com).
5
   Improved by Jim Wilson (wilson@cygnus.com).
6
 
7
This file is part of GCC.
8
 
9
GCC is free software; you can redistribute it and/or modify
10
it under the terms of the GNU General Public License as published by
11
the Free Software Foundation; either version 3, or (at your option)
12
any later version.
13
 
14
GCC is distributed in the hope that it will be useful,
15
but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with GCC; see the file COPYING3.  If not see
21
<http://www.gnu.org/licenses/>.  */
22
 
23
#ifndef GCC_SH_H
24
#define GCC_SH_H
25
 
26
#define TARGET_VERSION \
27
  fputs (" (Hitachi SH)", stderr);
28
 
29
/* Unfortunately, insn-attrtab.c doesn't include insn-codes.h.  We can't
30
   include it here, because bconfig.h is also included by gencodes.c .  */
31
/* ??? No longer true.  */
32
extern int code_for_indirect_jump_scratch;
33
 
34
#define TARGET_CPU_CPP_BUILTINS() \
35
do { \
36
  builtin_define ("__sh__"); \
37
  builtin_assert ("cpu=sh"); \
38
  builtin_assert ("machine=sh"); \
39
  switch ((int) sh_cpu) \
40
    { \
41
    case PROCESSOR_SH1: \
42
      builtin_define ("__sh1__"); \
43
      break; \
44
    case PROCESSOR_SH2: \
45
      builtin_define ("__sh2__"); \
46
      break; \
47
    case PROCESSOR_SH2E: \
48
      builtin_define ("__SH2E__"); \
49
      break; \
50
    case PROCESSOR_SH2A: \
51
      builtin_define ("__SH2A__"); \
52
      builtin_define (TARGET_SH2A_DOUBLE \
53
                      ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
54
                      : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
55
                      : "__SH2A_NOFPU__"); \
56
      break; \
57
    case PROCESSOR_SH3: \
58
      builtin_define ("__sh3__"); \
59
      builtin_define ("__SH3__"); \
60
      if (TARGET_HARD_SH4) \
61
        builtin_define ("__SH4_NOFPU__"); \
62
      break; \
63
    case PROCESSOR_SH3E: \
64
      builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
65
      break; \
66
    case PROCESSOR_SH4: \
67
      builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
68
      break; \
69
    case PROCESSOR_SH4A: \
70
      builtin_define ("__SH4A__"); \
71
      builtin_define (TARGET_SH4 \
72
                      ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
73
                      : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
74
                      : "__SH4_NOFPU__"); \
75
      break; \
76
    case PROCESSOR_SH5: \
77
      { \
78
        builtin_define_with_value ("__SH5__", \
79
                                   TARGET_SHMEDIA64 ? "64" : "32", 0); \
80
        builtin_define_with_value ("__SHMEDIA__", \
81
                                   TARGET_SHMEDIA ? "1" : "0", 0); \
82
        if (! TARGET_FPU_DOUBLE) \
83
          builtin_define ("__SH4_NOFPU__"); \
84
      } \
85
    } \
86
  if (TARGET_FPU_ANY) \
87
    builtin_define ("__SH_FPU_ANY__"); \
88
  if (TARGET_FPU_DOUBLE) \
89
    builtin_define ("__SH_FPU_DOUBLE__"); \
90
  if (TARGET_HITACHI) \
91
    builtin_define ("__HITACHI__"); \
92
  builtin_define (TARGET_LITTLE_ENDIAN \
93
                  ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
94
} while (0)
95
 
96
/* We can not debug without a frame pointer.  */
97
/* #define CAN_DEBUG_WITHOUT_FP */
98
 
99
#define CONDITIONAL_REGISTER_USAGE do                                   \
100
{                                                                       \
101
  int regno;                                                            \
102
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)               \
103
    if (! VALID_REGISTER_P (regno))                                     \
104
      fixed_regs[regno] = call_used_regs[regno] = 1;                    \
105
  /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs.  */ \
106
  if (TARGET_SH5)                                                       \
107
    {                                                                   \
108
      call_used_regs[FIRST_GENERAL_REG + 8]                             \
109
        = call_used_regs[FIRST_GENERAL_REG + 9] = 1;                    \
110
      call_really_used_regs[FIRST_GENERAL_REG + 8]                      \
111
        = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1;             \
112
    }                                                                   \
113
  if (TARGET_SHMEDIA)                                                   \
114
    {                                                                   \
115
      regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS;                \
116
      CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]);                \
117
      regno_reg_class[FIRST_FP_REG] = FP_REGS;                          \
118
    }                                                                   \
119
  if (flag_pic)                                                         \
120
    {                                                                   \
121
      fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;                          \
122
      call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;                      \
123
    }                                                                   \
124
  /* Renesas saves and restores mac registers on call.  */              \
125
  if (TARGET_HITACHI && ! TARGET_NOMACSAVE)                             \
126
    {                                                                   \
127
      call_really_used_regs[MACH_REG] = 0;                               \
128
      call_really_used_regs[MACL_REG] = 0;                               \
129
    }                                                                   \
130
  for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0);               \
131
       regno <= LAST_FP_REG; regno += 2)                                \
132
    SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno);           \
133
  if (TARGET_SHMEDIA)                                                   \
134
    {                                                                   \
135
      for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
136
        if (! fixed_regs[regno] && call_really_used_regs[regno])        \
137
          SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);   \
138
    }                                                                   \
139
  else                                                                  \
140
    for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
141
      if (! fixed_regs[regno] && call_really_used_regs[regno])          \
142
        SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);     \
143
} while (0)
144
 
145
/* Nonzero if this is an ELF target - compile time only */
146
#define TARGET_ELF 0
147
 
148
/* Nonzero if we should generate code using type 2E insns.  */
149
#define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
150
 
151
/* Nonzero if we should generate code using type 2A insns.  */
152
#define TARGET_SH2A TARGET_HARD_SH2A
153
/* Nonzero if we should generate code using type 2A SF insns.  */
154
#define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
155
/* Nonzero if we should generate code using type 2A DF insns.  */
156
#define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
157
 
158
/* Nonzero if we should generate code using type 3E insns.  */
159
#define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
160
 
161
/* Nonzero if the cache line size is 32.  */
162
#define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
163
 
164
/* Nonzero if we schedule for a superscalar implementation.  */
165
#define TARGET_SUPERSCALAR TARGET_HARD_SH4
166
 
167
/* Nonzero if the target has separate instruction and data caches.  */
168
#define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
169
 
170
/* Nonzero if a double-precision FPU is available.  */
171
#define TARGET_FPU_DOUBLE \
172
  ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
173
 
174
/* Nonzero if an FPU is available.  */
175
#define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
176
 
177
/* Nonzero if we should generate code using type 4 insns.  */
178
#undef TARGET_SH4
179
#define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
180
 
181
/* Nonzero if we're generating code for the common subset of
182
   instructions present on both SH4a and SH4al-dsp.  */
183
#define TARGET_SH4A_ARCH TARGET_SH4A
184
 
185
/* Nonzero if we're generating code for SH4a, unless the use of the
186
   FPU is disabled (which makes it compatible with SH4al-dsp).  */
187
#define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
188
 
189
/* Nonzero if we should generate code using the SHcompact instruction
190
   set and 32-bit ABI.  */
191
#define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
192
 
193
/* Nonzero if we should generate code using the SHmedia instruction
194
   set and ABI.  */
195
#define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
196
 
197
/* Nonzero if we should generate code using the SHmedia ISA and 32-bit
198
   ABI.  */
199
#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
200
 
201
/* Nonzero if we should generate code using the SHmedia ISA and 64-bit
202
   ABI.  */
203
#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
204
 
205
/* Nonzero if we should generate code using SHmedia FPU instructions.  */
206
#define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
207
 
208
/* This is not used by the SH2E calling convention  */
209
#define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
210
  (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
211
   && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
212
 
213
#ifndef TARGET_CPU_DEFAULT
214
#define TARGET_CPU_DEFAULT SELECT_SH1
215
#define SUPPORT_SH1 1
216
#define SUPPORT_SH2E 1
217
#define SUPPORT_SH4 1
218
#define SUPPORT_SH4_SINGLE 1
219
#define SUPPORT_SH2A 1
220
#define SUPPORT_SH2A_SINGLE 1
221
#endif
222
 
223
#define TARGET_DIVIDE_INV \
224
  (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
225
   || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
226
   || sh_div_strategy == SH_DIV_INV_CALL \
227
   || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
228
#define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
229
#define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
230
#define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
231
#define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
232
#define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
233
#define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
234
#define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
235
#define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
236
#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
237
#define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
238
#define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
239
 
240
#define SELECT_SH1               (MASK_SH1)
241
#define SELECT_SH2               (MASK_SH2 | SELECT_SH1)
242
#define SELECT_SH2E              (MASK_SH_E | MASK_SH2 | MASK_SH1 \
243
                                  | MASK_FPU_SINGLE)
244
#define SELECT_SH2A              (MASK_SH_E | MASK_HARD_SH2A \
245
                                  | MASK_HARD_SH2A_DOUBLE \
246
                                  | MASK_SH2 | MASK_SH1)
247
#define SELECT_SH2A_NOFPU        (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
248
#define SELECT_SH2A_SINGLE_ONLY  (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
249
                                  | MASK_SH1 | MASK_FPU_SINGLE)
250
#define SELECT_SH2A_SINGLE       (MASK_SH_E | MASK_HARD_SH2A \
251
                                  | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
252
                                  | MASK_SH2 | MASK_SH1)
253
#define SELECT_SH3               (MASK_SH3 | SELECT_SH2)
254
#define SELECT_SH3E              (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
255
#define SELECT_SH4_NOFPU         (MASK_HARD_SH4 | SELECT_SH3)
256
#define SELECT_SH4_SINGLE_ONLY   (MASK_HARD_SH4 | SELECT_SH3E)
257
#define SELECT_SH4               (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
258
                                  | SELECT_SH3)
259
#define SELECT_SH4_SINGLE        (MASK_FPU_SINGLE | SELECT_SH4)
260
#define SELECT_SH4A_NOFPU        (MASK_SH4A | SELECT_SH4_NOFPU)
261
#define SELECT_SH4A_SINGLE_ONLY  (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
262
#define SELECT_SH4A              (MASK_SH4A | SELECT_SH4)
263
#define SELECT_SH4A_SINGLE       (MASK_SH4A | SELECT_SH4_SINGLE)
264
#define SELECT_SH5_64MEDIA       (MASK_SH5 | MASK_SH4)
265
#define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
266
#define SELECT_SH5_32MEDIA       (MASK_SH5 | MASK_SH4 | MASK_SH_E)
267
#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
268
#define SELECT_SH5_COMPACT       (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
269
#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
270
 
271
#if SUPPORT_SH1
272
#define SUPPORT_SH2 1
273
#endif
274
#if SUPPORT_SH2
275
#define SUPPORT_SH3 1
276
#endif
277
#if SUPPORT_SH3
278
#define SUPPORT_SH4_NOFPU 1
279
#endif
280
#if SUPPORT_SH4_NOFPU
281
#define SUPPORT_SH4A_NOFPU 1
282
#define SUPPORT_SH4AL 1
283
#define SUPPORT_SH2A_NOFPU 1
284
#endif
285
 
286
#if SUPPORT_SH2E
287
#define SUPPORT_SH3E 1
288
#endif
289
#if SUPPORT_SH3E
290
#define SUPPORT_SH4_SINGLE_ONLY 1
291
#define SUPPORT_SH4A_SINGLE_ONLY 1
292
#define SUPPORT_SH2A_SINGLE_ONLY 1
293
#endif
294
 
295
#if SUPPORT_SH4
296
#define SUPPORT_SH4A 1
297
#endif
298
 
299
#if SUPPORT_SH4_SINGLE
300
#define SUPPORT_SH4A_SINGLE 1
301
#endif
302
 
303
#if SUPPORT_SH5_COMPAT
304
#define SUPPORT_SH5_32MEDIA 1
305
#endif
306
 
307
#if SUPPORT_SH5_COMPACT_NOFPU
308
#define SUPPORT_SH5_32MEDIA_NOFPU 1
309
#endif
310
 
311
#define SUPPORT_ANY_SH5_32MEDIA \
312
  (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
313
#define SUPPORT_ANY_SH5_64MEDIA \
314
  (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
315
#define SUPPORT_ANY_SH5 \
316
  (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
317
 
318
/* Reset all target-selection flags.  */
319
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
320
                   | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
321
                   | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
322
 
323
/* This defaults us to big-endian.  */
324
#ifndef TARGET_ENDIAN_DEFAULT
325
#define TARGET_ENDIAN_DEFAULT 0
326
#endif
327
 
328
#ifndef TARGET_OPT_DEFAULT
329
#define TARGET_OPT_DEFAULT  MASK_ADJUST_UNROLL
330
#endif
331
 
332
#define TARGET_DEFAULT \
333
  (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
334
 
335
#ifndef SH_MULTILIB_CPU_DEFAULT
336
#define SH_MULTILIB_CPU_DEFAULT "m1"
337
#endif
338
 
339
#if TARGET_ENDIAN_DEFAULT
340
#define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
341
#else
342
#define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
343
#endif
344
 
345
#define CPP_SPEC " %(subtarget_cpp_spec) "
346
 
347
#ifndef SUBTARGET_CPP_SPEC
348
#define SUBTARGET_CPP_SPEC ""
349
#endif
350
 
351
#ifndef SUBTARGET_EXTRA_SPECS
352
#define SUBTARGET_EXTRA_SPECS
353
#endif
354
 
355
#define EXTRA_SPECS                                             \
356
  { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },                 \
357
  { "link_emul_prefix", LINK_EMUL_PREFIX },                     \
358
  { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL },           \
359
  { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
360
  { "subtarget_link_spec", SUBTARGET_LINK_SPEC },               \
361
  { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC },   \
362
  { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC },     \
363
  { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC },         \
364
  { "subtarget_asm_spec", SUBTARGET_ASM_SPEC },                 \
365
  SUBTARGET_EXTRA_SPECS
366
 
367
#if TARGET_CPU_DEFAULT & MASK_HARD_SH4
368
#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
369
#else
370
#define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
371
#endif
372
 
373
#define SH_ASM_SPEC \
374
 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
375
%(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
376
%{m2a:--isa=sh2a} \
377
%{m2a-single:--isa=sh2a} \
378
%{m2a-single-only:--isa=sh2a} \
379
%{m2a-nofpu:--isa=sh2a-nofpu} \
380
%{m5-compact*:--isa=SHcompact} \
381
%{m5-32media*:--isa=SHmedia --abi=32} \
382
%{m5-64media*:--isa=SHmedia --abi=64} \
383
%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
384
 
385
#define ASM_SPEC SH_ASM_SPEC
386
 
387
#ifndef SUBTARGET_ASM_ENDIAN_SPEC
388
#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
389
#define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
390
#else
391
#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
392
#endif
393
#endif
394
 
395
#if STRICT_NOFPU == 1
396
/* Strict nofpu means that the compiler should tell the assembler
397
   to reject FPU instructions. E.g. from ASM inserts.  */
398
#if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
399
#define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
400
#else
401
/* If there were an -isa option for sh5-nofpu then it would also go here. */
402
#define SUBTARGET_ASM_ISA_SPEC \
403
 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
404
#endif
405
#else /* ! STRICT_NOFPU */
406
#define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
407
#endif
408
 
409
#ifndef SUBTARGET_ASM_SPEC
410
#define SUBTARGET_ASM_SPEC ""
411
#endif
412
 
413
#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
414
#define LINK_EMUL_PREFIX "sh%{!mb:l}"
415
#else
416
#define LINK_EMUL_PREFIX "sh%{ml:l}"
417
#endif
418
 
419
#if TARGET_CPU_DEFAULT & MASK_SH5
420
#if TARGET_CPU_DEFAULT & MASK_SH_E
421
#define LINK_DEFAULT_CPU_EMUL "32"
422
#if TARGET_CPU_DEFAULT & MASK_SH1
423
#define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
424
#else
425
#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
426
#endif /* MASK_SH1 */
427
#else /* !MASK_SH_E */
428
#define LINK_DEFAULT_CPU_EMUL "64"
429
#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
430
#endif /* MASK_SH_E */
431
#define ASM_ISA_DEFAULT_SPEC \
432
" %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
433
#else /* !MASK_SH5 */
434
#define LINK_DEFAULT_CPU_EMUL ""
435
#define ASM_ISA_DEFAULT_SPEC ""
436
#endif /* MASK_SH5 */
437
 
438
#define SUBTARGET_LINK_EMUL_SUFFIX ""
439
#define SUBTARGET_LINK_SPEC ""
440
 
441
/* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
442
   so that we can undo the damage without code replication.  */
443
#define LINK_SPEC SH_LINK_SPEC
444
 
445
#define SH_LINK_SPEC "\
446
-m %(link_emul_prefix)\
447
%{m5-compact*|m5-32media*:32}\
448
%{m5-64media*:64}\
449
%{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
450
%(subtarget_link_emul_suffix) \
451
%{mrelax:-relax} %(subtarget_link_spec)"
452
 
453
#ifndef SH_DIV_STR_FOR_SIZE
454
#define SH_DIV_STR_FOR_SIZE "call"
455
#endif
456
 
457
#define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
458
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)                                \
459
do {                                                                    \
460
  if (LEVEL)                                                            \
461
    {                                                                   \
462
      flag_omit_frame_pointer = -1;                                     \
463
      if (! SIZE)                                                       \
464
        sh_div_str = "inv:minlat";                                      \
465
    }                                                                   \
466
  if (SIZE)                                                             \
467
    {                                                                   \
468
      target_flags |= MASK_SMALLCODE;                                   \
469
      sh_div_str = SH_DIV_STR_FOR_SIZE ;                                \
470
    }                                                                   \
471
  /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
472
     haven't been parsed yet, hence we'd read only the default. \
473
     sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
474
     it's OK to always set flag_branch_target_load_optimize.  */        \
475
  if (LEVEL > 1)                                                        \
476
    {                                                                   \
477
      flag_branch_target_load_optimize = 1;                             \
478
      if (! (SIZE))                                                     \
479
        target_flags |= MASK_SAVE_ALL_TARGET_REGS;                      \
480
    }                                                                   \
481
  /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE     \
482
     here, so leave it to OVERRIDE_OPTIONS to set                       \
483
    flag_finite_math_only.  We set it to 2 here so we know if the user  \
484
    explicitly requested this to be on or off.  */                      \
485
  flag_finite_math_only = 2;                                            \
486
  /* If flag_schedule_insns is 1, we set it to 2 here so we know if     \
487
     the user explicitly requested this to be on or off.  */            \
488
  if (flag_schedule_insns > 0)                                          \
489
    flag_schedule_insns = 2;                                            \
490
} while (0)
491
 
492
#define ASSEMBLER_DIALECT assembler_dialect
493
 
494
extern int assembler_dialect;
495
 
496
enum sh_divide_strategy_e {
497
  /* SH5 strategies.  */
498
  SH_DIV_CALL,
499
  SH_DIV_CALL2,
500
  SH_DIV_FP, /* We could do this also for SH4.  */
501
  SH_DIV_INV,
502
  SH_DIV_INV_MINLAT,
503
  SH_DIV_INV20U,
504
  SH_DIV_INV20L,
505
  SH_DIV_INV_CALL,
506
  SH_DIV_INV_CALL2,
507
  SH_DIV_INV_FP,
508
  /* SH1 .. SH4 strategies.  Because of the small number of registers
509
     available, the compiler uses knowledge of the actual set of registers
510
     being clobbered by the different functions called.  */
511
  SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency.  */
512
  SH_DIV_CALL_FP,     /* FPU needed, small size, high latency.  */
513
  SH_DIV_CALL_TABLE,  /* No FPU, large size, medium latency. */
514
  SH_DIV_INTRINSIC
515
};
516
 
517
extern enum sh_divide_strategy_e sh_div_strategy;
518
 
519
#ifndef SH_DIV_STRATEGY_DEFAULT
520
#define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
521
#endif
522
 
523
#define OVERRIDE_OPTIONS                                                \
524
do {                                                                    \
525
  int regno;                                                            \
526
                                                                        \
527
  if (flag_finite_math_only == 2)                                       \
528
    flag_finite_math_only                                               \
529
      = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;           \
530
  if (TARGET_SH2E && !flag_finite_math_only)                            \
531
    target_flags |= MASK_IEEE;                                          \
532
  sh_cpu = CPU_SH1;                                                     \
533
  assembler_dialect = 0;                                                \
534
  if (TARGET_SH2)                                                       \
535
    sh_cpu = CPU_SH2;                                                   \
536
  if (TARGET_SH2E)                                                      \
537
    sh_cpu = CPU_SH2E;                                                  \
538
  if (TARGET_SH2A)                                                      \
539
    {                                                                   \
540
      sh_cpu = CPU_SH2A;                                                \
541
      if (TARGET_SH2A_DOUBLE)                                           \
542
        target_flags |= MASK_FMOVD;                                     \
543
    }                                                                   \
544
  if (TARGET_SH3)                                                       \
545
    sh_cpu = CPU_SH3;                                                   \
546
  if (TARGET_SH3E)                                                      \
547
    sh_cpu = CPU_SH3E;                                                  \
548
  if (TARGET_SH4)                                                       \
549
    {                                                                   \
550
      assembler_dialect = 1;                                            \
551
      sh_cpu = CPU_SH4;                                                 \
552
    }                                                                   \
553
  if (TARGET_SH4A_ARCH)                                                 \
554
    {                                                                   \
555
      assembler_dialect = 1;                                            \
556
      sh_cpu = CPU_SH4A;                                                \
557
    }                                                                   \
558
  if (TARGET_SH5)                                                       \
559
    {                                                                   \
560
      sh_cpu = CPU_SH5;                                                 \
561
      target_flags |= MASK_ALIGN_DOUBLE;                                \
562
      if (TARGET_SHMEDIA_FPU)                                           \
563
        target_flags |= MASK_FMOVD;                                     \
564
      if (TARGET_SHMEDIA)                                               \
565
        {                                                               \
566
          /* There are no delay slots on SHmedia.  */                   \
567
          flag_delayed_branch = 0;                                      \
568
          /* Relaxation isn't yet supported for SHmedia */              \
569
          target_flags &= ~MASK_RELAX;                                  \
570
          /* After reload, if conversion does little good but can cause \
571
             ICEs:                                                      \
572
             - find_if_block doesn't do anything for SH because we don't\
573
               have conditional execution patterns.  (We use conditional\
574
               move patterns, which are handled differently, and only   \
575
               before reload).                                          \
576
             - find_cond_trap doesn't do anything for the SH because we \       
577
               don't have conditional traps.                            \
578
             - find_if_case_1 uses redirect_edge_and_branch_force in    \
579
               the only path that does an optimization, and this causes \
580
               an ICE when branch targets are in registers.             \
581
             - find_if_case_2 doesn't do anything for the SHmedia after \
582
               reload except when it can redirect a tablejump - and     \
583
               that's rather rare.  */                                  \
584
          flag_if_conversion2 = 0;                                      \
585
          if (! strcmp (sh_div_str, "call"))                            \
586
            sh_div_strategy = SH_DIV_CALL;                              \
587
          else if (! strcmp (sh_div_str, "call2"))                      \
588
            sh_div_strategy = SH_DIV_CALL2;                             \
589
          if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)            \
590
            sh_div_strategy = SH_DIV_FP;                                \
591
          else if (! strcmp (sh_div_str, "inv"))                        \
592
            sh_div_strategy = SH_DIV_INV;                               \
593
          else if (! strcmp (sh_div_str, "inv:minlat"))                 \
594
            sh_div_strategy = SH_DIV_INV_MINLAT;                        \
595
          else if (! strcmp (sh_div_str, "inv20u"))                     \
596
            sh_div_strategy = SH_DIV_INV20U;                            \
597
          else if (! strcmp (sh_div_str, "inv20l"))                     \
598
            sh_div_strategy = SH_DIV_INV20L;                            \
599
          else if (! strcmp (sh_div_str, "inv:call2"))                  \
600
            sh_div_strategy = SH_DIV_INV_CALL2;                         \
601
          else if (! strcmp (sh_div_str, "inv:call"))                   \
602
            sh_div_strategy = SH_DIV_INV_CALL;                          \
603
          else if (! strcmp (sh_div_str, "inv:fp"))                     \
604
            {                                                           \
605
              if (TARGET_FPU_ANY)                                       \
606
                sh_div_strategy = SH_DIV_INV_FP;                        \
607
              else                                                      \
608
                sh_div_strategy = SH_DIV_INV;                           \
609
            }                                                           \
610
        }                                                               \
611
      /* -fprofile-arcs needs a working libgcov .  In unified tree      \
612
         configurations with newlib, this requires to configure with    \
613
         --with-newlib --with-headers.  But there is no way to check    \
614
         here we have a working libgcov, so just assume that we have.  */\
615
      if (profile_flag)                                                 \
616
        warning (0, "profiling is still experimental for this target");\
617
    }                                                                   \
618
  else                                                                  \
619
    {                                                                   \
620
       /* Only the sh64-elf assembler fully supports .quad properly.  */\
621
       targetm.asm_out.aligned_op.di = NULL;                            \
622
       targetm.asm_out.unaligned_op.di = NULL;                          \
623
    }                                                                   \
624
  if (TARGET_SH1)                                                       \
625
    {                                                                   \
626
      if (! strcmp (sh_div_str, "call-div1"))                           \
627
        sh_div_strategy = SH_DIV_CALL_DIV1;                             \
628
      else if (! strcmp (sh_div_str, "call-fp")                         \
629
               && (TARGET_FPU_DOUBLE                                    \
630
                   || (TARGET_HARD_SH4 && TARGET_SH2E)                  \
631
                   || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))            \
632
        sh_div_strategy = SH_DIV_CALL_FP;                               \
633
      else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)       \
634
        sh_div_strategy = SH_DIV_CALL_TABLE;                            \
635
      else                                                              \
636
        /* Pick one that makes most sense for the target in general.    \
637
           It is not much good to use different functions depending     \
638
           on -Os, since then we'll end up with two different functions \
639
           when some of the code is compiled for size, and some for     \
640
           speed.  */                                                   \
641
                                                                        \
642
        /* SH4 tends to emphasize speed.  */                            \
643
        if (TARGET_HARD_SH4)                                            \
644
          sh_div_strategy = SH_DIV_CALL_TABLE;                          \
645
        /* These have their own way of doing things.  */                \
646
        else if (TARGET_SH2A)                                           \
647
          sh_div_strategy = SH_DIV_INTRINSIC;                           \
648
        /* ??? Should we use the integer SHmedia function instead?  */  \
649
        else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)                    \
650
          sh_div_strategy = SH_DIV_CALL_FP;                             \
651
        /* SH1 .. SH3 cores often go into small-footprint systems, so   \
652
           default to the smallest implementation available.  */        \
653
        else if (TARGET_SH2)    /* ??? EXPERIMENTAL */                  \
654
          sh_div_strategy = SH_DIV_CALL_TABLE;                          \
655
        else                                                            \
656
          sh_div_strategy = SH_DIV_CALL_DIV1;                           \
657
    }                                                                   \
658
  if (!TARGET_SH1)                                                      \
659
    TARGET_PRETEND_CMOVE = 0;                                           \
660
  if (sh_divsi3_libfunc[0])                                             \
661
    ; /* User supplied - leave it alone.  */                            \
662
  else if (TARGET_DIVIDE_CALL_FP)                                       \
663
    sh_divsi3_libfunc = "__sdivsi3_i4";                                 \
664
  else if (TARGET_DIVIDE_CALL_TABLE)                                    \
665
    sh_divsi3_libfunc = "__sdivsi3_i4i";                                \
666
  else if (TARGET_SH5)                                                  \
667
    sh_divsi3_libfunc = "__sdivsi3_1";                                  \
668
  else                                                                  \
669
    sh_divsi3_libfunc = "__sdivsi3";                                    \
670
  if (TARGET_FMOVD)                                                     \
671
    reg_class_from_letter['e' - 'a'] = NO_REGS;                         \
672
                                                                        \
673
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)               \
674
    if (! VALID_REGISTER_P (regno))                                     \
675
      sh_register_names[regno][0] = '\0';                               \
676
                                                                        \
677
  for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)                    \
678
    if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))                 \
679
      sh_additional_register_names[regno][0] = '\0';                    \
680
                                                                        \
681
  if (flag_omit_frame_pointer < 0)                                      \
682
   {                                                                    \
683
     /* The debugging information is sufficient,                        \
684
        but gdb doesn't implement this yet */                           \
685
     if (0)                                                             \
686
      flag_omit_frame_pointer                                           \
687
        = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);                   \
688
     else                                                               \
689
      flag_omit_frame_pointer = 0;                                      \
690
   }                                                                    \
691
                                                                        \
692
  if ((flag_pic && ! TARGET_PREFERGOT)                                  \
693
      || (TARGET_SHMEDIA && !TARGET_PT_FIXED))                          \
694
    flag_no_function_cse = 1;                                           \
695
                                                                        \
696
  if (SMALL_REGISTER_CLASSES)                                           \
697
    {                                                                   \
698
      /* Never run scheduling before reload, since that can             \
699
         break global alloc, and generates slower code anyway due       \
700
         to the pressure on R0.  */                                     \
701
      /* Enable sched1 for SH4; ready queue will be reordered by        \
702
         the target hooks when pressure is high. We can not do this for \
703
         SH3 and lower as they give spill failures for R0.  */          \
704
      if (!TARGET_HARD_SH4)                                             \
705
        flag_schedule_insns = 0;                                        \
706
      /* ??? Current exception handling places basic block boundaries   \
707
         after call_insns.  It causes the high pressure on R0 and gives \
708
         spill failures for R0 in reload.  See PR 22553 and the thread  \
709
         on gcc-patches                                                 \
710
         <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>.  */ \
711
      else if (flag_exceptions)                                         \
712
        {                                                               \
713
          if (flag_schedule_insns == 1)                                 \
714
            warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
715
          flag_schedule_insns = 0;                                      \
716
        }                                                               \
717
    }                                                                   \
718
                                                                        \
719
  if (align_loops == 0)                                                 \
720
    align_loops =  1 << (TARGET_SH5 ? 3 : 2);                           \
721
  if (align_jumps == 0)                                                 \
722
    align_jumps = 1 << CACHE_LOG;                                       \
723
  else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))                      \
724
    align_jumps = TARGET_SHMEDIA ? 4 : 2;                               \
725
                                                                        \
726
  /* Allocation boundary (in *bytes*) for the code of a function.       \
727
     SH1: 32 bit alignment is faster, because instructions are always   \
728
     fetched as a pair from a longword boundary.                        \
729
     SH2 .. SH5 : align to cache line start.  */                        \
730
  if (align_functions == 0)                                             \
731
    align_functions                                                     \
732
      = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);      \
733
  /* The linker relaxation code breaks when a function contains         \
734
     alignments that are larger than that at the start of a             \
735
     compilation unit.  */                                              \
736
  if (TARGET_RELAX)                                                     \
737
    {                                                                   \
738
      int min_align                                                     \
739
        = align_loops > align_jumps ? align_loops : align_jumps;        \
740
                                                                        \
741
      /* Also take possible .long constants / mova tables int account.  */\
742
      if (min_align < 4)                                                \
743
        min_align = 4;                                                  \
744
      if (align_functions < min_align)                                  \
745
        align_functions = min_align;                                    \
746
    }                                                                   \
747
} while (0)
748
 
749
/* Target machine storage layout.  */
750
 
751
/* Define this if most significant bit is lowest numbered
752
   in instructions that operate on numbered bit-fields.  */
753
 
754
#define BITS_BIG_ENDIAN  0
755
 
756
/* Define this if most significant byte of a word is the lowest numbered.  */
757
#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
758
 
759
/* Define this if most significant word of a multiword number is the lowest
760
   numbered.  */
761
#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
762
 
763
/* Define this to set the endianness to use in libgcc2.c, which can
764
   not depend on target_flags.  */
765
#if defined(__LITTLE_ENDIAN__)
766
#define LIBGCC2_WORDS_BIG_ENDIAN 0
767
#else
768
#define LIBGCC2_WORDS_BIG_ENDIAN 1
769
#endif
770
 
771
#define MAX_BITS_PER_WORD 64
772
 
773
/* Width in bits of an `int'.  We want just 32-bits, even if words are
774
   longer.  */
775
#define INT_TYPE_SIZE 32
776
 
777
/* Width in bits of a `long'.  */
778
#define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
779
 
780
/* Width in bits of a `long long'.  */
781
#define LONG_LONG_TYPE_SIZE 64
782
 
783
/* Width in bits of a `long double'.  */
784
#define LONG_DOUBLE_TYPE_SIZE 64
785
 
786
/* Width of a word, in units (bytes).  */
787
#define UNITS_PER_WORD  (TARGET_SHMEDIA ? 8 : 4)
788
#define MIN_UNITS_PER_WORD 4
789
 
790
/* Scaling factor for Dwarf data offsets for CFI information.
791
   The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
792
   SHmedia; however, since we do partial register saves for the registers
793
   visible to SHcompact, and for target registers for SHMEDIA32, we have
794
   to allow saves that are only 4-byte aligned.  */
795
#define DWARF_CIE_DATA_ALIGNMENT -4
796
 
797
/* Width in bits of a pointer.
798
   See also the macro `Pmode' defined below.  */
799
#define POINTER_SIZE  (TARGET_SHMEDIA64 ? 64 : 32)
800
 
801
/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
802
#define PARM_BOUNDARY   (TARGET_SH5 ? 64 : 32)
803
 
804
/* Boundary (in *bits*) on which stack pointer should be aligned.  */
805
#define STACK_BOUNDARY  BIGGEST_ALIGNMENT
806
 
807
/* The log (base 2) of the cache line size, in bytes.  Processors prior to
808
   SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
809
   The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
810
#define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
811
 
812
/* ABI given & required minimum allocation boundary (in *bits*) for the
813
   code of a function.  */
814
#define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
815
 
816
/* On SH5, the lowest bit is used to indicate SHmedia functions, so
817
   the vbit must go into the delta field of
818
   pointers-to-member-functions.  */
819
#define TARGET_PTRMEMFUNC_VBIT_LOCATION \
820
  (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
821
 
822
/* Alignment of field after `int : 0' in a structure.  */
823
#define EMPTY_FIELD_BOUNDARY  32
824
 
825
/* No data type wants to be aligned rounder than this.  */
826
#define BIGGEST_ALIGNMENT  (TARGET_ALIGN_DOUBLE ? 64 : 32)
827
 
828
/* The best alignment to use in cases where we have a choice.  */
829
#define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
830
 
831
/* Make strings word-aligned so strcpy from constants will be faster.  */
832
#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
833
  ((TREE_CODE (EXP) == STRING_CST       \
834
    && (ALIGN) < FASTEST_ALIGNMENT)     \
835
    ? FASTEST_ALIGNMENT : (ALIGN))
836
 
837
/* get_mode_alignment assumes complex values are always held in multiple
838
   registers, but that is not the case on the SH; CQImode and CHImode are
839
   held in a single integer register.  SH5 also holds CSImode and SCmode
840
   values in integer registers.  This is relevant for argument passing on
841
   SHcompact as we use a stack temp in order to pass CSImode by reference.  */
842
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
843
  ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
844
    || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
845
   ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
846
   : (unsigned) ALIGN)
847
 
848
/* Make arrays of chars word-aligned for the same reasons.  */
849
#define DATA_ALIGNMENT(TYPE, ALIGN)             \
850
  (TREE_CODE (TYPE) == ARRAY_TYPE               \
851
   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode    \
852
   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
853
 
854
/* Number of bits which any structure or union's size must be a
855
   multiple of.  Each structure or union's size is rounded up to a
856
   multiple of this.  */
857
#define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
858
 
859
/* Set this nonzero if move instructions will actually fail to work
860
   when given unaligned data.  */
861
#define STRICT_ALIGNMENT 1
862
 
863
/* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm.  */
864
#define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
865
  barrier_align (LABEL_AFTER_BARRIER)
866
 
867
#define LOOP_ALIGN(A_LABEL) \
868
  ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
869
   ? 0 : sh_loop_align (A_LABEL))
870
 
871
#define LABEL_ALIGN(A_LABEL) \
872
(                                                                       \
873
  (PREV_INSN (A_LABEL)                                                  \
874
   && GET_CODE (PREV_INSN (A_LABEL)) == INSN                            \
875
   && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE       \
876
   && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN)         \
877
   /* explicit alignment insn in constant tables.  */                   \
878
  ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0))              \
879
  : 0)
880
 
881
/* Jump tables must be 32 bit aligned, no matter the size of the element.  */
882
#define ADDR_VEC_ALIGN(ADDR_VEC) 2
883
 
884
/* The base two logarithm of the known minimum alignment of an insn length.  */
885
#define INSN_LENGTH_ALIGNMENT(A_INSN)                                   \
886
  (GET_CODE (A_INSN) == INSN                                            \
887
   ? 1 << TARGET_SHMEDIA                                                \
888
   : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN   \
889
   ? 1 << TARGET_SHMEDIA                                                \
890
   : CACHE_LOG)
891
 
892
/* Standard register usage.  */
893
 
894
/* Register allocation for the Renesas calling convention:
895
 
896
        r0              arg return
897
        r1..r3          scratch
898
        r4..r7          args in
899
        r8..r13         call saved
900
        r14             frame pointer/call saved
901
        r15             stack pointer
902
        ap              arg pointer (doesn't really exist, always eliminated)
903
        pr              subroutine return address
904
        t               t bit
905
        mach            multiply/accumulate result, high part
906
        macl            multiply/accumulate result, low part.
907
        fpul            fp/int communication register
908
        rap             return address pointer register
909
        fr0             fp arg return
910
        fr1..fr3        scratch floating point registers
911
        fr4..fr11       fp args in
912
        fr12..fr15      call saved floating point registers  */
913
 
914
#define MAX_REGISTER_NAME_LENGTH 5
915
extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
916
 
917
#define SH_REGISTER_NAMES_INITIALIZER                                   \
918
{                                                                       \
919
  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",         \
920
  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",        \
921
  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",        \
922
  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",        \
923
  "r32",  "r33",  "r34",  "r35",  "r36",  "r37",  "r38",  "r39",        \
924
  "r40",  "r41",  "r42",  "r43",  "r44",  "r45",  "r46",  "r47",        \
925
  "r48",  "r49",  "r50",  "r51",  "r52",  "r53",  "r54",  "r55",        \
926
  "r56",  "r57",  "r58",  "r59",  "r60",  "r61",  "r62",  "r63",        \
927
  "fr0",  "fr1",  "fr2",  "fr3",  "fr4",  "fr5",  "fr6",  "fr7",        \
928
  "fr8",  "fr9",  "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",       \
929
  "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",       \
930
  "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",       \
931
  "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",       \
932
  "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",       \
933
  "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",       \
934
  "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",       \
935
  "tr0",  "tr1",  "tr2",  "tr3",  "tr4",  "tr5",  "tr6",  "tr7",        \
936
  "xd0",  "xd2",  "xd4",  "xd6",  "xd8",  "xd10", "xd12", "xd14",       \
937
  "gbr",  "ap",   "pr",   "t",    "mach", "macl", "fpul", "fpscr",      \
938
  "rap",  "sfp"                                                         \
939
}
940
 
941
#define REGNAMES_ARR_INDEX_1(index) \
942
  (sh_register_names[index])
943
#define REGNAMES_ARR_INDEX_2(index) \
944
  REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
945
#define REGNAMES_ARR_INDEX_4(index) \
946
  REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
947
#define REGNAMES_ARR_INDEX_8(index) \
948
  REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
949
#define REGNAMES_ARR_INDEX_16(index) \
950
  REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
951
#define REGNAMES_ARR_INDEX_32(index) \
952
  REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
953
#define REGNAMES_ARR_INDEX_64(index) \
954
  REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
955
 
956
#define REGISTER_NAMES \
957
{ \
958
  REGNAMES_ARR_INDEX_64 (0), \
959
  REGNAMES_ARR_INDEX_64 (64), \
960
  REGNAMES_ARR_INDEX_8 (128), \
961
  REGNAMES_ARR_INDEX_8 (136), \
962
  REGNAMES_ARR_INDEX_8 (144), \
963
  REGNAMES_ARR_INDEX_2 (152) \
964
}
965
 
966
#define ADDREGNAMES_SIZE 32
967
#define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
968
extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
969
  [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
970
 
971
#define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER                        \
972
{                                                                       \
973
  "dr0",  "dr2",  "dr4",  "dr6",  "dr8",  "dr10", "dr12", "dr14",       \
974
  "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",       \
975
  "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",       \
976
  "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62"        \
977
}
978
 
979
#define ADDREGNAMES_REGNO(index) \
980
  ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
981
   : (-1))
982
 
983
#define ADDREGNAMES_ARR_INDEX_1(index) \
984
  { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
985
#define ADDREGNAMES_ARR_INDEX_2(index) \
986
  ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
987
#define ADDREGNAMES_ARR_INDEX_4(index) \
988
  ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
989
#define ADDREGNAMES_ARR_INDEX_8(index) \
990
  ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
991
#define ADDREGNAMES_ARR_INDEX_16(index) \
992
  ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
993
#define ADDREGNAMES_ARR_INDEX_32(index) \
994
  ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
995
 
996
#define ADDITIONAL_REGISTER_NAMES \
997
{                                       \
998
  ADDREGNAMES_ARR_INDEX_32 (0)          \
999
}
1000
 
1001
/* Number of actual hardware registers.
1002
   The hardware registers are assigned numbers for the compiler
1003
   from 0 to just below FIRST_PSEUDO_REGISTER.
1004
   All registers that the compiler knows about must be given numbers,
1005
   even those that are not normally considered general registers.  */
1006
 
1007
/* There are many other relevant definitions in sh.md's md_constants.  */
1008
 
1009
#define FIRST_GENERAL_REG R0_REG
1010
#define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1011
#define FIRST_FP_REG DR0_REG
1012
#define LAST_FP_REG  (FIRST_FP_REG + \
1013
                      (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1014
#define FIRST_XD_REG XD0_REG
1015
#define LAST_XD_REG  (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1016
#define FIRST_TARGET_REG TR0_REG
1017
#define LAST_TARGET_REG  (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1018
 
1019
#define GENERAL_REGISTER_P(REGNO) \
1020
  IN_RANGE ((REGNO), \
1021
            (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1022
            (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1023
 
1024
#define GENERAL_OR_AP_REGISTER_P(REGNO) \
1025
  (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG)    \
1026
   || ((REGNO) == FRAME_POINTER_REGNUM))
1027
 
1028
#define FP_REGISTER_P(REGNO) \
1029
  ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1030
 
1031
#define XD_REGISTER_P(REGNO) \
1032
  ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1033
 
1034
#define FP_OR_XD_REGISTER_P(REGNO) \
1035
  (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1036
 
1037
#define FP_ANY_REGISTER_P(REGNO) \
1038
  (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1039
 
1040
#define SPECIAL_REGISTER_P(REGNO) \
1041
  ((REGNO) == GBR_REG || (REGNO) == T_REG \
1042
   || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1043
 
1044
#define TARGET_REGISTER_P(REGNO) \
1045
  ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1046
 
1047
#define SHMEDIA_REGISTER_P(REGNO) \
1048
  (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1049
   || TARGET_REGISTER_P (REGNO))
1050
 
1051
/* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1052
   that should be fixed.  */
1053
#define VALID_REGISTER_P(REGNO) \
1054
  (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1055
   || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1056
   || (REGNO) == FRAME_POINTER_REGNUM \
1057
   || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1058
   || (TARGET_SH2E && (REGNO) == FPUL_REG))
1059
 
1060
/* The mode that should be generally used to store a register by
1061
   itself in the stack, or to load it back.  */
1062
#define REGISTER_NATURAL_MODE(REGNO) \
1063
  (FP_REGISTER_P (REGNO) ? SFmode \
1064
   : XD_REGISTER_P (REGNO) ? DFmode \
1065
   : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1066
   ? DImode \
1067
   : SImode)
1068
 
1069
#define FIRST_PSEUDO_REGISTER 154
1070
 
1071
/* Don't count soft frame pointer.  */
1072
#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1073
 
1074
/* 1 for registers that have pervasive standard uses
1075
   and are not available for the register allocator.
1076
 
1077
   Mach register is fixed 'cause it's only 10 bits wide for SH1.
1078
   It is 32 bits wide for SH2.  */
1079
 
1080
#define FIXED_REGISTERS                                                 \
1081
{                                                                       \
1082
/* Regular registers.  */                                               \
1083
  0,      0,      0,      0,      0,      0,      0,      0,            \
1084
  0,      0,      0,      0,      0,      0,      0,      1,            \
1085
  /* r16 is reserved, r18 is the former pr.  */                         \
1086
  1,      0,      0,      0,      0,      0,      0,      0,            \
1087
  /* r24 is reserved for the OS; r25, for the assembler or linker.  */  \
1088
  /* r26 is a global variable data pointer; r27 is for constants.  */   \
1089
  1,      1,      1,      1,      0,      0,      0,      0,            \
1090
  0,      0,      0,      0,      0,      0,      0,      0,            \
1091
  0,      0,      0,      0,      0,      0,      0,      0,            \
1092
  0,      0,      0,      0,      0,      0,      0,      0,            \
1093
  0,      0,      0,      0,      0,      0,      0,      1,            \
1094
/* FP registers.  */                                                    \
1095
  0,      0,      0,      0,      0,      0,      0,      0,            \
1096
  0,      0,      0,      0,      0,      0,      0,      0,            \
1097
  0,      0,      0,      0,      0,      0,      0,      0,            \
1098
  0,      0,      0,      0,      0,      0,      0,      0,            \
1099
  0,      0,      0,      0,      0,      0,      0,      0,            \
1100
  0,      0,      0,      0,      0,      0,      0,      0,            \
1101
  0,      0,      0,      0,      0,      0,      0,      0,            \
1102
  0,      0,      0,      0,      0,      0,      0,      0,            \
1103
/* Branch target registers.  */                                         \
1104
  0,      0,      0,      0,      0,      0,      0,      0,            \
1105
/* XD registers.  */                                                    \
1106
  0,      0,      0,      0,      0,      0,      0,      0,            \
1107
/*"gbr",  "ap",   "pr",   "t",    "mach", "macl", "fpul", "fpscr", */   \
1108
  1,      1,      1,      1,      1,      1,      0,      1,            \
1109
/*"rap",  "sfp" */                                                      \
1110
  1,      1,                                                            \
1111
}
1112
 
1113
/* 1 for registers not available across function calls.
1114
   These must include the FIXED_REGISTERS and also any
1115
   registers that can be used without being saved.
1116
   The latter must include the registers where values are returned
1117
   and the register where structure-value addresses are passed.
1118
   Aside from that, you can include as many other registers as you like.  */
1119
 
1120
#define CALL_USED_REGISTERS                                             \
1121
{                                                                       \
1122
/* Regular registers.  */                                               \
1123
  1,      1,      1,      1,      1,      1,      1,      1,            \
1124
  /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs.   \
1125
     Only the lower 32bits of R10-R14 are guaranteed to be preserved    \
1126
     across SH5 function calls.  */                                     \
1127
  0,      0,      0,      0,      0,      0,      0,      1,            \
1128
  1,      1,      1,      1,      1,      1,      1,      1,            \
1129
  1,      1,      1,      1,      0,      0,      0,      0,            \
1130
  0,      0,      0,      0,      1,      1,      1,      1,            \
1131
  1,      1,      1,      1,      0,      0,      0,      0,            \
1132
  0,      0,      0,      0,      0,      0,      0,      0,            \
1133
  0,      0,      0,      0,      1,      1,      1,      1,            \
1134
/* FP registers.  */                                                    \
1135
  1,      1,      1,      1,      1,      1,      1,      1,            \
1136
  1,      1,      1,      1,      0,      0,      0,      0,            \
1137
  1,      1,      1,      1,      1,      1,      1,      1,            \
1138
  1,      1,      1,      1,      1,      1,      1,      1,            \
1139
  1,      1,      1,      1,      0,      0,      0,      0,            \
1140
  0,      0,      0,      0,      0,      0,      0,      0,            \
1141
  0,      0,      0,      0,      0,      0,      0,      0,            \
1142
  0,      0,      0,      0,      0,      0,      0,      0,            \
1143
/* Branch target registers.  */                                         \
1144
  1,      1,      1,      1,      1,      0,      0,      0,            \
1145
/* XD registers.  */                                                    \
1146
  1,      1,      1,      1,      1,      1,      0,      0,            \
1147
/*"gbr",  "ap",   "pr",   "t",    "mach", "macl", "fpul", "fpscr", */   \
1148
  1,      1,      1,      1,      1,      1,      1,      1,            \
1149
/*"rap",  "sfp" */                                                      \
1150
  1,      1,                                                            \
1151
}
1152
 
1153
/* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1154
   fixed, like PIC_OFFSET_TABLE_REGNUM.  */
1155
#define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1156
 
1157
/* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1158
   across SHcompact function calls.  We can't tell whether a called
1159
   function is SHmedia or SHcompact, so we assume it may be when
1160
   compiling SHmedia code with the 32-bit ABI, since that's the only
1161
   ABI that can be linked with SHcompact code.  */
1162
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1163
  (TARGET_SHMEDIA32 \
1164
   && GET_MODE_SIZE (MODE) > 4 \
1165
   && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1166
        && (REGNO) <= FIRST_GENERAL_REG + 15) \
1167
       || TARGET_REGISTER_P (REGNO) \
1168
       || (REGNO) == PR_MEDIA_REG))
1169
 
1170
/* Return number of consecutive hard regs needed starting at reg REGNO
1171
   to hold something of mode MODE.
1172
   This is ordinarily the length in words of a value of mode MODE
1173
   but can be less for certain modes in special long registers.
1174
 
1175
   On the SH all but the XD regs are UNITS_PER_WORD bits wide.  */
1176
 
1177
#define HARD_REGNO_NREGS(REGNO, MODE) \
1178
   (XD_REGISTER_P (REGNO) \
1179
    ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1180
    : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1181
    ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1182
    : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1183
 
1184
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1185
   We can allow any mode in any general register.  The special registers
1186
   only allow SImode.  Don't allow any mode in the PR.  */
1187
 
1188
/* We cannot hold DCmode values in the XD registers because alter_reg
1189
   handles subregs of them incorrectly.  We could work around this by
1190
   spacing the XD registers like the DR registers, but this would require
1191
   additional memory in every compilation to hold larger register vectors.
1192
   We could hold SFmode / SCmode values in XD registers, but that
1193
   would require a tertiary reload when reloading from / to memory,
1194
   and a secondary reload to reload from / to general regs; that
1195
   seems to be a loosing proposition.  */
1196
/* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1197
   it won't be ferried through GP registers first.  */
1198
#define HARD_REGNO_MODE_OK(REGNO, MODE)         \
1199
  (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1200
   : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1201
   : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1202
   ? 1 \
1203
   : (MODE) == V2SFmode \
1204
   ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1205
      || GENERAL_REGISTER_P (REGNO)) \
1206
   : (MODE) == V4SFmode \
1207
   ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1208
      || GENERAL_REGISTER_P (REGNO)) \
1209
   : (MODE) == V16SFmode \
1210
   ? (TARGET_SHMEDIA \
1211
      ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1212
      : (REGNO) == FIRST_XD_REG) \
1213
   : FP_REGISTER_P (REGNO) \
1214
   ? ((MODE) == SFmode || (MODE) == SImode \
1215
      || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1216
      || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1217
           || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1218
                                  || (MODE) == V2SFmode || (MODE) == TImode))) \
1219
          && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1220
      || ((TARGET_SH4 || TARGET_SHMEDIA) \
1221
          && (MODE) == TImode \
1222
          && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1223
   : XD_REGISTER_P (REGNO) \
1224
   ? (MODE) == DFmode \
1225
   : TARGET_REGISTER_P (REGNO) \
1226
   ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1227
   : (REGNO) == PR_REG ? (MODE) == SImode \
1228
   : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1229
   : 1)
1230
 
1231
/* Value is 1 if it is a good idea to tie two pseudo registers
1232
   when one has mode MODE1 and one has mode MODE2.
1233
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1234
   for any hard reg, then this must be 0 for correct output.
1235
   That's the case for xd registers: we don't hold SFmode values in
1236
   them, so we can't tie an SFmode pseudos with one in another
1237
   floating-point mode.  */
1238
 
1239
#define MODES_TIEABLE_P(MODE1, MODE2) \
1240
  ((MODE1) == (MODE2) \
1241
   || (TARGET_SHMEDIA \
1242
       && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1243
       && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1244
   || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1245
       && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1246
                              && (GET_MODE_SIZE (MODE2) <= 4)) \
1247
                          : ((MODE1) != SFmode && (MODE2) != SFmode))))
1248
 
1249
/* A C expression that is nonzero if hard register NEW_REG can be
1250
   considered for use as a rename register for OLD_REG register */
1251
 
1252
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1253
   sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1254
 
1255
/* Specify the registers used for certain standard purposes.
1256
   The values of these macros are register numbers.  */
1257
 
1258
/* Define this if the program counter is overloaded on a register.  */
1259
/* #define PC_REGNUM            15*/
1260
 
1261
/* Register to use for pushing function arguments.  */
1262
#define STACK_POINTER_REGNUM    SP_REG
1263
 
1264
/* Base register for access to local variables of the function.  */
1265
#define HARD_FRAME_POINTER_REGNUM       FP_REG
1266
 
1267
/* Base register for access to local variables of the function.  */
1268
#define FRAME_POINTER_REGNUM    153
1269
 
1270
/* Fake register that holds the address on the stack of the
1271
   current function's return address.  */
1272
#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1273
 
1274
/* Register to hold the addressing base for position independent
1275
   code access to data items.  */
1276
#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1277
 
1278
#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1279
 
1280
/* Value should be nonzero if functions must have frame pointers.
1281
   Zero means the frame pointer need not be set up (and parms may be accessed
1282
   via the stack pointer) in functions that seem suitable.  */
1283
 
1284
#define FRAME_POINTER_REQUIRED  0
1285
 
1286
/* Definitions for register eliminations.
1287
 
1288
   We have three registers that can be eliminated on the SH.  First, the
1289
   frame pointer register can often be eliminated in favor of the stack
1290
   pointer register.  Secondly, the argument pointer register can always be
1291
   eliminated; it is replaced with either the stack or frame pointer.
1292
   Third, there is the return address pointer, which can also be replaced
1293
   with either the stack or the frame pointer.  */
1294
 
1295
/* This is an array of structures.  Each structure initializes one pair
1296
   of eliminable registers.  The "from" register number is given first,
1297
   followed by "to".  Eliminations of the same "from" register are listed
1298
   in order of preference.  */
1299
 
1300
/* If you add any registers here that are not actually hard registers,
1301
   and that have any alternative of elimination that doesn't always
1302
   apply, you need to amend calc_live_regs to exclude it, because
1303
   reload spills all eliminable registers where it sees an
1304
   can_eliminate == 0 entry, thus making them 'live' .
1305
   If you add any hard registers that can be eliminated in different
1306
   ways, you have to patch reload to spill them only when all alternatives
1307
   of elimination fail.  */
1308
 
1309
#define ELIMINABLE_REGS                                         \
1310
{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},            \
1311
 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                 \
1312
 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},            \
1313
 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},        \
1314
 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},   \
1315
 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},                   \
1316
 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1317
 
1318
/* Given FROM and TO register numbers, say whether this elimination
1319
   is allowed.  */
1320
#define CAN_ELIMINATE(FROM, TO) \
1321
  (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1322
 
1323
/* Define the offset between two registers, one to be eliminated, and the other
1324
   its replacement, at the start of a routine.  */
1325
 
1326
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1327
  OFFSET = initial_elimination_offset ((FROM), (TO))
1328
 
1329
/* Base register for access to arguments of the function.  */
1330
#define ARG_POINTER_REGNUM      AP_REG
1331
 
1332
/* Register in which the static-chain is passed to a function.  */
1333
#define STATIC_CHAIN_REGNUM     (TARGET_SH5 ? 1 : 3)
1334
 
1335
/* Don't default to pcc-struct-return, because we have already specified
1336
   exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1337
   target hook.  */
1338
 
1339
#define DEFAULT_PCC_STRUCT_RETURN 0
1340
 
1341
#define SHMEDIA_REGS_STACK_ADJUST() \
1342
  (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1343
   ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1344
      + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1345
   : 0)
1346
 
1347
 
1348
/* Define the classes of registers for register constraints in the
1349
   machine description.  Also define ranges of constants.
1350
 
1351
   One of the classes must always be named ALL_REGS and include all hard regs.
1352
   If there is more than one class, another class must be named NO_REGS
1353
   and contain no registers.
1354
 
1355
   The name GENERAL_REGS must be the name of a class (or an alias for
1356
   another name such as ALL_REGS).  This is the class of registers
1357
   that is allowed by "g" or "r" in a register constraint.
1358
   Also, registers outside this class are allocated only when
1359
   instructions express preferences for them.
1360
 
1361
   The classes must be numbered in nondecreasing order; that is,
1362
   a larger-numbered class must never be contained completely
1363
   in a smaller-numbered class.
1364
 
1365
   For any two classes, it is very desirable that there be another
1366
   class that represents their union.  */
1367
 
1368
/* The SH has two sorts of general registers, R0 and the rest.  R0 can
1369
   be used as the destination of some of the arithmetic ops. There are
1370
   also some special purpose registers; the T bit register, the
1371
   Procedure Return Register and the Multiply Accumulate Registers.  */
1372
/* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1373
   reg_class_subunion.  We don't want to have an actual union class
1374
   of these, because it would only be used when both classes are calculated
1375
   to give the same cost, but there is only one FPUL register.
1376
   Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1377
   applying to the actual instruction alternative considered.  E.g., the
1378
   y/r alternative of movsi_ie is considered to have no more cost that
1379
   the r/r alternative, which is patently untrue.  */
1380
 
1381
enum reg_class
1382
{
1383
  NO_REGS,
1384
  R0_REGS,
1385
  PR_REGS,
1386
  T_REGS,
1387
  MAC_REGS,
1388
  FPUL_REGS,
1389
  SIBCALL_REGS,
1390
  GENERAL_REGS,
1391
  FP0_REGS,
1392
  FP_REGS,
1393
  DF_HI_REGS,
1394
  DF_REGS,
1395
  FPSCR_REGS,
1396
  GENERAL_FP_REGS,
1397
  GENERAL_DF_REGS,
1398
  TARGET_REGS,
1399
  ALL_REGS,
1400
  LIM_REG_CLASSES
1401
};
1402
 
1403
#define N_REG_CLASSES  (int) LIM_REG_CLASSES
1404
 
1405
/* Give names of register classes as strings for dump file.  */
1406
#define REG_CLASS_NAMES \
1407
{                       \
1408
  "NO_REGS",            \
1409
  "R0_REGS",            \
1410
  "PR_REGS",            \
1411
  "T_REGS",             \
1412
  "MAC_REGS",           \
1413
  "FPUL_REGS",          \
1414
  "SIBCALL_REGS",       \
1415
  "GENERAL_REGS",       \
1416
  "FP0_REGS",           \
1417
  "FP_REGS",            \
1418
  "DF_HI_REGS",         \
1419
  "DF_REGS",            \
1420
  "FPSCR_REGS",         \
1421
  "GENERAL_FP_REGS",    \
1422
  "GENERAL_DF_REGS",    \
1423
  "TARGET_REGS",        \
1424
  "ALL_REGS",           \
1425
}
1426
 
1427
/* Define which registers fit in which classes.
1428
   This is an initializer for a vector of HARD_REG_SET
1429
   of length N_REG_CLASSES.  */
1430
 
1431
#define REG_CLASS_CONTENTS                                              \
1432
{                                                                       \
1433
/* NO_REGS:  */                                                         \
1434
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },       \
1435
/* R0_REGS:  */                                                         \
1436
  { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },       \
1437
/* PR_REGS:  */                                                         \
1438
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 },       \
1439
/* T_REGS:  */                                                          \
1440
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 },       \
1441
/* MAC_REGS:  */                                                        \
1442
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 },       \
1443
/* FPUL_REGS:  */                                                       \
1444
  { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 },       \
1445
/* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE.  */ \
1446
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },       \
1447
/* GENERAL_REGS:  */                                                    \
1448
  { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 },       \
1449
/* FP0_REGS:  */                                                        \
1450
  { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 },       \
1451
/* FP_REGS:  */                                                         \
1452
  { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 },       \
1453
/* DF_HI_REGS:  Initialized in CONDITIONAL_REGISTER_USAGE.  */          \
1454
  { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 },       \
1455
/* DF_REGS:  */                                                         \
1456
  { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 },       \
1457
/* FPSCR_REGS:  */                                                      \
1458
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 },       \
1459
/* GENERAL_FP_REGS:  */                                                 \
1460
  { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 },       \
1461
/* GENERAL_DF_REGS:  */                                                 \
1462
  { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 },       \
1463
/* TARGET_REGS:  */                                                     \
1464
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff },       \
1465
/* ALL_REGS:  */                                                        \
1466
  { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff },       \
1467
}
1468
 
1469
/* The same information, inverted:
1470
   Return the class number of the smallest class containing
1471
   reg number REGNO.  This could be a conditional expression
1472
   or could index an array.  */
1473
 
1474
extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1475
#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1476
 
1477
/* When defined, the compiler allows registers explicitly used in the
1478
   rtl to be used as spill registers but prevents the compiler from
1479
   extending the lifetime of these registers.  */
1480
 
1481
#define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1482
 
1483
/* The order in which register should be allocated.  */
1484
/* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1485
   and GENERAL_FP_REGS the alternate class.  Since FP0 is likely to be
1486
   spilled or used otherwise, we better have the FP_REGS allocated first.  */
1487
#define REG_ALLOC_ORDER \
1488
  {/* Caller-saved FPRs */ \
1489
    65, 66, 67, 68, 69, 70, 71, 64, \
1490
    72, 73, 74, 75, 80, 81, 82, 83, \
1491
    84, 85, 86, 87, 88, 89, 90, 91, \
1492
    92, 93, 94, 95, 96, 97, 98, 99, \
1493
   /* Callee-saved FPRs */ \
1494
    76, 77, 78, 79,100,101,102,103, \
1495
   104,105,106,107,108,109,110,111, \
1496
   112,113,114,115,116,117,118,119, \
1497
   120,121,122,123,124,125,126,127, \
1498
   136,137,138,139,140,141,142,143, \
1499
   /* FPSCR */ 151, \
1500
   /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1501
     1,  2,  3,  7,  6,  5,  4,  0, \
1502
     8,  9, 17, 19, 20, 21, 22, 23, \
1503
    36, 37, 38, 39, 40, 41, 42, 43, \
1504
    60, 61, 62, \
1505
   /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1506
    10, 11, 12, 13, 14, 18, \
1507
    /* SH5 callee-saved GPRs */ \
1508
    28, 29, 30, 31, 32, 33, 34, 35, \
1509
    44, 45, 46, 47, 48, 49, 50, 51, \
1510
    52, 53, 54, 55, 56, 57, 58, 59, \
1511
   /* FPUL */ 150, \
1512
   /* SH5 branch target registers */ \
1513
   128,129,130,131,132,133,134,135, \
1514
   /* Fixed registers */ \
1515
    15, 16, 24, 25, 26, 27, 63,144, \
1516
   145,146,147,148,149,152,153 }
1517
 
1518
/* The class value for index registers, and the one for base regs.  */
1519
#define INDEX_REG_CLASS \
1520
  (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1521
#define BASE_REG_CLASS   GENERAL_REGS
1522
 
1523
/* Get reg_class from a letter such as appears in the machine
1524
   description.  */
1525
extern enum reg_class reg_class_from_letter[];
1526
 
1527
/* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1528
#define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1529
  (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1530
 
1531
/* Overview of uppercase letter constraints:
1532
   A: Addresses (constraint len == 3)
1533
    Ac4: sh4 cache operations
1534
    Ac5: sh5 cache operations
1535
   Bxx: miscellaneous constraints
1536
    Bsc: SCRATCH - for the scratch register in movsi_ie in the
1537
         fldi0 / fldi0 cases
1538
   C: Constants other than only CONST_INT (constraint len == 3)
1539
    Css: signed 16 bit constant, literal or symbolic
1540
    Csu: unsigned 16 bit constant, literal or symbolic
1541
    Csy: label or symbol
1542
    Cpg: non-explicit constants that can be directly loaded into a general
1543
         purpose register in PIC code.  like 's' except we don't allow
1544
         PIC_DIRECT_ADDR_P
1545
   IJKLMNOP: CONT_INT constants
1546
    Ixx: signed xx bit
1547
    J16: 0xffffffff00000000 | 0x00000000ffffffff
1548
    Kxx: unsigned xx bit
1549
    M: 1
1550
    N: 0
1551
    P27: 1 | 2 | 8 | 16
1552
   Q: pc relative load operand
1553
   Rxx: reserved for exotic register classes.
1554
   S: extra memory (storage) constraints (constraint len == 3)
1555
    Sua: unaligned memory operations
1556
   W: vector
1557
   Z: zero in any mode
1558
 
1559
   unused CONST_INT constraint letters: LO
1560
   unused EXTRA_CONSTRAINT letters: D T U Y */
1561
 
1562
#define CONSTRAINT_LEN(C,STR) \
1563
  (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1564
    || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1565
    || (C) == 'R' || (C) == 'S') \
1566
   ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1567
 
1568
/* The letters I, J, K, L and M in a register constraint string
1569
   can be used to stand for particular ranges of immediate operands.
1570
   This macro defines what the ranges are.
1571
   C is the letter, and VALUE is a constant value.
1572
   Return 1 if VALUE is in the range specified by C.
1573
        I08: arithmetic operand -127..128, as used in add, sub, etc
1574
        I16: arithmetic operand -32768..32767, as used in SHmedia movi
1575
        K16: arithmetic operand 0..65535, as used in SHmedia shori
1576
        P27: shift operand 1,2,8 or 16
1577
        K08: logical operand 0..255, as used in and, or, etc.
1578
        M: constant 1
1579
        N: constant 0
1580
        I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1581
        I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1582
*/
1583
 
1584
#define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1585
                                 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1586
#define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1587
                                 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1588
#define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1589
                                 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1590
#define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1591
                                 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1592
#define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
1593
                                 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
1594
                                 && TARGET_SH2A)
1595
#define CONST_OK_FOR_I(VALUE, STR) \
1596
  ((STR)[1] == '0' && (STR)[2] == '6' ? CONST_OK_FOR_I06 (VALUE) \
1597
   : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1598
   : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1599
   : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1600
   : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
1601
   : 0)
1602
 
1603
#define CONST_OK_FOR_J16(VALUE) \
1604
  ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1605
   || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1606
#define CONST_OK_FOR_J(VALUE, STR) \
1607
  ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1608
   : 0)
1609
 
1610
#define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1611
                                 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1612
#define CONST_OK_FOR_K16(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1613
                                 && ((HOST_WIDE_INT)(VALUE)) <= 65535)
1614
#define CONST_OK_FOR_K(VALUE, STR) \
1615
  ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1616
   : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_K16 (VALUE)      \
1617
   : 0)
1618
#define CONST_OK_FOR_P27(VALUE) \
1619
  ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1620
#define CONST_OK_FOR_P(VALUE, STR) \
1621
  ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1622
   : 0)
1623
#define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1624
#define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1625
#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR)        \
1626
     ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR))      \
1627
    : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR))      \
1628
    : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR))      \
1629
    : (C) == 'M' ? CONST_OK_FOR_M (VALUE)               \
1630
    : (C) == 'N' ? CONST_OK_FOR_N (VALUE)               \
1631
    : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR))      \
1632
    : 0)
1633
 
1634
/* Similar, but for floating constants, and defining letters G and H.
1635
   Here VALUE is the CONST_DOUBLE rtx itself.  */
1636
 
1637
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)          \
1638
((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ())   \
1639
 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ())  \
1640
 : (C) == 'F')
1641
 
1642
/* Given an rtx X being reloaded into a reg required to be
1643
   in class CLASS, return the class of reg to actually use.
1644
   In general this is just CLASS; but on some machines
1645
   in some cases it is preferable to use a more restrictive class.  */
1646
 
1647
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1648
  ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1649
   && (GET_CODE (X) == CONST_DOUBLE \
1650
       || GET_CODE (X) == SYMBOL_REF \
1651
       || PIC_DIRECT_ADDR_P (X)) \
1652
   ? GENERAL_REGS \
1653
   : (CLASS)) \
1654
 
1655
#if 0
1656
#define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1657
  ((((REGCLASS_HAS_FP_REG (CLASS)                                       \
1658
      && (GET_CODE (X) == REG                                           \
1659
      && (GENERAL_OR_AP_REGISTER_P (REGNO (X))                          \
1660
          || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode             \
1661
              && TARGET_FMOVD))))                                       \
1662
     || (REGCLASS_HAS_GENERAL_REG (CLASS)                               \
1663
         && GET_CODE (X) == REG                                         \
1664
         && FP_REGISTER_P (REGNO (X))))                                 \
1665
    && ! TARGET_SHMEDIA                                                 \
1666
    && ((MODE) == SFmode || (MODE) == SImode))                          \
1667
   ? FPUL_REGS                                                          \
1668
   : (((CLASS) == FPUL_REGS                                             \
1669
       || (REGCLASS_HAS_FP_REG (CLASS)                                  \
1670
           && ! TARGET_SHMEDIA && MODE == SImode))                      \
1671
      && (GET_CODE (X) == MEM                                           \
1672
          || (GET_CODE (X) == REG                                       \
1673
              && (REGNO (X) >= FIRST_PSEUDO_REGISTER                    \
1674
                  || REGNO (X) == T_REG                                 \
1675
                  || system_reg_operand (X, VOIDmode)))))               \
1676
   ? GENERAL_REGS                                                       \
1677
   : (((CLASS) == TARGET_REGS                                           \
1678
       || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))                  \
1679
      && !EXTRA_CONSTRAINT_Csy (X)                                      \
1680
      && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X))))     \
1681
   ? GENERAL_REGS                                                       \
1682
   : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS)                       \
1683
      && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X))        \
1684
      && (CLASS) != REGNO_REG_CLASS (REGNO (X)))                        \
1685
   ? GENERAL_REGS                                                       \
1686
   : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG                    \
1687
      && TARGET_REGISTER_P (REGNO (X)))                                 \
1688
   ? GENERAL_REGS : (ELSE))
1689
 
1690
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1691
 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1692
 
1693
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X)  \
1694
  ((REGCLASS_HAS_FP_REG (CLASS)                                         \
1695
    && ! TARGET_SHMEDIA                                                 \
1696
    && immediate_operand ((X), (MODE))                                  \
1697
    && ! ((fp_zero_operand (X) || fp_one_operand (X))                   \
1698
          && (MODE) == SFmode && fldi_ok ()))                           \
1699
   ? R0_REGS                                                            \
1700
   : ((CLASS) == FPUL_REGS                                              \
1701
      && ((GET_CODE (X) == REG                                          \
1702
           && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG           \
1703
               || REGNO (X) == T_REG))                                  \
1704
          || GET_CODE (X) == PLUS))                                     \
1705
   ? GENERAL_REGS                                                       \
1706
   : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE))            \
1707
   ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X))        \
1708
      ? GENERAL_REGS                                                    \
1709
      : R0_REGS)                                                        \
1710
   : ((CLASS) == FPSCR_REGS                                             \
1711
      && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER)   \
1712
          || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1713
   ? GENERAL_REGS                                                       \
1714
   : (REGCLASS_HAS_FP_REG (CLASS)                                       \
1715
      && TARGET_SHMEDIA                                                 \
1716
      && immediate_operand ((X), (MODE))                                \
1717
      && (X) != CONST0_RTX (GET_MODE (X))                               \
1718
      && GET_MODE (X) != V4SFmode)                                      \
1719
   ? GENERAL_REGS                                                       \
1720
   : (((MODE) == QImode || (MODE) == HImode)                            \
1721
      && TARGET_SHMEDIA && inqhi_operand ((X), (MODE)))                 \
1722
   ? GENERAL_REGS                                                       \
1723
   : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS                         \
1724
      && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X)))          \
1725
   ? TARGET_REGS                                                        \
1726
   : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1727
#else
1728
#define HAVE_SECONDARY_RELOADS
1729
#endif
1730
 
1731
/* Return the maximum number of consecutive registers
1732
   needed to represent mode MODE in a register of class CLASS.
1733
 
1734
   If TARGET_SHMEDIA, we need two FP registers per word.
1735
   Otherwise we will need at most one register per word.  */
1736
#define CLASS_MAX_NREGS(CLASS, MODE) \
1737
    (TARGET_SHMEDIA \
1738
     && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1739
     ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1740
     : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1741
 
1742
/* If defined, gives a class of registers that cannot be used as the
1743
   operand of a SUBREG that changes the mode of the object illegally.  */
1744
/* ??? We need to renumber the internal numbers for the frnn registers
1745
   when in little endian in order to allow mode size changes.  */
1746
 
1747
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)                           \
1748
  sh_cannot_change_mode_class (FROM, TO, CLASS)
1749
 
1750
/* Stack layout; function entry, exit and calling.  */
1751
 
1752
/* Define the number of registers that can hold parameters.
1753
   These macros are used only in other macro definitions below.  */
1754
 
1755
#define NPARM_REGS(MODE) \
1756
  (TARGET_FPU_ANY && (MODE) == SFmode \
1757
   ? (TARGET_SH5 ? 12 : 8) \
1758
   : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1759
                    || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1760
   ? (TARGET_SH5 ? 12 : 8) \
1761
   : (TARGET_SH5 ? 8 : 4))
1762
 
1763
#define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1764
#define FIRST_RET_REG  (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1765
 
1766
#define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1767
#define FIRST_FP_RET_REG FIRST_FP_REG
1768
 
1769
/* Define this if pushing a word on the stack
1770
   makes the stack pointer a smaller address.  */
1771
#define STACK_GROWS_DOWNWARD
1772
 
1773
/*  Define this macro to nonzero if the addresses of local variable slots
1774
    are at negative offsets from the frame pointer.  */
1775
#define FRAME_GROWS_DOWNWARD 1
1776
 
1777
/* Offset from the frame pointer to the first local variable slot to
1778
   be allocated.  */
1779
#define STARTING_FRAME_OFFSET  0
1780
 
1781
/* If we generate an insn to push BYTES bytes,
1782
   this says how many the stack pointer really advances by.  */
1783
/* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1784
   When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1785
   do correct alignment.  */
1786
#if 0
1787
#define PUSH_ROUNDING(NPUSHED)  (((NPUSHED) + 3) & ~3)
1788
#endif
1789
 
1790
/* Offset of first parameter from the argument pointer register value.  */
1791
#define FIRST_PARM_OFFSET(FNDECL)  0
1792
 
1793
/* Value is the number of byte of arguments automatically
1794
   popped when returning from a subroutine call.
1795
   FUNDECL is the declaration node of the function (as a tree),
1796
   FUNTYPE is the data type of the function (as a tree),
1797
   or for a library call it is an identifier node for the subroutine name.
1798
   SIZE is the number of bytes of arguments passed on the stack.
1799
 
1800
   On the SH, the caller does not pop any of its arguments that were passed
1801
   on the stack.  */
1802
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)  0
1803
 
1804
/* Value is the number of bytes of arguments automatically popped when
1805
   calling a subroutine.
1806
   CUM is the accumulated argument list.
1807
 
1808
   On SHcompact, the call trampoline pops arguments off the stack.  */
1809
#define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1810
 
1811
/* Some subroutine macros specific to this machine.  */
1812
 
1813
#define BASE_RETURN_VALUE_REG(MODE) \
1814
  ((TARGET_FPU_ANY && ((MODE) == SFmode))                       \
1815
   ? FIRST_FP_RET_REG                                   \
1816
   : TARGET_FPU_ANY && (MODE) == SCmode         \
1817
   ? FIRST_FP_RET_REG                                   \
1818
   : (TARGET_FPU_DOUBLE                                 \
1819
      && ((MODE) == DFmode || (MODE) == SFmode          \
1820
          || (MODE) == DCmode || (MODE) == SCmode ))    \
1821
   ? FIRST_FP_RET_REG                                   \
1822
   : FIRST_RET_REG)
1823
 
1824
#define BASE_ARG_REG(MODE) \
1825
  ((TARGET_SH2E && ((MODE) == SFmode))                  \
1826
   ? FIRST_FP_PARM_REG                                  \
1827
   : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1828
                    || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1829
   ? FIRST_FP_PARM_REG                                  \
1830
   : FIRST_PARM_REG)
1831
 
1832
/* Define how to find the value returned by a function.
1833
   VALTYPE is the data type of the value (as a tree).
1834
   If the precise function being called is known, FUNC is its FUNCTION_DECL;
1835
   otherwise, FUNC is 0.
1836
   For the SH, this is like LIBCALL_VALUE, except that we must change the
1837
   mode like PROMOTE_MODE does.
1838
   ??? PROMOTE_MODE is ignored for non-scalar types.  The set of types
1839
   tested here has to be kept in sync with the one in explow.c:promote_mode.  */
1840
 
1841
#define FUNCTION_VALUE(VALTYPE, FUNC)                                   \
1842
  gen_rtx_REG (                                                         \
1843
           ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT           \
1844
             && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4                 \
1845
             && (TREE_CODE (VALTYPE) == INTEGER_TYPE                    \
1846
                 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE                \
1847
                 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE                 \
1848
                 || TREE_CODE (VALTYPE) == REAL_TYPE                    \
1849
                 || TREE_CODE (VALTYPE) == OFFSET_TYPE))                \
1850
             && sh_promote_prototypes (VALTYPE)                         \
1851
            ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1852
           BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1853
 
1854
/* Define how to find the value returned by a library function
1855
   assuming the value has mode MODE.  */
1856
#define LIBCALL_VALUE(MODE) \
1857
  gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1858
 
1859
/* 1 if N is a possible register number for a function value.  */
1860
#define FUNCTION_VALUE_REGNO_P(REGNO) \
1861
  ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1862
   || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1863
 
1864
/* 1 if N is a possible register number for function argument passing.  */
1865
/* ??? There are some callers that pass REGNO as int, and others that pass
1866
   it as unsigned.  We get warnings unless we do casts everywhere.  */
1867
#define FUNCTION_ARG_REGNO_P(REGNO) \
1868
  (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG                     \
1869
    && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1870
   || (TARGET_FPU_ANY                                                   \
1871
       && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG            \
1872
       && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG            \
1873
                                           + NPARM_REGS (SFmode))))
1874
 
1875
/* Define a data type for recording info about an argument list
1876
   during the scan of that argument list.  This data type should
1877
   hold all necessary information about the function itself
1878
   and about the args processed so far, enough to enable macros
1879
   such as FUNCTION_ARG to determine where the next arg should go.
1880
 
1881
   On SH, this is a single integer, which is a number of words
1882
   of arguments scanned so far (including the invisible argument,
1883
   if any, which holds the structure-value-address).
1884
   Thus NARGREGS or more means all following args should go on the stack.  */
1885
 
1886
enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1887
struct sh_args {
1888
    int arg_count[2];
1889
    int force_mem;
1890
  /* Nonzero if a prototype is available for the function.  */
1891
    int prototype_p;
1892
  /* The number of an odd floating-point register, that should be used
1893
     for the next argument of type float.  */
1894
    int free_single_fp_reg;
1895
  /* Whether we're processing an outgoing function call.  */
1896
    int outgoing;
1897
  /* The number of general-purpose registers that should have been
1898
     used to pass partial arguments, that are passed totally on the
1899
     stack.  On SHcompact, a call trampoline will pop them off the
1900
     stack before calling the actual function, and, if the called
1901
     function is implemented in SHcompact mode, the incoming arguments
1902
     decoder will push such arguments back onto the stack.  For
1903
     incoming arguments, STACK_REGS also takes into account other
1904
     arguments passed by reference, that the decoder will also push
1905
     onto the stack.  */
1906
    int stack_regs;
1907
  /* The number of general-purpose registers that should have been
1908
     used to pass arguments, if the arguments didn't have to be passed
1909
     by reference.  */
1910
    int byref_regs;
1911
  /* Set as by shcompact_byref if the current argument is to be passed
1912
     by reference.  */
1913
    int byref;
1914
 
1915
  /* call_cookie is a bitmask used by call expanders, as well as
1916
     function prologue and epilogues, to allow SHcompact to comply
1917
     with the SH5 32-bit ABI, that requires 64-bit registers to be
1918
     used even though only the lower 32-bit half is visible in
1919
     SHcompact mode.  The strategy is to call SHmedia trampolines.
1920
 
1921
     The alternatives for each of the argument-passing registers are
1922
     (a) leave it unchanged; (b) pop it off the stack; (c) load its
1923
     contents from the address in it; (d) add 8 to it, storing the
1924
     result in the next register, then (c); (e) copy it from some
1925
     floating-point register,
1926
 
1927
     Regarding copies from floating-point registers, r2 may only be
1928
     copied from dr0.  r3 may be copied from dr0 or dr2.  r4 maybe
1929
     copied from dr0, dr2 or dr4.  r5 maybe copied from dr0, dr2,
1930
     dr4 or dr6.  r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1931
     r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1932
     dr10.
1933
 
1934
     The bit mask is structured as follows:
1935
 
1936
     - 1 bit to tell whether to set up a return trampoline.
1937
 
1938
     - 3 bits to count the number consecutive registers to pop off the
1939
       stack.
1940
 
1941
     - 4 bits for each of r9, r8, r7 and r6.
1942
 
1943
     - 3 bits for each of r5, r4, r3 and r2.
1944
 
1945
     - 3 bits set to 0 (the most significant ones)
1946
 
1947
        3           2            1           0
1948
       1098 7654 3210 9876 5432 1098 7654 3210
1949
       FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1950
       2223 3344 4555 6666 7777 8888 9999 SSS-
1951
 
1952
     - If F is set, the register must be copied from an FP register,
1953
       whose number is encoded in the remaining bits.
1954
 
1955
     - Else, if L is set, the register must be loaded from the address
1956
       contained in it.  If the P bit is *not* set, the address of the
1957
       following dword should be computed first, and stored in the
1958
       following register.
1959
 
1960
     - Else, if P is set, the register alone should be popped off the
1961
       stack.
1962
 
1963
     - After all this processing, the number of registers represented
1964
       in SSS will be popped off the stack.  This is an optimization
1965
       for pushing/popping consecutive registers, typically used for
1966
       varargs and large arguments partially passed in registers.
1967
 
1968
     - If T is set, a return trampoline will be set up for 64-bit
1969
     return values to be split into 2 32-bit registers.  */
1970
#define CALL_COOKIE_RET_TRAMP_SHIFT 0
1971
#define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1972
#define CALL_COOKIE_STACKSEQ_SHIFT 1
1973
#define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1974
#define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1975
  (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1976
#define CALL_COOKIE_INT_REG_SHIFT(REG) \
1977
  (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1978
#define CALL_COOKIE_INT_REG(REG, VAL) \
1979
  ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1980
#define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1981
  (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1982
    long call_cookie;
1983
 
1984
  /* This is set to nonzero when the call in question must use the Renesas ABI,
1985
     even without the -mrenesas option.  */
1986
    int renesas_abi;
1987
};
1988
 
1989
#define CUMULATIVE_ARGS  struct sh_args
1990
 
1991
#define GET_SH_ARG_CLASS(MODE) \
1992
  ((TARGET_FPU_ANY && (MODE) == SFmode) \
1993
   ? SH_ARG_FLOAT \
1994
   /* There's no mention of complex float types in the SH5 ABI, so we
1995
      should presumably handle them as aggregate types.  */ \
1996
   : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1997
   ? SH_ARG_INT \
1998
   : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1999
                           || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
2000
   ? SH_ARG_FLOAT : SH_ARG_INT)
2001
 
2002
#define ROUND_ADVANCE(SIZE) \
2003
  (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2004
 
2005
/* Round a register number up to a proper boundary for an arg of mode
2006
   MODE.
2007
 
2008
   The SH doesn't care about double alignment, so we only
2009
   round doubles to even regs when asked to explicitly.  */
2010
 
2011
#define ROUND_REG(CUM, MODE) \
2012
   (((TARGET_ALIGN_DOUBLE                                       \
2013
      || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode)  \
2014
          && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
2015
     && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD)           \
2016
    ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]           \
2017
       + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1))  \
2018
    : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
2019
 
2020
/* Initialize a variable CUM of type CUMULATIVE_ARGS
2021
   for a call to a function whose data type is FNTYPE.
2022
   For a library call, FNTYPE is 0.
2023
 
2024
   On SH, the offset always starts at 0: the first parm reg is always
2025
   the same reg for a given argument class.
2026
 
2027
   For TARGET_HITACHI, the structure value pointer is passed in memory.  */
2028
 
2029
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
2030
  sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
2031
 
2032
#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
2033
  sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
2034
 
2035
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)    \
2036
        sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
2037
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)    \
2038
        sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
2039
 
2040
/* Return boolean indicating arg of mode MODE will be passed in a reg.
2041
   This macro is only used in this file.  */
2042
 
2043
#define PASS_IN_REG_P(CUM, MODE, TYPE) \
2044
  (((TYPE) == 0 \
2045
    || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2046
        && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2047
            || ! (AGGREGATE_TYPE_P (TYPE) \
2048
                  || (!TARGET_FPU_ANY \
2049
                      && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2050
                          && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2051
   && ! (CUM).force_mem \
2052
   && (TARGET_SH2E \
2053
       ? ((MODE) == BLKmode \
2054
          ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2055
              + int_size_in_bytes (TYPE)) \
2056
             <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2057
          : ((ROUND_REG((CUM), (MODE)) \
2058
              + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2059
             <= NPARM_REGS (MODE))) \
2060
       : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2061
 
2062
/* By accident we got stuck with passing SCmode on SH4 little endian
2063
   in two registers that are nominally successive - which is different from
2064
   two single SFmode values, where we take endianness translation into
2065
   account.  That does not work at all if an odd number of registers is
2066
   already in use, so that got fixed, but library functions are still more
2067
   likely to use complex numbers without mixing them with SFmode arguments
2068
   (which in C would have to be structures), so for the sake of ABI
2069
   compatibility the way SCmode values are passed when an even number of
2070
   FP registers is in use remains different from a pair of SFmode values for
2071
   now.
2072
   I.e.:
2073
   foo (double); a: fr5,fr4
2074
   foo (float a, float b); a: fr5 b: fr4
2075
   foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2076
                            this should be the other way round...
2077
   foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7  */
2078
#define FUNCTION_ARG_SCmode_WART 1
2079
 
2080
/* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2081
   register in SHcompact mode, it must be padded in the most
2082
   significant end.  This means that passing it by reference wouldn't
2083
   pad properly on a big-endian machine.  In this particular case, we
2084
   pass this argument on the stack, in a way that the call trampoline
2085
   will load its value into the appropriate register.  */
2086
#define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2087
  ((MODE) == BLKmode \
2088
   && TARGET_SHCOMPACT \
2089
   && ! TARGET_LITTLE_ENDIAN \
2090
   && int_size_in_bytes (TYPE) > 4 \
2091
   && int_size_in_bytes (TYPE) < 8)
2092
 
2093
/* Minimum alignment for an argument to be passed by callee-copy
2094
   reference.  We need such arguments to be aligned to 8 byte
2095
   boundaries, because they'll be loaded using quad loads.  */
2096
#define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2097
 
2098
/* The SH5 ABI requires floating-point arguments to be passed to
2099
   functions without a prototype in both an FP register and a regular
2100
   register or the stack.  When passing the argument in both FP and
2101
   general-purpose registers, list the FP register first.  */
2102
#define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2103
  (gen_rtx_PARALLEL                                                     \
2104
   ((MODE),                                                             \
2105
    gen_rtvec (2,                                                       \
2106
               gen_rtx_EXPR_LIST                                        \
2107
               (VOIDmode,                                               \
2108
                ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2109
                 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG               \
2110
                                + (CUM).arg_count[(int) SH_ARG_FLOAT])  \
2111
                 : NULL_RTX),                                           \
2112
                const0_rtx),                                            \
2113
               gen_rtx_EXPR_LIST                                        \
2114
               (VOIDmode,                                               \
2115
                ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2116
                 ? gen_rtx_REG ((MODE), FIRST_PARM_REG                  \
2117
                                + (CUM).arg_count[(int) SH_ARG_INT])    \
2118
                 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG               \
2119
                                + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2120
                const0_rtx))))
2121
 
2122
/* The SH5 ABI requires regular registers or stack slots to be
2123
   reserved for floating-point arguments.  Registers are taken care of
2124
   in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2125
   Unfortunately, there's no way to just reserve a stack slot, so
2126
   we'll end up needlessly storing a copy of the argument in the
2127
   stack.  For incoming arguments, however, the PARALLEL will be
2128
   optimized to the register-only form, and the value in the stack
2129
   slot won't be used at all.  */
2130
#define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2131
  ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)              \
2132
   ? gen_rtx_REG ((MODE), (REG))                                        \
2133
   : gen_rtx_PARALLEL ((MODE),                                          \
2134
                       gen_rtvec (2,                                    \
2135
                                  gen_rtx_EXPR_LIST                     \
2136
                                  (VOIDmode, NULL_RTX,                  \
2137
                                   const0_rtx),                         \
2138
                                  gen_rtx_EXPR_LIST                     \
2139
                                  (VOIDmode, gen_rtx_REG ((MODE),       \
2140
                                                          (REG)),       \
2141
                                   const0_rtx))))
2142
 
2143
#define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2144
  (TARGET_SH5                                                   \
2145
   && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2146
       || (MODE) == DCmode) \
2147
   && ((CUM).arg_count[(int) SH_ARG_INT]                        \
2148
       + (((MODE) == BLKmode ? int_size_in_bytes (TYPE)         \
2149
                             : GET_MODE_SIZE (MODE))            \
2150
          + 7) / 8) > NPARM_REGS (SImode))
2151
 
2152
/* Perform any needed actions needed for a function that is receiving a
2153
   variable number of arguments.  */
2154
 
2155
/* Implement `va_start' for varargs and stdarg.  */
2156
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2157
  sh_va_start (valist, nextarg)
2158
 
2159
/* Call the function profiler with a given profile label.
2160
   We use two .aligns, so as to make sure that both the .long is aligned
2161
   on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2162
   from the trapa instruction.  */
2163
 
2164
#define FUNCTION_PROFILER(STREAM,LABELNO)                       \
2165
{                                                               \
2166
  if (TARGET_SHMEDIA)                                           \
2167
    {                                                           \
2168
      fprintf((STREAM), "\tmovi\t33,r0\n");                     \
2169
      fprintf((STREAM), "\ttrapa\tr0\n");                       \
2170
      asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO));    \
2171
    }                                                           \
2172
  else                                                          \
2173
    {                                                           \
2174
      fprintf((STREAM), "\t.align\t2\n");                       \
2175
      fprintf((STREAM), "\ttrapa\t#33\n");                      \
2176
      fprintf((STREAM), "\t.align\t2\n");                       \
2177
      asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO));    \
2178
    }                                                           \
2179
}
2180
 
2181
/* Define this macro if the code for function profiling should come
2182
   before the function prologue.  Normally, the profiling code comes
2183
   after.  */
2184
 
2185
#define PROFILE_BEFORE_PROLOGUE
2186
 
2187
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2188
   the stack pointer does not matter.  The value is tested only in
2189
   functions that have frame pointers.
2190
   No definition is equivalent to always zero.  */
2191
 
2192
#define EXIT_IGNORE_STACK 1
2193
 
2194
/*
2195
   On the SH, the trampoline looks like
2196
   2 0002 D202                  mov.l   l2,r2
2197
   1 0000 D301                  mov.l   l1,r3
2198
   3 0004 422B                  jmp     @r2
2199
   4 0006 0009                  nop
2200
   5 0008 00000000      l1:     .long   area
2201
   6 000c 00000000      l2:     .long   function  */
2202
 
2203
/* Length in units of the trampoline for entering a nested function.  */
2204
#define TRAMPOLINE_SIZE  (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2205
 
2206
/* Alignment required for a trampoline in bits .  */
2207
#define TRAMPOLINE_ALIGNMENT \
2208
  ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2209
   : TARGET_SHMEDIA ? 256 : 64)
2210
 
2211
/* Emit RTL insns to initialize the variable parts of a trampoline.
2212
   FNADDR is an RTX for the address of the function's pure code.
2213
   CXT is an RTX for the static chain value for the function.  */
2214
 
2215
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2216
  sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2217
 
2218
/* On SH5, trampolines are SHmedia code, so add 1 to the address.  */
2219
 
2220
#define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do                             \
2221
{                                                                       \
2222
  if (TARGET_SHMEDIA)                                                   \
2223
    (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx,    \
2224
                                   gen_reg_rtx (Pmode), 0,               \
2225
                                   OPTAB_LIB_WIDEN);                    \
2226
} while (0)
2227
 
2228
/* A C expression whose value is RTL representing the value of the return
2229
   address for the frame COUNT steps up from the current frame.
2230
   FRAMEADDR is already the frame pointer of the COUNT frame, so we
2231
   can ignore COUNT.  */
2232
 
2233
#define RETURN_ADDR_RTX(COUNT, FRAME)   \
2234
  (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2235
 
2236
/* A C expression whose value is RTL representing the location of the
2237
   incoming return address at the beginning of any function, before the
2238
   prologue.  This RTL is either a REG, indicating that the return
2239
   value is saved in REG, or a MEM representing a location in
2240
   the stack.  */
2241
#define INCOMING_RETURN_ADDR_RTX \
2242
  gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2243
 
2244
/* Addressing modes, and classification of registers for them.  */
2245
#define HAVE_POST_INCREMENT  TARGET_SH1
2246
#define HAVE_PRE_DECREMENT   TARGET_SH1
2247
 
2248
#define USE_LOAD_POST_INCREMENT(mode)    ((mode == SImode || mode == DImode) \
2249
                                           ? 0 : TARGET_SH1)
2250
#define USE_LOAD_PRE_DECREMENT(mode)     0
2251
#define USE_STORE_POST_INCREMENT(mode)   0
2252
#define USE_STORE_PRE_DECREMENT(mode)    ((mode == SImode || mode == DImode) \
2253
                                           ? 0 : TARGET_SH1)
2254
 
2255
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2256
  (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2257
   < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2258
 
2259
#define STORE_BY_PIECES_P(SIZE, ALIGN) \
2260
  (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2261
   < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2262
 
2263
/* Macros to check register numbers against specific register classes.  */
2264
 
2265
/* These assume that REGNO is a hard or pseudo reg number.
2266
   They give nonzero only if REGNO is a hard reg of the suitable class
2267
   or a pseudo reg currently allocated to a suitable hard reg.
2268
   Since they use reg_renumber, they are safe only once reg_renumber
2269
   has been allocated, which happens in local-alloc.c.  */
2270
 
2271
#define REGNO_OK_FOR_BASE_P(REGNO) \
2272
  (GENERAL_OR_AP_REGISTER_P (REGNO) \
2273
   || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2274
#define REGNO_OK_FOR_INDEX_P(REGNO) \
2275
  (TARGET_SHMEDIA \
2276
   ? (GENERAL_REGISTER_P (REGNO) \
2277
      || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2278
   : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2279
 
2280
/* Maximum number of registers that can appear in a valid memory
2281
   address.  */
2282
 
2283
#define MAX_REGS_PER_ADDRESS 2
2284
 
2285
/* Recognize any constant value that is a valid address.  */
2286
 
2287
#define CONSTANT_ADDRESS_P(X)   (GET_CODE (X) == LABEL_REF)
2288
 
2289
/* Nonzero if the constant value X is a legitimate general operand.  */
2290
 
2291
#define LEGITIMATE_CONSTANT_P(X) \
2292
  (TARGET_SHMEDIA                                                       \
2293
   ? ((GET_MODE (X) != DFmode                                           \
2294
       && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT)           \
2295
      || (X) == CONST0_RTX (GET_MODE (X))                               \
2296
      || ! TARGET_SHMEDIA_FPU                                           \
2297
      || TARGET_SHMEDIA64)                                              \
2298
   : (GET_CODE (X) != CONST_DOUBLE                                      \
2299
      || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode               \
2300
      || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2301
 
2302
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2303
   and check its validity for a certain class.
2304
   We have two alternate definitions for each of them.
2305
   The usual definition accepts all pseudo regs; the other rejects
2306
   them unless they have been allocated suitable hard regs.
2307
   The symbol REG_OK_STRICT causes the latter definition to be used.  */
2308
 
2309
#ifndef REG_OK_STRICT
2310
 
2311
/* Nonzero if X is a hard reg that can be used as a base reg
2312
   or if it is a pseudo reg.  */
2313
#define REG_OK_FOR_BASE_P(X) \
2314
  (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2315
 
2316
/* Nonzero if X is a hard reg that can be used as an index
2317
   or if it is a pseudo reg.  */
2318
#define REG_OK_FOR_INDEX_P(X) \
2319
  ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2320
    : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2321
 
2322
/* Nonzero if X/OFFSET is a hard reg that can be used as an index
2323
   or if X is a pseudo reg.  */
2324
#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2325
  ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2326
    : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2327
 
2328
#else
2329
 
2330
/* Nonzero if X is a hard reg that can be used as a base reg.  */
2331
#define REG_OK_FOR_BASE_P(X) \
2332
  REGNO_OK_FOR_BASE_P (REGNO (X))
2333
 
2334
/* Nonzero if X is a hard reg that can be used as an index.  */
2335
#define REG_OK_FOR_INDEX_P(X) \
2336
  REGNO_OK_FOR_INDEX_P (REGNO (X))
2337
 
2338
/* Nonzero if X/OFFSET is a hard reg that can be used as an index.  */
2339
#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2340
  (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2341
 
2342
#endif
2343
 
2344
/* The 'Q' constraint is a pc relative load operand.  */
2345
#define EXTRA_CONSTRAINT_Q(OP)                                          \
2346
  (GET_CODE (OP) == MEM                                                 \
2347
   && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF)                          \
2348
       || (GET_CODE (XEXP ((OP), 0)) == CONST                            \
2349
           && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS         \
2350
           && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2351
           && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2352
 
2353
/* Extra address constraints.  */
2354
#define EXTRA_CONSTRAINT_A(OP, STR) 0
2355
 
2356
/* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2357
   operand is not SCRATCH (i.e. REG) then R0 is probably being
2358
   used, hence mova is being used, hence do not select this pattern */
2359
#define EXTRA_CONSTRAINT_Bsc(OP)    (GET_CODE(OP) == SCRATCH)
2360
#define EXTRA_CONSTRAINT_B(OP, STR) \
2361
  ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2362
   : 0)
2363
 
2364
/* The `Css' constraint is a signed 16-bit constant, literal or symbolic.  */
2365
#define EXTRA_CONSTRAINT_Css(OP) \
2366
  (GET_CODE (OP) == CONST \
2367
   && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2368
   && (GET_MODE (XEXP ((OP), 0)) == DImode \
2369
       || GET_MODE (XEXP ((OP), 0)) == SImode) \
2370
   && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2371
   && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2372
   && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2373
       || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2374
           && (MOVI_SHORI_BASE_OPERAND_P \
2375
               (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2376
           && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2377
                              1)) == CONST_INT)))
2378
 
2379
/* The `Csu' constraint is an unsigned 16-bit constant, literal or symbolic.  */
2380
#define EXTRA_CONSTRAINT_Csu(OP) \
2381
  (GET_CODE (OP) == CONST \
2382
   && GET_CODE (XEXP ((OP), 0)) == ZERO_EXTEND \
2383
   && (GET_MODE (XEXP ((OP), 0)) == DImode \
2384
       || GET_MODE (XEXP ((OP), 0)) == SImode) \
2385
   && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2386
   && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2387
   && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2388
       || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2389
           && (MOVI_SHORI_BASE_OPERAND_P \
2390
               (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2391
           && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2392
                              1)) == CONST_INT)))
2393
 
2394
/* Check whether OP is a datalabel unspec.  */
2395
#define DATALABEL_REF_NO_CONST_P(OP) \
2396
  (GET_CODE (OP) == UNSPEC \
2397
   && XINT ((OP), 1) == UNSPEC_DATALABEL \
2398
   && XVECLEN ((OP), 0) == 1 \
2399
   && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2400
 
2401
#define GOT_ENTRY_P(OP) \
2402
  (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2403
   && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2404
 
2405
#define GOTPLT_ENTRY_P(OP) \
2406
  (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2407
   && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2408
 
2409
#define UNSPEC_GOTOFF_P(OP) \
2410
  (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2411
 
2412
#define GOTOFF_P(OP) \
2413
  (GET_CODE (OP) == CONST \
2414
   && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2415
       || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2416
           && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2417
           && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2418
 
2419
#define PIC_ADDR_P(OP) \
2420
  (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2421
   && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2422
 
2423
#define PIC_OFFSET_P(OP) \
2424
  (PIC_ADDR_P (OP) \
2425
   && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2426
   && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2427
 
2428
#define PIC_DIRECT_ADDR_P(OP) \
2429
  (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2430
 
2431
#define NON_PIC_REFERENCE_P(OP) \
2432
  (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2433
   || (GET_CODE (OP) == CONST \
2434
       && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2435
           || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2436
           || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2437
   || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2438
       && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2439
           || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2440
           || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2441
       && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2442
 
2443
#define PIC_REFERENCE_P(OP) \
2444
  (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2445
   || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2446
 
2447
#define MOVI_SHORI_BASE_OPERAND_P(OP) \
2448
  (flag_pic \
2449
   ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP)  || GOTOFF_P (OP) \
2450
      || PIC_OFFSET_P (OP)) \
2451
   : NON_PIC_REFERENCE_P (OP))
2452
 
2453
/* The `Csy' constraint is a label or a symbol.  */
2454
#define EXTRA_CONSTRAINT_Csy(OP) \
2455
  (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2456
 
2457
/* A zero in any shape or form.  */
2458
#define EXTRA_CONSTRAINT_Z(OP) \
2459
  ((OP) == CONST0_RTX (GET_MODE (OP)))
2460
 
2461
/* Any vector constant we can handle.  */
2462
#define EXTRA_CONSTRAINT_W(OP) \
2463
  (GET_CODE (OP) == CONST_VECTOR \
2464
   && (sh_rep_vec ((OP), VOIDmode) \
2465
       || (HOST_BITS_PER_WIDE_INT >= 64 \
2466
           ? sh_const_vec ((OP), VOIDmode) \
2467
           : sh_1el_vec ((OP), VOIDmode))))
2468
 
2469
/* A non-explicit constant that can be loaded directly into a general purpose
2470
   register.  This is like 's' except we don't allow PIC_DIRECT_ADDR_P.  */
2471
#define EXTRA_CONSTRAINT_Cpg(OP) \
2472
  (CONSTANT_P (OP) \
2473
   && GET_CODE (OP) != CONST_INT \
2474
   && GET_CODE (OP) != CONST_DOUBLE \
2475
   && (!flag_pic \
2476
       || (LEGITIMATE_PIC_OPERAND_P (OP) \
2477
        && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2478
        && GET_CODE (OP) != LABEL_REF)))
2479
#define EXTRA_CONSTRAINT_C(OP, STR) \
2480
  ((STR)[1] == 's' && (STR)[2] == 's' ? EXTRA_CONSTRAINT_Css (OP) \
2481
   : (STR)[1] == 's' && (STR)[2] == 'u' ? EXTRA_CONSTRAINT_Csu (OP) \
2482
   : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2483
   : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2484
   : 0)
2485
 
2486
#define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2487
#define EXTRA_CONSTRAINT_Sr0(OP) \
2488
  (memory_operand((OP), GET_MODE (OP)) \
2489
   && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2490
#define EXTRA_CONSTRAINT_Sua(OP) \
2491
  (memory_operand((OP), GET_MODE (OP)) \
2492
   && GET_CODE (XEXP (OP, 0)) != PLUS)
2493
#define EXTRA_CONSTRAINT_S(OP, STR) \
2494
  ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2495
   : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2496
   : 0)
2497
 
2498
#define EXTRA_CONSTRAINT_STR(OP, C, STR)                \
2499
  ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2500
   : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2501
   : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2502
   : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2503
   : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2504
   : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2505
   : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2506
   : 0)
2507
 
2508
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2509
   that is a valid memory address for an instruction.
2510
   The MODE argument is the machine mode for the MEM expression
2511
   that wants to use this address.  */
2512
 
2513
#define MODE_DISP_OK_4(X,MODE) \
2514
(GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64        \
2515
 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2516
 
2517
#define MODE_DISP_OK_8(X,MODE) \
2518
((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60)   \
2519
 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2520
 
2521
#undef MODE_DISP_OK_4
2522
#define MODE_DISP_OK_4(X,MODE) \
2523
((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64       \
2524
  && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2525
  || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383)   \
2526
  && ! (INTVAL(X) & 3) && TARGET_SH2A))
2527
 
2528
#undef MODE_DISP_OK_8
2529
#define MODE_DISP_OK_8(X,MODE) \
2530
(((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60)  \
2531
  && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2532
 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192)     \
2533
  && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2534
 
2535
#define BASE_REGISTER_RTX_P(X)                          \
2536
  ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))       \
2537
   || (GET_CODE (X) == SUBREG                           \
2538
       && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2539
                                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2540
       && GET_CODE (SUBREG_REG (X)) == REG              \
2541
       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2542
 
2543
/* Since this must be r0, which is a single register class, we must check
2544
   SUBREGs more carefully, to be sure that we don't accept one that extends
2545
   outside the class.  */
2546
#define INDEX_REGISTER_RTX_P(X)                         \
2547
  ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))      \
2548
   || (GET_CODE (X) == SUBREG                           \
2549
       && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2550
                                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2551
       && GET_CODE (SUBREG_REG (X)) == REG              \
2552
       && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2553
 
2554
/* Jump to LABEL if X is a valid address RTX.  This must also take
2555
   REG_OK_STRICT into account when deciding about valid registers, but it uses
2556
   the above macros so we are in luck.
2557
 
2558
   Allow  REG
2559
          REG+disp
2560
          REG+r0
2561
          REG++
2562
          --REG  */
2563
 
2564
/* ??? The SH2e does not have the REG+disp addressing mode when loading values
2565
   into the FRx registers.  We implement this by setting the maximum offset
2566
   to zero when the value is SFmode.  This also restricts loading of SFmode
2567
   values into the integer registers, but that can't be helped.  */
2568
 
2569
/* The SH allows a displacement in a QI or HI amode, but only when the
2570
   other operand is R0. GCC doesn't handle this very well, so we forgo
2571
   all of that.
2572
 
2573
   A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2574
   DI can be any number 0..60.  */
2575
 
2576
#define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL)                         \
2577
  do {                                                                  \
2578
    if (GET_CODE (OP) == CONST_INT)                                     \
2579
      {                                                                 \
2580
        if (TARGET_SHMEDIA)                                             \
2581
          {                                                             \
2582
            int MODE_SIZE;                                              \
2583
            /* Check if this the address of an unaligned load / store.  */\
2584
            if ((MODE) == VOIDmode)                                     \
2585
             {                                                          \
2586
              if (CONST_OK_FOR_I06 (INTVAL (OP)))                       \
2587
                goto LABEL;                                             \
2588
              break;                                                    \
2589
             }                                                          \
2590
            MODE_SIZE = GET_MODE_SIZE (MODE);                           \
2591
            if (! (INTVAL (OP) & (MODE_SIZE - 1))                       \
2592
                && INTVAL (OP) >= -512 * MODE_SIZE                      \
2593
                && INTVAL (OP) < 512 * MODE_SIZE)                       \
2594
              goto LABEL;                                               \
2595
            else                                                        \
2596
              break;                                                    \
2597
          }                                                             \
2598
        if (MODE_DISP_OK_4 ((OP), (MODE)))  goto LABEL;                 \
2599
        if (MODE_DISP_OK_8 ((OP), (MODE)))  goto LABEL;                 \
2600
      }                                                                 \
2601
  } while(0)
2602
 
2603
#define ALLOW_INDEXED_ADDRESS \
2604
  ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2605
 
2606
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)                        \
2607
{                                                                       \
2608
  if (BASE_REGISTER_RTX_P (X))                                          \
2609
    goto LABEL;                                                         \
2610
  else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC)        \
2611
           && ! TARGET_SHMEDIA                                          \
2612
           && BASE_REGISTER_RTX_P (XEXP ((X), 0)))                       \
2613
    goto LABEL;                                                         \
2614
  else if (GET_CODE (X) == PLUS                                         \
2615
           && ((MODE) != PSImode || reload_completed))                  \
2616
    {                                                                   \
2617
      rtx xop0 = XEXP ((X), 0);                                          \
2618
      rtx xop1 = XEXP ((X), 1);                                         \
2619
      if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0))      \
2620
        GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL);                   \
2621
      if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode              \
2622
           || ((xop0 == stack_pointer_rtx                               \
2623
                || xop0 == hard_frame_pointer_rtx)                      \
2624
               && REG_P (xop1) && REGNO (xop1) == R0_REG)               \
2625
           || ((xop1 == stack_pointer_rtx                               \
2626
                || xop1 == hard_frame_pointer_rtx)                      \
2627
               && REG_P (xop0) && REGNO (xop0) == R0_REG))              \
2628
          && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4)            \
2629
              || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8)          \
2630
              || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)                    \
2631
                  && TARGET_FMOVD && MODE == DFmode)))                  \
2632
        {                                                               \
2633
          if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2634
            goto LABEL;                                                 \
2635
          if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2636
            goto LABEL;                                                 \
2637
        }                                                               \
2638
    }                                                                   \
2639
}
2640
 
2641
/* Try machine-dependent ways of modifying an illegitimate address
2642
   to be legitimate.  If we find one, return the new, valid address.
2643
   This macro is used in only one place: `memory_address' in explow.c.
2644
 
2645
   OLDX is the address as it was before break_out_memory_refs was called.
2646
   In some cases it is useful to look at this to decide what needs to be done.
2647
 
2648
   MODE and WIN are passed so that this macro can use
2649
   GO_IF_LEGITIMATE_ADDRESS.
2650
 
2651
   It is always safe for this macro to do nothing.  It exists to recognize
2652
   opportunities to optimize the output.
2653
 
2654
   For the SH, if X is almost suitable for indexing, but the offset is
2655
   out of range, convert it into a normal form so that cse has a chance
2656
   of reducing the number of address registers used.  */
2657
 
2658
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)                     \
2659
{                                                               \
2660
  if (flag_pic)                                                 \
2661
    (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);        \
2662
  if (GET_CODE (X) == PLUS                                      \
2663
      && (GET_MODE_SIZE (MODE) == 4                             \
2664
          || GET_MODE_SIZE (MODE) == 8)                         \
2665
      && GET_CODE (XEXP ((X), 1)) == CONST_INT                  \
2666
      && BASE_REGISTER_RTX_P (XEXP ((X), 0))                     \
2667
      && ! TARGET_SHMEDIA                                       \
2668
      && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode)                     \
2669
      && ! (TARGET_SH2E && (MODE) == SFmode))                   \
2670
    {                                                           \
2671
      rtx index_rtx = XEXP ((X), 1);                            \
2672
      HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;   \
2673
      rtx sum;                                                  \
2674
                                                                \
2675
      GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN);          \
2676
      /* On rare occasions, we might get an unaligned pointer   \
2677
         that is indexed in a way to give an aligned address.   \
2678
         Therefore, keep the lower two bits in offset_base.  */ \
2679
      /* Instead of offset_base 128..131 use 124..127, so that  \
2680
         simple add suffices.  */                               \
2681
      if (offset > 127)                                         \
2682
        {                                                       \
2683
          offset_base = ((offset + 4) & ~60) - 4;               \
2684
        }                                                       \
2685
      else                                                      \
2686
        offset_base = offset & ~60;                             \
2687
      /* Sometimes the normal form does not suit DImode.  We    \
2688
         could avoid that by using smaller ranges, but that     \
2689
         would give less optimized code when SImode is          \
2690
         prevalent.  */                                         \
2691
      if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64)    \
2692
        {                                                       \
2693
          sum = expand_binop (Pmode, add_optab, XEXP ((X), 0),   \
2694
                              GEN_INT (offset_base), NULL_RTX, 0, \
2695
                              OPTAB_LIB_WIDEN);                 \
2696
                                                                \
2697
          (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2698
          goto WIN;                                             \
2699
        }                                                       \
2700
    }                                                           \
2701
}
2702
 
2703
/* A C compound statement that attempts to replace X, which is an address
2704
   that needs reloading, with a valid memory address for an operand of
2705
   mode MODE.  WIN is a C statement label elsewhere in the code.
2706
 
2707
   Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2708
   of the address.  That will allow inheritance of the address reloads.  */
2709
 
2710
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)     \
2711
{                                                                       \
2712
  if (GET_CODE (X) == PLUS                                              \
2713
      && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8)       \
2714
      && GET_CODE (XEXP (X, 1)) == CONST_INT                            \
2715
      && BASE_REGISTER_RTX_P (XEXP (X, 0))                               \
2716
      && ! TARGET_SHMEDIA                                               \
2717
      && ! (TARGET_SH4 && (MODE) == DFmode)                             \
2718
      && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)    \
2719
      && (ALLOW_INDEXED_ADDRESS                                         \
2720
          || XEXP ((X), 0) == stack_pointer_rtx                          \
2721
          || XEXP ((X), 0) == hard_frame_pointer_rtx))                   \
2722
    {                                                                   \
2723
      rtx index_rtx = XEXP (X, 1);                                      \
2724
      HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;           \
2725
      rtx sum;                                                          \
2726
                                                                        \
2727
      if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7))            \
2728
        {                                                               \
2729
          push_reload (X, NULL_RTX, &X, NULL,                           \
2730
                       BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM),    \
2731
                       (TYPE));                                         \
2732
          goto WIN;                                                     \
2733
        }                                                               \
2734
      if (TARGET_SH2E && MODE == SFmode)                                \
2735
        {                                                               \
2736
          X = copy_rtx (X);                                             \
2737
          push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL,         \
2738
                       R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM),           \
2739
                       (TYPE));                                         \
2740
          goto WIN;                                                     \
2741
        }                                                               \
2742
      /* Instead of offset_base 128..131 use 124..127, so that          \
2743
         simple add suffices.  */                                       \
2744
      if (offset > 127)                                                 \
2745
        {                                                               \
2746
          offset_base = ((offset + 4) & ~60) - 4;                       \
2747
        }                                                               \
2748
      else                                                              \
2749
        offset_base = offset & ~60;                                     \
2750
      /* Sometimes the normal form does not suit DImode.  We            \
2751
         could avoid that by using smaller ranges, but that             \
2752
         would give less optimized code when SImode is                  \
2753
         prevalent.  */                                                 \
2754
      if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64)            \
2755
        {                                                               \
2756
          sum = gen_rtx_PLUS (Pmode, XEXP (X, 0),                        \
2757
                         GEN_INT (offset_base));                        \
2758
          X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2759
          push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL,                \
2760
                       BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM),    \
2761
                       (TYPE));                                         \
2762
          goto WIN;                                                     \
2763
        }                                                               \
2764
    }                                                                   \
2765
  /* We must re-recognize what we created before.  */                   \
2766
  else if (GET_CODE (X) == PLUS                                         \
2767
           && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8)  \
2768
           && GET_CODE (XEXP (X, 0)) == PLUS                             \
2769
           && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT              \
2770
           && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0))         \
2771
           && GET_CODE (XEXP (X, 1)) == CONST_INT                       \
2772
           && ! TARGET_SHMEDIA                                          \
2773
           && ! (TARGET_SH2E && MODE == SFmode))                        \
2774
    {                                                                   \
2775
      /* Because this address is so complex, we know it must have       \
2776
         been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,        \
2777
         it is already unshared, and needs no further unsharing.  */    \
2778
      push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2779
                   BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2780
      goto WIN;                                                         \
2781
    }                                                                   \
2782
}
2783
 
2784
/* Go to LABEL if ADDR (a legitimate address expression)
2785
   has an effect that depends on the machine mode it is used for.
2786
 
2787
   ??? Strictly speaking, we should also include all indexed addressing,
2788
   because the index scale factor is the length of the operand.
2789
   However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2790
   high if we did that.  So we rely on reload to fix things up.  */
2791
 
2792
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)                        \
2793
{                                                                       \
2794
  if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC)          \
2795
    goto LABEL;                                                         \
2796
}
2797
 
2798
/* Specify the machine mode that this machine uses
2799
   for the index in the tablejump instruction.  */
2800
#define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2801
 
2802
#define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2803
((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2804
 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2805
 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2806
 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2807
 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2808
 : SImode)
2809
 
2810
/* Define as C expression which evaluates to nonzero if the tablejump
2811
   instruction expects the table to contain offsets from the address of the
2812
   table.
2813
   Do not define this if the table should contain absolute addresses.  */
2814
#define CASE_VECTOR_PC_RELATIVE 1
2815
 
2816
/* Define it here, so that it doesn't get bumped to 64-bits on SHmedia.  */
2817
#define FLOAT_TYPE_SIZE 32
2818
 
2819
/* Since the SH2e has only `float' support, it is desirable to make all
2820
   floating point types equivalent to `float'.  */
2821
#define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2822
 
2823
#if defined(__SH2E__) || defined(__SH3E__) || defined( __SH4_SINGLE_ONLY__)
2824
#define LIBGCC2_DOUBLE_TYPE_SIZE 32
2825
#else
2826
#define LIBGCC2_DOUBLE_TYPE_SIZE 64
2827
#endif
2828
 
2829
/* 'char' is signed by default.  */
2830
#define DEFAULT_SIGNED_CHAR  1
2831
 
2832
/* The type of size_t unsigned int.  */
2833
#define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2834
 
2835
#undef  PTRDIFF_TYPE
2836
#define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2837
 
2838
#define WCHAR_TYPE "short unsigned int"
2839
#define WCHAR_TYPE_SIZE 16
2840
 
2841
#define SH_ELF_WCHAR_TYPE "long int"
2842
 
2843
/* Max number of bytes we can move from memory to memory
2844
   in one reasonably fast instruction.  */
2845
#define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2846
 
2847
/* Maximum value possibly taken by MOVE_MAX.  Must be defined whenever
2848
   MOVE_MAX is not a compile-time constant.  */
2849
#define MAX_MOVE_MAX 8
2850
 
2851
/* Max number of bytes we want move_by_pieces to be able to copy
2852
   efficiently.  */
2853
#define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2854
 
2855
/* Define if operations between registers always perform the operation
2856
   on the full register even if a narrower mode is specified.  */
2857
#define WORD_REGISTER_OPERATIONS
2858
 
2859
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2860
   will either zero-extend or sign-extend.  The value of this macro should
2861
   be the code that says which one of the two operations is implicitly
2862
   done, UNKNOWN if none.  */
2863
/* For SHmedia, we can truncate to QImode easier using zero extension.  */
2864
/* FP registers can load SImode values, but don't implicitly sign-extend
2865
   them to DImode.  */
2866
#define LOAD_EXTEND_OP(MODE) \
2867
 (((MODE) == QImode  && TARGET_SHMEDIA) ? ZERO_EXTEND \
2868
  : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2869
 
2870
/* Define if loading short immediate values into registers sign extends.  */
2871
#define SHORT_IMMEDIATES_SIGN_EXTEND
2872
 
2873
/* Nonzero if access to memory by bytes is no faster than for words.  */
2874
#define SLOW_BYTE_ACCESS 1
2875
 
2876
/* Immediate shift counts are truncated by the output routines (or was it
2877
   the assembler?).  Shift counts in a register are truncated by SH.  Note
2878
   that the native compiler puts too large (> 32) immediate shift counts
2879
   into a register and shifts by the register, letting the SH decide what
2880
   to do instead of doing that itself.  */
2881
/* ??? The library routines in lib1funcs.asm truncate the shift count.
2882
   However, the SH3 has hardware shifts that do not truncate exactly as gcc
2883
   expects - the sign bit is significant - so it appears that we need to
2884
   leave this zero for correct SH3 code.  */
2885
#define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2886
 
2887
/* All integers have the same format so truncation is easy.  */
2888
/* But SHmedia must sign-extend DImode when truncating to SImode.  */
2889
#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2890
 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2891
 
2892
/* Define this if addresses of constant functions
2893
   shouldn't be put through pseudo regs where they can be cse'd.
2894
   Desirable on machines where ordinary constants are expensive
2895
   but a CALL with constant address is cheap.  */
2896
/*#define NO_FUNCTION_CSE 1*/
2897
 
2898
/* The machine modes of pointers and functions.  */
2899
#define Pmode  (TARGET_SHMEDIA64 ? DImode : SImode)
2900
#define FUNCTION_MODE  Pmode
2901
 
2902
/* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2903
   are actually function calls with some special constraints on arguments
2904
   and register usage.
2905
 
2906
   These macros tell reorg that the references to arguments and
2907
   register clobbers for insns of type sfunc do not appear to happen
2908
   until after the millicode call.  This allows reorg to put insns
2909
   which set the argument registers into the delay slot of the millicode
2910
   call -- thus they act more like traditional CALL_INSNs.
2911
 
2912
   get_attr_is_sfunc will try to recognize the given insn, so make sure to
2913
   filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2914
   in particular.  */
2915
 
2916
#define INSN_SETS_ARE_DELAYED(X)                \
2917
  ((GET_CODE (X) == INSN                        \
2918
    && GET_CODE (PATTERN (X)) != SEQUENCE       \
2919
    && GET_CODE (PATTERN (X)) != USE            \
2920
    && GET_CODE (PATTERN (X)) != CLOBBER        \
2921
    && get_attr_is_sfunc (X)))
2922
 
2923
#define INSN_REFERENCES_ARE_DELAYED(X)          \
2924
  ((GET_CODE (X) == INSN                        \
2925
    && GET_CODE (PATTERN (X)) != SEQUENCE       \
2926
    && GET_CODE (PATTERN (X)) != USE            \
2927
    && GET_CODE (PATTERN (X)) != CLOBBER        \
2928
    && get_attr_is_sfunc (X)))
2929
 
2930
 
2931
/* Position Independent Code.  */
2932
 
2933
/* We can't directly access anything that contains a symbol,
2934
   nor can we indirect via the constant pool.  */
2935
#define LEGITIMATE_PIC_OPERAND_P(X)                             \
2936
        ((! nonpic_symbol_mentioned_p (X)                       \
2937
          && (GET_CODE (X) != SYMBOL_REF                        \
2938
              || ! CONSTANT_POOL_ADDRESS_P (X)                  \
2939
              || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2940
         || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2941
 
2942
#define SYMBOLIC_CONST_P(X)     \
2943
((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)      \
2944
  && nonpic_symbol_mentioned_p (X))
2945
 
2946
/* Compute extra cost of moving data between one register class
2947
   and another.  */
2948
 
2949
/* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2950
   uses this information.  Hence, the general register <-> floating point
2951
   register information here is not used for SFmode.  */
2952
 
2953
#define REGCLASS_HAS_GENERAL_REG(CLASS) \
2954
  ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2955
    || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2956
 
2957
#define REGCLASS_HAS_FP_REG(CLASS) \
2958
  ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2959
   || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2960
 
2961
#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2962
  sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2963
 
2964
/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option?  This
2965
   would be so that people with slow memory systems could generate
2966
   different code that does fewer memory accesses.  */
2967
 
2968
/* A C expression for the cost of a branch instruction.  A value of 1
2969
   is the default; other values are interpreted relative to that.
2970
   The SH1 does not have delay slots, hence we get a pipeline stall
2971
   at every branch.  The SH4 is superscalar, so the single delay slot
2972
   is not sufficient to keep both pipelines filled.  */
2973
#define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2974
 
2975
/* Assembler output control.  */
2976
 
2977
/* A C string constant describing how to begin a comment in the target
2978
   assembler language.  The compiler assumes that the comment will end at
2979
   the end of the line.  */
2980
#define ASM_COMMENT_START "!"
2981
 
2982
#define ASM_APP_ON              ""
2983
#define ASM_APP_OFF             ""
2984
#define FILE_ASM_OP             "\t.file\n"
2985
#define SET_ASM_OP              "\t.set\t"
2986
 
2987
/* How to change between sections.  */
2988
 
2989
#define TEXT_SECTION_ASM_OP             (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2990
#define DATA_SECTION_ASM_OP             "\t.data"
2991
 
2992
#if defined CRT_BEGIN || defined CRT_END
2993
/* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant.  */
2994
# undef TEXT_SECTION_ASM_OP
2995
# if __SHMEDIA__ == 1 && __SH5__ == 32
2996
#  define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2997
# else
2998
#  define TEXT_SECTION_ASM_OP "\t.text"
2999
# endif
3000
#endif
3001
 
3002
 
3003
/* If defined, a C expression whose value is a string containing the
3004
   assembler operation to identify the following data as
3005
   uninitialized global data.  If not defined, and neither
3006
   `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
3007
   uninitialized global data will be output in the data section if
3008
   `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
3009
   used.  */
3010
#ifndef BSS_SECTION_ASM_OP
3011
#define BSS_SECTION_ASM_OP      "\t.section\t.bss"
3012
#endif
3013
 
3014
/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
3015
   separate, explicit argument.  If you define this macro, it is used
3016
   in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
3017
   handling the required alignment of the variable.  The alignment is
3018
   specified as the number of bits.
3019
 
3020
   Try to use function `asm_output_aligned_bss' defined in file
3021
   `varasm.c' when defining this macro.  */
3022
#ifndef ASM_OUTPUT_ALIGNED_BSS
3023
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3024
  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
3025
#endif
3026
 
3027
/* Define this so that jump tables go in same section as the current function,
3028
   which could be text or it could be a user defined section.  */
3029
#define JUMP_TABLES_IN_TEXT_SECTION 1
3030
 
3031
#undef DO_GLOBAL_CTORS_BODY
3032
#define DO_GLOBAL_CTORS_BODY                    \
3033
{                                               \
3034
  typedef (*pfunc)();                           \
3035
  extern pfunc __ctors[];                       \
3036
  extern pfunc __ctors_end[];                   \
3037
  pfunc *p;                                     \
3038
  for (p = __ctors_end; p > __ctors; )          \
3039
    {                                           \
3040
      (*--p)();                                 \
3041
    }                                           \
3042
}
3043
 
3044
#undef DO_GLOBAL_DTORS_BODY
3045
#define DO_GLOBAL_DTORS_BODY                    \
3046
{                                               \
3047
  typedef (*pfunc)();                           \
3048
  extern pfunc __dtors[];                       \
3049
  extern pfunc __dtors_end[];                   \
3050
  pfunc *p;                                     \
3051
  for (p = __dtors; p < __dtors_end; p++)       \
3052
    {                                           \
3053
      (*p)();                                   \
3054
    }                                           \
3055
}
3056
 
3057
#define ASM_OUTPUT_REG_PUSH(file, v) \
3058
{                                                       \
3059
  if (TARGET_SHMEDIA)                                   \
3060
    {                                                   \
3061
      fprintf ((file), "\taddi.l\tr15,-8,r15\n");       \
3062
      fprintf ((file), "\tst.q\tr15,0,r%d\n", (v));     \
3063
    }                                                   \
3064
  else                                                  \
3065
    fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));      \
3066
}
3067
 
3068
#define ASM_OUTPUT_REG_POP(file, v) \
3069
{                                                       \
3070
  if (TARGET_SHMEDIA)                                   \
3071
    {                                                   \
3072
      fprintf ((file), "\tld.q\tr15,0,r%d\n", (v));     \
3073
      fprintf ((file), "\taddi.l\tr15,8,r15\n");        \
3074
    }                                                   \
3075
  else                                                  \
3076
    fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));      \
3077
}
3078
 
3079
/* DBX register number for a given compiler register number.  */
3080
/* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3081
   to match gdb.  */
3082
/* svr4.h undefines this macro, yet we really want to use the same numbers
3083
   for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER.  */
3084
/* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3085
   register exists, so we should return -1 for invalid register numbers.  */
3086
#define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3087
 
3088
/* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3089
   used to use the encodings 245..260, but that doesn't make sense:
3090
   PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3091
   the FP registers stay the same when switching between compact and media
3092
   mode.  Hence, we also need to use the same dwarf frame columns.
3093
   Likewise, we need to support unwind information for SHmedia registers
3094
   even in compact code.  */
3095
#define SH_DBX_REGISTER_NUMBER(REGNO) \
3096
  (IN_RANGE ((REGNO), \
3097
             (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3098
             FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3099
   ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3100
  : ((int) (REGNO) >= FIRST_FP_REG \
3101
     && ((int) (REGNO) \
3102
         <= (FIRST_FP_REG + \
3103
             ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3104
   ? ((unsigned) (REGNO) - FIRST_FP_REG \
3105
      + (TARGET_SH5 ? 77 : 25)) \
3106
   : XD_REGISTER_P (REGNO) \
3107
   ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3108
   : TARGET_REGISTER_P (REGNO) \
3109
   ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3110
   : (REGNO) == PR_REG \
3111
   ? (TARGET_SH5 ? 18 : 17) \
3112
   : (REGNO) == PR_MEDIA_REG \
3113
   ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3114
   : (REGNO) == T_REG \
3115
   ? (TARGET_SH5 ? 242 : 18) \
3116
   : (REGNO) == GBR_REG \
3117
   ? (TARGET_SH5 ? 238 : 19) \
3118
   : (REGNO) == MACH_REG \
3119
   ? (TARGET_SH5 ? 239 : 20) \
3120
   : (REGNO) == MACL_REG \
3121
   ? (TARGET_SH5 ? 240 : 21) \
3122
   : (REGNO) == FPUL_REG \
3123
   ? (TARGET_SH5 ? 244 : 23) \
3124
   : (unsigned) -1)
3125
 
3126
/* This is how to output a reference to a symbol_ref.  On SH5,
3127
   references to non-code symbols must be preceded by `datalabel'.  */
3128
#define ASM_OUTPUT_SYMBOL_REF(FILE,SYM)                 \
3129
  do                                                    \
3130
    {                                                   \
3131
      if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM))   \
3132
        fputs ("datalabel ", (FILE));                   \
3133
      assemble_name ((FILE), XSTR ((SYM), 0));           \
3134
    }                                                   \
3135
  while (0)
3136
 
3137
/* This is how to output an assembler line
3138
   that says to advance the location counter
3139
   to a multiple of 2**LOG bytes.  */
3140
 
3141
#define ASM_OUTPUT_ALIGN(FILE,LOG)      \
3142
  if ((LOG) != 0)                        \
3143
    fprintf ((FILE), "\t.align %d\n", (LOG))
3144
 
3145
/* Globalizing directive for a label.  */
3146
#define GLOBAL_ASM_OP "\t.global\t"
3147
 
3148
/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE)            */
3149
 
3150
/* Output a relative address table.  */
3151
 
3152
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL)                 \
3153
  switch (GET_MODE (BODY))                                              \
3154
    {                                                                   \
3155
    case SImode:                                                        \
3156
      if (TARGET_SH5)                                                   \
3157
        {                                                               \
3158
          asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n",    \
3159
                       (VALUE), (REL));                                 \
3160
          break;                                                        \
3161
        }                                                               \
3162
      asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL));  \
3163
      break;                                                            \
3164
    case HImode:                                                        \
3165
      if (TARGET_SH5)                                                   \
3166
        {                                                               \
3167
          asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n",    \
3168
                       (VALUE), (REL));                                 \
3169
          break;                                                        \
3170
        }                                                               \
3171
      asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL));  \
3172
      break;                                                            \
3173
    case QImode:                                                        \
3174
      if (TARGET_SH5)                                                   \
3175
        {                                                               \
3176
          asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n",    \
3177
                       (VALUE), (REL));                                 \
3178
          break;                                                        \
3179
        }                                                               \
3180
      asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL));  \
3181
      break;                                                            \
3182
    default:                                                            \
3183
      break;                                                            \
3184
    }
3185
 
3186
/* Output an absolute table element.  */
3187
 
3188
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE)                           \
3189
  if (! optimize || TARGET_BIGTABLE)                                    \
3190
    asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE));                \
3191
  else                                                                  \
3192
    asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3193
 
3194
 
3195
/* A C statement to be executed just prior to the output of
3196
   assembler code for INSN, to modify the extracted operands so
3197
   they will be output differently.
3198
 
3199
   Here the argument OPVEC is the vector containing the operands
3200
   extracted from INSN, and NOPERANDS is the number of elements of
3201
   the vector which contain meaningful data for this insn.
3202
   The contents of this vector are what will be used to convert the insn
3203
   template into assembler code, so you can change the assembler output
3204
   by changing the contents of the vector.  */
3205
 
3206
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3207
  final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3208
 
3209
/* Print operand X (an rtx) in assembler syntax to file FILE.
3210
   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3211
   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
3212
 
3213
#define PRINT_OPERAND(STREAM, X, CODE)  print_operand ((STREAM), (X), (CODE))
3214
 
3215
/* Print a memory address as an operand to reference that memory location.  */
3216
 
3217
#define PRINT_OPERAND_ADDRESS(STREAM,X)  print_operand_address ((STREAM), (X))
3218
 
3219
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3220
  ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ','     \
3221
   || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3222
 
3223
/* Recognize machine-specific patterns that may appear within
3224
   constants.  Used for PIC-specific UNSPECs.  */
3225
#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3226
  do                                                                    \
3227
    if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3228
      {                                                                 \
3229
        switch (XINT ((X), 1))                                          \
3230
          {                                                             \
3231
          case UNSPEC_DATALABEL:                                        \
3232
            fputs ("datalabel ", (STREAM));                             \
3233
            output_addr_const ((STREAM), XVECEXP ((X), 0, 0));            \
3234
            break;                                                      \
3235
          case UNSPEC_PIC:                                              \
3236
            /* GLOBAL_OFFSET_TABLE or local symbols, no suffix.  */     \
3237
            output_addr_const ((STREAM), XVECEXP ((X), 0, 0));            \
3238
            break;                                                      \
3239
          case UNSPEC_GOT:                                              \
3240
            output_addr_const ((STREAM), XVECEXP ((X), 0, 0));            \
3241
            fputs ("@GOT", (STREAM));                                   \
3242
            break;                                                      \
3243
          case UNSPEC_GOTOFF:                                           \
3244
            output_addr_const ((STREAM), XVECEXP ((X), 0, 0));            \
3245
            fputs ("@GOTOFF", (STREAM));                                \
3246
            break;                                                      \
3247
          case UNSPEC_PLT:                                              \
3248
            output_addr_const ((STREAM), XVECEXP ((X), 0, 0));            \
3249
            fputs ("@PLT", (STREAM));                                   \
3250
            break;                                                      \
3251
          case UNSPEC_GOTPLT:                                           \
3252
            output_addr_const ((STREAM), XVECEXP ((X), 0, 0));            \
3253
            fputs ("@GOTPLT", (STREAM));                                \
3254
            break;                                                      \
3255
          case UNSPEC_DTPOFF:                                           \
3256
            output_addr_const ((STREAM), XVECEXP ((X), 0, 0));            \
3257
            fputs ("@DTPOFF", (STREAM));                                \
3258
            break;                                                      \
3259
          case UNSPEC_GOTTPOFF:                                         \
3260
            output_addr_const ((STREAM), XVECEXP ((X), 0, 0));            \
3261
            fputs ("@GOTTPOFF", (STREAM));                              \
3262
            break;                                                      \
3263
          case UNSPEC_TPOFF:                                            \
3264
            output_addr_const ((STREAM), XVECEXP ((X), 0, 0));            \
3265
            fputs ("@TPOFF", (STREAM));                                 \
3266
            break;                                                      \
3267
          case UNSPEC_CALLER:                                           \
3268
            {                                                           \
3269
              char name[32];                                            \
3270
              /* LPCS stands for Label for PIC Call Site.  */           \
3271
              ASM_GENERATE_INTERNAL_LABEL                               \
3272
                (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0)));             \
3273
              assemble_name ((STREAM), name);                           \
3274
            }                                                           \
3275
            break;                                                      \
3276
          default:                                                      \
3277
            goto FAIL;                                                  \
3278
          }                                                             \
3279
        break;                                                          \
3280
      }                                                                 \
3281
    else                                                                \
3282
      goto FAIL;                                                        \
3283
  while (0)
3284
 
3285
 
3286
extern struct rtx_def *sh_compare_op0;
3287
extern struct rtx_def *sh_compare_op1;
3288
 
3289
/* Which processor to schedule for.  The elements of the enumeration must
3290
   match exactly the cpu attribute in the sh.md file.  */
3291
 
3292
enum processor_type {
3293
  PROCESSOR_SH1,
3294
  PROCESSOR_SH2,
3295
  PROCESSOR_SH2E,
3296
  PROCESSOR_SH2A,
3297
  PROCESSOR_SH3,
3298
  PROCESSOR_SH3E,
3299
  PROCESSOR_SH4,
3300
  PROCESSOR_SH4A,
3301
  PROCESSOR_SH5
3302
};
3303
 
3304
#define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3305
extern enum processor_type sh_cpu;
3306
 
3307
extern int optimize; /* needed for gen_casesi.  */
3308
 
3309
enum mdep_reorg_phase_e
3310
{
3311
  SH_BEFORE_MDEP_REORG,
3312
  SH_INSERT_USES_LABELS,
3313
  SH_SHORTEN_BRANCHES0,
3314
  SH_FIXUP_PCLOAD,
3315
  SH_SHORTEN_BRANCHES1,
3316
  SH_AFTER_MDEP_REORG
3317
};
3318
 
3319
extern enum mdep_reorg_phase_e mdep_reorg_phase;
3320
 
3321
/* Handle Renesas compiler's pragmas.  */
3322
#define REGISTER_TARGET_PRAGMAS() do {                                  \
3323
  c_register_pragma (0, "interrupt", sh_pr_interrupt);                   \
3324
  c_register_pragma (0, "trapa", sh_pr_trapa);                           \
3325
  c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs);       \
3326
} while (0)
3327
 
3328
extern tree sh_deferred_function_attributes;
3329
extern tree *sh_deferred_function_attributes_tail;
3330
 
3331
/* Set when processing a function with interrupt attribute.  */
3332
 
3333
extern int current_function_interrupt;
3334
 
3335
 
3336
/* Instructions with unfilled delay slots take up an
3337
   extra two bytes for the nop in the delay slot.
3338
   sh-dsp parallel processing insns are four bytes long.  */
3339
 
3340
#define ADJUST_INSN_LENGTH(X, LENGTH)                           \
3341
  (LENGTH) += sh_insn_length_adjustment (X);
3342
 
3343
/* Define this macro if it is advisable to hold scalars in registers
3344
   in a wider mode than that declared by the program.  In such cases,
3345
   the value is constrained to be within the bounds of the declared
3346
   type, but kept valid in the wider mode.  The signedness of the
3347
   extension may differ from that of the type.
3348
 
3349
   Leaving the unsignedp unchanged gives better code than always setting it
3350
   to 0.  This is despite the fact that we have only signed char and short
3351
   load instructions.  */
3352
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3353
  if (GET_MODE_CLASS (MODE) == MODE_INT                 \
3354
      && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3355
    (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)),  \
3356
    (MODE) = (TARGET_SH1 ? SImode \
3357
              : TARGET_SHMEDIA32 ? SImode : DImode);
3358
 
3359
#define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3360
 
3361
#define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3362
 
3363
/* ??? Define ACCUMULATE_OUTGOING_ARGS?  This is more efficient than pushing
3364
   and popping arguments.  However, we do have push/pop instructions, and
3365
   rather limited offsets (4 bits) in load/store instructions, so it isn't
3366
   clear if this would give better code.  If implemented, should check for
3367
   compatibility problems.  */
3368
 
3369
#define SH_DYNAMIC_SHIFT_COST \
3370
  (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3371
 
3372
 
3373
#define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3374
 
3375
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3376
 
3377
#define ACTUAL_NORMAL_MODE(ENTITY) \
3378
  (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3379
 
3380
#define NORMAL_MODE(ENTITY) \
3381
  (sh_cfun_interrupt_handler_p () \
3382
   ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3383
   : ACTUAL_NORMAL_MODE (ENTITY))
3384
 
3385
#define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3386
 
3387
#define MODE_EXIT(ENTITY) \
3388
  (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3389
 
3390
#define EPILOGUE_USES(REGNO)       ((TARGET_SH2E || TARGET_SH4)         \
3391
                                    && (REGNO) == FPSCR_REG)
3392
 
3393
#define MODE_NEEDED(ENTITY, INSN)                                       \
3394
  (recog_memoized (INSN) >= 0                                            \
3395
   ? get_attr_fp_mode (INSN)                                            \
3396
   : FP_MODE_NONE)
3397
 
3398
#define MODE_AFTER(MODE, INSN)                  \
3399
     (TARGET_HITACHI                            \
3400
      && recog_memoized (INSN) >= 0              \
3401
      && get_attr_fp_set (INSN) != FP_SET_NONE  \
3402
      ? (int) get_attr_fp_set (INSN)            \
3403
      : (MODE))
3404
 
3405
#define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3406
  ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3407
 
3408
#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3409
  fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3410
 
3411
#define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3412
  sh_can_redirect_branch ((INSN), (SEQ))
3413
 
3414
#define DWARF_FRAME_RETURN_COLUMN \
3415
  (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3416
 
3417
#define EH_RETURN_DATA_REGNO(N) \
3418
  ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3419
 
3420
#define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3421
#define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3422
 
3423
/* We have to distinguish between code and data, so that we apply
3424
   datalabel where and only where appropriate.  Use sdataN for data.  */
3425
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3426
 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3427
  | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3428
  | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3429
 
3430
/* Handle special EH pointer encodings.  Absolute, pc-relative, and
3431
   indirect are handled automatically.  */
3432
#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3433
  do { \
3434
    if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3435
        && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3436
      { \
3437
        gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3438
        SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3439
        if (0) goto DONE; \
3440
      } \
3441
  } while (0)
3442
 
3443
#if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3444
/* SH constant pool breaks the devices in crtstuff.c to control section
3445
   in where code resides.  We have to write it as asm code.  */
3446
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3447
   asm (SECTION_OP "\n\
3448
        mov.l   1f,r1\n\
3449
        mova    2f,r0\n\
3450
        braf    r1\n\
3451
        lds     r0,pr\n\
3452
0:      .p2align 2\n\
3453
1:      .long   " USER_LABEL_PREFIX #FUNC " - 0b\n\
3454
2:\n" TEXT_SECTION_ASM_OP);
3455
#endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3456
 
3457
#define SIMULTANEOUS_PREFETCHES 2
3458
 
3459
/* FIXME: middle-end support for highpart optimizations is missing.  */
3460
#define high_life_started reload_in_progress
3461
 
3462
#endif /* ! GCC_SH_H */

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