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/* This file contains the definitions and documentation for the
2
   Register Transfer Expressions (rtx's) that make up the
3
   Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4
   Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
5
   2005, 2006, 2007 Free Software Foundation, Inc.
6
 
7
This file is part of GCC.
8
 
9
GCC is free software; you can redistribute it and/or modify it under
10
the terms of the GNU General Public License as published by the Free
11
Software Foundation; either version 3, or (at your option) any later
12
version.
13
 
14
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15
WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
17
for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with GCC; see the file COPYING3.  If not see
21
.  */
22
 
23
 
24
/* Expression definitions and descriptions for all targets are in this file.
25
   Some will not be used for some targets.
26
 
27
   The fields in the cpp macro call "DEF_RTL_EXPR()"
28
   are used to create declarations in the C source of the compiler.
29
 
30
   The fields are:
31
 
32
   1.  The internal name of the rtx used in the C source.
33
   It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
34
   By convention these are in UPPER_CASE.
35
 
36
   2.  The name of the rtx in the external ASCII format read by
37
   read_rtx(), and printed by print_rtx().
38
   These names are stored in rtx_name[].
39
   By convention these are the internal (field 1) names in lower_case.
40
 
41
   3.  The print format, and type of each rtx->u.fld[] (field) in this rtx.
42
   These formats are stored in rtx_format[].
43
   The meaning of the formats is documented in front of this array in rtl.c
44
 
45
   4.  The class of the rtx.  These are stored in rtx_class and are accessed
46
   via the GET_RTX_CLASS macro.  They are defined as follows:
47
 
48
     RTX_CONST_OBJ
49
         an rtx code that can be used to represent a constant object
50
         (e.g, CONST_INT)
51
     RTX_OBJ
52
         an rtx code that can be used to represent an object (e.g, REG, MEM)
53
     RTX_COMPARE
54
         an rtx code for a comparison (e.g, LT, GT)
55
     RTX_COMM_COMPARE
56
         an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
57
     RTX_UNARY
58
         an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
59
     RTX_COMM_ARITH
60
         an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
61
     RTX_TERNARY
62
         an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
63
     RTX_BIN_ARITH
64
         an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
65
     RTX_BITFIELD_OPS
66
         an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
67
     RTX_INSN
68
         an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
69
     RTX_MATCH
70
         an rtx code for something that matches in insns (e.g, MATCH_DUP)
71
     RTX_AUTOINC
72
         an rtx code for autoincrement addressing modes (e.g. POST_DEC)
73
     RTX_EXTRA
74
         everything else
75
 
76
   All of the expressions that appear only in machine descriptions,
77
   not in RTL used by the compiler itself, are at the end of the file.  */
78
 
79
/* Unknown, or no such operation; the enumeration constant should have
80
   value zero.  */
81
DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
82
 
83
/* ---------------------------------------------------------------------
84
   Expressions used in constructing lists.
85
   --------------------------------------------------------------------- */
86
 
87
/* a linked list of expressions */
88
DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
89
 
90
/* a linked list of instructions.
91
   The insns are represented in print by their uids.  */
92
DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
93
 
94
/* a linked list of dependencies.
95
   The insns are represented in print by their uids.
96
   Operand 2 is the status of a dependence (see sched-int.h for more).  */
97
DEF_RTL_EXPR(DEPS_LIST, "deps_list", "uei", RTX_EXTRA)
98
 
99
/* SEQUENCE appears in the result of a `gen_...' function
100
   for a DEFINE_EXPAND that wants to make several insns.
101
   Its elements are the bodies of the insns that should be made.
102
   `emit_insn' takes the SEQUENCE apart and makes separate insns.  */
103
DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
104
 
105
/* Refers to the address of its argument.  This is only used in alias.c.  */
106
DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
107
 
108
/* ----------------------------------------------------------------------
109
   Expression types used for things in the instruction chain.
110
 
111
   All formats must start with "iuu" to handle the chain.
112
   Each insn expression holds an rtl instruction and its semantics
113
   during back-end processing.
114
   See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
115
 
116
   ---------------------------------------------------------------------- */
117
 
118
/* An instruction that cannot jump.  */
119
DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
120
 
121
/* An instruction that can possibly jump.
122
   Fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
123
DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
124
 
125
/* An instruction that can possibly call a subroutine
126
   but which will not change which instruction comes next
127
   in the current function.
128
   Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
129
   All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
130
DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
131
 
132
/* A marker that indicates that control will not flow through.  */
133
DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
134
 
135
/* Holds a label that is followed by instructions.
136
   Operand:
137
   4: is used in jump.c for the use-count of the label.
138
   5: is used in flow.c to point to the chain of label_ref's to this label.
139
   6: is a number that is unique in the entire compilation.
140
   7: is the user-given name of the label, if any.  */
141
DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
142
 
143
#ifdef USE_MAPPED_LOCATION
144
/* Say where in the code a source line starts, for symbol table's sake.
145
   Operand:
146
   4: unused if line number > 0, note-specific data otherwise.
147
   5: line number if > 0, enum note_insn otherwise.
148
   6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL.  */
149
#else
150
/* Say where in the code a source line starts, for symbol table's sake.
151
   Operand:
152
   4: filename, if line number > 0, note-specific data otherwise.
153
   5: line number if > 0, enum note_insn otherwise.
154
   6: unique number if line number == note_insn_deleted_label.  */
155
#endif
156
DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
157
 
158
/* ----------------------------------------------------------------------
159
   Top level constituents of INSN, JUMP_INSN and CALL_INSN.
160
   ---------------------------------------------------------------------- */
161
 
162
/* Conditionally execute code.
163
   Operand 0 is the condition that if true, the code is executed.
164
   Operand 1 is the code to be executed (typically a SET).
165
 
166
   Semantics are that there are no side effects if the condition
167
   is false.  This pattern is created automatically by the if_convert
168
   pass run after reload or by target-specific splitters.  */
169
DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
170
 
171
/* Several operations to be done in parallel (perhaps under COND_EXEC).  */
172
DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
173
 
174
/* A string that is passed through to the assembler as input.
175
     One can obviously pass comments through by using the
176
     assembler comment syntax.
177
     These occur in an insn all by themselves as the PATTERN.
178
     They also appear inside an ASM_OPERANDS
179
     as a convenient way to hold a string.  */
180
DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
181
 
182
#ifdef USE_MAPPED_LOCATION
183
/* An assembler instruction with operands.
184
   1st operand is the instruction template.
185
   2nd operand is the constraint for the output.
186
   3rd operand is the number of the output this expression refers to.
187
     When an insn stores more than one value, a separate ASM_OPERANDS
188
     is made for each output; this integer distinguishes them.
189
   4th is a vector of values of input operands.
190
   5th is a vector of modes and constraints for the input operands.
191
     Each element is an ASM_INPUT containing a constraint string
192
     and whose mode indicates the mode of the input operand.
193
   6th is the source line number.  */
194
DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
195
#else
196
/* An assembler instruction with operands.
197
   1st operand is the instruction template.
198
   2nd operand is the constraint for the output.
199
   3rd operand is the number of the output this expression refers to.
200
     When an insn stores more than one value, a separate ASM_OPERANDS
201
     is made for each output; this integer distinguishes them.
202
   4th is a vector of values of input operands.
203
   5th is a vector of modes and constraints for the input operands.
204
     Each element is an ASM_INPUT containing a constraint string
205
     and whose mode indicates the mode of the input operand.
206
   6th is the name of the containing source file.
207
   7th is the source line number.  */
208
DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
209
#endif
210
 
211
/* A machine-specific operation.
212
   1st operand is a vector of operands being used by the operation so that
213
     any needed reloads can be done.
214
   2nd operand is a unique value saying which of a number of machine-specific
215
     operations is to be performed.
216
   (Note that the vector must be the first operand because of the way that
217
   genrecog.c record positions within an insn.)
218
   This can occur all by itself in a PATTERN, as a component of a PARALLEL,
219
   or inside an expression.  */
220
DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
221
 
222
/* Similar, but a volatile operation and one which may trap.  */
223
DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
224
 
225
/* Vector of addresses, stored as full words.  */
226
/* Each element is a LABEL_REF to a CODE_LABEL whose address we want.  */
227
DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
228
 
229
/* Vector of address differences X0 - BASE, X1 - BASE, ...
230
   First operand is BASE; the vector contains the X's.
231
   The machine mode of this rtx says how much space to leave
232
   for each difference and is adjusted by branch shortening if
233
   CASE_VECTOR_SHORTEN_MODE is defined.
234
   The third and fourth operands store the target labels with the
235
   minimum and maximum addresses respectively.
236
   The fifth operand stores flags for use by branch shortening.
237
  Set at the start of shorten_branches:
238
   min_align: the minimum alignment for any of the target labels.
239
   base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
240
   min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
241
   max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
242
   min_after_base: true iff minimum address target label is after BASE.
243
   max_after_base: true iff maximum address target label is after BASE.
244
  Set by the actual branch shortening process:
245
   offset_unsigned: true iff offsets have to be treated as unsigned.
246
   scale: scaling that is necessary to make offsets fit into the mode.
247
 
248
   The third, fourth and fifth operands are only valid when
249
   CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
250
   compilations.  */
251
 
252
DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
253
 
254
/* Memory prefetch, with attributes supported on some targets.
255
   Operand 1 is the address of the memory to fetch.
256
   Operand 2 is 1 for a write access, 0 otherwise.
257
   Operand 3 is the level of temporal locality; 0 means there is no
258
   temporal locality and 1, 2, and 3 are for increasing levels of temporal
259
   locality.
260
 
261
   The attributes specified by operands 2 and 3 are ignored for targets
262
   whose prefetch instructions do not support them.  */
263
DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
264
 
265
/* ----------------------------------------------------------------------
266
   At the top level of an instruction (perhaps under PARALLEL).
267
   ---------------------------------------------------------------------- */
268
 
269
/* Assignment.
270
   Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
271
   Operand 2 is the value stored there.
272
   ALL assignment must use SET.
273
   Instructions that do multiple assignments must use multiple SET,
274
   under PARALLEL.  */
275
DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
276
 
277
/* Indicate something is used in a way that we don't want to explain.
278
   For example, subroutine calls will use the register
279
   in which the static chain is passed.  */
280
DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
281
 
282
/* Indicate something is clobbered in a way that we don't want to explain.
283
   For example, subroutine calls will clobber some physical registers
284
   (the ones that are by convention not saved).  */
285
DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
286
 
287
/* Call a subroutine.
288
   Operand 1 is the address to call.
289
   Operand 2 is the number of arguments.  */
290
 
291
DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
292
 
293
/* Return from a subroutine.  */
294
 
295
DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
296
 
297
/* Conditional trap.
298
   Operand 1 is the condition.
299
   Operand 2 is the trap code.
300
   For an unconditional trap, make the condition (const_int 1).  */
301
DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
302
 
303
/* Placeholder for _Unwind_Resume before we know if a function call
304
   or a branch is needed.  Operand 1 is the exception region from
305
   which control is flowing.  */
306
DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
307
 
308
/* ----------------------------------------------------------------------
309
   Primitive values for use in expressions.
310
   ---------------------------------------------------------------------- */
311
 
312
/* numeric integer constant */
313
DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
314
 
315
/* numeric floating point constant.
316
   Operands hold the value.  They are all 'w' and there may be from 2 to 6;
317
   see real.h.  */
318
DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
319
 
320
/* Describes a vector constant.  */
321
DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
322
 
323
/* String constant.  Used for attributes in machine descriptions and
324
   for special cases in DWARF2 debug output.  NOT used for source-
325
   language string constants.  */
326
DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
327
 
328
/* This is used to encapsulate an expression whose value is constant
329
   (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
330
   recognized as a constant operand rather than by arithmetic instructions.  */
331
 
332
DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
333
 
334
/* program counter.  Ordinary jumps are represented
335
   by a SET whose first operand is (PC).  */
336
DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
337
 
338
/* Used in the cselib routines to describe a value.  Objects of this
339
   kind are only allocated in cselib.c, in an alloc pool instead of
340
   in GC memory.  The only operand of a VALUE is a cselib_val_struct.  */
341
DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
342
 
343
/* A register.  The "operand" is the register number, accessed with
344
   the REGNO macro.  If this number is less than FIRST_PSEUDO_REGISTER
345
   than a hardware register is being referred to.  The second operand
346
   holds the original register number - this will be different for a
347
   pseudo register that got turned into a hard register.  The third
348
   operand points to a reg_attrs structure.
349
   This rtx needs to have as many (or more) fields as a MEM, since we
350
   can change REG rtx's into MEMs during reload.  */
351
DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
352
 
353
/* A scratch register.  This represents a register used only within a
354
   single insn.  It will be turned into a REG during register allocation
355
   or reload unless the constraint indicates that the register won't be
356
   needed, in which case it can remain a SCRATCH.  This code is
357
   marked as having one operand so it can be turned into a REG.  */
358
DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
359
 
360
/* One word of a multi-word value.
361
   The first operand is the complete value; the second says which word.
362
   The WORDS_BIG_ENDIAN flag controls whether word number 0
363
   (as numbered in a SUBREG) is the most or least significant word.
364
 
365
   This is also used to refer to a value in a different machine mode.
366
   For example, it can be used to refer to a SImode value as if it were
367
   Qimode, or vice versa.  Then the word number is always 0.  */
368
DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
369
 
370
/* This one-argument rtx is used for move instructions
371
   that are guaranteed to alter only the low part of a destination.
372
   Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
373
   has an unspecified effect on the high part of REG,
374
   but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
375
   is guaranteed to alter only the bits of REG that are in HImode.
376
 
377
   The actual instruction used is probably the same in both cases,
378
   but the register constraints may be tighter when STRICT_LOW_PART
379
   is in use.  */
380
 
381
DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
382
 
383
/* (CONCAT a b) represents the virtual concatenation of a and b
384
   to make a value that has as many bits as a and b put together.
385
   This is used for complex values.  Normally it appears only
386
   in DECL_RTLs and during RTL generation, but not in the insn chain.  */
387
DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
388
 
389
/* A memory location; operand is the address.  The second operand is the
390
   alias set to which this MEM belongs.  We use `0' instead of `w' for this
391
   field so that the field need not be specified in machine descriptions.  */
392
DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
393
 
394
/* Reference to an assembler label in the code for this function.
395
   The operand is a CODE_LABEL found in the insn chain.  */
396
DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
397
 
398
/* Reference to a named label:
399
   Operand 0: label name
400
   Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
401
   Operand 2: tree from which this symbol is derived, or null.
402
   This is either a DECL node, or some kind of constant.  */
403
DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
404
 
405
/* The condition code register is represented, in our imagination,
406
   as a register holding a value that can be compared to zero.
407
   In fact, the machine has already compared them and recorded the
408
   results; but instructions that look at the condition code
409
   pretend to be looking at the entire value and comparing it.  */
410
DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
411
 
412
/* ----------------------------------------------------------------------
413
   Expressions for operators in an rtl pattern
414
   ---------------------------------------------------------------------- */
415
 
416
/* if_then_else.  This is used in representing ordinary
417
   conditional jump instructions.
418
     Operand:
419
     0:  condition
420
     1:  then expr
421
     2:  else expr */
422
DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
423
 
424
/* Comparison, produces a condition code result.  */
425
DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
426
 
427
/* plus */
428
DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
429
 
430
/* Operand 0 minus operand 1.  */
431
DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
432
 
433
/* Minus operand 0.  */
434
DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
435
 
436
DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
437
 
438
/* Operand 0 divided by operand 1.  */
439
DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
440
/* Remainder of operand 0 divided by operand 1.  */
441
DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
442
 
443
/* Unsigned divide and remainder.  */
444
DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
445
DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
446
 
447
/* Bitwise operations.  */
448
DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
449
DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
450
DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
451
DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
452
 
453
/* Operand:
454
     0:  value to be shifted.
455
     1:  number of bits.  */
456
DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
457
DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
458
DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
459
DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
460
DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
461
 
462
/* Minimum and maximum values of two operands.  We need both signed and
463
   unsigned forms.  (We cannot use MIN for SMIN because it conflicts
464
   with a macro of the same name.)   The signed variants should be used
465
   with floating point.  Further, if both operands are zeros, or if either
466
   operand is NaN, then it is unspecified which of the two operands is
467
   returned as the result.  */
468
 
469
DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
470
DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
471
DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
472
DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
473
 
474
/* These unary operations are used to represent incrementation
475
   and decrementation as they occur in memory addresses.
476
   The amount of increment or decrement are not represented
477
   because they can be understood from the machine-mode of the
478
   containing MEM.  These operations exist in only two cases:
479
   1. pushes onto the stack.
480
   2. created automatically by the life_analysis pass in flow.c.  */
481
DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
482
DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
483
DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
484
DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
485
 
486
/* These binary operations are used to represent generic address
487
   side-effects in memory addresses, except for simple incrementation
488
   or decrementation which use the above operations.  They are
489
   created automatically by the life_analysis pass in flow.c.
490
   The first operand is a REG which is used as the address.
491
   The second operand is an expression that is assigned to the
492
   register, either before (PRE_MODIFY) or after (POST_MODIFY)
493
   evaluating the address.
494
   Currently, the compiler can only handle second operands of the
495
   form (plus (reg) (reg)) and (plus (reg) (const_int)), where
496
   the first operand of the PLUS has to be the same register as
497
   the first operand of the *_MODIFY.  */
498
DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
499
DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
500
 
501
/* Comparison operations.  The ordered comparisons exist in two
502
   flavors, signed and unsigned.  */
503
DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
504
DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
505
DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
506
DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
507
DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
508
DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
509
DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
510
DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
511
DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
512
DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
513
 
514
/* Additional floating point unordered comparison flavors.  */
515
DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
516
DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
517
 
518
/* These are equivalent to unordered or ...  */
519
DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
520
DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
521
DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
522
DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
523
DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
524
 
525
/* This is an ordered NE, ie !UNEQ, ie false for NaN.  */
526
DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
527
 
528
/* Represents the result of sign-extending the sole operand.
529
   The machine modes of the operand and of the SIGN_EXTEND expression
530
   determine how much sign-extension is going on.  */
531
DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
532
 
533
/* Similar for zero-extension (such as unsigned short to int).  */
534
DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
535
 
536
/* Similar but here the operand has a wider mode.  */
537
DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
538
 
539
/* Similar for extending floating-point values (such as SFmode to DFmode).  */
540
DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
541
DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
542
 
543
/* Conversion of fixed point operand to floating point value.  */
544
DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
545
 
546
/* With fixed-point machine mode:
547
   Conversion of floating point operand to fixed point value.
548
   Value is defined only when the operand's value is an integer.
549
   With floating-point machine mode (and operand with same mode):
550
   Operand is rounded toward zero to produce an integer value
551
   represented in floating point.  */
552
DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
553
 
554
/* Conversion of unsigned fixed point operand to floating point value.  */
555
DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
556
 
557
/* With fixed-point machine mode:
558
   Conversion of floating point operand to *unsigned* fixed point value.
559
   Value is defined only when the operand's value is an integer.  */
560
DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
561
 
562
/* Absolute value */
563
DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
564
 
565
/* Square root */
566
DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
567
 
568
/* Find first bit that is set.
569
   Value is 1 + number of trailing zeros in the arg.,
570
   or 0 if arg is 0.  */
571
DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
572
 
573
/* Count leading zeros.  */
574
DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
575
 
576
/* Count trailing zeros.  */
577
DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
578
 
579
/* Population count (number of 1 bits).  */
580
DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
581
 
582
/* Population parity (number of 1 bits modulo 2).  */
583
DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
584
 
585
/* Reference to a signed bit-field of specified size and position.
586
   Operand 0 is the memory unit (usually SImode or QImode) which
587
   contains the field's first bit.  Operand 1 is the width, in bits.
588
   Operand 2 is the number of bits in the memory unit before the
589
   first bit of this field.
590
   If BITS_BIG_ENDIAN is defined, the first bit is the msb and
591
   operand 2 counts from the msb of the memory unit.
592
   Otherwise, the first bit is the lsb and operand 2 counts from
593
   the lsb of the memory unit.
594
   This kind of expression can not appear as an lvalue in RTL.  */
595
DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
596
 
597
/* Similar for unsigned bit-field.
598
   But note!  This kind of expression _can_ appear as an lvalue.  */
599
DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
600
 
601
/* For RISC machines.  These save memory when splitting insns.  */
602
 
603
/* HIGH are the high-order bits of a constant expression.  */
604
DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
605
 
606
/* LO_SUM is the sum of a register and the low-order bits
607
   of a constant expression.  */
608
DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
609
 
610
/* Describes a merge operation between two vector values.
611
   Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
612
   that specifies where the parts of the result are taken from.  Set bits
613
   indicate operand 0, clear bits indicate operand 1.  The parts are defined
614
   by the mode of the vectors.  */
615
DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
616
 
617
/* Describes an operation that selects parts of a vector.
618
   Operands 0 is the source vector, operand 1 is a PARALLEL that contains
619
   a CONST_INT for each of the subparts of the result vector, giving the
620
   number of the source subpart that should be stored into it.  */
621
DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
622
 
623
/* Describes a vector concat operation.  Operands 0 and 1 are the source
624
   vectors, the result is a vector that is as long as operands 0 and 1
625
   combined and is the concatenation of the two source vectors.  */
626
DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
627
 
628
/* Describes an operation that converts a small vector into a larger one by
629
   duplicating the input values.  The output vector mode must have the same
630
   submodes as the input vector mode, and the number of output parts must be
631
   an integer multiple of the number of input parts.  */
632
DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
633
 
634
/* Addition with signed saturation */
635
DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
636
 
637
/* Addition with unsigned saturation */
638
DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
639
 
640
/* Operand 0 minus operand 1, with signed saturation.  */
641
DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
642
 
643
/* Negation with signed saturation.  */
644
DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
645
 
646
/* Shift left with signed saturation.  */
647
DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
648
 
649
/* Operand 0 minus operand 1, with unsigned saturation.  */
650
DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
651
 
652
/* Signed saturating truncate.  */
653
DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
654
 
655
/* Unsigned saturating truncate.  */
656
DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
657
 
658
/* Information about the variable and its location.  */
659
DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
660
 
661
/* All expressions from this point forward appear only in machine
662
   descriptions.  */
663
#ifdef GENERATOR_FILE
664
 
665
/* Include a secondary machine-description file at this point.  */
666
DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
667
 
668
/* Pattern-matching operators:  */
669
 
670
/* Use the function named by the second arg (the string)
671
   as a predicate; if matched, store the structure that was matched
672
   in the operand table at index specified by the first arg (the integer).
673
   If the second arg is the null string, the structure is just stored.
674
 
675
   A third string argument indicates to the register allocator restrictions
676
   on where the operand can be allocated.
677
 
678
   If the target needs no restriction on any instruction this field should
679
   be the null string.
680
 
681
   The string is prepended by:
682
   '=' to indicate the operand is only written to.
683
   '+' to indicate the operand is both read and written to.
684
 
685
   Each character in the string represents an allocable class for an operand.
686
   'g' indicates the operand can be any valid class.
687
   'i' indicates the operand can be immediate (in the instruction) data.
688
   'r' indicates the operand can be in a register.
689
   'm' indicates the operand can be in memory.
690
   'o' a subset of the 'm' class.  Those memory addressing modes that
691
       can be offset at compile time (have a constant added to them).
692
 
693
   Other characters indicate target dependent operand classes and
694
   are described in each target's machine description.
695
 
696
   For instructions with more than one operand, sets of classes can be
697
   separated by a comma to indicate the appropriate multi-operand constraints.
698
   There must be a 1 to 1 correspondence between these sets of classes in
699
   all operands for an instruction.
700
   */
701
DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
702
 
703
/* Match a SCRATCH or a register.  When used to generate rtl, a
704
   SCRATCH is generated.  As for MATCH_OPERAND, the mode specifies
705
   the desired mode and the first argument is the operand number.
706
   The second argument is the constraint.  */
707
DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
708
 
709
/* Apply a predicate, AND match recursively the operands of the rtx.
710
   Operand 0 is the operand-number, as in match_operand.
711
   Operand 1 is a predicate to apply (as a string, a function name).
712
   Operand 2 is a vector of expressions, each of which must match
713
   one subexpression of the rtx this construct is matching.  */
714
DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
715
 
716
/* Match a PARALLEL of arbitrary length.  The predicate is applied
717
   to the PARALLEL and the initial expressions in the PARALLEL are matched.
718
   Operand 0 is the operand-number, as in match_operand.
719
   Operand 1 is a predicate to apply to the PARALLEL.
720
   Operand 2 is a vector of expressions, each of which must match the
721
   corresponding element in the PARALLEL.  */
722
DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
723
 
724
/* Match only something equal to what is stored in the operand table
725
   at the index specified by the argument.  Use with MATCH_OPERAND.  */
726
DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
727
 
728
/* Match only something equal to what is stored in the operand table
729
   at the index specified by the argument.  Use with MATCH_OPERATOR.  */
730
DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
731
 
732
/* Match only something equal to what is stored in the operand table
733
   at the index specified by the argument.  Use with MATCH_PARALLEL.  */
734
DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
735
 
736
/* Appears only in define_predicate/define_special_predicate
737
   expressions.  Evaluates true only if the operand has an RTX code
738
   from the set given by the argument (a comma-separated list).  If the
739
   second argument is present and nonempty, it is a sequence of digits
740
   and/or letters which indicates the subexpression to test, using the
741
   same syntax as genextract/genrecog's location strings: 0-9 for
742
   XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
743
   the result of the one before it.  */
744
DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
745
 
746
/* Appears only in define_predicate/define_special_predicate
747
    expressions.  The argument is a C expression to be injected at this
748
    point in the predicate formula.  */
749
DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
750
 
751
/* Insn (and related) definitions.  */
752
 
753
/* Definition of the pattern for one kind of instruction.
754
   Operand:
755
   0: names this instruction.
756
      If the name is the null string, the instruction is in the
757
      machine description just to be recognized, and will never be emitted by
758
      the tree to rtl expander.
759
   1: is the pattern.
760
   2: is a string which is a C expression
761
      giving an additional condition for recognizing this pattern.
762
      A null string means no extra condition.
763
   3: is the action to execute if this pattern is matched.
764
      If this assembler code template starts with a * then it is a fragment of
765
      C code to run to decide on a template to use.  Otherwise, it is the
766
      template to use.
767
   4: optionally, a vector of attributes for this insn.
768
     */
769
DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
770
 
771
/* Definition of a peephole optimization.
772
   1st operand: vector of insn patterns to match
773
   2nd operand: C expression that must be true
774
   3rd operand: template or C code to produce assembler output.
775
   4: optionally, a vector of attributes for this insn.
776
 
777
   This form is deprecated; use define_peephole2 instead.  */
778
DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
779
 
780
/* Definition of a split operation.
781
   1st operand: insn pattern to match
782
   2nd operand: C expression that must be true
783
   3rd operand: vector of insn patterns to place into a SEQUENCE
784
   4th operand: optionally, some C code to execute before generating the
785
        insns.  This might, for example, create some RTX's and store them in
786
        elements of `recog_data.operand' for use by the vector of
787
        insn-patterns.
788
        (`operands' is an alias here for `recog_data.operand').  */
789
DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
790
 
791
/* Definition of an insn and associated split.
792
   This is the concatenation, with a few modifications, of a define_insn
793
   and a define_split which share the same pattern.
794
   Operand:
795
   0: names this instruction.
796
      If the name is the null string, the instruction is in the
797
      machine description just to be recognized, and will never be emitted by
798
      the tree to rtl expander.
799
   1: is the pattern.
800
   2: is a string which is a C expression
801
      giving an additional condition for recognizing this pattern.
802
      A null string means no extra condition.
803
   3: is the action to execute if this pattern is matched.
804
      If this assembler code template starts with a * then it is a fragment of
805
      C code to run to decide on a template to use.  Otherwise, it is the
806
      template to use.
807
   4: C expression that must be true for split.  This may start with "&&"
808
      in which case the split condition is the logical and of the insn
809
      condition and what follows the "&&" of this operand.
810
   5: vector of insn patterns to place into a SEQUENCE
811
   6: optionally, some C code to execute before generating the
812
        insns.  This might, for example, create some RTX's and store them in
813
        elements of `recog_data.operand' for use by the vector of
814
        insn-patterns.
815
        (`operands' is an alias here for `recog_data.operand').
816
   7: optionally, a vector of attributes for this insn.  */
817
DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
818
 
819
/* Definition of an RTL peephole operation.
820
   Follows the same arguments as define_split.  */
821
DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
822
 
823
/* Define how to generate multiple insns for a standard insn name.
824
   1st operand: the insn name.
825
   2nd operand: vector of insn-patterns.
826
        Use match_operand to substitute an element of `recog_data.operand'.
827
   3rd operand: C expression that must be true for this to be available.
828
        This may not test any operands.
829
   4th operand: Extra C code to execute before generating the insns.
830
        This might, for example, create some RTX's and store them in
831
        elements of `recog_data.operand' for use by the vector of
832
        insn-patterns.
833
        (`operands' is an alias here for `recog_data.operand').  */
834
DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
835
 
836
/* Define a requirement for delay slots.
837
   1st operand: Condition involving insn attributes that, if true,
838
                indicates that the insn requires the number of delay slots
839
                shown.
840
   2nd operand: Vector whose length is the three times the number of delay
841
                slots required.
842
                Each entry gives three conditions, each involving attributes.
843
                The first must be true for an insn to occupy that delay slot
844
                location.  The second is true for all insns that can be
845
                annulled if the branch is true and the third is true for all
846
                insns that can be annulled if the branch is false.
847
 
848
   Multiple DEFINE_DELAYs may be present.  They indicate differing
849
   requirements for delay slots.  */
850
DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
851
 
852
/* Define attribute computation for `asm' instructions.  */
853
DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
854
 
855
/* Definition of a conditional execution meta operation.  Automatically
856
   generates new instances of DEFINE_INSN, selected by having attribute
857
   "predicable" true.  The new pattern will contain a COND_EXEC and the
858
   predicate at top-level.
859
 
860
   Operand:
861
   0: The predicate pattern.  The top-level form should match a
862
      relational operator.  Operands should have only one alternative.
863
   1: A C expression giving an additional condition for recognizing
864
      the generated pattern.
865
   2: A template or C code to produce assembler output.  */
866
DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
867
 
868
/* Definition of an operand predicate.  The difference between
869
   DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
870
   not warn about a match_operand with no mode if it has a predicate
871
   defined with DEFINE_SPECIAL_PREDICATE.
872
 
873
   Operand:
874
   0: The name of the predicate.
875
   1: A boolean expression which computes whether or not the predicate
876
      matches.  This expression can use IOR, AND, NOT, MATCH_OPERAND,
877
      MATCH_CODE, and MATCH_TEST.  It must be specific enough that genrecog
878
      can calculate the set of RTX codes that can possibly match.
879
   2: A C function body which must return true for the predicate to match.
880
      Optional.  Use this when the test is too complicated to fit into a
881
      match_test expression.  */
882
DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
883
DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
884
 
885
/* Definition of a register operand constraint.  This simply maps the
886
   constraint string to a register class.
887
 
888
   Operand:
889
   0: The name of the constraint (often, but not always, a single letter).
890
   1: A C expression which evaluates to the appropriate register class for
891
      this constraint.  If this is not just a constant, it should look only
892
      at -m switches and the like.
893
   2: A docstring for this constraint, in Texinfo syntax; not currently
894
      used, in future will be incorporated into the manual's list of
895
      machine-specific operand constraints.  */
896
DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
897
 
898
/* Definition of a non-register operand constraint.  These look at the
899
   operand and decide whether it fits the constraint.
900
 
901
   DEFINE_CONSTRAINT gets no special treatment if it fails to match.
902
   It is appropriate for constant-only constraints, and most others.
903
 
904
   DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
905
   to match, if it doesn't already, by converting the operand to the form
906
   (mem (reg X)) where X is a base register.  It is suitable for constraints
907
   that describe a subset of all memory references.
908
 
909
   DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
910
   to match, if it doesn't already, by converting the operand to the form
911
   (reg X) where X is a base register.  It is suitable for constraints that
912
   describe a subset of all address references.
913
 
914
   When in doubt, use plain DEFINE_CONSTRAINT.
915
 
916
   Operand:
917
   0: The name of the constraint (often, but not always, a single letter).
918
   1: A docstring for this constraint, in Texinfo syntax; not currently
919
      used, in future will be incorporated into the manual's list of
920
      machine-specific operand constraints.
921
   2: A boolean expression which computes whether or not the constraint
922
      matches.  It should follow the same rules as a define_predicate
923
      expression, including the bit about specifying the set of RTX codes
924
      that could possibly match.  MATCH_TEST subexpressions may make use of
925
      these variables:
926
        `op'    - the RTL object defining the operand.
927
        `mode'  - the mode of `op'.
928
        `ival'  - INTVAL(op), if op is a CONST_INT.
929
        `hval'  - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
930
        `lval'  - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
931
        `rval'  - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
932
                  CONST_DOUBLE.
933
      Do not use ival/hval/lval/rval if op is not the appropriate kind of
934
      RTL object.  */
935
DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
936
DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
937
DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
938
 
939
 
940
/* Constructions for CPU pipeline description described by NDFAs.  */
941
 
942
/* (define_cpu_unit string [string]) describes cpu functional
943
   units (separated by comma).
944
 
945
   1st operand: Names of cpu functional units.
946
   2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
947
 
948
   All define_reservations, define_cpu_units, and
949
   define_query_cpu_units should have unique names which may not be
950
   "nothing".  */
951
DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
952
 
953
/* (define_query_cpu_unit string [string]) describes cpu functional
954
   units analogously to define_cpu_unit.  The reservation of such
955
   units can be queried for automaton state.  */
956
DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
957
 
958
/* (exclusion_set string string) means that each CPU functional unit
959
   in the first string can not be reserved simultaneously with any
960
   unit whose name is in the second string and vise versa.  CPU units
961
   in the string are separated by commas.  For example, it is useful
962
   for description CPU with fully pipelined floating point functional
963
   unit which can execute simultaneously only single floating point
964
   insns or only double floating point insns.  All CPU functional
965
   units in a set should belong to the same automaton.  */
966
DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
967
 
968
/* (presence_set string string) means that each CPU functional unit in
969
   the first string can not be reserved unless at least one of pattern
970
   of units whose names are in the second string is reserved.  This is
971
   an asymmetric relation.  CPU units or unit patterns in the strings
972
   are separated by commas.  Pattern is one unit name or unit names
973
   separated by white-spaces.
974
 
975
   For example, it is useful for description that slot1 is reserved
976
   after slot0 reservation for a VLIW processor.  We could describe it
977
   by the following construction
978
 
979
      (presence_set "slot1" "slot0")
980
 
981
   Or slot1 is reserved only after slot0 and unit b0 reservation.  In
982
   this case we could write
983
 
984
      (presence_set "slot1" "slot0 b0")
985
 
986
   All CPU functional units in a set should belong to the same
987
   automaton.  */
988
DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
989
 
990
/* (final_presence_set string string) is analogous to `presence_set'.
991
   The difference between them is when checking is done.  When an
992
   instruction is issued in given automaton state reflecting all
993
   current and planned unit reservations, the automaton state is
994
   changed.  The first state is a source state, the second one is a
995
   result state.  Checking for `presence_set' is done on the source
996
   state reservation, checking for `final_presence_set' is done on the
997
   result reservation.  This construction is useful to describe a
998
   reservation which is actually two subsequent reservations.  For
999
   example, if we use
1000
 
1001
      (presence_set "slot1" "slot0")
1002
 
1003
   the following insn will be never issued (because slot1 requires
1004
   slot0 which is absent in the source state).
1005
 
1006
      (define_reservation "insn_and_nop" "slot0 + slot1")
1007
 
1008
   but it can be issued if we use analogous `final_presence_set'.  */
1009
DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1010
 
1011
/* (absence_set string string) means that each CPU functional unit in
1012
   the first string can be reserved only if each pattern of units
1013
   whose names are in the second string is not reserved.  This is an
1014
   asymmetric relation (actually exclusion set is analogous to this
1015
   one but it is symmetric).  CPU units or unit patterns in the string
1016
   are separated by commas.  Pattern is one unit name or unit names
1017
   separated by white-spaces.
1018
 
1019
   For example, it is useful for description that slot0 can not be
1020
   reserved after slot1 or slot2 reservation for a VLIW processor.  We
1021
   could describe it by the following construction
1022
 
1023
      (absence_set "slot2" "slot0, slot1")
1024
 
1025
   Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1026
   slot1 and unit b1 are reserved .  In this case we could write
1027
 
1028
      (absence_set "slot2" "slot0 b0, slot1 b1")
1029
 
1030
   All CPU functional units in a set should to belong the same
1031
   automaton.  */
1032
DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1033
 
1034
/* (final_absence_set string string) is analogous to `absence_set' but
1035
   checking is done on the result (state) reservation.  See comments
1036
   for `final_presence_set'.  */
1037
DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1038
 
1039
/* (define_bypass number out_insn_names in_insn_names) names bypass
1040
   with given latency (the first number) from insns given by the first
1041
   string (see define_insn_reservation) into insns given by the second
1042
   string.  Insn names in the strings are separated by commas.  The
1043
   third operand is optional name of function which is additional
1044
   guard for the bypass.  The function will get the two insns as
1045
   parameters.  If the function returns zero the bypass will be
1046
   ignored for this case.  Additional guard is necessary to recognize
1047
   complicated bypasses, e.g. when consumer is load address.  */
1048
DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1049
 
1050
/* (define_automaton string) describes names of automata generated and
1051
   used for pipeline hazards recognition.  The names are separated by
1052
   comma.  Actually it is possibly to generate the single automaton
1053
   but unfortunately it can be very large.  If we use more one
1054
   automata, the summary size of the automata usually is less than the
1055
   single one.  The automaton name is used in define_cpu_unit and
1056
   define_query_cpu_unit.  All automata should have unique names.  */
1057
DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1058
 
1059
/* (automata_option string) describes option for generation of
1060
   automata.  Currently there are the following options:
1061
 
1062
   o "no-minimization" which makes no minimization of automata.  This
1063
     is only worth to do when we are debugging the description and
1064
     need to look more accurately at reservations of states.
1065
 
1066
   o "time" which means printing additional time statistics about
1067
      generation of automata.
1068
 
1069
   o "v" which means generation of file describing the result
1070
     automata.  The file has suffix `.dfa' and can be used for the
1071
     description verification and debugging.
1072
 
1073
   o "w" which means generation of warning instead of error for
1074
     non-critical errors.
1075
 
1076
   o "ndfa" which makes nondeterministic finite state automata.
1077
 
1078
   o "progress" which means output of a progress bar showing how many
1079
     states were generated so far for automaton being processed.  */
1080
DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1081
 
1082
/* (define_reservation string string) names reservation (the first
1083
   string) of cpu functional units (the 2nd string).  Sometimes unit
1084
   reservations for different insns contain common parts.  In such
1085
   case, you can describe common part and use its name (the 1st
1086
   parameter) in regular expression in define_insn_reservation.  All
1087
   define_reservations, define_cpu_units, and define_query_cpu_units
1088
   should have unique names which may not be "nothing".  */
1089
DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1090
 
1091
/* (define_insn_reservation name default_latency condition regexpr)
1092
   describes reservation of cpu functional units (the 3nd operand) for
1093
   instruction which is selected by the condition (the 2nd parameter).
1094
   The first parameter is used for output of debugging information.
1095
   The reservations are described by a regular expression according
1096
   the following syntax:
1097
 
1098
       regexp = regexp "," oneof
1099
              | oneof
1100
 
1101
       oneof = oneof "|" allof
1102
             | allof
1103
 
1104
       allof = allof "+" repeat
1105
             | repeat
1106
 
1107
       repeat = element "*" number
1108
              | element
1109
 
1110
       element = cpu_function_unit_name
1111
               | reservation_name
1112
               | result_name
1113
               | "nothing"
1114
               | "(" regexp ")"
1115
 
1116
       1. "," is used for describing start of the next cycle in
1117
       reservation.
1118
 
1119
       2. "|" is used for describing the reservation described by the
1120
       first regular expression *or* the reservation described by the
1121
       second regular expression *or* etc.
1122
 
1123
       3. "+" is used for describing the reservation described by the
1124
       first regular expression *and* the reservation described by the
1125
       second regular expression *and* etc.
1126
 
1127
       4. "*" is used for convenience and simply means sequence in
1128
       which the regular expression are repeated NUMBER times with
1129
       cycle advancing (see ",").
1130
 
1131
       5. cpu functional unit name which means its reservation.
1132
 
1133
       6. reservation name -- see define_reservation.
1134
 
1135
       7. string "nothing" means no units reservation.  */
1136
 
1137
DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1138
 
1139
/* Expressions used for insn attributes.  */
1140
 
1141
/* Definition of an insn attribute.
1142
   1st operand: name of the attribute
1143
   2nd operand: comma-separated list of possible attribute values
1144
   3rd operand: expression for the default value of the attribute.  */
1145
DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1146
 
1147
/* Marker for the name of an attribute.  */
1148
DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1149
 
1150
/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1151
   in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1152
   pattern.
1153
 
1154
   (set_attr "name" "value") is equivalent to
1155
   (set (attr "name") (const_string "value"))  */
1156
DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1157
 
1158
/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1159
   specify that attribute values are to be assigned according to the
1160
   alternative matched.
1161
 
1162
   The following three expressions are equivalent:
1163
 
1164
   (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1165
                            (eq_attrq "alternative" "2") (const_string "a2")]
1166
                           (const_string "a3")))
1167
   (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1168
                                 (const_string "a3")])
1169
   (set_attr "att" "a1,a2,a3")
1170
 */
1171
DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1172
 
1173
/* A conditional expression true if the value of the specified attribute of
1174
   the current insn equals the specified value.  The first operand is the
1175
   attribute name and the second is the comparison value.  */
1176
DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1177
 
1178
/* A special case of the above representing a set of alternatives.  The first
1179
   operand is bitmap of the set, the second one is the default value.  */
1180
DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1181
 
1182
/* A conditional expression which is true if the specified flag is
1183
   true for the insn being scheduled in reorg.
1184
 
1185
   genattr.c defines the following flags which can be tested by
1186
   (attr_flag "foo") expressions in eligible_for_delay.
1187
 
1188
   forward, backward, very_likely, likely, very_unlikely, and unlikely.  */
1189
 
1190
DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1191
 
1192
/* General conditional. The first operand is a vector composed of pairs of
1193
   expressions.  The first element of each pair is evaluated, in turn.
1194
   The value of the conditional is the second expression of the first pair
1195
   whose first expression evaluates nonzero.  If none of the expressions is
1196
   true, the second operand will be used as the value of the conditional.  */
1197
DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1198
 
1199
#endif /* GENERATOR_FILE */
1200
 
1201
/*
1202
Local variables:
1203
mode:c
1204
End:
1205
*/

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