OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.dg/] [vect/] [vect-82_64.c] - Blame information for rev 405

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 149 jeremybenn
/* { dg-do run { target { { powerpc*-*-* && lp64 } && powerpc_altivec_ok } } } */
2
/* { dg-do compile { target { { powerpc*-*-* && ilp32 } && powerpc_altivec_ok } } } */
3
/* { dg-options "-O2 -ftree-vectorize -mpowerpc64 -fdump-tree-vect-stats -maltivec" } */
4
 
5
#include <stdarg.h>
6
#include "tree-vect.h"
7
 
8
#define N 16
9
 
10
int main1 ()
11
{
12
  long long unsigned int ca[N];
13
  int i;
14
 
15
  for (i = 0; i < N; i++)
16
    {
17
      ca[i] = 0;
18
    }
19
 
20
  /* check results:  */
21
  for (i = 0; i < N; i++)
22
    {
23
      if (ca[i] != 0)
24
        abort ();
25
    }
26
 
27
  return 0;
28
}
29
 
30
int main (void)
31
{
32
  check_vect ();
33
 
34
  return main1 ();
35
}
36
 
37
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
38
/* { dg-final { cleanup-tree-dump "vect" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.