OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [mips/] [asm-1.c] - Blame information for rev 154

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 149 jeremybenn
/* PR target/17565.  GCC used to put the asm into the delay slot
2
   of the call.  */
3
/* { dg-do assemble } */
4
/* { dg-mips-options "-O -mno-mips16" } */
5
int foo (int n)
6
{
7
  register int k asm ("$16") = n;
8
  if (k > 0)
9
    {
10
      bar ();
11
      asm ("li %0,0x12345678" : "=r" (k));
12
    }
13
  return k;
14
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.