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280 |
jeremybenn |
/* Natural loop analysis code for GNU compiler.
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Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
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Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "system.h"
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#include "coretypes.h"
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#include "tm.h"
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#include "rtl.h"
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#include "hard-reg-set.h"
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#include "obstack.h"
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#include "basic-block.h"
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#include "cfgloop.h"
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#include "expr.h"
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#include "output.h"
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#include "graphds.h"
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#include "params.h"
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/* Checks whether BB is executed exactly once in each LOOP iteration. */
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bool
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just_once_each_iteration_p (const struct loop *loop, const_basic_block bb)
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{
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/* It must be executed at least once each iteration. */
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if (!dominated_by_p (CDI_DOMINATORS, loop->latch, bb))
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return false;
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/* And just once. */
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if (bb->loop_father != loop)
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return false;
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/* But this was not enough. We might have some irreducible loop here. */
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if (bb->flags & BB_IRREDUCIBLE_LOOP)
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return false;
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return true;
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}
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/* Marks blocks and edges that are part of non-recognized loops; i.e. we
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throw away all latch edges and mark blocks inside any remaining cycle.
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Everything is a bit complicated due to fact we do not want to do this
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for parts of cycles that only "pass" through some loop -- i.e. for
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each cycle, we want to mark blocks that belong directly to innermost
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loop containing the whole cycle.
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LOOPS is the loop tree. */
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#define LOOP_REPR(LOOP) ((LOOP)->num + last_basic_block)
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#define BB_REPR(BB) ((BB)->index + 1)
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bool
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mark_irreducible_loops (void)
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{
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basic_block act;
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struct graph_edge *ge;
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edge e;
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edge_iterator ei;
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int src, dest;
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unsigned depth;
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struct graph *g;
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int num = number_of_loops ();
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struct loop *cloop;
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bool irred_loop_found = false;
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int i;
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gcc_assert (current_loops != NULL);
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/* Reset the flags. */
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FOR_BB_BETWEEN (act, ENTRY_BLOCK_PTR, EXIT_BLOCK_PTR, next_bb)
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{
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act->flags &= ~BB_IRREDUCIBLE_LOOP;
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FOR_EACH_EDGE (e, ei, act->succs)
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e->flags &= ~EDGE_IRREDUCIBLE_LOOP;
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}
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/* Create the edge lists. */
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g = new_graph (last_basic_block + num);
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FOR_BB_BETWEEN (act, ENTRY_BLOCK_PTR, EXIT_BLOCK_PTR, next_bb)
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FOR_EACH_EDGE (e, ei, act->succs)
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{
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/* Ignore edges to exit. */
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if (e->dest == EXIT_BLOCK_PTR)
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continue;
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src = BB_REPR (act);
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dest = BB_REPR (e->dest);
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/* Ignore latch edges. */
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if (e->dest->loop_father->header == e->dest
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&& e->dest->loop_father->latch == act)
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continue;
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/* Edges inside a single loop should be left where they are. Edges
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to subloop headers should lead to representative of the subloop,
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but from the same place.
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Edges exiting loops should lead from representative
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of the son of nearest common ancestor of the loops in that
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act lays. */
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if (e->dest->loop_father->header == e->dest)
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dest = LOOP_REPR (e->dest->loop_father);
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if (!flow_bb_inside_loop_p (act->loop_father, e->dest))
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{
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depth = 1 + loop_depth (find_common_loop (act->loop_father,
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e->dest->loop_father));
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if (depth == loop_depth (act->loop_father))
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cloop = act->loop_father;
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else
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cloop = VEC_index (loop_p, act->loop_father->superloops, depth);
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src = LOOP_REPR (cloop);
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}
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add_edge (g, src, dest)->data = e;
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}
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/* Find the strongly connected components. */
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graphds_scc (g, NULL);
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/* Mark the irreducible loops. */
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for (i = 0; i < g->n_vertices; i++)
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for (ge = g->vertices[i].succ; ge; ge = ge->succ_next)
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{
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edge real = (edge) ge->data;
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/* edge E in graph G is irreducible if it connects two vertices in the
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same scc. */
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/* All edges should lead from a component with higher number to the
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one with lower one. */
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gcc_assert (g->vertices[ge->src].component >= g->vertices[ge->dest].component);
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if (g->vertices[ge->src].component != g->vertices[ge->dest].component)
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continue;
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real->flags |= EDGE_IRREDUCIBLE_LOOP;
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irred_loop_found = true;
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if (flow_bb_inside_loop_p (real->src->loop_father, real->dest))
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real->src->flags |= BB_IRREDUCIBLE_LOOP;
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}
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free_graph (g);
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loops_state_set (LOOPS_HAVE_MARKED_IRREDUCIBLE_REGIONS);
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return irred_loop_found;
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}
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/* Counts number of insns inside LOOP. */
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int
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num_loop_insns (const struct loop *loop)
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{
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basic_block *bbs, bb;
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unsigned i, ninsns = 0;
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rtx insn;
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bbs = get_loop_body (loop);
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for (i = 0; i < loop->num_nodes; i++)
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{
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bb = bbs[i];
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FOR_BB_INSNS (bb, insn)
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if (NONDEBUG_INSN_P (insn))
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ninsns++;
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}
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free (bbs);
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if (!ninsns)
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ninsns = 1; /* To avoid division by zero. */
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return ninsns;
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}
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/* Counts number of insns executed on average per iteration LOOP. */
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int
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average_num_loop_insns (const struct loop *loop)
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{
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basic_block *bbs, bb;
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unsigned i, binsns, ninsns, ratio;
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rtx insn;
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ninsns = 0;
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bbs = get_loop_body (loop);
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for (i = 0; i < loop->num_nodes; i++)
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{
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bb = bbs[i];
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binsns = 0;
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FOR_BB_INSNS (bb, insn)
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if (NONDEBUG_INSN_P (insn))
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binsns++;
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ratio = loop->header->frequency == 0
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? BB_FREQ_MAX
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: (bb->frequency * BB_FREQ_MAX) / loop->header->frequency;
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ninsns += binsns * ratio;
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}
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free (bbs);
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ninsns /= BB_FREQ_MAX;
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if (!ninsns)
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ninsns = 1; /* To avoid division by zero. */
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return ninsns;
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}
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/* Returns expected number of iterations of LOOP, according to
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measured or guessed profile. No bounding is done on the
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value. */
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gcov_type
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expected_loop_iterations_unbounded (const struct loop *loop)
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{
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edge e;
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edge_iterator ei;
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if (loop->latch->count || loop->header->count)
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{
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gcov_type count_in, count_latch, expected;
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count_in = 0;
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count_latch = 0;
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FOR_EACH_EDGE (e, ei, loop->header->preds)
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if (e->src == loop->latch)
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count_latch = e->count;
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else
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count_in += e->count;
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if (count_in == 0)
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expected = count_latch * 2;
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else
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expected = (count_latch + count_in - 1) / count_in;
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return expected;
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}
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else
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{
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int freq_in, freq_latch;
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freq_in = 0;
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freq_latch = 0;
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FOR_EACH_EDGE (e, ei, loop->header->preds)
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if (e->src == loop->latch)
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freq_latch = EDGE_FREQUENCY (e);
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else
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freq_in += EDGE_FREQUENCY (e);
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if (freq_in == 0)
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return freq_latch * 2;
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return (freq_latch + freq_in - 1) / freq_in;
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}
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271 |
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}
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272 |
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273 |
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/* Returns expected number of LOOP iterations. The returned value is bounded
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by REG_BR_PROB_BASE. */
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275 |
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276 |
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unsigned
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expected_loop_iterations (const struct loop *loop)
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{
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279 |
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gcov_type expected = expected_loop_iterations_unbounded (loop);
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return (expected > REG_BR_PROB_BASE ? REG_BR_PROB_BASE : expected);
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}
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282 |
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283 |
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/* Returns the maximum level of nesting of subloops of LOOP. */
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284 |
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285 |
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unsigned
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get_loop_level (const struct loop *loop)
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{
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288 |
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const struct loop *ploop;
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289 |
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unsigned mx = 0, l;
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290 |
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for (ploop = loop->inner; ploop; ploop = ploop->next)
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{
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293 |
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l = get_loop_level (ploop);
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294 |
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if (l >= mx)
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mx = l + 1;
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296 |
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}
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297 |
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return mx;
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298 |
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}
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299 |
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300 |
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/* Returns estimate on cost of computing SEQ. */
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301 |
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|
302 |
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static unsigned
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303 |
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seq_cost (const_rtx seq, bool speed)
|
304 |
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{
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305 |
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unsigned cost = 0;
|
306 |
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rtx set;
|
307 |
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|
308 |
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for (; seq; seq = NEXT_INSN (seq))
|
309 |
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{
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310 |
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set = single_set (seq);
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311 |
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if (set)
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312 |
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cost += rtx_cost (set, SET, speed);
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else
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314 |
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cost++;
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315 |
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}
|
316 |
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317 |
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return cost;
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318 |
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}
|
319 |
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|
320 |
|
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/* The properties of the target. */
|
321 |
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|
322 |
|
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unsigned target_avail_regs; /* Number of available registers. */
|
323 |
|
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unsigned target_res_regs; /* Number of registers reserved for temporary
|
324 |
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expressions. */
|
325 |
|
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unsigned target_reg_cost[2]; /* The cost for register when there still
|
326 |
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is some reserve, but we are approaching
|
327 |
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the number of available registers. */
|
328 |
|
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unsigned target_spill_cost[2]; /* The cost for register when we need
|
329 |
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to spill. */
|
330 |
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|
331 |
|
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/* Initialize the constants for computing set costs. */
|
332 |
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|
333 |
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void
|
334 |
|
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init_set_costs (void)
|
335 |
|
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{
|
336 |
|
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int speed;
|
337 |
|
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rtx seq;
|
338 |
|
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rtx reg1 = gen_raw_REG (SImode, FIRST_PSEUDO_REGISTER);
|
339 |
|
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rtx reg2 = gen_raw_REG (SImode, FIRST_PSEUDO_REGISTER + 1);
|
340 |
|
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rtx addr = gen_raw_REG (Pmode, FIRST_PSEUDO_REGISTER + 2);
|
341 |
|
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rtx mem = validize_mem (gen_rtx_MEM (SImode, addr));
|
342 |
|
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unsigned i;
|
343 |
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|
344 |
|
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target_avail_regs = 0;
|
345 |
|
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
|
346 |
|
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if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i)
|
347 |
|
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&& !fixed_regs[i])
|
348 |
|
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target_avail_regs++;
|
349 |
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|
350 |
|
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target_res_regs = 3;
|
351 |
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|
352 |
|
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for (speed = 0; speed < 2; speed++)
|
353 |
|
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{
|
354 |
|
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crtl->maybe_hot_insn_p = speed;
|
355 |
|
|
/* Set up the costs for using extra registers:
|
356 |
|
|
|
357 |
|
|
1) If not many free registers remain, we should prefer having an
|
358 |
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additional move to decreasing the number of available registers.
|
359 |
|
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(TARGET_REG_COST).
|
360 |
|
|
2) If no registers are available, we need to spill, which may require
|
361 |
|
|
storing the old value to memory and loading it back
|
362 |
|
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(TARGET_SPILL_COST). */
|
363 |
|
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|
364 |
|
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start_sequence ();
|
365 |
|
|
emit_move_insn (reg1, reg2);
|
366 |
|
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seq = get_insns ();
|
367 |
|
|
end_sequence ();
|
368 |
|
|
target_reg_cost [speed] = seq_cost (seq, speed);
|
369 |
|
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|
370 |
|
|
start_sequence ();
|
371 |
|
|
emit_move_insn (mem, reg1);
|
372 |
|
|
emit_move_insn (reg2, mem);
|
373 |
|
|
seq = get_insns ();
|
374 |
|
|
end_sequence ();
|
375 |
|
|
target_spill_cost [speed] = seq_cost (seq, speed);
|
376 |
|
|
}
|
377 |
|
|
default_rtl_profile ();
|
378 |
|
|
}
|
379 |
|
|
|
380 |
|
|
/* Estimates cost of increased register pressure caused by making N_NEW new
|
381 |
|
|
registers live around the loop. N_OLD is the number of registers live
|
382 |
|
|
around the loop. */
|
383 |
|
|
|
384 |
|
|
unsigned
|
385 |
|
|
estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed)
|
386 |
|
|
{
|
387 |
|
|
unsigned cost;
|
388 |
|
|
unsigned regs_needed = n_new + n_old;
|
389 |
|
|
|
390 |
|
|
/* If we have enough registers, we should use them and not restrict
|
391 |
|
|
the transformations unnecessarily. */
|
392 |
|
|
if (regs_needed + target_res_regs <= target_avail_regs)
|
393 |
|
|
return 0;
|
394 |
|
|
|
395 |
|
|
if (regs_needed <= target_avail_regs)
|
396 |
|
|
/* If we are close to running out of registers, try to preserve
|
397 |
|
|
them. */
|
398 |
|
|
cost = target_reg_cost [speed] * n_new;
|
399 |
|
|
else
|
400 |
|
|
/* If we run out of registers, it is very expensive to add another
|
401 |
|
|
one. */
|
402 |
|
|
cost = target_spill_cost [speed] * n_new;
|
403 |
|
|
|
404 |
|
|
if (optimize && (flag_ira_region == IRA_REGION_ALL
|
405 |
|
|
|| flag_ira_region == IRA_REGION_MIXED)
|
406 |
|
|
&& number_of_loops () <= (unsigned) IRA_MAX_LOOPS_NUM)
|
407 |
|
|
/* IRA regional allocation deals with high register pressure
|
408 |
|
|
better. So decrease the cost (to do more accurate the cost
|
409 |
|
|
calculation for IRA, we need to know how many registers lives
|
410 |
|
|
through the loop transparently). */
|
411 |
|
|
cost /= 2;
|
412 |
|
|
|
413 |
|
|
return cost;
|
414 |
|
|
}
|
415 |
|
|
|
416 |
|
|
/* Sets EDGE_LOOP_EXIT flag for all loop exits. */
|
417 |
|
|
|
418 |
|
|
void
|
419 |
|
|
mark_loop_exit_edges (void)
|
420 |
|
|
{
|
421 |
|
|
basic_block bb;
|
422 |
|
|
edge e;
|
423 |
|
|
|
424 |
|
|
if (number_of_loops () <= 1)
|
425 |
|
|
return;
|
426 |
|
|
|
427 |
|
|
FOR_EACH_BB (bb)
|
428 |
|
|
{
|
429 |
|
|
edge_iterator ei;
|
430 |
|
|
|
431 |
|
|
FOR_EACH_EDGE (e, ei, bb->succs)
|
432 |
|
|
{
|
433 |
|
|
if (loop_outer (bb->loop_father)
|
434 |
|
|
&& loop_exit_edge_p (bb->loop_father, e))
|
435 |
|
|
e->flags |= EDGE_LOOP_EXIT;
|
436 |
|
|
else
|
437 |
|
|
e->flags &= ~EDGE_LOOP_EXIT;
|
438 |
|
|
}
|
439 |
|
|
}
|
440 |
|
|
}
|
441 |
|
|
|