OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [alpha/] [alpha.opt] - Blame information for rev 282

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 282 jeremybenn
; Options for the DEC Alpha port of the compiler
2
;
3
; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
4
;
5
; This file is part of GCC.
6
;
7
; GCC is free software; you can redistribute it and/or modify it under
8
; the terms of the GNU General Public License as published by the Free
9
; Software Foundation; either version 3, or (at your option) any later
10
; version.
11
;
12
; GCC is distributed in the hope that it will be useful, but WITHOUT
13
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
; License for more details.
16
;
17
; You should have received a copy of the GNU General Public License
18
; along with GCC; see the file COPYING3.  If not see
19
; .
20
 
21
msoft-float
22
Target Report Mask(SOFT_FP)
23
Do not use hardware fp
24
 
25
mfp-regs
26
Target Report Mask(FPREGS)
27
Use fp registers
28
 
29
mgas
30
Target RejectNegative Mask(GAS)
31
Assume GAS
32
 
33
malpha-as
34
Target RejectNegative InverseMask(GAS)
35
Do not assume GAS
36
 
37
mieee-conformant
38
Target RejectNegative Mask(IEEE_CONFORMANT)
39
Request IEEE-conformant math library routines (OSF/1)
40
 
41
mieee
42
Target Report RejectNegative Mask(IEEE)
43
Emit IEEE-conformant code, without inexact exceptions
44
 
45
mieee-with-inexact
46
Target Report RejectNegative Mask(IEEE_WITH_INEXACT)
47
 
48
mbuild-constants
49
Target Report Mask(BUILD_CONSTANTS)
50
Do not emit complex integer constants to read-only memory
51
 
52
mfloat-vax
53
Target Report RejectNegative Mask(FLOAT_VAX)
54
Use VAX fp
55
 
56
mfloat-ieee
57
Target Report RejectNegative InverseMask(FLOAT_VAX)
58
Do not use VAX fp
59
 
60
mbwx
61
Target Report Mask(BWX)
62
Emit code for the byte/word ISA extension
63
 
64
mmax
65
Target Report Mask(MAX)
66
Emit code for the motion video ISA extension
67
 
68
mfix
69
Target Report Mask(FIX)
70
Emit code for the fp move and sqrt ISA extension
71
 
72
mcix
73
Target Report Mask(CIX)
74
Emit code for the counting ISA extension
75
 
76
mexplicit-relocs
77
Target Report Mask(EXPLICIT_RELOCS)
78
Emit code using explicit relocation directives
79
 
80
msmall-data
81
Target Report RejectNegative Mask(SMALL_DATA)
82
Emit 16-bit relocations to the small data areas
83
 
84
mlarge-data
85
Target Report RejectNegative InverseMask(SMALL_DATA)
86
Emit 32-bit relocations to the small data areas
87
 
88
msmall-text
89
Target Report RejectNegative Mask(SMALL_TEXT)
90
Emit direct branches to local functions
91
 
92
mlarge-text
93
Target Report RejectNegative InverseMask(SMALL_TEXT)
94
Emit indirect branches to local functions
95
 
96
mtls-kernel
97
Target Report Mask(TLS_KERNEL)
98
Emit rdval instead of rduniq for thread pointer
99
 
100
mlong-double-128
101
Target Report RejectNegative Mask(LONG_DOUBLE_128)
102
Use 128-bit long double
103
 
104
mlong-double-64
105
Target Report RejectNegative InverseMask(LONG_DOUBLE_128)
106
Use 64-bit long double
107
 
108
mcpu=
109
Target RejectNegative Joined Var(alpha_cpu_string)
110
Use features of and schedule given CPU
111
 
112
mtune=
113
Target RejectNegative Joined Var(alpha_tune_string)
114
Schedule given CPU
115
 
116
mfp-rounding-mode=
117
Target RejectNegative Joined Var(alpha_fprm_string)
118
Control the generated fp rounding mode
119
 
120
mfp-trap-mode=
121
Target RejectNegative Joined Var(alpha_fptm_string)
122
Control the IEEE trap mode
123
 
124
mtrap-precision=
125
Target RejectNegative Joined Var(alpha_tp_string)
126
Control the precision given to fp exceptions
127
 
128
mmemory-latency=
129
Target RejectNegative Joined Var(alpha_mlat_string)
130
Tune expected memory latency
131
 
132
mtls-size=
133
Target RejectNegative Joined UInteger Var(alpha_tls_size) Init(32)
134
Specify bit size of immediate TLS offsets

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.