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jeremybenn |
;; Generic ARM Pipeline Description
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;; Copyright (C) 2003, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; . */
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(define_automaton "arm")
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;; Write buffer
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;
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; Strictly, we should model a 4-deep write buffer for ARM7xx based chips
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;
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; The write buffer on some of the arm6 processors is hard to model exactly.
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; There is room in the buffer for up to two addresses and up to eight words
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; of memory, but the two needn't be split evenly. When writing the two
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; addresses are fully pipelined. However, a read from memory that is not
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; currently in the cache will block until the writes have completed.
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; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so
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; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous
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; (they aren't allowed to be at present) then there is a startup cost of 1MCLK
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; cycle to add as well.
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(define_cpu_unit "write_buf" "arm")
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;; Write blockage unit
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;
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; The write_blockage unit models (partially), the fact that reads will stall
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; until the write buffer empties.
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; The f_mem_r and r_mem_f could also block, but they are to the stack,
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; so we don't model them here
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(define_cpu_unit "write_blockage" "arm")
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;; Core
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;
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(define_cpu_unit "core" "arm")
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(define_insn_reservation "r_mem_f_wbuf" 5
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "r_mem_f")))
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"core+write_buf*3")
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(define_insn_reservation "store_wbuf" 5
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store1")))
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"core+write_buf*3+write_blockage*5")
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(define_insn_reservation "store2_wbuf" 7
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store2")))
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"core+write_buf*4+write_blockage*7")
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(define_insn_reservation "store3_wbuf" 9
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store3")))
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"core+write_buf*5+write_blockage*9")
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(define_insn_reservation "store4_wbuf" 11
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store4")))
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"core+write_buf*6+write_blockage*11")
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(define_insn_reservation "store2" 3
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "model_wbuf" "no")
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(eq_attr "type" "store2")))
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"core*3")
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(define_insn_reservation "store3" 4
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "model_wbuf" "no")
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(eq_attr "type" "store3")))
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"core*4")
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(define_insn_reservation "store4" 5
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "model_wbuf" "no")
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(eq_attr "type" "store4")))
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"core*5")
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(define_insn_reservation "store_ldsched" 1
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "ldsched" "yes")
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(eq_attr "type" "store1")))
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"core")
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(define_insn_reservation "load_ldsched_xscale" 3
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "ldsched" "yes")
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(and (eq_attr "type" "load_byte,load1")
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(eq_attr "is_xscale" "yes"))))
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"core")
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(define_insn_reservation "load_ldsched" 2
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "ldsched" "yes")
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(and (eq_attr "type" "load_byte,load1")
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(eq_attr "is_xscale" "no"))))
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"core")
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(define_insn_reservation "load_or_store" 2
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "ldsched" "!yes")
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(eq_attr "type" "load_byte,load1,load2,load3,load4,store1")))
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"core*2")
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(define_insn_reservation "mult" 16
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "ldsched" "no") (eq_attr "type" "mult")))
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"core*16")
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(define_insn_reservation "mult_ldsched_strongarm" 3
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "ldsched" "yes")
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(and (eq_attr "is_strongarm" "yes")
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(eq_attr "type" "mult"))))
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"core*2")
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(define_insn_reservation "mult_ldsched" 4
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "ldsched" "yes")
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(and (eq_attr "is_strongarm" "no")
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(eq_attr "type" "mult"))))
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"core*4")
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(define_insn_reservation "multi_cycle" 32
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(and (eq_attr "generic_sched" "yes")
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(and (eq_attr "core_cycles" "multi")
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(eq_attr "type" "!mult,load_byte,load1,load2,load3,load4,store1,store2,store3,store4")))
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"core*32")
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(define_insn_reservation "single_cycle" 1
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(and (eq_attr "generic_sched" "yes")
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(eq_attr "core_cycles" "single"))
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"core")
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