Subversion Repositories openrisc_me

/* Output routines for GCC for ARM.

   Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,

   2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010

   Free Software Foundation, Inc.

   Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)

   and Martin Simmons (@harleqn.co.uk).

   More major hacks by Richard Earnshaw (rearnsha@arm.com).

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it

   under the terms of the GNU General Public License as published

   by the Free Software Foundation; either version 3, or (at your

   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with GCC; see the file COPYING3.  If not see

   <http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "system.h"

#include "coretypes.h"

#include "tm.h"

#include "rtl.h"

#include "tree.h"

#include "obstack.h"

#include "regs.h"

#include "hard-reg-set.h"

#include "real.h"

#include "insn-config.h"

#include "conditions.h"

#include "output.h"

#include "insn-attr.h"

#include "flags.h"

#include "reload.h"

#include "function.h"

#include "expr.h"

#include "optabs.h"

#include "toplev.h"

#include "recog.h"

#include "cgraph.h"

#include "ggc.h"

#include "except.h"

#include "c-pragma.h"

#include "integrate.h"

#include "tm_p.h"

#include "target.h"

#include "target-def.h"

#include "debug.h"

#include "langhooks.h"

#include "df.h"

#include "intl.h"

#include "libfuncs.h"

/* Forward definitions of types.  */

typedef struct minipool_node    Mnode;

typedef struct minipool_fixup   Mfix;

void (*arm_lang_output_object_attributes_hook)(void);

/* Forward function declarations.  */

static int arm_compute_static_chain_stack_bytes (void);

static arm_stack_offsets *arm_get_frame_offsets (void);

static void arm_add_gc_roots (void);

static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,

                             HOST_WIDE_INT, rtx, rtx, int, int);

static unsigned bit_count (unsigned long);

static int arm_address_register_rtx_p (rtx, int);

static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);

static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);

static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);

static rtx arm_legitimize_address (rtx, rtx, enum machine_mode);

static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode);

inline static int thumb1_index_register_rtx_p (rtx, int);

static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);

static int thumb_far_jump_used_p (void);

static bool thumb_force_lr_save (void);

static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);

static rtx emit_sfm (int, int);

static unsigned arm_size_return_regs (void);

static bool arm_assemble_integer (rtx, unsigned int, int);

static const char *fp_const_from_val (REAL_VALUE_TYPE *);

static arm_cc get_arm_condition_code (rtx);

static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);

static rtx is_jump_table (rtx);

static const char *output_multi_immediate (rtx *, const char *, const char *,

                                           int, HOST_WIDE_INT);

static const char *shift_op (rtx, HOST_WIDE_INT *);

static struct machine_function *arm_init_machine_status (void);

static void thumb_exit (FILE *, int);

static rtx is_jump_table (rtx);

static HOST_WIDE_INT get_jump_table_size (rtx);

static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);

static Mnode *add_minipool_forward_ref (Mfix *);

static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);

static Mnode *add_minipool_backward_ref (Mfix *);

static void assign_minipool_offsets (Mfix *);

static void arm_print_value (FILE *, rtx);

static void dump_minipool (rtx);

static int arm_barrier_cost (rtx);

static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);

static void push_minipool_barrier (rtx, HOST_WIDE_INT);

static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,

                               rtx);

static void arm_reorg (void);

static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);

static unsigned long arm_compute_save_reg0_reg12_mask (void);

static unsigned long arm_compute_save_reg_mask (void);

static unsigned long arm_isr_value (tree);

static unsigned long arm_compute_func_type (void);

static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);

static tree arm_handle_pcs_attribute (tree *, tree, tree, int, bool *);

static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);

#if TARGET_DLLIMPORT_DECL_ATTRIBUTES

static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);

#endif

static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);

static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);

static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT);

static int arm_comp_type_attributes (const_tree, const_tree);

static void arm_set_default_type_attributes (tree);

static int arm_adjust_cost (rtx, rtx, rtx, int);

static int count_insns_for_constant (HOST_WIDE_INT, int);

static int arm_get_strip_length (int);

static bool arm_function_ok_for_sibcall (tree, tree);

static enum machine_mode arm_promote_function_mode (const_tree,

                                                    enum machine_mode, int *,

                                                    const_tree, int);

static bool arm_return_in_memory (const_tree, const_tree);

static rtx arm_function_value (const_tree, const_tree, bool);

static rtx arm_libcall_value (enum machine_mode, const_rtx);

static void arm_internal_label (FILE *, const char *, unsigned long);

static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,

                                 tree);

static bool arm_have_conditional_execution (void);

static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);

static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);

static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);

static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);

static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);

static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);

static bool arm_rtx_costs (rtx, int, int, int *, bool);

static int arm_address_cost (rtx, bool);

static bool arm_memory_load_p (rtx);

static bool arm_cirrus_insn_p (rtx);

static void cirrus_reorg (rtx);

static void arm_init_builtins (void);

static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);

static void arm_init_iwmmxt_builtins (void);

static rtx safe_vector_operand (rtx, enum machine_mode);

static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);

static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);

static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);

static void emit_constant_insn (rtx cond, rtx pattern);

static rtx emit_set_insn (rtx, rtx);

static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,

                                  tree, bool);

static rtx aapcs_allocate_return_reg (enum machine_mode, const_tree,

                                      const_tree);

static int aapcs_select_return_coproc (const_tree, const_tree);

#ifdef OBJECT_FORMAT_ELF

static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;

static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;

#endif

#ifndef ARM_PE

static void arm_encode_section_info (tree, rtx, int);

#endif

static void arm_file_end (void);

static void arm_file_start (void);

static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,

                                        tree, int *, int);

static bool arm_pass_by_reference (CUMULATIVE_ARGS *,

                                   enum machine_mode, const_tree, bool);

static bool arm_promote_prototypes (const_tree);

static bool arm_default_short_enums (void);

static bool arm_align_anon_bitfield (void);

static bool arm_return_in_msb (const_tree);

static bool arm_must_pass_in_stack (enum machine_mode, const_tree);

static bool arm_return_in_memory (const_tree, const_tree);

#ifdef TARGET_UNWIND_INFO

static void arm_unwind_emit (FILE *, rtx);

static bool arm_output_ttype (rtx);

#endif

static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);

static rtx arm_dwarf_register_span (rtx);

static tree arm_cxx_guard_type (void);

static bool arm_cxx_guard_mask_bit (void);

static tree arm_get_cookie_size (tree);

static bool arm_cookie_has_size (void);

static bool arm_cxx_cdtor_returns_this (void);

static bool arm_cxx_key_method_may_be_inline (void);

static void arm_cxx_determine_class_data_visibility (tree);

static bool arm_cxx_class_data_always_comdat (void);

static bool arm_cxx_use_aeabi_atexit (void);

static void arm_init_libfuncs (void);

static tree arm_build_builtin_va_list (void);

static void arm_expand_builtin_va_start (tree, rtx);

static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);

static bool arm_handle_option (size_t, const char *, int);

static void arm_target_help (void);

static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);

static bool arm_cannot_copy_insn_p (rtx);

static bool arm_tls_symbol_p (rtx x);

static int arm_issue_rate (void);

static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;

static bool arm_allocate_stack_slots_for_args (void);

static const char *arm_invalid_parameter_type (const_tree t);

static const char *arm_invalid_return_type (const_tree t);

static tree arm_promoted_type (const_tree t);

static tree arm_convert_to_type (tree type, tree expr);

static bool arm_scalar_mode_supported_p (enum machine_mode);

static bool arm_frame_pointer_required (void);

static bool arm_can_eliminate (const int, const int);

static void arm_asm_trampoline_template (FILE *);

static void arm_trampoline_init (rtx, tree, rtx);

static rtx arm_trampoline_adjust_address (rtx);

/* Table of machine attributes.  */

static const struct attribute_spec arm_attribute_table[] =

{

  /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */

  /* Function calls made to this symbol must be done indirectly, because

     it may lie outside of the 26 bit addressing range of a normal function

     call.  */

  { "long_call",    0, 0, false, true,  true,  NULL },

  /* Whereas these functions are always known to reside within the 26 bit

     addressing range.  */

  { "short_call",   0, 0, false, true,  true,  NULL },

  /* Specify the procedure call conventions for a function.  */

  { "pcs",          1, 1, false, true,  true,  arm_handle_pcs_attribute },

  /* Interrupt Service Routines have special prologue and epilogue requirements.  */

  { "isr",          0, 1, false, false, false, arm_handle_isr_attribute },

  { "interrupt",    0, 1, false, false, false, arm_handle_isr_attribute },

  { "naked",        0, 0, true,  false, false, arm_handle_fndecl_attribute },

#ifdef ARM_PE

  /* ARM/PE has three new attributes:

     interfacearm - ?

     dllexport - for exporting a function/variable that will live in a dll

     dllimport - for importing a function/variable from a dll

     Microsoft allows multiple declspecs in one __declspec, separating

     them with spaces.  We do NOT support this.  Instead, use __declspec

     multiple times.

  */

  { "dllimport",    0, 0, true,  false, false, NULL },

  { "dllexport",    0, 0, true,  false, false, NULL },

  { "interfacearm", 0, 0, true,  false, false, arm_handle_fndecl_attribute },

#elif TARGET_DLLIMPORT_DECL_ATTRIBUTES

  { "dllimport",    0, 0, false, false, false, handle_dll_attribute },

  { "dllexport",    0, 0, false, false, false, handle_dll_attribute },

  { "notshared",    0, 0, false, true, false, arm_handle_notshared_attribute },

#endif

  { NULL,           0, 0, false, false, false, NULL }

};

/* Initialize the GCC target structure.  */

#if TARGET_DLLIMPORT_DECL_ATTRIBUTES

#undef  TARGET_MERGE_DECL_ATTRIBUTES

#define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes

#endif

#undef TARGET_LEGITIMIZE_ADDRESS

#define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address

#undef  TARGET_ATTRIBUTE_TABLE

#define TARGET_ATTRIBUTE_TABLE arm_attribute_table

#undef TARGET_ASM_FILE_START

#define TARGET_ASM_FILE_START arm_file_start

#undef TARGET_ASM_FILE_END

#define TARGET_ASM_FILE_END arm_file_end

#undef  TARGET_ASM_ALIGNED_SI_OP

#define TARGET_ASM_ALIGNED_SI_OP NULL

#undef  TARGET_ASM_INTEGER

#define TARGET_ASM_INTEGER arm_assemble_integer

#undef  TARGET_ASM_FUNCTION_PROLOGUE

#define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue

#undef  TARGET_ASM_FUNCTION_EPILOGUE

#define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue

#undef  TARGET_DEFAULT_TARGET_FLAGS

#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)

#undef  TARGET_HANDLE_OPTION

#define TARGET_HANDLE_OPTION arm_handle_option

#undef  TARGET_HELP

#define TARGET_HELP arm_target_help

#undef  TARGET_COMP_TYPE_ATTRIBUTES

#define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes

#undef  TARGET_SET_DEFAULT_TYPE_ATTRIBUTES

#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes

#undef  TARGET_SCHED_ADJUST_COST

#define TARGET_SCHED_ADJUST_COST arm_adjust_cost

#undef TARGET_ENCODE_SECTION_INFO

#ifdef ARM_PE

#define TARGET_ENCODE_SECTION_INFO  arm_pe_encode_section_info

#else

#define TARGET_ENCODE_SECTION_INFO  arm_encode_section_info

#endif

#undef  TARGET_STRIP_NAME_ENCODING

#define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding

#undef  TARGET_ASM_INTERNAL_LABEL

#define TARGET_ASM_INTERNAL_LABEL arm_internal_label

#undef  TARGET_FUNCTION_OK_FOR_SIBCALL

#define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall

#undef  TARGET_FUNCTION_VALUE

#define TARGET_FUNCTION_VALUE arm_function_value

#undef  TARGET_LIBCALL_VALUE

#define TARGET_LIBCALL_VALUE arm_libcall_value

#undef  TARGET_ASM_OUTPUT_MI_THUNK

#define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk

#undef  TARGET_ASM_CAN_OUTPUT_MI_THUNK

#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall

#undef  TARGET_RTX_COSTS

#define TARGET_RTX_COSTS arm_rtx_costs

#undef  TARGET_ADDRESS_COST

#define TARGET_ADDRESS_COST arm_address_cost

#undef TARGET_SHIFT_TRUNCATION_MASK

#define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask

#undef TARGET_VECTOR_MODE_SUPPORTED_P

#define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p

#undef  TARGET_MACHINE_DEPENDENT_REORG

#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg

#undef  TARGET_INIT_BUILTINS

#define TARGET_INIT_BUILTINS  arm_init_builtins

#undef  TARGET_EXPAND_BUILTIN

#define TARGET_EXPAND_BUILTIN arm_expand_builtin

#undef TARGET_INIT_LIBFUNCS

#define TARGET_INIT_LIBFUNCS arm_init_libfuncs

#undef TARGET_PROMOTE_FUNCTION_MODE

#define TARGET_PROMOTE_FUNCTION_MODE arm_promote_function_mode

#undef TARGET_PROMOTE_PROTOTYPES

#define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes

#undef TARGET_PASS_BY_REFERENCE

#define TARGET_PASS_BY_REFERENCE arm_pass_by_reference

#undef TARGET_ARG_PARTIAL_BYTES

#define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes

#undef  TARGET_SETUP_INCOMING_VARARGS

#define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs

#undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS

#define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args

#undef TARGET_ASM_TRAMPOLINE_TEMPLATE

#define TARGET_ASM_TRAMPOLINE_TEMPLATE arm_asm_trampoline_template

#undef TARGET_TRAMPOLINE_INIT

#define TARGET_TRAMPOLINE_INIT arm_trampoline_init

#undef TARGET_TRAMPOLINE_ADJUST_ADDRESS

#define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address

#undef TARGET_DEFAULT_SHORT_ENUMS

#define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums

#undef TARGET_ALIGN_ANON_BITFIELD

#define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield

#undef TARGET_NARROW_VOLATILE_BITFIELD

#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false

#undef TARGET_CXX_GUARD_TYPE

#define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type

#undef TARGET_CXX_GUARD_MASK_BIT

#define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit

#undef TARGET_CXX_GET_COOKIE_SIZE

#define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size

#undef TARGET_CXX_COOKIE_HAS_SIZE

#define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size

#undef TARGET_CXX_CDTOR_RETURNS_THIS

#define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this

#undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE

#define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline

#undef TARGET_CXX_USE_AEABI_ATEXIT

#define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit

#undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY

#define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \

  arm_cxx_determine_class_data_visibility

#undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT

#define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat

#undef TARGET_RETURN_IN_MSB

#define TARGET_RETURN_IN_MSB arm_return_in_msb

#undef TARGET_RETURN_IN_MEMORY

#define TARGET_RETURN_IN_MEMORY arm_return_in_memory

#undef TARGET_MUST_PASS_IN_STACK

#define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack

#ifdef TARGET_UNWIND_INFO

#undef TARGET_UNWIND_EMIT

#define TARGET_UNWIND_EMIT arm_unwind_emit

/* EABI unwinding tables use a different format for the typeinfo tables.  */

#undef TARGET_ASM_TTYPE

#define TARGET_ASM_TTYPE arm_output_ttype

#undef TARGET_ARM_EABI_UNWINDER

#define TARGET_ARM_EABI_UNWINDER true

#endif /* TARGET_UNWIND_INFO */

#undef TARGET_DWARF_HANDLE_FRAME_UNSPEC

#define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec

#undef TARGET_DWARF_REGISTER_SPAN

#define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span

#undef  TARGET_CANNOT_COPY_INSN_P

#define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p

#ifdef HAVE_AS_TLS

#undef TARGET_HAVE_TLS

#define TARGET_HAVE_TLS true

#endif

#undef TARGET_HAVE_CONDITIONAL_EXECUTION

#define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution

#undef TARGET_CANNOT_FORCE_CONST_MEM

#define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem

#undef TARGET_MAX_ANCHOR_OFFSET

#define TARGET_MAX_ANCHOR_OFFSET 4095

/* The minimum is set such that the total size of the block

   for a particular anchor is -4088 + 1 + 4095 bytes, which is

   divisible by eight, ensuring natural spacing of anchors.  */

#undef TARGET_MIN_ANCHOR_OFFSET

#define TARGET_MIN_ANCHOR_OFFSET -4088

#undef TARGET_SCHED_ISSUE_RATE

#define TARGET_SCHED_ISSUE_RATE arm_issue_rate

#undef TARGET_MANGLE_TYPE

#define TARGET_MANGLE_TYPE arm_mangle_type

#undef TARGET_BUILD_BUILTIN_VA_LIST

#define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list

#undef TARGET_EXPAND_BUILTIN_VA_START

#define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start

#undef TARGET_GIMPLIFY_VA_ARG_EXPR

#define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr

#ifdef HAVE_AS_TLS

#undef TARGET_ASM_OUTPUT_DWARF_DTPREL

#define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel

#endif

#undef TARGET_LEGITIMATE_ADDRESS_P

#define TARGET_LEGITIMATE_ADDRESS_P     arm_legitimate_address_p

#undef TARGET_INVALID_PARAMETER_TYPE

#define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type

#undef TARGET_INVALID_RETURN_TYPE

#define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type

#undef TARGET_PROMOTED_TYPE

#define TARGET_PROMOTED_TYPE arm_promoted_type

#undef TARGET_CONVERT_TO_TYPE

#define TARGET_CONVERT_TO_TYPE arm_convert_to_type

#undef TARGET_SCALAR_MODE_SUPPORTED_P

#define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p

#undef TARGET_FRAME_POINTER_REQUIRED

#define TARGET_FRAME_POINTER_REQUIRED arm_frame_pointer_required

#undef TARGET_CAN_ELIMINATE

#define TARGET_CAN_ELIMINATE arm_can_eliminate

struct gcc_target targetm = TARGET_INITIALIZER;

/* Obstack for minipool constant handling.  */

static struct obstack minipool_obstack;

static char *         minipool_startobj;

/* The maximum number of insns skipped which

   will be conditionalised if possible.  */

static int max_insns_skipped = 5;

extern FILE * asm_out_file;

/* True if we are currently building a constant table.  */

int making_const_table;

/* The processor for which instructions should be scheduled.  */

enum processor_type arm_tune = arm_none;

/* The default processor used if not overridden by commandline.  */

static enum processor_type arm_default_cpu = arm_none;

/* Which floating point hardware to schedule for.  */

int arm_fpu_attr;

/* Which floating popint hardware to use.  */

const struct arm_fpu_desc *arm_fpu_desc;

/* Whether to use floating point hardware.  */

enum float_abi_type arm_float_abi;

/* Which __fp16 format to use.  */

enum arm_fp16_format_type arm_fp16_format;

/* Which ABI to use.  */

enum arm_abi_type arm_abi;

/* Which thread pointer model to use.  */

enum arm_tp_type target_thread_pointer = TP_AUTO;

/* Used to parse -mstructure_size_boundary command line option.  */

int    arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;

/* Used for Thumb call_via trampolines.  */

rtx thumb_call_via_label[14];

static int thumb_call_reg_needed;

/* Bit values used to identify processor capabilities.  */

#define FL_CO_PROC    (1 << 0)        /* Has external co-processor bus */

#define FL_ARCH3M     (1 << 1)        /* Extended multiply */

#define FL_MODE26     (1 << 2)        /* 26-bit mode support */

#define FL_MODE32     (1 << 3)        /* 32-bit mode support */

#define FL_ARCH4      (1 << 4)        /* Architecture rel 4 */

#define FL_ARCH5      (1 << 5)        /* Architecture rel 5 */

#define FL_THUMB      (1 << 6)        /* Thumb aware */

#define FL_LDSCHED    (1 << 7)        /* Load scheduling necessary */

#define FL_STRONG     (1 << 8)        /* StrongARM */

#define FL_ARCH5E     (1 << 9)        /* DSP extensions to v5 */

#define FL_XSCALE     (1 << 10)       /* XScale */

#define FL_CIRRUS     (1 << 11)       /* Cirrus/DSP.  */

#define FL_ARCH6      (1 << 12)       /* Architecture rel 6.  Adds

                                         media instructions.  */

#define FL_VFPV2      (1 << 13)       /* Vector Floating Point V2.  */

#define FL_WBUF       (1 << 14)       /* Schedule for write buffer ops.

                                         Note: ARM6 & 7 derivatives only.  */

#define FL_ARCH6K     (1 << 15)       /* Architecture rel 6 K extensions.  */

#define FL_THUMB2     (1 << 16)       /* Thumb-2.  */

#define FL_NOTM       (1 << 17)       /* Instructions not present in the 'M'

                                         profile.  */

#define FL_DIV        (1 << 18)       /* Hardware divide.  */

#define FL_VFPV3      (1 << 19)       /* Vector Floating Point V3.  */

#define FL_NEON       (1 << 20)       /* Neon instructions.  */

#define FL_ARCH7EM    (1 << 21)       /* Instructions present in the ARMv7E-M

                                         architecture.  */

#define FL_IWMMXT     (1 << 29)       /* XScale v2 or "Intel Wireless MMX technology".  */

#define FL_FOR_ARCH2    FL_NOTM

#define FL_FOR_ARCH3    (FL_FOR_ARCH2 | FL_MODE32)

#define FL_FOR_ARCH3M   (FL_FOR_ARCH3 | FL_ARCH3M)

#define FL_FOR_ARCH4    (FL_FOR_ARCH3M | FL_ARCH4)

#define FL_FOR_ARCH4T   (FL_FOR_ARCH4 | FL_THUMB)

#define FL_FOR_ARCH5    (FL_FOR_ARCH4 | FL_ARCH5)

#define FL_FOR_ARCH5T   (FL_FOR_ARCH5 | FL_THUMB)

#define FL_FOR_ARCH5E   (FL_FOR_ARCH5 | FL_ARCH5E)

#define FL_FOR_ARCH5TE  (FL_FOR_ARCH5E | FL_THUMB)

#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE

#define FL_FOR_ARCH6    (FL_FOR_ARCH5TE | FL_ARCH6)

#define FL_FOR_ARCH6J   FL_FOR_ARCH6

#define FL_FOR_ARCH6K   (FL_FOR_ARCH6 | FL_ARCH6K)

#define FL_FOR_ARCH6Z   FL_FOR_ARCH6

#define FL_FOR_ARCH6ZK  FL_FOR_ARCH6K

#define FL_FOR_ARCH6T2  (FL_FOR_ARCH6 | FL_THUMB2)

#define FL_FOR_ARCH6M   (FL_FOR_ARCH6 & ~FL_NOTM)

#define FL_FOR_ARCH7    (FL_FOR_ARCH6T2 &~ FL_NOTM)

#define FL_FOR_ARCH7A   (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)

#define FL_FOR_ARCH7R   (FL_FOR_ARCH7A | FL_DIV)

#define FL_FOR_ARCH7M   (FL_FOR_ARCH7 | FL_DIV)

#define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)

/* The bits in this mask specify which

   instructions we are allowed to generate.  */

static unsigned long insn_flags = 0;

/* The bits in this mask specify which instruction scheduling options should

   be used.  */

static unsigned long tune_flags = 0;

/* The following are used in the arm.md file as equivalents to bits

   in the above two flag variables.  */

/* Nonzero if this chip supports the ARM Architecture 3M extensions.  */

int arm_arch3m = 0;

/* Nonzero if this chip supports the ARM Architecture 4 extensions.  */

int arm_arch4 = 0;

/* Nonzero if this chip supports the ARM Architecture 4t extensions.  */

int arm_arch4t = 0;

/* Nonzero if this chip supports the ARM Architecture 5 extensions.  */

int arm_arch5 = 0;

/* Nonzero if this chip supports the ARM Architecture 5E extensions.  */

int arm_arch5e = 0;

/* Nonzero if this chip supports the ARM Architecture 6 extensions.  */

int arm_arch6 = 0;

/* Nonzero if this chip supports the ARM 6K extensions.  */

int arm_arch6k = 0;

/* Nonzero if instructions not present in the 'M' profile can be used.  */

int arm_arch_notm = 0;

/* Nonzero if instructions present in ARMv7E-M can be used.  */

int arm_arch7em = 0;

/* Nonzero if this chip can benefit from load scheduling.  */

int arm_ld_sched = 0;

/* Nonzero if this chip is a StrongARM.  */

int arm_tune_strongarm = 0;

/* Nonzero if this chip is a Cirrus variant.  */

int arm_arch_cirrus = 0;

/* Nonzero if this chip supports Intel Wireless MMX technology.  */

int arm_arch_iwmmxt = 0;

/* Nonzero if this chip is an XScale.  */

int arm_arch_xscale = 0;

/* Nonzero if tuning for XScale  */

int arm_tune_xscale = 0;

/* Nonzero if we want to tune for stores that access the write-buffer.

   This typically means an ARM6 or ARM7 with MMU or MPU.  */

int arm_tune_wbuf = 0;

/* Nonzero if tuning for Cortex-A9.  */

int arm_tune_cortex_a9 = 0;

/* Nonzero if generating Thumb instructions.  */

int thumb_code = 0;

/* Nonzero if we should define __THUMB_INTERWORK__ in the

   preprocessor.

   XXX This is a bit of a hack, it's intended to help work around

   problems in GLD which doesn't understand that armv5t code is

   interworking clean.  */

int arm_cpp_interwork = 0;

/* Nonzero if chip supports Thumb 2.  */

int arm_arch_thumb2;

/* Nonzero if chip supports integer division instruction.  */

int arm_arch_hwdiv;

/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we

   must report the mode of the memory reference from PRINT_OPERAND to

   PRINT_OPERAND_ADDRESS.  */

enum machine_mode output_memory_reference_mode;

/* The register number to be used for the PIC offset register.  */

unsigned arm_pic_register = INVALID_REGNUM;

/* Set to 1 after arm_reorg has started.  Reset to start at the start of

   the next function.  */

static int after_arm_reorg = 0;

/* The maximum number of insns to be used when loading a constant.  */

static int arm_constant_limit = 3;

static enum arm_pcs arm_pcs_default;