OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [arm/] [iwmmxt.md] - Blame information for rev 282

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 282 jeremybenn
;; ??? This file needs auditing for thumb2
2
;; Patterns for the Intel Wireless MMX technology architecture.
3
;; Copyright (C) 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
4
;; Contributed by Red Hat.
5
 
6
;; This file is part of GCC.
7
 
8
;; GCC is free software; you can redistribute it and/or modify it under
9
;; the terms of the GNU General Public License as published by the Free
10
;; Software Foundation; either version 3, or (at your option) any later
11
;; version.
12
 
13
;; GCC is distributed in the hope that it will be useful, but WITHOUT
14
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
;; License for more details.
17
 
18
;; You should have received a copy of the GNU General Public License
19
;; along with GCC; see the file COPYING3.  If not see
20
;; .
21
 
22
;; Integer element sizes implemented by IWMMXT.
23
(define_mode_iterator VMMX [V2SI V4HI V8QI])
24
 
25
;; Integer element sizes for shifts.
26
(define_mode_iterator VSHFT [V4HI V2SI DI])
27
 
28
;; Determine element size suffix from vector mode.
29
(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
30
 
31
(define_insn "iwmmxt_iordi3"
32
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
33
        (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
34
                (match_operand:DI 2 "register_operand"  "y,r,r")))]
35
  "TARGET_REALLY_IWMMXT"
36
  "@
37
   wor%?\\t%0, %1, %2
38
   #
39
   #"
40
  [(set_attr "predicable" "yes")
41
   (set_attr "length" "4,8,8")])
42
 
43
(define_insn "iwmmxt_xordi3"
44
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
45
        (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
46
                (match_operand:DI 2 "register_operand"  "y,r,r")))]
47
  "TARGET_REALLY_IWMMXT"
48
  "@
49
   wxor%?\\t%0, %1, %2
50
   #
51
   #"
52
  [(set_attr "predicable" "yes")
53
   (set_attr "length" "4,8,8")])
54
 
55
(define_insn "iwmmxt_anddi3"
56
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
57
        (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
58
                (match_operand:DI 2 "register_operand"  "y,r,r")))]
59
  "TARGET_REALLY_IWMMXT"
60
  "@
61
   wand%?\\t%0, %1, %2
62
   #
63
   #"
64
  [(set_attr "predicable" "yes")
65
   (set_attr "length" "4,8,8")])
66
 
67
(define_insn "iwmmxt_nanddi3"
68
  [(set (match_operand:DI                 0 "register_operand" "=y")
69
        (and:DI (match_operand:DI         1 "register_operand"  "y")
70
                (not:DI (match_operand:DI 2 "register_operand"  "y"))))]
71
  "TARGET_REALLY_IWMMXT"
72
  "wandn%?\\t%0, %1, %2"
73
  [(set_attr "predicable" "yes")])
74
 
75
(define_insn "*iwmmxt_arm_movdi"
76
  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy")
77
        (match_operand:DI 1 "di_operand"              "rIK,mi,r,y,yr,y,yrUy,y"))]
78
  "TARGET_REALLY_IWMMXT
79
   && (   register_operand (operands[0], DImode)
80
       || register_operand (operands[1], DImode))"
81
  "*
82
{
83
  switch (which_alternative)
84
    {
85
    default:
86
      return output_move_double (operands);
87
    case 0:
88
      return \"#\";
89
    case 3:
90
      return \"wmov%?\\t%0,%1\";
91
    case 4:
92
      return \"tmcrr%?\\t%0,%Q1,%R1\";
93
    case 5:
94
      return \"tmrrc%?\\t%Q0,%R0,%1\";
95
    case 6:
96
      return \"wldrd%?\\t%0,%1\";
97
    case 7:
98
      return \"wstrd%?\\t%1,%0\";
99
    }
100
}"
101
  [(set_attr "length"         "8,8,8,4,4,4,4,4")
102
   (set_attr "type"           "*,load1,store2,*,*,*,*,*")
103
   (set_attr "pool_range"     "*,1020,*,*,*,*,*,*")
104
   (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")]
105
)
106
 
107
(define_insn "*iwmmxt_movsi_insn"
108
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,rk, m,z,r,?z,Uy,z")
109
        (match_operand:SI 1 "general_operand"      "rk, I,K,mi,rk,r,z,Uy,z, z"))]
110
  "TARGET_REALLY_IWMMXT
111
   && (   register_operand (operands[0], SImode)
112
       || register_operand (operands[1], SImode))"
113
  "*
114
   switch (which_alternative)
115
   {
116
   case 0: return \"mov\\t%0, %1\";
117
   case 1: return \"mov\\t%0, %1\";
118
   case 2: return \"mvn\\t%0, #%B1\";
119
   case 3: return \"ldr\\t%0, %1\";
120
   case 4: return \"str\\t%1, %0\";
121
   case 5: return \"tmcr\\t%0, %1\";
122
   case 6: return \"tmrc\\t%0, %1\";
123
   case 7: return arm_output_load_gr (operands);
124
   case 8: return \"wstrw\\t%1, %0\";
125
   default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\";
126
  }"
127
  [(set_attr "type"           "*,*,*,load1,store1,*,*,load1,store1,*")
128
   (set_attr "length"         "*,*,*,*,        *,*,*,  16,     *,8")
129
   (set_attr "pool_range"     "*,*,*,4096,     *,*,*,1024,     *,*")
130
   (set_attr "neg_pool_range" "*,*,*,4084,     *,*,*,   *,  1012,*")
131
   ;; Note - the "predicable" attribute is not allowed to have alternatives.
132
   ;; Since the wSTRw wCx instruction is not predicable, we cannot support
133
   ;; predicating any of the alternatives in this template.  Instead,
134
   ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
135
   (set_attr "predicable"     "no")
136
   ;; Also - we have to pretend that these insns clobber the condition code
137
   ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
138
   ;; them.
139
   (set_attr "conds" "clob")]
140
)
141
 
142
;; Because iwmmxt_movsi_insn is not predicable, we provide the
143
;; cond_exec version explicitly, with appropriate constraints.
144
 
145
(define_insn "*cond_iwmmxt_movsi_insn"
146
  [(cond_exec
147
     (match_operator 2 "arm_comparison_operator"
148
      [(match_operand 3 "cc_register" "")
149
      (const_int 0)])
150
     (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
151
          (match_operand:SI 1 "general_operand"      "rI,K,mi,r,r,z")))]
152
  "TARGET_REALLY_IWMMXT
153
   && (   register_operand (operands[0], SImode)
154
       || register_operand (operands[1], SImode))"
155
  "*
156
   switch (which_alternative)
157
   {
158
   case 0: return \"mov%?\\t%0, %1\";
159
   case 1: return \"mvn%?\\t%0, #%B1\";
160
   case 2: return \"ldr%?\\t%0, %1\";
161
   case 3: return \"str%?\\t%1, %0\";
162
   case 4: return \"tmcr%?\\t%0, %1\";
163
   default: return \"tmrc%?\\t%0, %1\";
164
  }"
165
  [(set_attr "type"           "*,*,load1,store1,*,*")
166
   (set_attr "pool_range"     "*,*,4096,     *,*,*")
167
   (set_attr "neg_pool_range" "*,*,4084,     *,*,*")]
168
)
169
 
170
(define_insn "mov_internal"
171
  [(set (match_operand:VMMX 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r,?m")
172
        (match_operand:VMMX 1 "general_operand"       "y,y,mi,y,r,r,mi,r"))]
173
  "TARGET_REALLY_IWMMXT"
174
  "*
175
   switch (which_alternative)
176
   {
177
   case 0: return \"wmov%?\\t%0, %1\";
178
   case 1: return \"wstrd%?\\t%1, %0\";
179
   case 2: return \"wldrd%?\\t%0, %1\";
180
   case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
181
   case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
182
   case 5: return \"#\";
183
   default: return output_move_double (operands);
184
   }"
185
  [(set_attr "predicable" "yes")
186
   (set_attr "length"         "4,     4,   4,4,4,8,   8,8")
187
   (set_attr "type"           "*,store1,load1,*,*,*,load1,store1")
188
   (set_attr "pool_range"     "*,     *, 256,*,*,*, 256,*")
189
   (set_attr "neg_pool_range" "*,     *, 244,*,*,*, 244,*")])
190
 
191
;; Vector add/subtract
192
 
193
(define_insn "*add3_iwmmxt"
194
  [(set (match_operand:VMMX            0 "register_operand" "=y")
195
        (plus:VMMX (match_operand:VMMX 1 "register_operand"  "y")
196
                   (match_operand:VMMX 2 "register_operand"  "y")))]
197
  "TARGET_REALLY_IWMMXT"
198
  "wadd%?\\t%0, %1, %2"
199
  [(set_attr "predicable" "yes")])
200
 
201
(define_insn "ssaddv8qi3"
202
  [(set (match_operand:V8QI               0 "register_operand" "=y")
203
        (ss_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
204
                      (match_operand:V8QI 2 "register_operand"  "y")))]
205
  "TARGET_REALLY_IWMMXT"
206
  "waddbss%?\\t%0, %1, %2"
207
  [(set_attr "predicable" "yes")])
208
 
209
(define_insn "ssaddv4hi3"
210
  [(set (match_operand:V4HI               0 "register_operand" "=y")
211
        (ss_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
212
                      (match_operand:V4HI 2 "register_operand"  "y")))]
213
  "TARGET_REALLY_IWMMXT"
214
  "waddhss%?\\t%0, %1, %2"
215
  [(set_attr "predicable" "yes")])
216
 
217
(define_insn "ssaddv2si3"
218
  [(set (match_operand:V2SI               0 "register_operand" "=y")
219
        (ss_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
220
                      (match_operand:V2SI 2 "register_operand"  "y")))]
221
  "TARGET_REALLY_IWMMXT"
222
  "waddwss%?\\t%0, %1, %2"
223
  [(set_attr "predicable" "yes")])
224
 
225
(define_insn "usaddv8qi3"
226
  [(set (match_operand:V8QI               0 "register_operand" "=y")
227
        (us_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
228
                      (match_operand:V8QI 2 "register_operand"  "y")))]
229
  "TARGET_REALLY_IWMMXT"
230
  "waddbus%?\\t%0, %1, %2"
231
  [(set_attr "predicable" "yes")])
232
 
233
(define_insn "usaddv4hi3"
234
  [(set (match_operand:V4HI               0 "register_operand" "=y")
235
        (us_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
236
                      (match_operand:V4HI 2 "register_operand"  "y")))]
237
  "TARGET_REALLY_IWMMXT"
238
  "waddhus%?\\t%0, %1, %2"
239
  [(set_attr "predicable" "yes")])
240
 
241
(define_insn "usaddv2si3"
242
  [(set (match_operand:V2SI               0 "register_operand" "=y")
243
        (us_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
244
                      (match_operand:V2SI 2 "register_operand"  "y")))]
245
  "TARGET_REALLY_IWMMXT"
246
  "waddwus%?\\t%0, %1, %2"
247
  [(set_attr "predicable" "yes")])
248
 
249
(define_insn "*sub3_iwmmxt"
250
  [(set (match_operand:VMMX             0 "register_operand" "=y")
251
        (minus:VMMX (match_operand:VMMX 1 "register_operand"  "y")
252
                    (match_operand:VMMX 2 "register_operand"  "y")))]
253
  "TARGET_REALLY_IWMMXT"
254
  "wsub%?\\t%0, %1, %2"
255
  [(set_attr "predicable" "yes")])
256
 
257
(define_insn "sssubv8qi3"
258
  [(set (match_operand:V8QI                0 "register_operand" "=y")
259
        (ss_minus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
260
                       (match_operand:V8QI 2 "register_operand"  "y")))]
261
  "TARGET_REALLY_IWMMXT"
262
  "wsubbss%?\\t%0, %1, %2"
263
  [(set_attr "predicable" "yes")])
264
 
265
(define_insn "sssubv4hi3"
266
  [(set (match_operand:V4HI                0 "register_operand" "=y")
267
        (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
268
                       (match_operand:V4HI 2 "register_operand" "y")))]
269
  "TARGET_REALLY_IWMMXT"
270
  "wsubhss%?\\t%0, %1, %2"
271
  [(set_attr "predicable" "yes")])
272
 
273
(define_insn "sssubv2si3"
274
  [(set (match_operand:V2SI                0 "register_operand" "=y")
275
        (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
276
                       (match_operand:V2SI 2 "register_operand" "y")))]
277
  "TARGET_REALLY_IWMMXT"
278
  "wsubwss%?\\t%0, %1, %2"
279
  [(set_attr "predicable" "yes")])
280
 
281
(define_insn "ussubv8qi3"
282
  [(set (match_operand:V8QI                0 "register_operand" "=y")
283
        (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
284
                       (match_operand:V8QI 2 "register_operand" "y")))]
285
  "TARGET_REALLY_IWMMXT"
286
  "wsubbus%?\\t%0, %1, %2"
287
  [(set_attr "predicable" "yes")])
288
 
289
(define_insn "ussubv4hi3"
290
  [(set (match_operand:V4HI                0 "register_operand" "=y")
291
        (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
292
                       (match_operand:V4HI 2 "register_operand" "y")))]
293
  "TARGET_REALLY_IWMMXT"
294
  "wsubhus%?\\t%0, %1, %2"
295
  [(set_attr "predicable" "yes")])
296
 
297
(define_insn "ussubv2si3"
298
  [(set (match_operand:V2SI                0 "register_operand" "=y")
299
        (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
300
                       (match_operand:V2SI 2 "register_operand" "y")))]
301
  "TARGET_REALLY_IWMMXT"
302
  "wsubwus%?\\t%0, %1, %2"
303
  [(set_attr "predicable" "yes")])
304
 
305
(define_insn "*mulv4hi3_iwmmxt"
306
  [(set (match_operand:V4HI            0 "register_operand" "=y")
307
        (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
308
                   (match_operand:V4HI 2 "register_operand" "y")))]
309
  "TARGET_REALLY_IWMMXT"
310
  "wmulul%?\\t%0, %1, %2"
311
  [(set_attr "predicable" "yes")])
312
 
313
(define_insn "smulv4hi3_highpart"
314
  [(set (match_operand:V4HI                                0 "register_operand" "=y")
315
        (truncate:V4HI
316
         (lshiftrt:V4SI
317
          (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
318
                     (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
319
          (const_int 16))))]
320
  "TARGET_REALLY_IWMMXT"
321
  "wmulsm%?\\t%0, %1, %2"
322
  [(set_attr "predicable" "yes")])
323
 
324
(define_insn "umulv4hi3_highpart"
325
  [(set (match_operand:V4HI                                0 "register_operand" "=y")
326
        (truncate:V4HI
327
         (lshiftrt:V4SI
328
          (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
329
                     (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
330
          (const_int 16))))]
331
  "TARGET_REALLY_IWMMXT"
332
  "wmulum%?\\t%0, %1, %2"
333
  [(set_attr "predicable" "yes")])
334
 
335
(define_insn "iwmmxt_wmacs"
336
  [(set (match_operand:DI               0 "register_operand" "=y")
337
        (unspec:DI [(match_operand:DI   1 "register_operand" "0")
338
                    (match_operand:V4HI 2 "register_operand" "y")
339
                    (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
340
  "TARGET_REALLY_IWMMXT"
341
  "wmacs%?\\t%0, %2, %3"
342
  [(set_attr "predicable" "yes")])
343
 
344
(define_insn "iwmmxt_wmacsz"
345
  [(set (match_operand:DI               0 "register_operand" "=y")
346
        (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
347
                    (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
348
  "TARGET_REALLY_IWMMXT"
349
  "wmacsz%?\\t%0, %1, %2"
350
  [(set_attr "predicable" "yes")])
351
 
352
(define_insn "iwmmxt_wmacu"
353
  [(set (match_operand:DI               0 "register_operand" "=y")
354
        (unspec:DI [(match_operand:DI   1 "register_operand" "0")
355
                    (match_operand:V4HI 2 "register_operand" "y")
356
                    (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
357
  "TARGET_REALLY_IWMMXT"
358
  "wmacu%?\\t%0, %2, %3"
359
  [(set_attr "predicable" "yes")])
360
 
361
(define_insn "iwmmxt_wmacuz"
362
  [(set (match_operand:DI               0 "register_operand" "=y")
363
        (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
364
                    (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
365
  "TARGET_REALLY_IWMMXT"
366
  "wmacuz%?\\t%0, %1, %2"
367
  [(set_attr "predicable" "yes")])
368
 
369
;; Same as xordi3, but don't show input operands so that we don't think
370
;; they are live.
371
(define_insn "iwmmxt_clrdi"
372
  [(set (match_operand:DI 0 "register_operand" "=y")
373
        (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
374
  "TARGET_REALLY_IWMMXT"
375
  "wxor%?\\t%0, %0, %0"
376
  [(set_attr "predicable" "yes")])
377
 
378
;; Seems like cse likes to generate these, so we have to support them.
379
 
380
(define_insn "*iwmmxt_clrv8qi"
381
  [(set (match_operand:V8QI 0 "register_operand" "=y")
382
        (const_vector:V8QI [(const_int 0) (const_int 0)
383
                            (const_int 0) (const_int 0)
384
                            (const_int 0) (const_int 0)
385
                            (const_int 0) (const_int 0)]))]
386
  "TARGET_REALLY_IWMMXT"
387
  "wxor%?\\t%0, %0, %0"
388
  [(set_attr "predicable" "yes")])
389
 
390
(define_insn "*iwmmxt_clrv4hi"
391
  [(set (match_operand:V4HI 0 "register_operand" "=y")
392
        (const_vector:V4HI [(const_int 0) (const_int 0)
393
                            (const_int 0) (const_int 0)]))]
394
  "TARGET_REALLY_IWMMXT"
395
  "wxor%?\\t%0, %0, %0"
396
  [(set_attr "predicable" "yes")])
397
 
398
(define_insn "*iwmmxt_clrv2si"
399
  [(set (match_operand:V2SI 0 "register_operand" "=y")
400
        (const_vector:V2SI [(const_int 0) (const_int 0)]))]
401
  "TARGET_REALLY_IWMMXT"
402
  "wxor%?\\t%0, %0, %0"
403
  [(set_attr "predicable" "yes")])
404
 
405
;; Unsigned averages/sum of absolute differences
406
 
407
(define_insn "iwmmxt_uavgrndv8qi3"
408
  [(set (match_operand:V8QI              0 "register_operand" "=y")
409
        (ashiftrt:V8QI
410
         (plus:V8QI (plus:V8QI
411
                     (match_operand:V8QI 1 "register_operand" "y")
412
                     (match_operand:V8QI 2 "register_operand" "y"))
413
                    (const_vector:V8QI [(const_int 1)
414
                                        (const_int 1)
415
                                        (const_int 1)
416
                                        (const_int 1)
417
                                        (const_int 1)
418
                                        (const_int 1)
419
                                        (const_int 1)
420
                                        (const_int 1)]))
421
         (const_int 1)))]
422
  "TARGET_REALLY_IWMMXT"
423
  "wavg2br%?\\t%0, %1, %2"
424
  [(set_attr "predicable" "yes")])
425
 
426
(define_insn "iwmmxt_uavgrndv4hi3"
427
  [(set (match_operand:V4HI              0 "register_operand" "=y")
428
        (ashiftrt:V4HI
429
         (plus:V4HI (plus:V4HI
430
                     (match_operand:V4HI 1 "register_operand" "y")
431
                     (match_operand:V4HI 2 "register_operand" "y"))
432
                    (const_vector:V4HI [(const_int 1)
433
                                        (const_int 1)
434
                                        (const_int 1)
435
                                        (const_int 1)]))
436
         (const_int 1)))]
437
  "TARGET_REALLY_IWMMXT"
438
  "wavg2hr%?\\t%0, %1, %2"
439
  [(set_attr "predicable" "yes")])
440
 
441
 
442
(define_insn "iwmmxt_uavgv8qi3"
443
  [(set (match_operand:V8QI                 0 "register_operand" "=y")
444
        (ashiftrt:V8QI (plus:V8QI
445
                        (match_operand:V8QI 1 "register_operand" "y")
446
                        (match_operand:V8QI 2 "register_operand" "y"))
447
                       (const_int 1)))]
448
  "TARGET_REALLY_IWMMXT"
449
  "wavg2b%?\\t%0, %1, %2"
450
  [(set_attr "predicable" "yes")])
451
 
452
(define_insn "iwmmxt_uavgv4hi3"
453
  [(set (match_operand:V4HI                 0 "register_operand" "=y")
454
        (ashiftrt:V4HI (plus:V4HI
455
                        (match_operand:V4HI 1 "register_operand" "y")
456
                        (match_operand:V4HI 2 "register_operand" "y"))
457
                       (const_int 1)))]
458
  "TARGET_REALLY_IWMMXT"
459
  "wavg2h%?\\t%0, %1, %2"
460
  [(set_attr "predicable" "yes")])
461
 
462
(define_insn "iwmmxt_psadbw"
463
  [(set (match_operand:V8QI                       0 "register_operand" "=y")
464
        (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
465
                              (match_operand:V8QI 2 "register_operand" "y"))))]
466
  "TARGET_REALLY_IWMMXT"
467
  "psadbw%?\\t%0, %1, %2"
468
  [(set_attr "predicable" "yes")])
469
 
470
 
471
;; Insert/extract/shuffle
472
 
473
(define_insn "iwmmxt_tinsrb"
474
  [(set (match_operand:V8QI                             0 "register_operand"    "=y")
475
        (vec_merge:V8QI (match_operand:V8QI             1 "register_operand"     "0")
476
                        (vec_duplicate:V8QI
477
                         (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
478
                        (match_operand:SI               3 "immediate_operand"    "i")))]
479
  "TARGET_REALLY_IWMMXT"
480
  "tinsrb%?\\t%0, %2, %3"
481
  [(set_attr "predicable" "yes")])
482
 
483
(define_insn "iwmmxt_tinsrh"
484
  [(set (match_operand:V4HI                             0 "register_operand"    "=y")
485
        (vec_merge:V4HI (match_operand:V4HI             1 "register_operand"     "0")
486
                        (vec_duplicate:V4HI
487
                         (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
488
                        (match_operand:SI               3 "immediate_operand"    "i")))]
489
  "TARGET_REALLY_IWMMXT"
490
  "tinsrh%?\\t%0, %2, %3"
491
  [(set_attr "predicable" "yes")])
492
 
493
(define_insn "iwmmxt_tinsrw"
494
  [(set (match_operand:V2SI                 0 "register_operand"    "=y")
495
        (vec_merge:V2SI (match_operand:V2SI 1 "register_operand"     "0")
496
                        (vec_duplicate:V2SI
497
                         (match_operand:SI  2 "nonimmediate_operand" "r"))
498
                        (match_operand:SI   3 "immediate_operand"    "i")))]
499
  "TARGET_REALLY_IWMMXT"
500
  "tinsrw%?\\t%0, %2, %3"
501
  [(set_attr "predicable" "yes")])
502
 
503
(define_insn "iwmmxt_textrmub"
504
  [(set (match_operand:SI                                  0 "register_operand" "=r")
505
        (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
506
                                       (parallel
507
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
508
  "TARGET_REALLY_IWMMXT"
509
  "textrmub%?\\t%0, %1, %2"
510
  [(set_attr "predicable" "yes")])
511
 
512
(define_insn "iwmmxt_textrmsb"
513
  [(set (match_operand:SI                                  0 "register_operand" "=r")
514
        (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
515
                                       (parallel
516
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
517
  "TARGET_REALLY_IWMMXT"
518
  "textrmsb%?\\t%0, %1, %2"
519
  [(set_attr "predicable" "yes")])
520
 
521
(define_insn "iwmmxt_textrmuh"
522
  [(set (match_operand:SI                                  0 "register_operand" "=r")
523
        (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
524
                                       (parallel
525
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
526
  "TARGET_REALLY_IWMMXT"
527
  "textrmuh%?\\t%0, %1, %2"
528
  [(set_attr "predicable" "yes")])
529
 
530
(define_insn "iwmmxt_textrmsh"
531
  [(set (match_operand:SI                                  0 "register_operand" "=r")
532
        (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
533
                                       (parallel
534
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
535
  "TARGET_REALLY_IWMMXT"
536
  "textrmsh%?\\t%0, %1, %2"
537
  [(set_attr "predicable" "yes")])
538
 
539
;; There are signed/unsigned variants of this instruction, but they are
540
;; pointless.
541
(define_insn "iwmmxt_textrmw"
542
  [(set (match_operand:SI                           0 "register_operand" "=r")
543
        (vec_select:SI (match_operand:V2SI          1 "register_operand" "y")
544
                       (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
545
  "TARGET_REALLY_IWMMXT"
546
  "textrmsw%?\\t%0, %1, %2"
547
  [(set_attr "predicable" "yes")])
548
 
549
(define_insn "iwmmxt_wshufh"
550
  [(set (match_operand:V4HI               0 "register_operand" "=y")
551
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
552
                      (match_operand:SI   2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
553
  "TARGET_REALLY_IWMMXT"
554
  "wshufh%?\\t%0, %1, %2"
555
  [(set_attr "predicable" "yes")])
556
 
557
;; Mask-generating comparisons
558
;;
559
;; Note - you cannot use patterns like these here:
560
;;
561
;;   (set: (match:) (: (match:) (match:)))
562
;;
563
;; Because GCC will assume that the truth value (1 or 0) is installed
564
;; into the entire destination vector, (with the '1' going into the least
565
;; significant element of the vector).  This is not how these instructions
566
;; behave.
567
;;
568
;; Unfortunately the current patterns are illegal.  They are SET insns
569
;; without a SET in them.  They work in most cases for ordinary code
570
;; generation, but there are circumstances where they can cause gcc to fail.
571
;; XXX - FIXME.
572
 
573
(define_insn "eqv8qi3"
574
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
575
                     (match_operand:V8QI 1 "register_operand"  "y")
576
                     (match_operand:V8QI 2 "register_operand"  "y")]
577
                    VUNSPEC_WCMP_EQ)]
578
  "TARGET_REALLY_IWMMXT"
579
  "wcmpeqb%?\\t%0, %1, %2"
580
  [(set_attr "predicable" "yes")])
581
 
582
(define_insn "eqv4hi3"
583
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
584
                     (match_operand:V4HI 1 "register_operand"  "y")
585
                     (match_operand:V4HI 2 "register_operand"  "y")]
586
                    VUNSPEC_WCMP_EQ)]
587
  "TARGET_REALLY_IWMMXT"
588
  "wcmpeqh%?\\t%0, %1, %2"
589
  [(set_attr "predicable" "yes")])
590
 
591
(define_insn "eqv2si3"
592
  [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y")
593
                          (match_operand:V2SI 1 "register_operand"  "y")
594
                          (match_operand:V2SI 2 "register_operand"  "y")]
595
                         VUNSPEC_WCMP_EQ)]
596
  "TARGET_REALLY_IWMMXT"
597
  "wcmpeqw%?\\t%0, %1, %2"
598
  [(set_attr "predicable" "yes")])
599
 
600
(define_insn "gtuv8qi3"
601
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
602
                     (match_operand:V8QI 1 "register_operand"  "y")
603
                     (match_operand:V8QI 2 "register_operand"  "y")]
604
                    VUNSPEC_WCMP_GTU)]
605
  "TARGET_REALLY_IWMMXT"
606
  "wcmpgtub%?\\t%0, %1, %2"
607
  [(set_attr "predicable" "yes")])
608
 
609
(define_insn "gtuv4hi3"
610
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
611
                     (match_operand:V4HI 1 "register_operand"  "y")
612
                     (match_operand:V4HI 2 "register_operand"  "y")]
613
                    VUNSPEC_WCMP_GTU)]
614
  "TARGET_REALLY_IWMMXT"
615
  "wcmpgtuh%?\\t%0, %1, %2"
616
  [(set_attr "predicable" "yes")])
617
 
618
(define_insn "gtuv2si3"
619
  [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
620
                     (match_operand:V2SI 1 "register_operand"  "y")
621
                     (match_operand:V2SI 2 "register_operand"  "y")]
622
                    VUNSPEC_WCMP_GTU)]
623
  "TARGET_REALLY_IWMMXT"
624
  "wcmpgtuw%?\\t%0, %1, %2"
625
  [(set_attr "predicable" "yes")])
626
 
627
(define_insn "gtv8qi3"
628
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
629
                     (match_operand:V8QI 1 "register_operand"  "y")
630
                     (match_operand:V8QI 2 "register_operand"  "y")]
631
                    VUNSPEC_WCMP_GT)]
632
  "TARGET_REALLY_IWMMXT"
633
  "wcmpgtsb%?\\t%0, %1, %2"
634
  [(set_attr "predicable" "yes")])
635
 
636
(define_insn "gtv4hi3"
637
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
638
                     (match_operand:V4HI 1 "register_operand"  "y")
639
                     (match_operand:V4HI 2 "register_operand"  "y")]
640
                    VUNSPEC_WCMP_GT)]
641
  "TARGET_REALLY_IWMMXT"
642
  "wcmpgtsh%?\\t%0, %1, %2"
643
  [(set_attr "predicable" "yes")])
644
 
645
(define_insn "gtv2si3"
646
  [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
647
                     (match_operand:V2SI 1 "register_operand"  "y")
648
                     (match_operand:V2SI 2 "register_operand"  "y")]
649
                    VUNSPEC_WCMP_GT)]
650
  "TARGET_REALLY_IWMMXT"
651
  "wcmpgtsw%?\\t%0, %1, %2"
652
  [(set_attr "predicable" "yes")])
653
 
654
;; Max/min insns
655
 
656
(define_insn "*smax3_iwmmxt"
657
  [(set (match_operand:VMMX            0 "register_operand" "=y")
658
        (smax:VMMX (match_operand:VMMX 1 "register_operand" "y")
659
                   (match_operand:VMMX 2 "register_operand" "y")))]
660
  "TARGET_REALLY_IWMMXT"
661
  "wmaxs%?\\t%0, %1, %2"
662
  [(set_attr "predicable" "yes")])
663
 
664
(define_insn "*umax3_iwmmxt"
665
  [(set (match_operand:VMMX            0 "register_operand" "=y")
666
        (umax:VMMX (match_operand:VMMX 1 "register_operand" "y")
667
                   (match_operand:VMMX 2 "register_operand" "y")))]
668
  "TARGET_REALLY_IWMMXT"
669
  "wmaxu%?\\t%0, %1, %2"
670
  [(set_attr "predicable" "yes")])
671
 
672
(define_insn "*smin3_iwmmxt"
673
  [(set (match_operand:VMMX            0 "register_operand" "=y")
674
        (smin:VMMX (match_operand:VMMX 1 "register_operand" "y")
675
                   (match_operand:VMMX 2 "register_operand" "y")))]
676
  "TARGET_REALLY_IWMMXT"
677
  "wmins%?\\t%0, %1, %2"
678
  [(set_attr "predicable" "yes")])
679
 
680
(define_insn "*umin3_iwmmxt"
681
  [(set (match_operand:VMMX            0 "register_operand" "=y")
682
        (umin:VMMX (match_operand:VMMX 1 "register_operand" "y")
683
                   (match_operand:VMMX 2 "register_operand" "y")))]
684
  "TARGET_REALLY_IWMMXT"
685
  "wminu%?\\t%0, %1, %2"
686
  [(set_attr "predicable" "yes")])
687
 
688
;; Pack/unpack insns.
689
 
690
(define_insn "iwmmxt_wpackhss"
691
  [(set (match_operand:V8QI                    0 "register_operand" "=y")
692
        (vec_concat:V8QI
693
         (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
694
         (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
695
  "TARGET_REALLY_IWMMXT"
696
  "wpackhss%?\\t%0, %1, %2"
697
  [(set_attr "predicable" "yes")])
698
 
699
(define_insn "iwmmxt_wpackwss"
700
  [(set (match_operand:V4HI                    0 "register_operand" "=y")
701
        (vec_concat:V4HI
702
         (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
703
         (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
704
  "TARGET_REALLY_IWMMXT"
705
  "wpackwss%?\\t%0, %1, %2"
706
  [(set_attr "predicable" "yes")])
707
 
708
(define_insn "iwmmxt_wpackdss"
709
  [(set (match_operand:V2SI                0 "register_operand" "=y")
710
        (vec_concat:V2SI
711
         (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
712
         (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
713
  "TARGET_REALLY_IWMMXT"
714
  "wpackdss%?\\t%0, %1, %2"
715
  [(set_attr "predicable" "yes")])
716
 
717
(define_insn "iwmmxt_wpackhus"
718
  [(set (match_operand:V8QI                    0 "register_operand" "=y")
719
        (vec_concat:V8QI
720
         (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
721
         (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
722
  "TARGET_REALLY_IWMMXT"
723
  "wpackhus%?\\t%0, %1, %2"
724
  [(set_attr "predicable" "yes")])
725
 
726
(define_insn "iwmmxt_wpackwus"
727
  [(set (match_operand:V4HI                    0 "register_operand" "=y")
728
        (vec_concat:V4HI
729
         (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
730
         (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
731
  "TARGET_REALLY_IWMMXT"
732
  "wpackwus%?\\t%0, %1, %2"
733
  [(set_attr "predicable" "yes")])
734
 
735
(define_insn "iwmmxt_wpackdus"
736
  [(set (match_operand:V2SI                0 "register_operand" "=y")
737
        (vec_concat:V2SI
738
         (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
739
         (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
740
  "TARGET_REALLY_IWMMXT"
741
  "wpackdus%?\\t%0, %1, %2"
742
  [(set_attr "predicable" "yes")])
743
 
744
 
745
(define_insn "iwmmxt_wunpckihb"
746
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
747
        (vec_merge:V8QI
748
         (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
749
                          (parallel [(const_int 4)
750
                                     (const_int 0)
751
                                     (const_int 5)
752
                                     (const_int 1)
753
                                     (const_int 6)
754
                                     (const_int 2)
755
                                     (const_int 7)
756
                                     (const_int 3)]))
757
         (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
758
                          (parallel [(const_int 0)
759
                                     (const_int 4)
760
                                     (const_int 1)
761
                                     (const_int 5)
762
                                     (const_int 2)
763
                                     (const_int 6)
764
                                     (const_int 3)
765
                                     (const_int 7)]))
766
         (const_int 85)))]
767
  "TARGET_REALLY_IWMMXT"
768
  "wunpckihb%?\\t%0, %1, %2"
769
  [(set_attr "predicable" "yes")])
770
 
771
(define_insn "iwmmxt_wunpckihh"
772
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
773
        (vec_merge:V4HI
774
         (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
775
                          (parallel [(const_int 0)
776
                                     (const_int 2)
777
                                     (const_int 1)
778
                                     (const_int 3)]))
779
         (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
780
                          (parallel [(const_int 2)
781
                                     (const_int 0)
782
                                     (const_int 3)
783
                                     (const_int 1)]))
784
         (const_int 5)))]
785
  "TARGET_REALLY_IWMMXT"
786
  "wunpckihh%?\\t%0, %1, %2"
787
  [(set_attr "predicable" "yes")])
788
 
789
(define_insn "iwmmxt_wunpckihw"
790
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
791
        (vec_merge:V2SI
792
         (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
793
                          (parallel [(const_int 0)
794
                                     (const_int 1)]))
795
         (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
796
                          (parallel [(const_int 1)
797
                                     (const_int 0)]))
798
         (const_int 1)))]
799
  "TARGET_REALLY_IWMMXT"
800
  "wunpckihw%?\\t%0, %1, %2"
801
  [(set_attr "predicable" "yes")])
802
 
803
(define_insn "iwmmxt_wunpckilb"
804
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
805
        (vec_merge:V8QI
806
         (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
807
                          (parallel [(const_int 0)
808
                                     (const_int 4)
809
                                     (const_int 1)
810
                                     (const_int 5)
811
                                     (const_int 2)
812
                                     (const_int 6)
813
                                     (const_int 3)
814
                                     (const_int 7)]))
815
         (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
816
                          (parallel [(const_int 4)
817
                                     (const_int 0)
818
                                     (const_int 5)
819
                                     (const_int 1)
820
                                     (const_int 6)
821
                                     (const_int 2)
822
                                     (const_int 7)
823
                                     (const_int 3)]))
824
         (const_int 85)))]
825
  "TARGET_REALLY_IWMMXT"
826
  "wunpckilb%?\\t%0, %1, %2"
827
  [(set_attr "predicable" "yes")])
828
 
829
(define_insn "iwmmxt_wunpckilh"
830
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
831
        (vec_merge:V4HI
832
         (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
833
                          (parallel [(const_int 2)
834
                                     (const_int 0)
835
                                     (const_int 3)
836
                                     (const_int 1)]))
837
         (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
838
                          (parallel [(const_int 0)
839
                                     (const_int 2)
840
                                     (const_int 1)
841
                                     (const_int 3)]))
842
         (const_int 5)))]
843
  "TARGET_REALLY_IWMMXT"
844
  "wunpckilh%?\\t%0, %1, %2"
845
  [(set_attr "predicable" "yes")])
846
 
847
(define_insn "iwmmxt_wunpckilw"
848
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
849
        (vec_merge:V2SI
850
         (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
851
                           (parallel [(const_int 1)
852
                                      (const_int 0)]))
853
         (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
854
                          (parallel [(const_int 0)
855
                                     (const_int 1)]))
856
         (const_int 1)))]
857
  "TARGET_REALLY_IWMMXT"
858
  "wunpckilw%?\\t%0, %1, %2"
859
  [(set_attr "predicable" "yes")])
860
 
861
(define_insn "iwmmxt_wunpckehub"
862
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
863
        (zero_extend:V4HI
864
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
865
                          (parallel [(const_int 4) (const_int 5)
866
                                     (const_int 6) (const_int 7)]))))]
867
  "TARGET_REALLY_IWMMXT"
868
  "wunpckehub%?\\t%0, %1"
869
  [(set_attr "predicable" "yes")])
870
 
871
(define_insn "iwmmxt_wunpckehuh"
872
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
873
        (zero_extend:V2SI
874
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
875
                          (parallel [(const_int 2) (const_int 3)]))))]
876
  "TARGET_REALLY_IWMMXT"
877
  "wunpckehuh%?\\t%0, %1"
878
  [(set_attr "predicable" "yes")])
879
 
880
(define_insn "iwmmxt_wunpckehuw"
881
  [(set (match_operand:DI                   0 "register_operand" "=y")
882
        (zero_extend:DI
883
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
884
                        (parallel [(const_int 1)]))))]
885
  "TARGET_REALLY_IWMMXT"
886
  "wunpckehuw%?\\t%0, %1"
887
  [(set_attr "predicable" "yes")])
888
 
889
(define_insn "iwmmxt_wunpckehsb"
890
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
891
        (sign_extend:V4HI
892
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
893
                          (parallel [(const_int 4) (const_int 5)
894
                                     (const_int 6) (const_int 7)]))))]
895
  "TARGET_REALLY_IWMMXT"
896
  "wunpckehsb%?\\t%0, %1"
897
  [(set_attr "predicable" "yes")])
898
 
899
(define_insn "iwmmxt_wunpckehsh"
900
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
901
        (sign_extend:V2SI
902
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
903
                          (parallel [(const_int 2) (const_int 3)]))))]
904
  "TARGET_REALLY_IWMMXT"
905
  "wunpckehsh%?\\t%0, %1"
906
  [(set_attr "predicable" "yes")])
907
 
908
(define_insn "iwmmxt_wunpckehsw"
909
  [(set (match_operand:DI                   0 "register_operand" "=y")
910
        (sign_extend:DI
911
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
912
                        (parallel [(const_int 1)]))))]
913
  "TARGET_REALLY_IWMMXT"
914
  "wunpckehsw%?\\t%0, %1"
915
  [(set_attr "predicable" "yes")])
916
 
917
(define_insn "iwmmxt_wunpckelub"
918
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
919
        (zero_extend:V4HI
920
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
921
                          (parallel [(const_int 0) (const_int 1)
922
                                     (const_int 2) (const_int 3)]))))]
923
  "TARGET_REALLY_IWMMXT"
924
  "wunpckelub%?\\t%0, %1"
925
  [(set_attr "predicable" "yes")])
926
 
927
(define_insn "iwmmxt_wunpckeluh"
928
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
929
        (zero_extend:V2SI
930
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
931
                          (parallel [(const_int 0) (const_int 1)]))))]
932
  "TARGET_REALLY_IWMMXT"
933
  "wunpckeluh%?\\t%0, %1"
934
  [(set_attr "predicable" "yes")])
935
 
936
(define_insn "iwmmxt_wunpckeluw"
937
  [(set (match_operand:DI                   0 "register_operand" "=y")
938
        (zero_extend:DI
939
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
940
                        (parallel [(const_int 0)]))))]
941
  "TARGET_REALLY_IWMMXT"
942
  "wunpckeluw%?\\t%0, %1"
943
  [(set_attr "predicable" "yes")])
944
 
945
(define_insn "iwmmxt_wunpckelsb"
946
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
947
        (sign_extend:V4HI
948
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
949
                          (parallel [(const_int 0) (const_int 1)
950
                                     (const_int 2) (const_int 3)]))))]
951
  "TARGET_REALLY_IWMMXT"
952
  "wunpckelsb%?\\t%0, %1"
953
  [(set_attr "predicable" "yes")])
954
 
955
(define_insn "iwmmxt_wunpckelsh"
956
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
957
        (sign_extend:V2SI
958
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
959
                          (parallel [(const_int 0) (const_int 1)]))))]
960
  "TARGET_REALLY_IWMMXT"
961
  "wunpckelsh%?\\t%0, %1"
962
  [(set_attr "predicable" "yes")])
963
 
964
(define_insn "iwmmxt_wunpckelsw"
965
  [(set (match_operand:DI                   0 "register_operand" "=y")
966
        (sign_extend:DI
967
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
968
                        (parallel [(const_int 0)]))))]
969
  "TARGET_REALLY_IWMMXT"
970
  "wunpckelsw%?\\t%0, %1"
971
  [(set_attr "predicable" "yes")])
972
 
973
;; Shifts
974
 
975
(define_insn "rorv4hi3"
976
  [(set (match_operand:V4HI                0 "register_operand" "=y")
977
        (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
978
                       (match_operand:SI   2 "register_operand" "z")))]
979
  "TARGET_REALLY_IWMMXT"
980
  "wrorhg%?\\t%0, %1, %2"
981
  [(set_attr "predicable" "yes")])
982
 
983
(define_insn "rorv2si3"
984
  [(set (match_operand:V2SI                0 "register_operand" "=y")
985
        (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
986
                       (match_operand:SI   2 "register_operand" "z")))]
987
  "TARGET_REALLY_IWMMXT"
988
  "wrorwg%?\\t%0, %1, %2"
989
  [(set_attr "predicable" "yes")])
990
 
991
(define_insn "rordi3"
992
  [(set (match_operand:DI              0 "register_operand" "=y")
993
        (rotatert:DI (match_operand:DI 1 "register_operand" "y")
994
                   (match_operand:SI   2 "register_operand" "z")))]
995
  "TARGET_REALLY_IWMMXT"
996
  "wrordg%?\\t%0, %1, %2"
997
  [(set_attr "predicable" "yes")])
998
 
999
(define_insn "ashr3_iwmmxt"
1000
  [(set (match_operand:VSHFT                 0 "register_operand" "=y")
1001
        (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
1002
                        (match_operand:SI    2 "register_operand" "z")))]
1003
  "TARGET_REALLY_IWMMXT"
1004
  "wsrag%?\\t%0, %1, %2"
1005
  [(set_attr "predicable" "yes")])
1006
 
1007
(define_insn "lshr3_iwmmxt"
1008
  [(set (match_operand:VSHFT                 0 "register_operand" "=y")
1009
        (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
1010
                        (match_operand:SI    2 "register_operand" "z")))]
1011
  "TARGET_REALLY_IWMMXT"
1012
  "wsrlg%?\\t%0, %1, %2"
1013
  [(set_attr "predicable" "yes")])
1014
 
1015
(define_insn "ashl3_iwmmxt"
1016
  [(set (match_operand:VSHFT               0 "register_operand" "=y")
1017
        (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
1018
                      (match_operand:SI    2 "register_operand" "z")))]
1019
  "TARGET_REALLY_IWMMXT"
1020
  "wsllg%?\\t%0, %1, %2"
1021
  [(set_attr "predicable" "yes")])
1022
 
1023
(define_insn "rorv4hi3_di"
1024
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1025
        (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1026
                       (match_operand:DI   2 "register_operand" "y")))]
1027
  "TARGET_REALLY_IWMMXT"
1028
  "wrorh%?\\t%0, %1, %2"
1029
  [(set_attr "predicable" "yes")])
1030
 
1031
(define_insn "rorv2si3_di"
1032
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1033
        (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1034
                       (match_operand:DI   2 "register_operand" "y")))]
1035
  "TARGET_REALLY_IWMMXT"
1036
  "wrorw%?\\t%0, %1, %2"
1037
  [(set_attr "predicable" "yes")])
1038
 
1039
(define_insn "rordi3_di"
1040
  [(set (match_operand:DI              0 "register_operand" "=y")
1041
        (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1042
                   (match_operand:DI   2 "register_operand" "y")))]
1043
  "TARGET_REALLY_IWMMXT"
1044
  "wrord%?\\t%0, %1, %2"
1045
  [(set_attr "predicable" "yes")])
1046
 
1047
(define_insn "ashrv4hi3_di"
1048
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1049
        (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1050
                       (match_operand:DI   2 "register_operand" "y")))]
1051
  "TARGET_REALLY_IWMMXT"
1052
  "wsrah%?\\t%0, %1, %2"
1053
  [(set_attr "predicable" "yes")])
1054
 
1055
(define_insn "ashrv2si3_di"
1056
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1057
        (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1058
                       (match_operand:DI   2 "register_operand" "y")))]
1059
  "TARGET_REALLY_IWMMXT"
1060
  "wsraw%?\\t%0, %1, %2"
1061
  [(set_attr "predicable" "yes")])
1062
 
1063
(define_insn "ashrdi3_di"
1064
  [(set (match_operand:DI              0 "register_operand" "=y")
1065
        (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1066
                   (match_operand:DI   2 "register_operand" "y")))]
1067
  "TARGET_REALLY_IWMMXT"
1068
  "wsrad%?\\t%0, %1, %2"
1069
  [(set_attr "predicable" "yes")])
1070
 
1071
(define_insn "lshrv4hi3_di"
1072
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1073
        (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1074
                       (match_operand:DI   2 "register_operand" "y")))]
1075
  "TARGET_REALLY_IWMMXT"
1076
  "wsrlh%?\\t%0, %1, %2"
1077
  [(set_attr "predicable" "yes")])
1078
 
1079
(define_insn "lshrv2si3_di"
1080
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1081
        (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1082
                       (match_operand:DI   2 "register_operand" "y")))]
1083
  "TARGET_REALLY_IWMMXT"
1084
  "wsrlw%?\\t%0, %1, %2"
1085
  [(set_attr "predicable" "yes")])
1086
 
1087
(define_insn "lshrdi3_di"
1088
  [(set (match_operand:DI              0 "register_operand" "=y")
1089
        (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1090
                     (match_operand:DI 2 "register_operand" "y")))]
1091
  "TARGET_REALLY_IWMMXT"
1092
  "wsrld%?\\t%0, %1, %2"
1093
  [(set_attr "predicable" "yes")])
1094
 
1095
(define_insn "ashlv4hi3_di"
1096
  [(set (match_operand:V4HI              0 "register_operand" "=y")
1097
        (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1098
                     (match_operand:DI   2 "register_operand" "y")))]
1099
  "TARGET_REALLY_IWMMXT"
1100
  "wsllh%?\\t%0, %1, %2"
1101
  [(set_attr "predicable" "yes")])
1102
 
1103
(define_insn "ashlv2si3_di"
1104
  [(set (match_operand:V2SI              0 "register_operand" "=y")
1105
        (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1106
                       (match_operand:DI 2 "register_operand" "y")))]
1107
  "TARGET_REALLY_IWMMXT"
1108
  "wsllw%?\\t%0, %1, %2"
1109
  [(set_attr "predicable" "yes")])
1110
 
1111
(define_insn "ashldi3_di"
1112
  [(set (match_operand:DI            0 "register_operand" "=y")
1113
        (ashift:DI (match_operand:DI 1 "register_operand" "y")
1114
                   (match_operand:DI 2 "register_operand" "y")))]
1115
  "TARGET_REALLY_IWMMXT"
1116
  "wslld%?\\t%0, %1, %2"
1117
  [(set_attr "predicable" "yes")])
1118
 
1119
(define_insn "iwmmxt_wmadds"
1120
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1121
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1122
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))]
1123
  "TARGET_REALLY_IWMMXT"
1124
  "wmadds%?\\t%0, %1, %2"
1125
  [(set_attr "predicable" "yes")])
1126
 
1127
(define_insn "iwmmxt_wmaddu"
1128
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1129
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1130
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))]
1131
  "TARGET_REALLY_IWMMXT"
1132
  "wmaddu%?\\t%0, %1, %2"
1133
  [(set_attr "predicable" "yes")])
1134
 
1135
(define_insn "iwmmxt_tmia"
1136
  [(set (match_operand:DI                    0 "register_operand" "=y")
1137
        (plus:DI (match_operand:DI           1 "register_operand" "0")
1138
                 (mult:DI (sign_extend:DI
1139
                           (match_operand:SI 2 "register_operand" "r"))
1140
                          (sign_extend:DI
1141
                           (match_operand:SI 3 "register_operand" "r")))))]
1142
  "TARGET_REALLY_IWMMXT"
1143
  "tmia%?\\t%0, %2, %3"
1144
  [(set_attr "predicable" "yes")])
1145
 
1146
(define_insn "iwmmxt_tmiaph"
1147
  [(set (match_operand:DI          0 "register_operand" "=y")
1148
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1149
                 (plus:DI
1150
                  (mult:DI (sign_extend:DI
1151
                            (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1152
                           (sign_extend:DI
1153
                            (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1154
                  (mult:DI (sign_extend:DI
1155
                            (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1156
                           (sign_extend:DI
1157
                            (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1158
  "TARGET_REALLY_IWMMXT"
1159
  "tmiaph%?\\t%0, %2, %3"
1160
  [(set_attr "predicable" "yes")])
1161
 
1162
(define_insn "iwmmxt_tmiabb"
1163
  [(set (match_operand:DI          0 "register_operand" "=y")
1164
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1165
                 (mult:DI (sign_extend:DI
1166
                           (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1167
                          (sign_extend:DI
1168
                           (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1169
  "TARGET_REALLY_IWMMXT"
1170
  "tmiabb%?\\t%0, %2, %3"
1171
  [(set_attr "predicable" "yes")])
1172
 
1173
(define_insn "iwmmxt_tmiatb"
1174
  [(set (match_operand:DI          0 "register_operand" "=y")
1175
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1176
                 (mult:DI (sign_extend:DI
1177
                           (truncate:HI (ashiftrt:SI
1178
                                         (match_operand:SI 2 "register_operand" "r")
1179
                                         (const_int 16))))
1180
                          (sign_extend:DI
1181
                           (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1182
  "TARGET_REALLY_IWMMXT"
1183
  "tmiatb%?\\t%0, %2, %3"
1184
  [(set_attr "predicable" "yes")])
1185
 
1186
(define_insn "iwmmxt_tmiabt"
1187
  [(set (match_operand:DI          0 "register_operand" "=y")
1188
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1189
                 (mult:DI (sign_extend:DI
1190
                           (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1191
                          (sign_extend:DI
1192
                           (truncate:HI (ashiftrt:SI
1193
                                         (match_operand:SI 3 "register_operand" "r")
1194
                                         (const_int 16)))))))]
1195
  "TARGET_REALLY_IWMMXT"
1196
  "tmiabt%?\\t%0, %2, %3"
1197
  [(set_attr "predicable" "yes")])
1198
 
1199
(define_insn "iwmmxt_tmiatt"
1200
  [(set (match_operand:DI          0 "register_operand" "=y")
1201
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1202
                 (mult:DI (sign_extend:DI
1203
                           (truncate:HI (ashiftrt:SI
1204
                                         (match_operand:SI 2 "register_operand" "r")
1205
                                         (const_int 16))))
1206
                          (sign_extend:DI
1207
                           (truncate:HI (ashiftrt:SI
1208
                                         (match_operand:SI 3 "register_operand" "r")
1209
                                         (const_int 16)))))))]
1210
  "TARGET_REALLY_IWMMXT"
1211
  "tmiatt%?\\t%0, %2, %3"
1212
  [(set_attr "predicable" "yes")])
1213
 
1214
(define_insn "iwmmxt_tbcstqi"
1215
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
1216
        (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
1217
  "TARGET_REALLY_IWMMXT"
1218
  "tbcstb%?\\t%0, %1"
1219
  [(set_attr "predicable" "yes")])
1220
 
1221
(define_insn "iwmmxt_tbcsthi"
1222
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
1223
        (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
1224
  "TARGET_REALLY_IWMMXT"
1225
  "tbcsth%?\\t%0, %1"
1226
  [(set_attr "predicable" "yes")])
1227
 
1228
(define_insn "iwmmxt_tbcstsi"
1229
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
1230
        (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
1231
  "TARGET_REALLY_IWMMXT"
1232
  "tbcstw%?\\t%0, %1"
1233
  [(set_attr "predicable" "yes")])
1234
 
1235
(define_insn "iwmmxt_tmovmskb"
1236
  [(set (match_operand:SI               0 "register_operand" "=r")
1237
        (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1238
  "TARGET_REALLY_IWMMXT"
1239
  "tmovmskb%?\\t%0, %1"
1240
  [(set_attr "predicable" "yes")])
1241
 
1242
(define_insn "iwmmxt_tmovmskh"
1243
  [(set (match_operand:SI               0 "register_operand" "=r")
1244
        (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1245
  "TARGET_REALLY_IWMMXT"
1246
  "tmovmskh%?\\t%0, %1"
1247
  [(set_attr "predicable" "yes")])
1248
 
1249
(define_insn "iwmmxt_tmovmskw"
1250
  [(set (match_operand:SI               0 "register_operand" "=r")
1251
        (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1252
  "TARGET_REALLY_IWMMXT"
1253
  "tmovmskw%?\\t%0, %1"
1254
  [(set_attr "predicable" "yes")])
1255
 
1256
(define_insn "iwmmxt_waccb"
1257
  [(set (match_operand:DI               0 "register_operand" "=y")
1258
        (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1259
  "TARGET_REALLY_IWMMXT"
1260
  "waccb%?\\t%0, %1"
1261
  [(set_attr "predicable" "yes")])
1262
 
1263
(define_insn "iwmmxt_wacch"
1264
  [(set (match_operand:DI               0 "register_operand" "=y")
1265
        (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1266
  "TARGET_REALLY_IWMMXT"
1267
  "wacch%?\\t%0, %1"
1268
  [(set_attr "predicable" "yes")])
1269
 
1270
(define_insn "iwmmxt_waccw"
1271
  [(set (match_operand:DI               0 "register_operand" "=y")
1272
        (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1273
  "TARGET_REALLY_IWMMXT"
1274
  "waccw%?\\t%0, %1"
1275
  [(set_attr "predicable" "yes")])
1276
 
1277
(define_insn "iwmmxt_walign"
1278
  [(set (match_operand:V8QI                           0 "register_operand" "=y,y")
1279
        (subreg:V8QI (ashiftrt:TI
1280
                      (subreg:TI (vec_concat:V16QI
1281
                                  (match_operand:V8QI 1 "register_operand" "y,y")
1282
                                  (match_operand:V8QI 2 "register_operand" "y,y")) 0)
1283
                      (mult:SI
1284
                       (match_operand:SI              3 "nonmemory_operand" "i,z")
1285
                       (const_int 8))) 0))]
1286
  "TARGET_REALLY_IWMMXT"
1287
  "@
1288
   waligni%?\\t%0, %1, %2, %3
1289
   walignr%U3%?\\t%0, %1, %2"
1290
  [(set_attr "predicable" "yes")])
1291
 
1292
(define_insn "iwmmxt_tmrc"
1293
  [(set (match_operand:SI                      0 "register_operand" "=r")
1294
        (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
1295
                            VUNSPEC_TMRC))]
1296
  "TARGET_REALLY_IWMMXT"
1297
  "tmrc%?\\t%0, %w1"
1298
  [(set_attr "predicable" "yes")])
1299
 
1300
(define_insn "iwmmxt_tmcr"
1301
  [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
1302
                        (match_operand:SI 1 "register_operand"  "r")]
1303
                       VUNSPEC_TMCR)]
1304
  "TARGET_REALLY_IWMMXT"
1305
  "tmcr%?\\t%w0, %1"
1306
  [(set_attr "predicable" "yes")])
1307
 
1308
(define_insn "iwmmxt_wsadb"
1309
  [(set (match_operand:V8QI               0 "register_operand" "=y")
1310
        (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1311
                      (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))]
1312
  "TARGET_REALLY_IWMMXT"
1313
  "wsadb%?\\t%0, %1, %2"
1314
  [(set_attr "predicable" "yes")])
1315
 
1316
(define_insn "iwmmxt_wsadh"
1317
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1318
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1319
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))]
1320
  "TARGET_REALLY_IWMMXT"
1321
  "wsadh%?\\t%0, %1, %2"
1322
  [(set_attr "predicable" "yes")])
1323
 
1324
(define_insn "iwmmxt_wsadbz"
1325
  [(set (match_operand:V8QI               0 "register_operand" "=y")
1326
        (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1327
                      (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1328
  "TARGET_REALLY_IWMMXT"
1329
  "wsadbz%?\\t%0, %1, %2"
1330
  [(set_attr "predicable" "yes")])
1331
 
1332
(define_insn "iwmmxt_wsadhz"
1333
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1334
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1335
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1336
  "TARGET_REALLY_IWMMXT"
1337
  "wsadhz%?\\t%0, %1, %2"
1338
  [(set_attr "predicable" "yes")])
1339
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.