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(* Common code for ARM NEON header file, documentation and test case

   generators.

   Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.

   Contributed by CodeSourcery.

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it under

   the terms of the GNU General Public License as published by the Free

   Software Foundation; either version 3, or (at your option) any later

   version.

   GCC is distributed in the hope that it will be useful, but WITHOUT ANY

   WARRANTY; without even the implied warranty of MERCHANTABILITY or

   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

   for more details.

   You should have received a copy of the GNU General Public License

   along with GCC; see the file COPYING3.  If not see

   .  *)

(* Shorthand types for vector elements.  *)

type elts = S8 | S16 | S32 | S64 | F32 | U8 | U16 | U32 | U64 | P8 | P16

          | I8 | I16 | I32 | I64 | B8 | B16 | B32 | B64 | Conv of elts * elts

          | Cast of elts * elts | NoElts

type eltclass = Signed | Unsigned | Float | Poly | Int | Bits

              | ConvClass of eltclass * eltclass | NoType

(* These vector types correspond directly to C types.  *)

type vectype = T_int8x8    | T_int8x16

             | T_int16x4   | T_int16x8

             | T_int32x2   | T_int32x4

             | T_int64x1   | T_int64x2

             | T_uint8x8   | T_uint8x16

             | T_uint16x4  | T_uint16x8

             | T_uint32x2  | T_uint32x4

             | T_uint64x1  | T_uint64x2

             | T_float32x2 | T_float32x4

             | T_poly8x8   | T_poly8x16

             | T_poly16x4  | T_poly16x8

             | T_immediate of int * int

             | T_int8      | T_int16

             | T_int32     | T_int64

             | T_uint8     | T_uint16

             | T_uint32    | T_uint64

             | T_poly8     | T_poly16

             | T_float32   | T_arrayof of int * vectype

             | T_ptrto of vectype | T_const of vectype

             | T_void      | T_intQI

             | T_intHI     | T_intSI

             | T_intDI     | T_floatSF

(* The meanings of the following are:

     TImode : "Tetra", two registers (four words).

     EImode : "hExa", three registers (six words).

     OImode : "Octa", four registers (eight words).

     CImode : "dodeCa", six registers (twelve words).

     XImode : "heXadeca", eight registers (sixteen words).

*)

type inttype = B_TImode | B_EImode | B_OImode | B_CImode | B_XImode

type shape_elt = Dreg | Qreg | Corereg | Immed | VecArray of int * shape_elt

               | PtrTo of shape_elt | CstPtrTo of shape_elt

               (* These next ones are used only in the test generator.  *)

               | Element_of_dreg        (* Used for "lane" variants.  *)

               | Element_of_qreg        (* Likewise.  *)

               | All_elements_of_dreg   (* Used for "dup" variants.  *)

               | Alternatives of shape_elt list (* Used for multiple valid operands *)

type shape_form = All of int * shape_elt

                | Long

                | Long_noreg of shape_elt

                | Wide

                | Wide_noreg of shape_elt

                | Narrow

                | Long_imm

                | Narrow_imm

                | Binary_imm of shape_elt

                | Use_operands of shape_elt array

                | By_scalar of shape_elt

                | Unary_scalar of shape_elt

                | Wide_lane

                | Wide_scalar

                | Pair_result of shape_elt

type arity = Arity0 of vectype

           | Arity1 of vectype * vectype

           | Arity2 of vectype * vectype * vectype

           | Arity3 of vectype * vectype * vectype * vectype

           | Arity4 of vectype * vectype * vectype * vectype * vectype

type vecmode = V8QI | V4HI | V2SI | V2SF | DI

             | V16QI | V8HI | V4SI | V4SF | V2DI

             | QI | HI | SI | SF

type opcode =

  (* Binary ops.  *)

    Vadd

  | Vmul

  | Vmla

  | Vmls

  | Vsub

  | Vceq

  | Vcge

  | Vcgt

  | Vcle

  | Vclt

  | Vcage

  | Vcagt

  | Vcale

  | Vcalt

  | Vtst

  | Vabd

  | Vaba

  | Vmax

  | Vmin

  | Vpadd

  | Vpada

  | Vpmax

  | Vpmin

  | Vrecps

  | Vrsqrts

  | Vshl

  | Vshr_n

  | Vshl_n

  | Vsra_n

  | Vsri

  | Vsli

  (* Logic binops.  *)

  | Vand

  | Vorr

  | Veor

  | Vbic

  | Vorn

  | Vbsl

  (* Ops with scalar.  *)

  | Vmul_lane

  | Vmla_lane

  | Vmls_lane

  | Vmul_n

  | Vmla_n

  | Vmls_n

  | Vmull_n

  | Vmull_lane

  | Vqdmull_n

  | Vqdmull_lane

  | Vqdmulh_n

  | Vqdmulh_lane

  (* Unary ops.  *)

  | Vabs

  | Vneg

  | Vcls

  | Vclz

  | Vcnt

  | Vrecpe

  | Vrsqrte

  | Vmvn

  (* Vector extract.  *)

  | Vext

  (* Reverse elements.  *)

  | Vrev64

  | Vrev32

  | Vrev16

  (* Transposition ops.  *)

  | Vtrn

  | Vzip

  | Vuzp

  (* Loads and stores (VLD1/VST1/VLD2...), elements and structures.  *)

  | Vldx of int

  | Vstx of int

  | Vldx_lane of int

  | Vldx_dup of int

  | Vstx_lane of int

  (* Set/extract lanes from a vector.  *)

  | Vget_lane

  | Vset_lane

  (* Initialize vector from bit pattern.  *)

  | Vcreate

  (* Set all lanes to same value.  *)

  | Vdup_n

  | Vmov_n  (* Is this the same?  *)

  (* Duplicate scalar to all lanes of vector.  *)

  | Vdup_lane

  (* Combine vectors.  *)

  | Vcombine

  (* Get quadword high/low parts.  *)

  | Vget_high

  | Vget_low

  (* Convert vectors.  *)

  | Vcvt

  | Vcvt_n

  (* Narrow/lengthen vectors.  *)

  | Vmovn

  | Vmovl

  (* Table lookup.  *)

  | Vtbl of int

  | Vtbx of int

  (* Reinterpret casts.  *)

  | Vreinterp

(* Features used for documentation, to distinguish between some instruction

   variants, and to signal special requirements (e.g. swapping arguments).  *)

type features =

    Halving

  | Rounding

  | Saturating

  | Dst_unsign

  | High_half

  | Doubling

  | Flipped of string  (* Builtin name to use with flipped arguments.  *)

  | InfoWord  (* Pass an extra word for signage/rounding etc. (always passed

                 for All _, Long, Wide, Narrow shape_forms.  *)

  | ReturnPtr  (* Pass explicit pointer to return value as first argument.  *)

    (* A specification as to the shape of instruction expected upon

       disassembly, used if it differs from the shape used to build the

       intrinsic prototype.  Multiple entries in the constructor's argument

       indicate that the intrinsic expands to more than one assembly

       instruction, each with a corresponding shape specified here.  *)

  | Disassembles_as of shape_form list

  | Builtin_name of string  (* Override the name of the builtin.  *)

    (* Override the name of the instruction.  If more than one name

       is specified, it means that the instruction can have any of those

       names.  *)

  | Instruction_name of string list

    (* Mark that the intrinsic yields no instructions, or expands to yield

       behavior that the test generator cannot test.  *)

  | No_op

    (* Mark that the intrinsic has constant arguments that cannot be set

       to the defaults (zero for pointers and one otherwise) in the test

       cases.  The function supplied must return the integer to be written

       into the testcase for the argument number (0-based) supplied to it.  *)

  | Const_valuator of (int -> int)

  | Fixed_return_reg

exception MixedMode of elts * elts

let rec elt_width = function

    S8 | U8 | P8 | I8 | B8 -> 8

  | S16 | U16 | P16 | I16 | B16 -> 16

  | S32 | F32 | U32 | I32 | B32 -> 32

  | S64 | U64 | I64 | B64 -> 64

  | Conv (a, b) ->

      let wa = elt_width a and wb = elt_width b in

      if wa = wb then wa else failwith "element width?"

  | Cast (a, b) -> raise (MixedMode (a, b))

  | NoElts -> failwith "No elts"

let rec elt_class = function

    S8 | S16 | S32 | S64 -> Signed

  | U8 | U16 | U32 | U64 -> Unsigned

  | P8 | P16 -> Poly

  | F32 -> Float

  | I8 | I16 | I32 | I64 -> Int

  | B8 | B16 | B32 | B64 -> Bits

  | Conv (a, b) | Cast (a, b) -> ConvClass (elt_class a, elt_class b)

  | NoElts -> NoType

let elt_of_class_width c w =

  match c, w with

    Signed, 8 -> S8

  | Signed, 16 -> S16

  | Signed, 32 -> S32

  | Signed, 64 -> S64

  | Float, 32 -> F32

  | Unsigned, 8 -> U8

  | Unsigned, 16 -> U16

  | Unsigned, 32 -> U32

  | Unsigned, 64 -> U64

  | Poly, 8 -> P8

  | Poly, 16 -> P16

  | Int, 8 -> I8

  | Int, 16 -> I16

  | Int, 32 -> I32

  | Int, 64 -> I64

  | Bits, 8 -> B8

  | Bits, 16 -> B16

  | Bits, 32 -> B32

  | Bits, 64 -> B64

  | _ -> failwith "Bad element type"

(* Return unsigned integer element the same width as argument.  *)

let unsigned_of_elt elt =

  elt_of_class_width Unsigned (elt_width elt)

let signed_of_elt elt =

  elt_of_class_width Signed (elt_width elt)

(* Return untyped bits element the same width as argument.  *)

let bits_of_elt elt =

  elt_of_class_width Bits (elt_width elt)

let non_signed_variant = function

    S8 -> I8

  | S16 -> I16

  | S32 -> I32

  | S64 -> I64

  | U8 -> I8

  | U16 -> I16

  | U32 -> I32

  | U64 -> I64

  | x -> x

let poly_unsigned_variant v =

  let elclass = match elt_class v with

    Poly -> Unsigned

  | x -> x in

  elt_of_class_width elclass (elt_width v)

let widen_elt elt =

  let w = elt_width elt

  and c = elt_class elt in

  elt_of_class_width c (w * 2)

let narrow_elt elt =

  let w = elt_width elt

  and c = elt_class elt in

  elt_of_class_width c (w / 2)

(* If we're trying to find a mode from a "Use_operands" instruction, use the

   last vector operand as the dominant mode used to invoke the correct builtin.

   We must stick to this rule in neon.md.  *)

let find_key_operand operands =

  let rec scan opno =

    match operands.(opno) with

      Qreg -> Qreg

    | Dreg -> Dreg

    | VecArray (_, Qreg) -> Qreg

    | VecArray (_, Dreg) -> Dreg

    | _ -> scan (opno-1)

  in

    scan ((Array.length operands) - 1)

let rec mode_of_elt elt shape =

  let flt = match elt_class elt with

    Float | ConvClass(_, Float) -> true | _ -> false in

  let idx =

    match elt_width elt with

      8 -> 0 | 16 -> 1 | 32 -> 2 | 64 -> 3

    | _ -> failwith "Bad element width"

  in match shape with

    All (_, Dreg) | By_scalar Dreg | Pair_result Dreg | Unary_scalar Dreg

  | Binary_imm Dreg | Long_noreg Dreg | Wide_noreg Dreg ->

      [| V8QI; V4HI; if flt then V2SF else V2SI; DI |].(idx)

  | All (_, Qreg) | By_scalar Qreg | Pair_result Qreg | Unary_scalar Qreg

  | Binary_imm Qreg | Long_noreg Qreg | Wide_noreg Qreg ->

      [| V16QI; V8HI; if flt then V4SF else V4SI; V2DI |].(idx)

  | All (_, (Corereg | PtrTo _ | CstPtrTo _)) ->

      [| QI; HI; if flt then SF else SI; DI |].(idx)

  | Long | Wide | Wide_lane | Wide_scalar

  | Long_imm ->

      [| V8QI; V4HI; V2SI; DI |].(idx)

  | Narrow | Narrow_imm -> [| V16QI; V8HI; V4SI; V2DI |].(idx)

  | Use_operands ops -> mode_of_elt elt (All (0, (find_key_operand ops)))

  | _ -> failwith "invalid shape"

(* Modify an element type dependent on the shape of the instruction and the

   operand number.  *)

let shapemap shape no =

  let ident = fun x -> x in

  match shape with

    All _ | Use_operands _ | By_scalar _ | Pair_result _ | Unary_scalar _

  | Binary_imm _ -> ident

  | Long | Long_noreg _ | Wide_scalar | Long_imm ->

      [| widen_elt; ident; ident |].(no)

  | Wide | Wide_noreg _ -> [| widen_elt; widen_elt; ident |].(no)

  | Wide_lane -> [| widen_elt; ident; ident; ident |].(no)

  | Narrow | Narrow_imm -> [| narrow_elt; ident; ident |].(no)

(* Register type (D/Q) of an operand, based on shape and operand number.  *)

let regmap shape no =

  match shape with

    All (_, reg) | Long_noreg reg | Wide_noreg reg -> reg

  | Long -> [| Qreg; Dreg; Dreg |].(no)

  | Wide -> [| Qreg; Qreg; Dreg |].(no)

  | Narrow -> [| Dreg; Qreg; Qreg |].(no)

  | Wide_lane -> [| Qreg; Dreg; Dreg; Immed |].(no)

  | Wide_scalar -> [| Qreg; Dreg; Corereg |].(no)

  | By_scalar reg -> [| reg; reg; Dreg; Immed |].(no)

  | Unary_scalar reg -> [| reg; Dreg; Immed |].(no)

  | Pair_result reg -> [| VecArray (2, reg); reg; reg |].(no)

  | Binary_imm reg -> [| reg; reg; Immed |].(no)

  | Long_imm -> [| Qreg; Dreg; Immed |].(no)

  | Narrow_imm -> [| Dreg; Qreg; Immed |].(no)

  | Use_operands these -> these.(no)

let type_for_elt shape elt no =

  let elt = (shapemap shape no) elt in

  let reg = regmap shape no in

  let rec type_for_reg_elt reg elt =

    match reg with

      Dreg ->

        begin match elt with

          S8 -> T_int8x8

        | S16 -> T_int16x4

        | S32 -> T_int32x2

        | S64 -> T_int64x1

        | U8 -> T_uint8x8

        | U16 -> T_uint16x4

        | U32 -> T_uint32x2

        | U64 -> T_uint64x1

        | F32 -> T_float32x2

        | P8 -> T_poly8x8

        | P16 -> T_poly16x4

        | _ -> failwith "Bad elt type"

        end

    | Qreg ->

        begin match elt with

          S8 -> T_int8x16

        | S16 -> T_int16x8

        | S32 -> T_int32x4

        | S64 -> T_int64x2

        | U8 -> T_uint8x16

        | U16 -> T_uint16x8

        | U32 -> T_uint32x4

        | U64 -> T_uint64x2

        | F32 -> T_float32x4

        | P8 -> T_poly8x16

        | P16 -> T_poly16x8

        | _ -> failwith "Bad elt type"

        end

    | Corereg ->

        begin match elt with

          S8 -> T_int8

        | S16 -> T_int16

        | S32 -> T_int32

        | S64 -> T_int64

        | U8 -> T_uint8

        | U16 -> T_uint16

        | U32 -> T_uint32

        | U64 -> T_uint64

        | P8 -> T_poly8

        | P16 -> T_poly16

        | F32 -> T_float32

        | _ -> failwith "Bad elt type"

        end

    | Immed ->

        T_immediate (0, 0)

    | VecArray (num, sub) ->

        T_arrayof (num, type_for_reg_elt sub elt)

    | PtrTo x ->

        T_ptrto (type_for_reg_elt x elt)

    | CstPtrTo x ->

        T_ptrto (T_const (type_for_reg_elt x elt))

    (* Anything else is solely for the use of the test generator.  *)

    | _ -> assert false

  in

    type_for_reg_elt reg elt

(* Return size of a vector type, in bits.  *)

let vectype_size = function

    T_int8x8 | T_int16x4 | T_int32x2 | T_int64x1

  | T_uint8x8 | T_uint16x4 | T_uint32x2 | T_uint64x1

  | T_float32x2 | T_poly8x8 | T_poly16x4 -> 64

  | T_int8x16 | T_int16x8 | T_int32x4 | T_int64x2

  | T_uint8x16 | T_uint16x8  | T_uint32x4  | T_uint64x2

  | T_float32x4 | T_poly8x16 | T_poly16x8 -> 128

  | _ -> raise Not_found

let inttype_for_array num elttype =

  let eltsize = vectype_size elttype in

  let numwords = (num * eltsize) / 32 in

  match numwords with

    4 -> B_TImode

  | 6 -> B_EImode

  | 8 -> B_OImode

  | 12 -> B_CImode

  | 16 -> B_XImode

  | _ -> failwith ("no int type for size " ^ string_of_int numwords)

(* These functions return pairs of (internal, external) types, where "internal"

   types are those seen by GCC, and "external" are those seen by the assembler.

   These types aren't necessarily the same, since the intrinsics can munge more

   than one C type into each assembler opcode.  *)

let make_sign_invariant func shape elt =

  let arity, elt' = func shape elt in

  arity, non_signed_variant elt'

(* Don't restrict any types.  *)

let elts_same make_arity shape elt =

  let vtype = type_for_elt shape elt in

  make_arity vtype, elt

(* As sign_invar_*, but when sign matters.  *)

let elts_same_io_lane =

  elts_same (fun vtype -> Arity4 (vtype 0, vtype 0, vtype 1, vtype 2, vtype 3))

let elts_same_io =

  elts_same (fun vtype -> Arity3 (vtype 0, vtype 0, vtype 1, vtype 2))

let elts_same_2_lane =

  elts_same (fun vtype -> Arity3 (vtype 0, vtype 1, vtype 2, vtype 3))

let elts_same_3 = elts_same_2_lane

let elts_same_2 =

  elts_same (fun vtype -> Arity2 (vtype 0, vtype 1, vtype 2))

let elts_same_1 =

  elts_same (fun vtype -> Arity1 (vtype 0, vtype 1))

(* Use for signed/unsigned invariant operations (i.e. where the operation

   doesn't depend on the sign of the data.  *)

let sign_invar_io_lane = make_sign_invariant elts_same_io_lane

let sign_invar_io = make_sign_invariant elts_same_io

let sign_invar_2_lane = make_sign_invariant elts_same_2_lane

let sign_invar_2 = make_sign_invariant elts_same_2

let sign_invar_1 = make_sign_invariant elts_same_1

(* Sign-sensitive comparison.  *)

let cmp_sign_matters shape elt =

  let vtype = type_for_elt shape elt

  and rtype = type_for_elt shape (unsigned_of_elt elt) 0 in

  Arity2 (rtype, vtype 1, vtype 2), elt

(* Signed/unsigned invariant comparison.  *)

let cmp_sign_invar shape elt =

  let shape', elt' = cmp_sign_matters shape elt in

  let elt'' =

    match non_signed_variant elt' with

      P8 -> I8

    | x -> x

  in

    shape', elt''

(* Comparison (VTST) where only the element width matters.  *)

let cmp_bits shape elt =

  let vtype = type_for_elt shape elt

  and rtype = type_for_elt shape (unsigned_of_elt elt) 0

  and bits_only = bits_of_elt elt in

  Arity2 (rtype, vtype 1, vtype 2), bits_only

let reg_shift shape elt =

  let vtype = type_for_elt shape elt

  and op2type = type_for_elt shape (signed_of_elt elt) 2 in

  Arity2 (vtype 0, vtype 1, op2type), elt

(* Genericised constant-shift type-generating function.  *)

let const_shift mkimm ?arity ?result shape elt =

  let op2type = (shapemap shape 2) elt in

  let op2width = elt_width op2type in

  let op2 = mkimm op2width

  and op1 = type_for_elt shape elt 1

  and r_elt =

    match result with

      None -> elt

    | Some restriction -> restriction elt in

  let rtype = type_for_elt shape r_elt 0 in

  match arity with

    None -> Arity2 (rtype, op1, op2), elt

  | Some mkarity -> mkarity rtype op1 op2, elt

(* Use for immediate right-shifts.  *)

let shift_right shape elt =

  const_shift (fun imm -> T_immediate (1, imm)) shape elt

let shift_right_acc shape elt =

  const_shift (fun imm -> T_immediate (1, imm))

    ~arity:(fun dst op1 op2 -> Arity3 (dst, dst, op1, op2)) shape elt

(* Use for immediate right-shifts when the operation doesn't care about

   signedness.  *)

let shift_right_sign_invar =

  make_sign_invariant shift_right

(* Immediate right-shift; result is unsigned even when operand is signed.  *)

let shift_right_to_uns shape elt =

  const_shift (fun imm -> T_immediate (1, imm)) ~result:unsigned_of_elt

    shape elt

(* Immediate left-shift.  *)

let shift_left shape elt =

  const_shift (fun imm -> T_immediate (0, imm - 1)) shape elt

(* Immediate left-shift, unsigned result.  *)

let shift_left_to_uns shape elt =

  const_shift (fun imm -> T_immediate (0, imm - 1)) ~result:unsigned_of_elt

    shape elt

(* Immediate left-shift, don't care about signs.  *)

let shift_left_sign_invar =

  make_sign_invariant shift_left

(* Shift left/right and insert: only element size matters.  *)

let shift_insert shape elt =

  let arity, elt =

    const_shift (fun imm -> T_immediate (1, imm))

    ~arity:(fun dst op1 op2 -> Arity3 (dst, dst, op1, op2)) shape elt in

  arity, bits_of_elt elt

(* Get/set lane.  *)

let get_lane shape elt =

  let vtype = type_for_elt shape elt in

  Arity2 (vtype 0, vtype 1, vtype 2),

    (match elt with P8 -> U8 | P16 -> U16 | S32 | U32 | F32 -> B32 | x -> x)

let set_lane shape elt =

  let vtype = type_for_elt shape elt in

  Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), bits_of_elt elt

let set_lane_notype shape elt =

  let vtype = type_for_elt shape elt in

  Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), NoElts

let create_vector shape elt =

  let vtype = type_for_elt shape U64 1

  and rtype = type_for_elt shape elt 0 in

  Arity1 (rtype, vtype), elt

let conv make_arity shape elt =

  let edest, esrc = match elt with

    Conv (edest, esrc) | Cast (edest, esrc) -> edest, esrc

  | _ -> failwith "Non-conversion element in conversion" in

  let vtype = type_for_elt shape esrc

  and rtype = type_for_elt shape edest 0 in

  make_arity rtype vtype, elt

let conv_1 = conv (fun rtype vtype -> Arity1 (rtype, vtype 1))

let conv_2 = conv (fun rtype vtype -> Arity2 (rtype, vtype 1, vtype 2))

(* Operation has an unsigned result even if operands are signed.  *)

let dst_unsign make_arity shape elt =

  let vtype = type_for_elt shape elt

  and rtype = type_for_elt shape (unsigned_of_elt elt) 0 in

  make_arity rtype vtype, elt

let dst_unsign_1 = dst_unsign (fun rtype vtype -> Arity1 (rtype, vtype 1))

let make_bits_only func shape elt =

  let arity, elt' = func shape elt in

  arity, bits_of_elt elt'

(* Extend operation.  *)

let extend shape elt =

  let vtype = type_for_elt shape elt in

  Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), bits_of_elt elt

(* Table look-up operations. Operand 2 is signed/unsigned for signed/unsigned

   integer ops respectively, or unsigned for polynomial ops.  *)

let table mkarity shape elt =

  let vtype = type_for_elt shape elt in

  let op2 = type_for_elt shape (poly_unsigned_variant elt) 2 in

  mkarity vtype op2, bits_of_elt elt

let table_2 = table (fun vtype op2 -> Arity2 (vtype 0, vtype 1, op2))

let table_io = table (fun vtype op2 -> Arity3 (vtype 0, vtype 0, vtype 1, op2))

(* Operations where only bits matter.  *)

let bits_1 = make_bits_only elts_same_1

let bits_2 = make_bits_only elts_same_2

let bits_3 = make_bits_only elts_same_3

(* Store insns.  *)

let store_1 shape elt =

  let vtype = type_for_elt shape elt in

  Arity2 (T_void, vtype 0, vtype 1), bits_of_elt elt

let store_3 shape elt =

  let vtype = type_for_elt shape elt in

  Arity3 (T_void, vtype 0, vtype 1, vtype 2), bits_of_elt elt

let make_notype func shape elt =

  let arity, _ = func shape elt in

  arity, NoElts

let notype_1 = make_notype elts_same_1

let notype_2 = make_notype elts_same_2

let notype_3 = make_notype elts_same_3

(* Bit-select operations (first operand is unsigned int).  *)

let bit_select shape elt =

  let vtype = type_for_elt shape elt

  and itype = type_for_elt shape (unsigned_of_elt elt) in

  Arity3 (vtype 0, itype 1, vtype 2, vtype 3), NoElts

(* Common lists of supported element types.  *)

let su_8_32 = [S8; S16; S32; U8; U16; U32]

let su_8_64 = S64 :: U64 :: su_8_32

let su_16_64 = [S16; S32; S64; U16; U32; U64]

let pf_su_8_32 = P8 :: P16 :: F32 :: su_8_32

let pf_su_8_64 = P8 :: P16 :: F32 :: su_8_64

let ops =

  [

    (* Addition.  *)

    Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_64;

    Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64;

    Vadd, [], Long, "vaddl", elts_same_2, su_8_32;

    Vadd, [], Wide, "vaddw", elts_same_2, su_8_32;

    Vadd, [Halving], All (3, Dreg), "vhadd", elts_same_2, su_8_32;

    Vadd, [Halving], All (3, Qreg), "vhaddQ", elts_same_2, su_8_32;

    Vadd, [Instruction_name ["vrhadd"]; Rounding; Halving],

      All (3, Dreg), "vRhadd", elts_same_2, su_8_32;

    Vadd, [Instruction_name ["vrhadd"]; Rounding; Halving],

      All (3, Qreg), "vRhaddQ", elts_same_2, su_8_32;

    Vadd, [Saturating], All (3, Dreg), "vqadd", elts_same_2, su_8_64;

    Vadd, [Saturating], All (3, Qreg), "vqaddQ", elts_same_2, su_8_64;

    Vadd, [High_half], Narrow, "vaddhn", sign_invar_2, su_16_64;

    Vadd, [Instruction_name ["vraddhn"]; Rounding; High_half],

      Narrow, "vRaddhn", sign_invar_2, su_16_64;

    (* Multiplication.  *)

    Vmul, [], All (3, Dreg), "vmul", sign_invar_2, P8 :: F32 :: su_8_32;

    Vmul, [], All (3, Qreg), "vmulQ", sign_invar_2, P8 :: F32 :: su_8_32;

    Vmul, [Saturating; Doubling; High_half], All (3, Dreg), "vqdmulh",

      elts_same_2, [S16; S32];

    Vmul, [Saturating; Doubling; High_half], All (3, Qreg), "vqdmulhQ",

      elts_same_2, [S16; S32];

    Vmul,

      [Saturating; Rounding; Doubling; High_half;

       Instruction_name ["vqrdmulh"]],

      All (3, Dreg), "vqRdmulh",

      elts_same_2, [S16; S32];

    Vmul,

      [Saturating; Rounding; Doubling; High_half;

       Instruction_name ["vqrdmulh"]],

      All (3, Qreg), "vqRdmulhQ",

      elts_same_2, [S16; S32];

    Vmul, [], Long, "vmull", elts_same_2, P8 :: su_8_32;

    Vmul, [Saturating; Doubling], Long, "vqdmull", elts_same_2, [S16; S32];

    (* Multiply-accumulate. *)

    Vmla, [], All (3, Dreg), "vmla", sign_invar_io, F32 :: su_8_32;

    Vmla, [], All (3, Qreg), "vmlaQ", sign_invar_io, F32 :: su_8_32;

    Vmla, [], Long, "vmlal", elts_same_io, su_8_32;

    Vmla, [Saturating; Doubling], Long, "vqdmlal", elts_same_io, [S16; S32];

    (* Multiply-subtract.  *)

    Vmls, [], All (3, Dreg), "vmls", sign_invar_io, F32 :: su_8_32;

    Vmls, [], All (3, Qreg), "vmlsQ", sign_invar_io, F32 :: su_8_32;

    Vmls, [], Long, "vmlsl", elts_same_io, su_8_32;

    Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32];

    (* Subtraction.  *)

    Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_64;

    Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64;

    Vsub, [], Long, "vsubl", elts_same_2, su_8_32;

    Vsub, [], Wide, "vsubw", elts_same_2, su_8_32;

    Vsub, [Halving], All (3, Dreg), "vhsub", elts_same_2, su_8_32;

    Vsub, [Halving], All (3, Qreg), "vhsubQ", elts_same_2, su_8_32;

    Vsub, [Saturating], All (3, Dreg), "vqsub", elts_same_2, su_8_64;

    Vsub, [Saturating], All (3, Qreg), "vqsubQ", elts_same_2, su_8_64;

    Vsub, [High_half], Narrow, "vsubhn", sign_invar_2, su_16_64;

    Vsub, [Instruction_name ["vrsubhn"]; Rounding; High_half],

      Narrow, "vRsubhn", sign_invar_2, su_16_64;

    (* Comparison, equal.  *)

    Vceq, [], All (3, Dreg), "vceq", cmp_sign_invar, P8 :: F32 :: su_8_32;

    Vceq, [], All (3, Qreg), "vceqQ", cmp_sign_invar, P8 :: F32 :: su_8_32;

    (* Comparison, greater-than or equal.  *)

    Vcge, [], All (3, Dreg), "vcge", cmp_sign_matters, F32 :: su_8_32;

    Vcge, [], All (3, Qreg), "vcgeQ", cmp_sign_matters, F32 :: su_8_32;

    (* Comparison, less-than or equal.  *)

    Vcle, [Flipped "vcge"], All (3, Dreg), "vcle", cmp_sign_matters,

      F32 :: su_8_32;

    Vcle, [Instruction_name ["vcge"]; Flipped "vcgeQ"],

      All (3, Qreg), "vcleQ", cmp_sign_matters,

      F32 :: su_8_32;

    (* Comparison, greater-than.  *)

    Vcgt, [], All (3, Dreg), "vcgt", cmp_sign_matters, F32 :: su_8_32;

    Vcgt, [], All (3, Qreg), "vcgtQ", cmp_sign_matters, F32 :: su_8_32;

    (* Comparison, less-than.  *)

    Vclt, [Flipped "vcgt"], All (3, Dreg), "vclt", cmp_sign_matters,

      F32 :: su_8_32;

    Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtQ"],

      All (3, Qreg), "vcltQ", cmp_sign_matters,

      F32 :: su_8_32;

    (* Compare absolute greater-than or equal.  *)

    Vcage, [Instruction_name ["vacge"]],

      All (3, Dreg), "vcage", cmp_sign_matters, [F32];

    Vcage, [Instruction_name ["vacge"]],

      All (3, Qreg), "vcageQ", cmp_sign_matters, [F32];

    (* Compare absolute less-than or equal.  *)

    Vcale, [Instruction_name ["vacge"]; Flipped "vcage"],

      All (3, Dreg), "vcale", cmp_sign_matters, [F32];

    Vcale, [Instruction_name ["vacge"]; Flipped "vcageQ"],

      All (3, Qreg), "vcaleQ", cmp_sign_matters, [F32];

    (* Compare absolute greater-than or equal.  *)

    Vcagt, [Instruction_name ["vacgt"]],

      All (3, Dreg), "vcagt", cmp_sign_matters, [F32];

    Vcagt, [Instruction_name ["vacgt"]],

      All (3, Qreg), "vcagtQ", cmp_sign_matters, [F32];

    (* Compare absolute less-than or equal.  *)

    Vcalt, [Instruction_name ["vacgt"]; Flipped "vcagt"],

      All (3, Dreg), "vcalt", cmp_sign_matters, [F32];

    Vcalt, [Instruction_name ["vacgt"]; Flipped "vcagtQ"],

      All (3, Qreg), "vcaltQ", cmp_sign_matters, [F32];

    (* Test bits.  *)

    Vtst, [], All (3, Dreg), "vtst", cmp_bits, P8 :: su_8_32;

    Vtst, [], All (3, Qreg), "vtstQ", cmp_bits, P8 :: su_8_32;

    (* Absolute difference.  *)

    Vabd, [], All (3, Dreg), "vabd", elts_same_2, F32 :: su_8_32;

    Vabd, [], All (3, Qreg), "vabdQ", elts_same_2, F32 :: su_8_32;

    Vabd, [], Long, "vabdl", elts_same_2, su_8_32;

    (* Absolute difference and accumulate.  *)

    Vaba, [], All (3, Dreg), "vaba", elts_same_io, su_8_32;

    Vaba, [], All (3, Qreg), "vabaQ", elts_same_io, su_8_32;

    Vaba, [], Long, "vabal", elts_same_io, su_8_32;

    (* Max.  *)

    Vmax, [], All (3, Dreg), "vmax", elts_same_2, F32 :: su_8_32;

    Vmax, [], All (3, Qreg), "vmaxQ", elts_same_2, F32 :: su_8_32;

    (* Min.  *)

    Vmin, [], All (3, Dreg), "vmin", elts_same_2, F32 :: su_8_32;

    Vmin, [], All (3, Qreg), "vminQ", elts_same_2, F32 :: su_8_32;

    (* Pairwise add.  *)

    Vpadd, [], All (3, Dreg), "vpadd", sign_invar_2, F32 :: su_8_32;

    Vpadd, [], Long_noreg Dreg, "vpaddl", elts_same_1, su_8_32;

    Vpadd, [], Long_noreg Qreg, "vpaddlQ", elts_same_1, su_8_32;

    (* Pairwise add, widen and accumulate.  *)

    Vpada, [], Wide_noreg Dreg, "vpadal", elts_same_2, su_8_32;

    Vpada, [], Wide_noreg Qreg, "vpadalQ", elts_same_2, su_8_32;

    (* Folding maximum, minimum.  *)

    Vpmax, [], All (3, Dreg), "vpmax", elts_same_2, F32 :: su_8_32;

    Vpmin, [], All (3, Dreg), "vpmin", elts_same_2, F32 :: su_8_32;

    (* Reciprocal step.  *)

    Vrecps, [], All (3, Dreg), "vrecps", elts_same_2, [F32];

    Vrecps, [], All (3, Qreg), "vrecpsQ", elts_same_2, [F32];

    Vrsqrts, [], All (3, Dreg), "vrsqrts", elts_same_2, [F32];

    Vrsqrts, [], All (3, Qreg), "vrsqrtsQ", elts_same_2, [F32];

    (* Vector shift left.  *)

    Vshl, [], All (3, Dreg), "vshl", reg_shift, su_8_64;

    Vshl, [], All (3, Qreg), "vshlQ", reg_shift, su_8_64;

    Vshl, [Instruction_name ["vrshl"]; Rounding],

      All (3, Dreg), "vRshl", reg_shift, su_8_64;

    Vshl, [Instruction_name ["vrshl"]; Rounding],

      All (3, Qreg), "vRshlQ", reg_shift, su_8_64;

    Vshl, [Saturating], All (3, Dreg), "vqshl", reg_shift, su_8_64;

    Vshl, [Saturating], All (3, Qreg), "vqshlQ", reg_shift, su_8_64;

    Vshl, [Instruction_name ["vqrshl"]; Saturating; Rounding],

      All (3, Dreg), "vqRshl", reg_shift, su_8_64;

    Vshl, [Instruction_name ["vqrshl"]; Saturating; Rounding],

      All (3, Qreg), "vqRshlQ", reg_shift, su_8_64;

    (* Vector shift right by constant.  *)

    Vshr_n, [], Binary_imm Dreg, "vshr_n", shift_right, su_8_64;

    Vshr_n, [], Binary_imm Qreg, "vshrQ_n", shift_right, su_8_64;

    Vshr_n, [Instruction_name ["vrshr"]; Rounding], Binary_imm Dreg,

      "vRshr_n", shift_right, su_8_64;

    Vshr_n, [Instruction_name ["vrshr"]; Rounding], Binary_imm Qreg,

      "vRshrQ_n", shift_right, su_8_64;

    Vshr_n, [], Narrow_imm, "vshrn_n", shift_right_sign_invar, su_16_64;

    Vshr_n, [Instruction_name ["vrshrn"]; Rounding], Narrow_imm, "vRshrn_n",

      shift_right_sign_invar, su_16_64;

    Vshr_n, [Saturating], Narrow_imm, "vqshrn_n", shift_right, su_16_64;

    Vshr_n, [Instruction_name ["vqrshrn"]; Saturating; Rounding], Narrow_imm,

      "vqRshrn_n", shift_right, su_16_64;

    Vshr_n, [Saturating; Dst_unsign], Narrow_imm, "vqshrun_n",

      shift_right_to_uns, [S16; S32; S64];

    Vshr_n, [Instruction_name ["vqrshrun"]; Saturating; Dst_unsign; Rounding],

      Narrow_imm, "vqRshrun_n", shift_right_to_uns, [S16; S32; S64];

    (* Vector shift left by constant.  *)

    Vshl_n, [], Binary_imm Dreg, "vshl_n", shift_left_sign_invar, su_8_64;

    Vshl_n, [], Binary_imm Qreg, "vshlQ_n", shift_left_sign_invar, su_8_64;

    Vshl_n, [Saturating], Binary_imm Dreg, "vqshl_n", shift_left, su_8_64;

    Vshl_n, [Saturating], Binary_imm Qreg, "vqshlQ_n", shift_left, su_8_64;

    Vshl_n, [Saturating; Dst_unsign], Binary_imm Dreg, "vqshlu_n",

      shift_left_to_uns, [S8; S16; S32; S64];

    Vshl_n, [Saturating; Dst_unsign], Binary_imm Qreg, "vqshluQ_n",

      shift_left_to_uns, [S8; S16; S32; S64];

    Vshl_n, [], Long_imm, "vshll_n", shift_left, su_8_32;

    (* Vector shift right by constant and accumulate.  *)

    Vsra_n, [], Binary_imm Dreg, "vsra_n", shift_right_acc, su_8_64;

    Vsra_n, [], Binary_imm Qreg, "vsraQ_n", shift_right_acc, su_8_64;

    Vsra_n, [Instruction_name ["vrsra"]; Rounding], Binary_imm Dreg,

      "vRsra_n", shift_right_acc, su_8_64;

    Vsra_n, [Instruction_name ["vrsra"]; Rounding], Binary_imm Qreg,

      "vRsraQ_n", shift_right_acc, su_8_64;

    (* Vector shift right and insert.  *)

    Vsri, [], Use_operands [| Dreg; Dreg; Immed |], "vsri_n", shift_insert,

      P8 :: P16 :: su_8_64;

    Vsri, [], Use_operands [| Qreg; Qreg; Immed |], "vsriQ_n", shift_insert,

      P8 :: P16 :: su_8_64;

    (* Vector shift left and insert.  *)

    Vsli, [], Use_operands [| Dreg; Dreg; Immed |], "vsli_n", shift_insert,

      P8 :: P16 :: su_8_64;

    Vsli, [], Use_operands [| Qreg; Qreg; Immed |], "vsliQ_n", shift_insert,

      P8 :: P16 :: su_8_64;

    (* Absolute value.  *)

    Vabs, [], All (2, Dreg), "vabs", elts_same_1, [S8; S16; S32; F32];

    Vabs, [], All (2, Qreg), "vabsQ", elts_same_1, [S8; S16; S32; F32];

    Vabs, [Saturating], All (2, Dreg), "vqabs", elts_same_1, [S8; S16; S32];

    Vabs, [Saturating], All (2, Qreg), "vqabsQ", elts_same_1, [S8; S16; S32];

    (* Negate.  *)

    Vneg, [], All (2, Dreg), "vneg", elts_same_1, [S8; S16; S32; F32];

    Vneg, [], All (2, Qreg), "vnegQ", elts_same_1, [S8; S16; S32; F32];

    Vneg, [Saturating], All (2, Dreg), "vqneg", elts_same_1, [S8; S16; S32];

    Vneg, [Saturating], All (2, Qreg), "vqnegQ", elts_same_1, [S8; S16; S32];