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jeremybenn |
;; Predicate definitions for ARM and Thumb
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;; Copyright (C) 2004, 2007, 2008 Free Software Foundation, Inc.
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;; Contributed by ARM Ltd.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_predicate "s_register_operand"
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(match_code "reg,subreg")
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{
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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/* We don't consider registers whose class is NO_REGS
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to be a register operand. */
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/* XXX might have to check for lo regs only for thumb ??? */
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return (GET_CODE (op) == REG
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&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
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|| REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
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})
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;; Any hard register.
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(define_predicate "arm_hard_register_operand"
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(match_code "reg")
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{
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return REGNO (op) < FIRST_PSEUDO_REGISTER;
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})
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;; A low register.
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(define_predicate "low_register_operand"
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(and (match_code "reg")
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(match_test "REGNO (op) <= LAST_LO_REGNUM")))
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;; A low register or const_int.
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(define_predicate "low_reg_or_int_operand"
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(ior (match_code "const_int")
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(match_operand 0 "low_register_operand")))
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;; Any core register, or any pseudo. */
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(define_predicate "arm_general_register_operand"
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(match_code "reg,subreg")
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{
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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return (GET_CODE (op) == REG
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&& (REGNO (op) <= LAST_ARM_REGNUM
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|| REGNO (op) >= FIRST_PSEUDO_REGISTER));
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})
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(define_predicate "f_register_operand"
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(match_code "reg,subreg")
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{
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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/* We don't consider registers whose class is NO_REGS
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to be a register operand. */
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return (GET_CODE (op) == REG
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&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
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|| REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
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})
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(define_predicate "vfp_register_operand"
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(match_code "reg,subreg")
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{
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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/* We don't consider registers whose class is NO_REGS
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to be a register operand. */
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return (GET_CODE (op) == REG
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&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
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|| REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
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|| (TARGET_VFPD32
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&& REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
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})
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(define_special_predicate "subreg_lowpart_operator"
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(and (match_code "subreg")
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(match_test "subreg_lowpart_p (op)")))
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;; Reg, subreg(reg) or const_int.
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(define_predicate "reg_or_int_operand"
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(ior (match_code "const_int")
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(match_operand 0 "s_register_operand")))
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(define_predicate "arm_immediate_operand"
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(and (match_code "const_int")
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(match_test "const_ok_for_arm (INTVAL (op))")))
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(define_predicate "arm_neg_immediate_operand"
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(and (match_code "const_int")
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(match_test "const_ok_for_arm (-INTVAL (op))")))
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(define_predicate "arm_not_immediate_operand"
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(and (match_code "const_int")
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(match_test "const_ok_for_arm (~INTVAL (op))")))
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;; Something valid on the RHS of an ARM data-processing instruction
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(define_predicate "arm_rhs_operand"
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(ior (match_operand 0 "s_register_operand")
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(match_operand 0 "arm_immediate_operand")))
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(define_predicate "arm_rhsm_operand"
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(ior (match_operand 0 "arm_rhs_operand")
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(match_operand 0 "memory_operand")))
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(define_predicate "arm_add_operand"
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(ior (match_operand 0 "arm_rhs_operand")
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(match_operand 0 "arm_neg_immediate_operand")))
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(define_predicate "arm_addimm_operand"
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(ior (match_operand 0 "arm_immediate_operand")
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(match_operand 0 "arm_neg_immediate_operand")))
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(define_predicate "arm_not_operand"
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(ior (match_operand 0 "arm_rhs_operand")
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(match_operand 0 "arm_not_immediate_operand")))
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;; True if the operand is a memory reference which contains an
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;; offsettable address.
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(define_predicate "offsettable_memory_operand"
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(and (match_code "mem")
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(match_test
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"offsettable_address_p (reload_completed | reload_in_progress,
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mode, XEXP (op, 0))")))
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;; True if the operand is a memory operand that does not have an
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;; automodified base register (and thus will not generate output reloads).
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(define_predicate "call_memory_operand"
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(and (match_code "mem")
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(and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
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!= RTX_AUTOINC")
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(match_operand 0 "memory_operand"))))
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(define_predicate "arm_reload_memory_operand"
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(and (match_code "mem,reg,subreg")
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(match_test "(!CONSTANT_P (op)
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&& (true_regnum(op) == -1
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|| (GET_CODE (op) == REG
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&& REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
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;; True for valid operands for the rhs of an floating point insns.
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;; Allows regs or certain consts on FPA, just regs for everything else.
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(define_predicate "arm_float_rhs_operand"
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(ior (match_operand 0 "s_register_operand")
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(and (match_code "const_double")
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(match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
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(define_predicate "arm_float_add_operand"
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(ior (match_operand 0 "arm_float_rhs_operand")
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(and (match_code "const_double")
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(match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
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(define_predicate "vfp_compare_operand"
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(ior (match_operand 0 "s_register_operand")
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(and (match_code "const_double")
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(match_test "arm_const_double_rtx (op)"))))
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(define_predicate "arm_float_compare_operand"
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(if_then_else (match_test "TARGET_VFP")
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(match_operand 0 "vfp_compare_operand")
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(match_operand 0 "arm_float_rhs_operand")))
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;; True for valid index operands.
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(define_predicate "index_operand"
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(ior (match_operand 0 "s_register_operand")
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(and (match_operand 0 "immediate_operand")
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(match_test "(GET_CODE (op) != CONST_INT
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|| (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
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;; True for operators that can be combined with a shift in ARM state.
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(define_special_predicate "shiftable_operator"
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(and (match_code "plus,minus,ior,xor,and")
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(match_test "mode == GET_MODE (op)")))
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;; True for logical binary operators.
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(define_special_predicate "logical_binary_operator"
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(and (match_code "ior,xor,and")
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(match_test "mode == GET_MODE (op)")))
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;; True for shift operators.
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(define_special_predicate "shift_operator"
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(and (ior (ior (and (match_code "mult")
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(match_test "power_of_two_operand (XEXP (op, 1), mode)"))
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(and (match_code "rotate")
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(match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
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&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
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(match_code "ashift,ashiftrt,lshiftrt,rotatert"))
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(match_test "mode == GET_MODE (op)")))
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;; True for operators that have 16-bit thumb variants. */
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(define_special_predicate "thumb_16bit_operator"
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(match_code "plus,minus,and,ior,xor"))
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;; True for EQ & NE
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(define_special_predicate "equality_operator"
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(match_code "eq,ne"))
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;; True for integer comparisons and, if FP is active, for comparisons
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;; other than LTGT or UNEQ.
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(define_special_predicate "arm_comparison_operator"
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(ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
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(and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
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&& (TARGET_FPA || TARGET_VFP)")
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(match_code "unordered,ordered,unlt,unle,unge,ungt"))))
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(define_special_predicate "minmax_operator"
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(and (match_code "smin,smax,umin,umax")
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(match_test "mode == GET_MODE (op)")))
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(define_special_predicate "cc_register"
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(and (match_code "reg")
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(and (match_test "REGNO (op) == CC_REGNUM")
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(ior (match_test "mode == GET_MODE (op)")
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(match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
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(define_special_predicate "dominant_cc_register"
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(match_code "reg")
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{
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if (mode == VOIDmode)
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{
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mode = GET_MODE (op);
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if (GET_MODE_CLASS (mode) != MODE_CC)
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return false;
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}
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return (cc_register (op, mode)
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&& (mode == CC_DNEmode
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|| mode == CC_DEQmode
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|| mode == CC_DLEmode
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|| mode == CC_DLTmode
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|| mode == CC_DGEmode
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|| mode == CC_DGTmode
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|| mode == CC_DLEUmode
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|| mode == CC_DLTUmode
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|| mode == CC_DGEUmode
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|| mode == CC_DGTUmode));
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})
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(define_special_predicate "arm_extendqisi_mem_op"
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(and (match_operand 0 "memory_operand")
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(match_test "arm_legitimate_address_outer_p (mode, XEXP (op, 0),
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SIGN_EXTEND, 0)")))
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(define_special_predicate "arm_reg_or_extendqisi_mem_op"
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(ior (match_operand 0 "arm_extendqisi_mem_op")
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(match_operand 0 "s_register_operand")))
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(define_predicate "power_of_two_operand"
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(match_code "const_int")
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{
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HOST_WIDE_INT value = INTVAL (op);
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return value != 0 && (value & (value - 1)) == 0;
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})
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(define_predicate "nonimmediate_di_operand"
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(match_code "reg,subreg,mem")
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{
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if (s_register_operand (op, mode))
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return true;
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
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})
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(define_predicate "di_operand"
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(ior (match_code "const_int,const_double")
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(and (match_code "reg,subreg,mem")
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(match_operand 0 "nonimmediate_di_operand"))))
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| 288 |
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| 289 |
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(define_predicate "nonimmediate_soft_df_operand"
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(match_code "reg,subreg,mem")
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{
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if (s_register_operand (op, mode))
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return true;
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| 295 |
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
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})
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| 301 |
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(define_predicate "soft_df_operand"
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(ior (match_code "const_double")
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(and (match_code "reg,subreg,mem")
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(match_operand 0 "nonimmediate_soft_df_operand"))))
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(define_predicate "const_shift_operand"
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| 307 |
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(and (match_code "const_int")
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(ior (match_operand 0 "power_of_two_operand")
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| 309 |
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(match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))
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| 311 |
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| 312 |
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(define_special_predicate "load_multiple_operation"
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(match_code "parallel")
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{
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HOST_WIDE_INT count = XVECLEN (op, 0);
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|
|
int dest_regno;
|
| 317 |
|
|
rtx src_addr;
|
| 318 |
|
|
HOST_WIDE_INT i = 1, base = 0;
|
| 319 |
|
|
rtx elt;
|
| 320 |
|
|
|
| 321 |
|
|
if (count <= 1
|
| 322 |
|
|
|| GET_CODE (XVECEXP (op, 0, 0)) != SET)
|
| 323 |
|
|
return false;
|
| 324 |
|
|
|
| 325 |
|
|
/* Check to see if this might be a write-back. */
|
| 326 |
|
|
if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
|
| 327 |
|
|
{
|
| 328 |
|
|
i++;
|
| 329 |
|
|
base = 1;
|
| 330 |
|
|
|
| 331 |
|
|
/* Now check it more carefully. */
|
| 332 |
|
|
if (GET_CODE (SET_DEST (elt)) != REG
|
| 333 |
|
|
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
|
| 334 |
|
|
|| GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
|
| 335 |
|
|
|| INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
|
| 336 |
|
|
return false;
|
| 337 |
|
|
}
|
| 338 |
|
|
|
| 339 |
|
|
/* Perform a quick check so we don't blow up below. */
|
| 340 |
|
|
if (count <= i
|
| 341 |
|
|
|| GET_CODE (XVECEXP (op, 0, i - 1)) != SET
|
| 342 |
|
|
|| GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
|
| 343 |
|
|
|| GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
|
| 344 |
|
|
return false;
|
| 345 |
|
|
|
| 346 |
|
|
dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
|
| 347 |
|
|
src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
|
| 348 |
|
|
|
| 349 |
|
|
for (; i < count; i++)
|
| 350 |
|
|
{
|
| 351 |
|
|
elt = XVECEXP (op, 0, i);
|
| 352 |
|
|
|
| 353 |
|
|
if (GET_CODE (elt) != SET
|
| 354 |
|
|
|| GET_CODE (SET_DEST (elt)) != REG
|
| 355 |
|
|
|| GET_MODE (SET_DEST (elt)) != SImode
|
| 356 |
|
|
|| REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
|
| 357 |
|
|
|| GET_CODE (SET_SRC (elt)) != MEM
|
| 358 |
|
|
|| GET_MODE (SET_SRC (elt)) != SImode
|
| 359 |
|
|
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
|
| 360 |
|
|
|| !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
|
| 361 |
|
|
|| GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
|
| 362 |
|
|
|| INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
|
| 363 |
|
|
return false;
|
| 364 |
|
|
}
|
| 365 |
|
|
|
| 366 |
|
|
return true;
|
| 367 |
|
|
})
|
| 368 |
|
|
|
| 369 |
|
|
(define_special_predicate "store_multiple_operation"
|
| 370 |
|
|
(match_code "parallel")
|
| 371 |
|
|
{
|
| 372 |
|
|
HOST_WIDE_INT count = XVECLEN (op, 0);
|
| 373 |
|
|
int src_regno;
|
| 374 |
|
|
rtx dest_addr;
|
| 375 |
|
|
HOST_WIDE_INT i = 1, base = 0;
|
| 376 |
|
|
rtx elt;
|
| 377 |
|
|
|
| 378 |
|
|
if (count <= 1
|
| 379 |
|
|
|| GET_CODE (XVECEXP (op, 0, 0)) != SET)
|
| 380 |
|
|
return false;
|
| 381 |
|
|
|
| 382 |
|
|
/* Check to see if this might be a write-back. */
|
| 383 |
|
|
if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
|
| 384 |
|
|
{
|
| 385 |
|
|
i++;
|
| 386 |
|
|
base = 1;
|
| 387 |
|
|
|
| 388 |
|
|
/* Now check it more carefully. */
|
| 389 |
|
|
if (GET_CODE (SET_DEST (elt)) != REG
|
| 390 |
|
|
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
|
| 391 |
|
|
|| GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
|
| 392 |
|
|
|| INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
|
| 393 |
|
|
return false;
|
| 394 |
|
|
}
|
| 395 |
|
|
|
| 396 |
|
|
/* Perform a quick check so we don't blow up below. */
|
| 397 |
|
|
if (count <= i
|
| 398 |
|
|
|| GET_CODE (XVECEXP (op, 0, i - 1)) != SET
|
| 399 |
|
|
|| GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
|
| 400 |
|
|
|| GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
|
| 401 |
|
|
return false;
|
| 402 |
|
|
|
| 403 |
|
|
src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
|
| 404 |
|
|
dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
|
| 405 |
|
|
|
| 406 |
|
|
for (; i < count; i++)
|
| 407 |
|
|
{
|
| 408 |
|
|
elt = XVECEXP (op, 0, i);
|
| 409 |
|
|
|
| 410 |
|
|
if (GET_CODE (elt) != SET
|
| 411 |
|
|
|| GET_CODE (SET_SRC (elt)) != REG
|
| 412 |
|
|
|| GET_MODE (SET_SRC (elt)) != SImode
|
| 413 |
|
|
|| REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
|
| 414 |
|
|
|| GET_CODE (SET_DEST (elt)) != MEM
|
| 415 |
|
|
|| GET_MODE (SET_DEST (elt)) != SImode
|
| 416 |
|
|
|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
|
| 417 |
|
|
|| !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
|
| 418 |
|
|
|| GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
|
| 419 |
|
|
|| INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
|
| 420 |
|
|
return false;
|
| 421 |
|
|
}
|
| 422 |
|
|
|
| 423 |
|
|
return true;
|
| 424 |
|
|
})
|
| 425 |
|
|
|
| 426 |
|
|
(define_special_predicate "multi_register_push"
|
| 427 |
|
|
(match_code "parallel")
|
| 428 |
|
|
{
|
| 429 |
|
|
if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
|
| 430 |
|
|
|| (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
|
| 431 |
|
|
|| (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
|
| 432 |
|
|
return false;
|
| 433 |
|
|
|
| 434 |
|
|
return true;
|
| 435 |
|
|
})
|
| 436 |
|
|
|
| 437 |
|
|
;;-------------------------------------------------------------------------
|
| 438 |
|
|
;;
|
| 439 |
|
|
;; Thumb predicates
|
| 440 |
|
|
;;
|
| 441 |
|
|
|
| 442 |
|
|
(define_predicate "thumb1_cmp_operand"
|
| 443 |
|
|
(ior (and (match_code "reg,subreg")
|
| 444 |
|
|
(match_operand 0 "s_register_operand"))
|
| 445 |
|
|
(and (match_code "const_int")
|
| 446 |
|
|
(match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
|
| 447 |
|
|
|
| 448 |
|
|
(define_predicate "thumb1_cmpneg_operand"
|
| 449 |
|
|
(and (match_code "const_int")
|
| 450 |
|
|
(match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
|
| 451 |
|
|
|
| 452 |
|
|
;; Return TRUE if a result can be stored in OP without clobbering the
|
| 453 |
|
|
;; condition code register. Prior to reload we only accept a
|
| 454 |
|
|
;; register. After reload we have to be able to handle memory as
|
| 455 |
|
|
;; well, since a pseudo may not get a hard reg and reload cannot
|
| 456 |
|
|
;; handle output-reloads on jump insns.
|
| 457 |
|
|
|
| 458 |
|
|
;; We could possibly handle mem before reload as well, but that might
|
| 459 |
|
|
;; complicate things with the need to handle increment
|
| 460 |
|
|
;; side-effects.
|
| 461 |
|
|
(define_predicate "thumb_cbrch_target_operand"
|
| 462 |
|
|
(and (match_code "reg,subreg,mem")
|
| 463 |
|
|
(ior (match_operand 0 "s_register_operand")
|
| 464 |
|
|
(and (match_test "reload_in_progress || reload_completed")
|
| 465 |
|
|
(match_operand 0 "memory_operand")))))
|
| 466 |
|
|
|
| 467 |
|
|
;;-------------------------------------------------------------------------
|
| 468 |
|
|
;;
|
| 469 |
|
|
;; MAVERICK predicates
|
| 470 |
|
|
;;
|
| 471 |
|
|
|
| 472 |
|
|
(define_predicate "cirrus_register_operand"
|
| 473 |
|
|
(match_code "reg,subreg")
|
| 474 |
|
|
{
|
| 475 |
|
|
if (GET_CODE (op) == SUBREG)
|
| 476 |
|
|
op = SUBREG_REG (op);
|
| 477 |
|
|
|
| 478 |
|
|
return (GET_CODE (op) == REG
|
| 479 |
|
|
&& (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
|
| 480 |
|
|
|| REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
|
| 481 |
|
|
})
|
| 482 |
|
|
|
| 483 |
|
|
(define_predicate "cirrus_fp_register"
|
| 484 |
|
|
(match_code "reg,subreg")
|
| 485 |
|
|
{
|
| 486 |
|
|
if (GET_CODE (op) == SUBREG)
|
| 487 |
|
|
op = SUBREG_REG (op);
|
| 488 |
|
|
|
| 489 |
|
|
return (GET_CODE (op) == REG
|
| 490 |
|
|
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|
| 491 |
|
|
|| REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
|
| 492 |
|
|
})
|
| 493 |
|
|
|
| 494 |
|
|
(define_predicate "cirrus_shift_const"
|
| 495 |
|
|
(and (match_code "const_int")
|
| 496 |
|
|
(match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
|
| 497 |
|
|
|
| 498 |
|
|
|
| 499 |
|
|
;; Neon predicates
|
| 500 |
|
|
|
| 501 |
|
|
(define_predicate "const_multiple_of_8_operand"
|
| 502 |
|
|
(match_code "const_int")
|
| 503 |
|
|
{
|
| 504 |
|
|
unsigned HOST_WIDE_INT val = INTVAL (op);
|
| 505 |
|
|
return (val & 7) == 0;
|
| 506 |
|
|
})
|
| 507 |
|
|
|
| 508 |
|
|
(define_predicate "imm_for_neon_mov_operand"
|
| 509 |
|
|
(match_code "const_vector")
|
| 510 |
|
|
{
|
| 511 |
|
|
return neon_immediate_valid_for_move (op, mode, NULL, NULL);
|
| 512 |
|
|
})
|
| 513 |
|
|
|
| 514 |
|
|
(define_predicate "imm_for_neon_logic_operand"
|
| 515 |
|
|
(match_code "const_vector")
|
| 516 |
|
|
{
|
| 517 |
|
|
return neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL);
|
| 518 |
|
|
})
|
| 519 |
|
|
|
| 520 |
|
|
(define_predicate "imm_for_neon_inv_logic_operand"
|
| 521 |
|
|
(match_code "const_vector")
|
| 522 |
|
|
{
|
| 523 |
|
|
return neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL);
|
| 524 |
|
|
})
|
| 525 |
|
|
|
| 526 |
|
|
(define_predicate "neon_logic_op2"
|
| 527 |
|
|
(ior (match_operand 0 "imm_for_neon_logic_operand")
|
| 528 |
|
|
(match_operand 0 "s_register_operand")))
|
| 529 |
|
|
|
| 530 |
|
|
(define_predicate "neon_inv_logic_op2"
|
| 531 |
|
|
(ior (match_operand 0 "imm_for_neon_inv_logic_operand")
|
| 532 |
|
|
(match_operand 0 "s_register_operand")))
|
| 533 |
|
|
|
| 534 |
|
|
;; TODO: We could check lane numbers more precisely based on the mode.
|
| 535 |
|
|
(define_predicate "neon_lane_number"
|
| 536 |
|
|
(and (match_code "const_int")
|
| 537 |
|
|
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
|
| 538 |
|
|
|
