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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [arm/] [vfp.md] - Blame information for rev 282

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1 282 jeremybenn 
;; ARM VFP instruction patterns
2 
;; Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3 
;; Written by CodeSourcery.
4 
;;
5 
;; This file is part of GCC.
6 
;;
7 
;; GCC is free software; you can redistribute it and/or modify it
8 
;; under the terms of the GNU General Public License as published by
9 
;; the Free Software Foundation; either version 3, or (at your option)
10 
;; any later version.
11 
;;
12 
;; GCC is distributed in the hope that it will be useful, but
13 
;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 
;; General Public License for more details.
16 
;;
17 
;; You should have received a copy of the GNU General Public License
18 
;; along with GCC; see the file COPYING3.  If not see
19 
;; .  */
20 
 
21 
;; Additional register numbers
22 
(define_constants
23 
  [(VFPCC_REGNUM 127)]
24 
)
25 
 
26 
;; The VFP "type" attributes differ from those used in the FPA model.
27 
;; fcpys        Single precision cpy.
28 
;; ffariths     Single precision abs, neg.
29 
;; ffarithd     Double precision abs, neg, cpy.
30 
;; fadds        Single precision add/sub.
31 
;; faddd        Double precision add/sub.
32 
;; fconsts      Single precision load immediate.
33 
;; fconstd      Double precision load immediate.
34 
;; fcmps        Single precision comparison.
35 
;; fcmpd        Double precision comparison.
36 
;; fmuls        Single precision multiply.
37 
;; fmuld        Double precision multiply.
38 
;; fmacs        Single precision multiply-accumulate.
39 
;; fmacd        Double precision multiply-accumulate.
40 
;; fdivs        Single precision sqrt or division.
41 
;; fdivd        Double precision sqrt or division.
42 
;; f_flag       fmstat operation
43 
;; f_load[sd]   Floating point load from memory.
44 
;; f_store[sd]  Floating point store to memory.
45 
;; f_2_r        Transfer vfp to arm reg.
46 
;; r_2_f        Transfer arm to vfp reg.
47 
;; f_cvt        Convert floating<->integral
48 
 
49 
;; SImode moves
50 
;; ??? For now do not allow loading constants into vfp regs.  This causes
51 
;; problems because small constants get converted into adds.
52 
(define_insn "*arm_movsi_vfp"
53 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
54 
      (match_operand:SI 1 "general_operand"        "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
55 
  "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
56 
   && (   s_register_operand (operands[0], SImode)
57 
       || s_register_operand (operands[1], SImode))"
58 
  "*
59 
  switch (which_alternative)
60 
    {
61 
    case 0: case 1:
62 
      return \"mov%?\\t%0, %1\";
63 
    case 2:
64 
      return \"mvn%?\\t%0, #%B1\";
65 
    case 3:
66 
      return \"movw%?\\t%0, %1\";
67 
    case 4:
68 
      return \"ldr%?\\t%0, %1\";
69 
    case 5:
70 
      return \"str%?\\t%1, %0\";
71 
    case 6:
72 
      return \"fmsr%?\\t%0, %1\\t%@ int\";
73 
    case 7:
74 
      return \"fmrs%?\\t%0, %1\\t%@ int\";
75 
    case 8:
76 
      return \"fcpys%?\\t%0, %1\\t%@ int\";
77 
    case 9: case 10:
78 
      return output_move_vfp (operands);
79 
    default:
80 
      gcc_unreachable ();
81 
    }
82 
  "
83 
  [(set_attr "predicable" "yes")
84 
   (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
85 
   (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
86 
   (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
87 
)
88 
 
89 
(define_insn "*thumb2_movsi_vfp"
90 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv")
91 
      (match_operand:SI 1 "general_operand"        "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
92 
  "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
93 
   && (   s_register_operand (operands[0], SImode)
94 
       || s_register_operand (operands[1], SImode))"
95 
  "*
96 
  switch (which_alternative)
97 
    {
98 
    case 0: case 1:
99 
      return \"mov%?\\t%0, %1\";
100 
    case 2:
101 
      return \"mvn%?\\t%0, #%B1\";
102 
    case 3:
103 
      return \"movw%?\\t%0, %1\";
104 
    case 4:
105 
      return \"ldr%?\\t%0, %1\";
106 
    case 5:
107 
      return \"str%?\\t%1, %0\";
108 
    case 6:
109 
      return \"fmsr%?\\t%0, %1\\t%@ int\";
110 
    case 7:
111 
      return \"fmrs%?\\t%0, %1\\t%@ int\";
112 
    case 8:
113 
      return \"fcpys%?\\t%0, %1\\t%@ int\";
114 
    case 9: case 10:
115 
      return output_move_vfp (operands);
116 
    default:
117 
      gcc_unreachable ();
118 
    }
119 
  "
120 
  [(set_attr "predicable" "yes")
121 
   (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
122 
   (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
123 
   (set_attr "neg_pool_range" "*,*,*,*,   0,*,*,*,*,1008,*")]
124 
)
125 
 
126 
 
127 
;; DImode moves
128 
 
129 
(define_insn "*arm_movdi_vfp"
130 
  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
131 
        (match_operand:DI 1 "di_operand"              "rIK,mi,r,r,w,w,Uvi,w"))]
132 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
133 
   && (   register_operand (operands[0], DImode)
134 
       || register_operand (operands[1], DImode))"
135 
  "*
136 
  switch (which_alternative)
137 
    {
138 
    case 0:
139 
      return \"#\";
140 
    case 1:
141 
    case 2:
142 
      return output_move_double (operands);
143 
    case 3:
144 
      return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
145 
    case 4:
146 
      return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
147 
    case 5:
148 
      if (TARGET_VFP_SINGLE)
149 
        return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
150 
      else
151 
        return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
152 
    case 6: case 7:
153 
      return output_move_vfp (operands);
154 
    default:
155 
      gcc_unreachable ();
156 
    }
157 
  "
158 
  [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
159 
   (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
160 
                               (eq_attr "alternative" "5")
161 
                                (if_then_else
162 
                                 (eq (symbol_ref "TARGET_VFP_SINGLE")
163 
                                     (const_int 1))
164 
                                 (const_int 8)
165 
                                 (const_int 4))]
166 
                              (const_int 4)))
167 
   (set_attr "predicable"    "yes")
168 
   (set_attr "pool_range"     "*,1020,*,*,*,*,1020,*")
169 
   (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
170 
)
171 
 
172 
(define_insn "*thumb2_movdi_vfp"
173 
  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
174 
        (match_operand:DI 1 "di_operand"              "rIK,mi,r,r,w,w,Uvi,w"))]
175 
  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
176 
  "*
177 
  switch (which_alternative)
178 
    {
179 
    case 0: case 1: case 2:
180 
      return (output_move_double (operands));
181 
    case 3:
182 
      return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
183 
    case 4:
184 
      return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
185 
    case 5:
186 
      if (TARGET_VFP_SINGLE)
187 
        return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
188 
      else
189 
        return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
190 
    case 6: case 7:
191 
      return output_move_vfp (operands);
192 
    default:
193 
      abort ();
194 
    }
195 
  "
196 
  [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store")
197 
   (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
198 
                               (eq_attr "alternative" "5")
199 
                                (if_then_else
200 
                                 (eq (symbol_ref "TARGET_VFP_SINGLE")
201 
                                     (const_int 1))
202 
                                 (const_int 8)
203 
                                 (const_int 4))]
204 
                              (const_int 4)))
205 
   (set_attr "pool_range"     "*,4096,*,*,*,*,1020,*")
206 
   (set_attr "neg_pool_range" "*,   0,*,*,*,*,1008,*")]
207 
)
208 
 
209 
;; HFmode moves
210 
(define_insn "*movhf_vfp_neon"
211 
  [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
212 
        (match_operand:HF 1 "general_operand"      " Um, t,m,r,t,r,r,t,F"))]
213 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
214 
   && (   s_register_operand (operands[0], HFmode)
215 
       || s_register_operand (operands[1], HFmode))"
216 
  "*
217 
  switch (which_alternative)
218 
    {
219 
    case 0:     /* S register from memory */
220 
      return \"vld1.16\\t{%z0}, %A1\";
221 
    case 1:     /* memory from S register */
222 
      return \"vst1.16\\t{%z1}, %A0\";
223 
    case 2:     /* ARM register from memory */
224 
      return \"ldrh\\t%0, %1\\t%@ __fp16\";
225 
    case 3:     /* memory from ARM register */
226 
      return \"strh\\t%1, %0\\t%@ __fp16\";
227 
    case 4:     /* S register from S register */
228 
      return \"fcpys\\t%0, %1\";
229 
    case 5:     /* ARM register from ARM register */
230 
      return \"mov\\t%0, %1\\t%@ __fp16\";
231 
    case 6:     /* S register from ARM register */
232 
      return \"fmsr\\t%0, %1\";
233 
    case 7:     /* ARM register from S register */
234 
      return \"fmrs\\t%0, %1\";
235 
    case 8:     /* ARM register from constant */
236 
      {
237 
        REAL_VALUE_TYPE r;
238 
        long bits;
239 
        rtx ops[4];
240 
 
241 
        REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
242 
        bits = real_to_target (NULL, &r, HFmode);
243 
        ops[0] = operands[0];
244 
        ops[1] = GEN_INT (bits);
245 
        ops[2] = GEN_INT (bits & 0xff00);
246 
        ops[3] = GEN_INT (bits & 0x00ff);
247 
 
248 
        if (arm_arch_thumb2)
249 
          output_asm_insn (\"movw\\t%0, %1\", ops);
250 
        else
251 
          output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
252 
        return \"\";
253 
       }
254 
    default:
255 
      gcc_unreachable ();
256 
    }
257 
  "
258 
  [(set_attr "conds" "unconditional")
259 
   (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
260 
   (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
261 
   (set_attr "length" "4,4,4,4,4,4,4,4,8")]
262 
)
263 
 
264 
;; FP16 without element load/store instructions.
265 
(define_insn "*movhf_vfp"
266 
  [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
267 
        (match_operand:HF 1 "general_operand"      " m,r,t,r,r,t,F"))]
268 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
269 
   && (   s_register_operand (operands[0], HFmode)
270 
       || s_register_operand (operands[1], HFmode))"
271 
  "*
272 
  switch (which_alternative)
273 
    {
274 
    case 0:     /* ARM register from memory */
275 
      return \"ldrh\\t%0, %1\\t%@ __fp16\";
276 
    case 1:     /* memory from ARM register */
277 
      return \"strh\\t%1, %0\\t%@ __fp16\";
278 
    case 2:     /* S register from S register */
279 
      return \"fcpys\\t%0, %1\";
280 
    case 3:     /* ARM register from ARM register */
281 
      return \"mov\\t%0, %1\\t%@ __fp16\";
282 
    case 4:     /* S register from ARM register */
283 
      return \"fmsr\\t%0, %1\";
284 
    case 5:     /* ARM register from S register */
285 
      return \"fmrs\\t%0, %1\";
286 
    case 6:     /* ARM register from constant */
287 
      {
288 
        REAL_VALUE_TYPE r;
289 
        long bits;
290 
        rtx ops[4];
291 
 
292 
        REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
293 
        bits = real_to_target (NULL, &r, HFmode);
294 
        ops[0] = operands[0];
295 
        ops[1] = GEN_INT (bits);
296 
        ops[2] = GEN_INT (bits & 0xff00);
297 
        ops[3] = GEN_INT (bits & 0x00ff);
298 
 
299 
        if (arm_arch_thumb2)
300 
          output_asm_insn (\"movw\\t%0, %1\", ops);
301 
        else
302 
          output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
303 
        return \"\";
304 
       }
305 
    default:
306 
      gcc_unreachable ();
307 
    }
308 
  "
309 
  [(set_attr "conds" "unconditional")
310 
   (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*")
311 
   (set_attr "length" "4,4,4,4,4,4,8")]
312 
)
313 
 
314 
 
315 
;; SFmode moves
316 
;; Disparage the w<->r cases because reloading an invalid address is
317 
;; preferable to loading the value via integer registers.
318 
 
319 
(define_insn "*movsf_vfp"
320 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
321 
        (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
322 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
323 
   && (   s_register_operand (operands[0], SFmode)
324 
       || s_register_operand (operands[1], SFmode))"
325 
  "*
326 
  switch (which_alternative)
327 
    {
328 
    case 0:
329 
      return \"fmsr%?\\t%0, %1\";
330 
    case 1:
331 
      return \"fmrs%?\\t%0, %1\";
332 
    case 2:
333 
      return \"fconsts%?\\t%0, #%G1\";
334 
    case 3: case 4:
335 
      return output_move_vfp (operands);
336 
    case 5:
337 
      return \"ldr%?\\t%0, %1\\t%@ float\";
338 
    case 6:
339 
      return \"str%?\\t%1, %0\\t%@ float\";
340 
    case 7:
341 
      return \"fcpys%?\\t%0, %1\";
342 
    case 8:
343 
      return \"mov%?\\t%0, %1\\t%@ float\";
344 
    default:
345 
      gcc_unreachable ();
346 
    }
347 
  "
348 
  [(set_attr "predicable" "yes")
349 
   (set_attr "type"
350 
     "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
351 
   (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
352 
   (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
353 
)
354 
 
355 
(define_insn "*thumb2_movsf_vfp"
356 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t  ,Uv,r ,m,t,r")
357 
        (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
358 
  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
359 
   && (   s_register_operand (operands[0], SFmode)
360 
       || s_register_operand (operands[1], SFmode))"
361 
  "*
362 
  switch (which_alternative)
363 
    {
364 
    case 0:
365 
      return \"fmsr%?\\t%0, %1\";
366 
    case 1:
367 
      return \"fmrs%?\\t%0, %1\";
368 
    case 2:
369 
      return \"fconsts%?\\t%0, #%G1\";
370 
    case 3: case 4:
371 
      return output_move_vfp (operands);
372 
    case 5:
373 
      return \"ldr%?\\t%0, %1\\t%@ float\";
374 
    case 6:
375 
      return \"str%?\\t%1, %0\\t%@ float\";
376 
    case 7:
377 
      return \"fcpys%?\\t%0, %1\";
378 
    case 8:
379 
      return \"mov%?\\t%0, %1\\t%@ float\";
380 
    default:
381 
      gcc_unreachable ();
382 
    }
383 
  "
384 
  [(set_attr "predicable" "yes")
385 
   (set_attr "type"
386 
     "r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*")
387 
   (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
388 
   (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
389 
)
390 
 
391 
 
392 
;; DFmode moves
393 
 
394 
(define_insn "*movdf_vfp"
395 
  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w  ,Uv,w,r")
396 
        (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dy,mF,r,UvF,w, w,r"))]
397 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
398 
   && (   register_operand (operands[0], DFmode)
399 
       || register_operand (operands[1], DFmode))"
400 
  "*
401 
  {
402 
    switch (which_alternative)
403 
      {
404 
      case 0:
405 
        return \"fmdrr%?\\t%P0, %Q1, %R1\";
406 
      case 1:
407 
        return \"fmrrd%?\\t%Q0, %R0, %P1\";
408 
      case 2:
409 
        gcc_assert (TARGET_VFP_DOUBLE);
410 
        return \"fconstd%?\\t%P0, #%G1\";
411 
      case 3: case 4:
412 
        return output_move_double (operands);
413 
      case 5: case 6:
414 
        return output_move_vfp (operands);
415 
      case 7:
416 
        if (TARGET_VFP_SINGLE)
417 
          return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
418 
        else
419 
          return \"fcpyd%?\\t%P0, %P1\";
420 
      case 8:
421 
        return \"#\";
422 
      default:
423 
        gcc_unreachable ();
424 
      }
425 
    }
426 
  "
427 
  [(set_attr "type"
428 
     "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
429 
   (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
430 
                               (eq_attr "alternative" "7")
431 
                                (if_then_else
432 
                                 (eq (symbol_ref "TARGET_VFP_SINGLE")
433 
                                     (const_int 1))
434 
                                 (const_int 8)
435 
                                 (const_int 4))]
436 
                              (const_int 4)))
437 
   (set_attr "predicable" "yes")
438 
   (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
439 
   (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")]
440 
)
441 
 
442 
(define_insn "*thumb2_movdf_vfp"
443 
  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w  ,Uv,w,r")
444 
        (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dy,mF,r,UvF,w, w,r"))]
445 
  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
446 
  "*
447 
  {
448 
    switch (which_alternative)
449 
      {
450 
      case 0:
451 
        return \"fmdrr%?\\t%P0, %Q1, %R1\";
452 
      case 1:
453 
        return \"fmrrd%?\\t%Q0, %R0, %P1\";
454 
      case 2:
455 
        gcc_assert (TARGET_VFP_DOUBLE);
456 
        return \"fconstd%?\\t%P0, #%G1\";
457 
      case 3: case 4: case 8:
458 
        return output_move_double (operands);
459 
      case 5: case 6:
460 
        return output_move_vfp (operands);
461 
      case 7:
462 
        if (TARGET_VFP_SINGLE)
463 
          return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
464 
        else
465 
          return \"fcpyd%?\\t%P0, %P1\";
466 
      default:
467 
        abort ();
468 
      }
469 
    }
470 
  "
471 
  [(set_attr "type"
472 
     "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
473 
   (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
474 
                               (eq_attr "alternative" "7")
475 
                                (if_then_else
476 
                                 (eq (symbol_ref "TARGET_VFP_SINGLE")
477 
                                     (const_int 1))
478 
                                 (const_int 8)
479 
                                 (const_int 4))]
480 
                              (const_int 4)))
481 
   (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
482 
   (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
483 
)
484 
 
485 
 
486 
;; Conditional move patterns
487 
 
488 
(define_insn "*movsfcc_vfp"
489 
  [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
490 
        (if_then_else:SF
491 
          (match_operator   3 "arm_comparison_operator"
492 
            [(match_operand 4 "cc_register" "") (const_int 0)])
493 
          (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
494 
          (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
495 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
496 
  "@
497 
   fcpys%D3\\t%0, %2
498 
   fcpys%d3\\t%0, %1
499 
   fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
500 
   fmsr%D3\\t%0, %2
501 
   fmsr%d3\\t%0, %1
502 
   fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
503 
   fmrs%D3\\t%0, %2
504 
   fmrs%d3\\t%0, %1
505 
   fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
506 
   [(set_attr "conds" "use")
507 
    (set_attr "length" "4,4,8,4,4,8,4,4,8")
508 
    (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
509 
)
510 
 
511 
(define_insn "*thumb2_movsfcc_vfp"
512 
  [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
513 
        (if_then_else:SF
514 
          (match_operator   3 "arm_comparison_operator"
515 
            [(match_operand 4 "cc_register" "") (const_int 0)])
516 
          (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
517 
          (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
518 
  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
519 
  "@
520 
   it\\t%D3\;fcpys%D3\\t%0, %2
521 
   it\\t%d3\;fcpys%d3\\t%0, %1
522 
   ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
523 
   it\\t%D3\;fmsr%D3\\t%0, %2
524 
   it\\t%d3\;fmsr%d3\\t%0, %1
525 
   ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
526 
   it\\t%D3\;fmrs%D3\\t%0, %2
527 
   it\\t%d3\;fmrs%d3\\t%0, %1
528 
   ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
529 
   [(set_attr "conds" "use")
530 
    (set_attr "length" "6,6,10,6,6,10,6,6,10")
531 
    (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
532 
)
533 
 
534 
(define_insn "*movdfcc_vfp"
535 
  [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
536 
        (if_then_else:DF
537 
          (match_operator   3 "arm_comparison_operator"
538 
            [(match_operand 4 "cc_register" "") (const_int 0)])
539 
          (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
540 
          (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
541 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
542 
  "@
543 
   fcpyd%D3\\t%P0, %P2
544 
   fcpyd%d3\\t%P0, %P1
545 
   fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
546 
   fmdrr%D3\\t%P0, %Q2, %R2
547 
   fmdrr%d3\\t%P0, %Q1, %R1
548 
   fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
549 
   fmrrd%D3\\t%Q0, %R0, %P2
550 
   fmrrd%d3\\t%Q0, %R0, %P1
551 
   fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
552 
   [(set_attr "conds" "use")
553 
    (set_attr "length" "4,4,8,4,4,8,4,4,8")
554 
    (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
555 
)
556 
 
557 
(define_insn "*thumb2_movdfcc_vfp"
558 
  [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
559 
        (if_then_else:DF
560 
          (match_operator   3 "arm_comparison_operator"
561 
            [(match_operand 4 "cc_register" "") (const_int 0)])
562 
          (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
563 
          (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
564 
  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
565 
  "@
566 
   it\\t%D3\;fcpyd%D3\\t%P0, %P2
567 
   it\\t%d3\;fcpyd%d3\\t%P0, %P1
568 
   ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
569 
   it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
570 
   it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
571 
   ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
572 
   it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
573 
   it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
574 
   ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
575 
   [(set_attr "conds" "use")
576 
    (set_attr "length" "6,6,10,6,6,10,6,6,10")
577 
    (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
578 
)
579 
 
580 
 
581 
;; Sign manipulation functions
582 
 
583 
(define_insn "*abssf2_vfp"
584 
  [(set (match_operand:SF         0 "s_register_operand" "=t")
585 
        (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
586 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
587 
  "fabss%?\\t%0, %1"
588 
  [(set_attr "predicable" "yes")
589 
   (set_attr "type" "ffariths")]
590 
)
591 
 
592 
(define_insn "*absdf2_vfp"
593 
  [(set (match_operand:DF         0 "s_register_operand" "=w")
594 
        (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
595 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
596 
  "fabsd%?\\t%P0, %P1"
597 
  [(set_attr "predicable" "yes")
598 
   (set_attr "type" "ffarithd")]
599 
)
600 
 
601 
(define_insn "*negsf2_vfp"
602 
  [(set (match_operand:SF         0 "s_register_operand" "=t,?r")
603 
        (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
604 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
605 
  "@
606 
   fnegs%?\\t%0, %1
607 
   eor%?\\t%0, %1, #-2147483648"
608 
  [(set_attr "predicable" "yes")
609 
   (set_attr "type" "ffariths")]
610 
)
611 
 
612 
(define_insn_and_split "*negdf2_vfp"
613 
  [(set (match_operand:DF         0 "s_register_operand" "=w,?r,?r")
614 
        (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
615 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
616 
  "@
617 
   fnegd%?\\t%P0, %P1
618 
   #
619 
   #"
620 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
621 
   && arm_general_register_operand (operands[0], DFmode)"
622 
  [(set (match_dup 0) (match_dup 1))]
623 
  "
624 
  if (REGNO (operands[0]) == REGNO (operands[1]))
625 
    {
626 
      operands[0] = gen_highpart (SImode, operands[0]);
627 
      operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
628 
    }
629 
  else
630 
    {
631 
      rtx in_hi, in_lo, out_hi, out_lo;
632 
 
633 
      in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
634 
                           GEN_INT (0x80000000));
635 
      in_lo = gen_lowpart (SImode, operands[1]);
636 
      out_hi = gen_highpart (SImode, operands[0]);
637 
      out_lo = gen_lowpart (SImode, operands[0]);
638 
 
639 
      if (REGNO (in_lo) == REGNO (out_hi))
640 
        {
641 
          emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
642 
          operands[0] = out_hi;
643 
          operands[1] = in_hi;
644 
        }
645 
      else
646 
        {
647 
          emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
648 
          operands[0] = out_lo;
649 
          operands[1] = in_lo;
650 
        }
651 
    }
652 
  "
653 
  [(set_attr "predicable" "yes")
654 
   (set_attr "length" "4,4,8")
655 
   (set_attr "type" "ffarithd")]
656 
)
657 
 
658 
 
659 
;; Arithmetic insns
660 
 
661 
(define_insn "*addsf3_vfp"
662 
  [(set (match_operand:SF          0 "s_register_operand" "=t")
663 
        (plus:SF (match_operand:SF 1 "s_register_operand" "t")
664 
                 (match_operand:SF 2 "s_register_operand" "t")))]
665 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
666 
  "fadds%?\\t%0, %1, %2"
667 
  [(set_attr "predicable" "yes")
668 
   (set_attr "type" "fadds")]
669 
)
670 
 
671 
(define_insn "*adddf3_vfp"
672 
  [(set (match_operand:DF          0 "s_register_operand" "=w")
673 
        (plus:DF (match_operand:DF 1 "s_register_operand" "w")
674 
                 (match_operand:DF 2 "s_register_operand" "w")))]
675 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
676 
  "faddd%?\\t%P0, %P1, %P2"
677 
  [(set_attr "predicable" "yes")
678 
   (set_attr "type" "faddd")]
679 
)
680 
 
681 
 
682 
(define_insn "*subsf3_vfp"
683 
  [(set (match_operand:SF           0 "s_register_operand" "=t")
684 
        (minus:SF (match_operand:SF 1 "s_register_operand" "t")
685 
                  (match_operand:SF 2 "s_register_operand" "t")))]
686 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
687 
  "fsubs%?\\t%0, %1, %2"
688 
  [(set_attr "predicable" "yes")
689 
   (set_attr "type" "fadds")]
690 
)
691 
 
692 
(define_insn "*subdf3_vfp"
693 
  [(set (match_operand:DF           0 "s_register_operand" "=w")
694 
        (minus:DF (match_operand:DF 1 "s_register_operand" "w")
695 
                  (match_operand:DF 2 "s_register_operand" "w")))]
696 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
697 
  "fsubd%?\\t%P0, %P1, %P2"
698 
  [(set_attr "predicable" "yes")
699 
   (set_attr "type" "faddd")]
700 
)
701 
 
702 
 
703 
;; Division insns
704 
 
705 
(define_insn "*divsf3_vfp"
706 
  [(set (match_operand:SF         0 "s_register_operand" "+t")
707 
        (div:SF (match_operand:SF 1 "s_register_operand" "t")
708 
                (match_operand:SF 2 "s_register_operand" "t")))]
709 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
710 
  "fdivs%?\\t%0, %1, %2"
711 
  [(set_attr "predicable" "yes")
712 
   (set_attr "type" "fdivs")]
713 
)
714 
 
715 
(define_insn "*divdf3_vfp"
716 
  [(set (match_operand:DF         0 "s_register_operand" "+w")
717 
        (div:DF (match_operand:DF 1 "s_register_operand" "w")
718 
                (match_operand:DF 2 "s_register_operand" "w")))]
719 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
720 
  "fdivd%?\\t%P0, %P1, %P2"
721 
  [(set_attr "predicable" "yes")
722 
   (set_attr "type" "fdivd")]
723 
)
724 
 
725 
 
726 
;; Multiplication insns
727 
 
728 
(define_insn "*mulsf3_vfp"
729 
  [(set (match_operand:SF          0 "s_register_operand" "+t")
730 
        (mult:SF (match_operand:SF 1 "s_register_operand" "t")
731 
                 (match_operand:SF 2 "s_register_operand" "t")))]
732 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
733 
  "fmuls%?\\t%0, %1, %2"
734 
  [(set_attr "predicable" "yes")
735 
   (set_attr "type" "fmuls")]
736 
)
737 
 
738 
(define_insn "*muldf3_vfp"
739 
  [(set (match_operand:DF          0 "s_register_operand" "+w")
740 
        (mult:DF (match_operand:DF 1 "s_register_operand" "w")
741 
                 (match_operand:DF 2 "s_register_operand" "w")))]
742 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
743 
  "fmuld%?\\t%P0, %P1, %P2"
744 
  [(set_attr "predicable" "yes")
745 
   (set_attr "type" "fmuld")]
746 
)
747 
 
748 
 
749 
(define_insn "*mulsf3negsf_vfp"
750 
  [(set (match_operand:SF                  0 "s_register_operand" "+t")
751 
        (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
752 
                 (match_operand:SF         2 "s_register_operand" "t")))]
753 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
754 
  "fnmuls%?\\t%0, %1, %2"
755 
  [(set_attr "predicable" "yes")
756 
   (set_attr "type" "fmuls")]
757 
)
758 
 
759 
(define_insn "*muldf3negdf_vfp"
760 
  [(set (match_operand:DF                  0 "s_register_operand" "+w")
761 
        (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
762 
                 (match_operand:DF         2 "s_register_operand" "w")))]
763 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
764 
  "fnmuld%?\\t%P0, %P1, %P2"
765 
  [(set_attr "predicable" "yes")
766 
   (set_attr "type" "fmuld")]
767 
)
768 
 
769 
 
770 
;; Multiply-accumulate insns
771 
 
772 
;; 0 = 1 * 2 + 0
773 
(define_insn "*mulsf3addsf_vfp"
774 
  [(set (match_operand:SF                   0 "s_register_operand" "=t")
775 
        (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
776 
                          (match_operand:SF 3 "s_register_operand" "t"))
777 
                 (match_operand:SF          1 "s_register_operand" "0")))]
778 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
779 
  "fmacs%?\\t%0, %2, %3"
780 
  [(set_attr "predicable" "yes")
781 
   (set_attr "type" "fmacs")]
782 
)
783 
 
784 
(define_insn "*muldf3adddf_vfp"
785 
  [(set (match_operand:DF                   0 "s_register_operand" "=w")
786 
        (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
787 
                          (match_operand:DF 3 "s_register_operand" "w"))
788 
                 (match_operand:DF          1 "s_register_operand" "0")))]
789 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
790 
  "fmacd%?\\t%P0, %P2, %P3"
791 
  [(set_attr "predicable" "yes")
792 
   (set_attr "type" "fmacd")]
793 
)
794 
 
795 
;; 0 = 1 * 2 - 0
796 
(define_insn "*mulsf3subsf_vfp"
797 
  [(set (match_operand:SF                    0 "s_register_operand" "=t")
798 
        (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
799 
                           (match_operand:SF 3 "s_register_operand" "t"))
800 
                  (match_operand:SF          1 "s_register_operand" "0")))]
801 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
802 
  "fmscs%?\\t%0, %2, %3"
803 
  [(set_attr "predicable" "yes")
804 
   (set_attr "type" "fmacs")]
805 
)
806 
 
807 
(define_insn "*muldf3subdf_vfp"
808 
  [(set (match_operand:DF                    0 "s_register_operand" "=w")
809 
        (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
810 
                           (match_operand:DF 3 "s_register_operand" "w"))
811 
                  (match_operand:DF          1 "s_register_operand" "0")))]
812 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
813 
  "fmscd%?\\t%P0, %P2, %P3"
814 
  [(set_attr "predicable" "yes")
815 
   (set_attr "type" "fmacd")]
816 
)
817 
 
818 
;; 0 = -(1 * 2) + 0
819 
(define_insn "*mulsf3negsfaddsf_vfp"
820 
  [(set (match_operand:SF                    0 "s_register_operand" "=t")
821 
        (minus:SF (match_operand:SF          1 "s_register_operand" "0")
822 
                  (mult:SF (match_operand:SF 2 "s_register_operand" "t")
823 
                           (match_operand:SF 3 "s_register_operand" "t"))))]
824 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
825 
  "fnmacs%?\\t%0, %2, %3"
826 
  [(set_attr "predicable" "yes")
827 
   (set_attr "type" "fmacs")]
828 
)
829 
 
830 
(define_insn "*fmuldf3negdfadddf_vfp"
831 
  [(set (match_operand:DF                    0 "s_register_operand" "=w")
832 
        (minus:DF (match_operand:DF          1 "s_register_operand" "0")
833 
                  (mult:DF (match_operand:DF 2 "s_register_operand" "w")
834 
                           (match_operand:DF 3 "s_register_operand" "w"))))]
835 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
836 
  "fnmacd%?\\t%P0, %P2, %P3"
837 
  [(set_attr "predicable" "yes")
838 
   (set_attr "type" "fmacd")]
839 
)
840 
 
841 
 
842 
;; 0 = -(1 * 2) - 0
843 
(define_insn "*mulsf3negsfsubsf_vfp"
844 
  [(set (match_operand:SF                     0 "s_register_operand" "=t")
845 
        (minus:SF (mult:SF
846 
                    (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
847 
                    (match_operand:SF         3 "s_register_operand" "t"))
848 
                  (match_operand:SF           1 "s_register_operand" "0")))]
849 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
850 
  "fnmscs%?\\t%0, %2, %3"
851 
  [(set_attr "predicable" "yes")
852 
   (set_attr "type" "fmacs")]
853 
)
854 
 
855 
(define_insn "*muldf3negdfsubdf_vfp"
856 
  [(set (match_operand:DF                     0 "s_register_operand" "=w")
857 
        (minus:DF (mult:DF
858 
                    (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
859 
                    (match_operand:DF         3 "s_register_operand" "w"))
860 
                  (match_operand:DF           1 "s_register_operand" "0")))]
861 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
862 
  "fnmscd%?\\t%P0, %P2, %P3"
863 
  [(set_attr "predicable" "yes")
864 
   (set_attr "type" "fmacd")]
865 
)
866 
 
867 
 
868 
;; Conversion routines
869 
 
870 
(define_insn "*extendsfdf2_vfp"
871 
  [(set (match_operand:DF                  0 "s_register_operand" "=w")
872 
        (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
873 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
874 
  "fcvtds%?\\t%P0, %1"
875 
  [(set_attr "predicable" "yes")
876 
   (set_attr "type" "f_cvt")]
877 
)
878 
 
879 
(define_insn "*truncdfsf2_vfp"
880 
  [(set (match_operand:SF                  0 "s_register_operand" "=t")
881 
        (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
882 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
883 
  "fcvtsd%?\\t%0, %P1"
884 
  [(set_attr "predicable" "yes")
885 
   (set_attr "type" "f_cvt")]
886 
)
887 
 
888 
(define_insn "extendhfsf2"
889 
  [(set (match_operand:SF                  0 "s_register_operand" "=t")
890 
        (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
891 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
892 
  "vcvtb%?.f32.f16\\t%0, %1"
893 
  [(set_attr "predicable" "yes")
894 
   (set_attr "type" "f_cvt")]
895 
)
896 
 
897 
(define_insn "truncsfhf2"
898 
  [(set (match_operand:HF                  0 "s_register_operand" "=t")
899 
        (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
900 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
901 
  "vcvtb%?.f16.f32\\t%0, %1"
902 
  [(set_attr "predicable" "yes")
903 
   (set_attr "type" "f_cvt")]
904 
)
905 
 
906 
(define_insn "*truncsisf2_vfp"
907 
  [(set (match_operand:SI                 0 "s_register_operand" "=t")
908 
        (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
909 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
910 
  "ftosizs%?\\t%0, %1"
911 
  [(set_attr "predicable" "yes")
912 
   (set_attr "type" "f_cvt")]
913 
)
914 
 
915 
(define_insn "*truncsidf2_vfp"
916 
  [(set (match_operand:SI                 0 "s_register_operand" "=t")
917 
        (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
918 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
919 
  "ftosizd%?\\t%0, %P1"
920 
  [(set_attr "predicable" "yes")
921 
   (set_attr "type" "f_cvt")]
922 
)
923 
 
924 
 
925 
(define_insn "fixuns_truncsfsi2"
926 
  [(set (match_operand:SI                 0 "s_register_operand" "=t")
927 
        (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
928 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
929 
  "ftouizs%?\\t%0, %1"
930 
  [(set_attr "predicable" "yes")
931 
   (set_attr "type" "f_cvt")]
932 
)
933 
 
934 
(define_insn "fixuns_truncdfsi2"
935 
  [(set (match_operand:SI                 0 "s_register_operand" "=t")
936 
        (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
937 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
938 
  "ftouizd%?\\t%0, %P1"
939 
  [(set_attr "predicable" "yes")
940 
   (set_attr "type" "f_cvt")]
941 
)
942 
 
943 
 
944 
(define_insn "*floatsisf2_vfp"
945 
  [(set (match_operand:SF           0 "s_register_operand" "=t")
946 
        (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
947 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
948 
  "fsitos%?\\t%0, %1"
949 
  [(set_attr "predicable" "yes")
950 
   (set_attr "type" "f_cvt")]
951 
)
952 
 
953 
(define_insn "*floatsidf2_vfp"
954 
  [(set (match_operand:DF           0 "s_register_operand" "=w")
955 
        (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
956 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
957 
  "fsitod%?\\t%P0, %1"
958 
  [(set_attr "predicable" "yes")
959 
   (set_attr "type" "f_cvt")]
960 
)
961 
 
962 
 
963 
(define_insn "floatunssisf2"
964 
  [(set (match_operand:SF           0 "s_register_operand" "=t")
965 
        (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
966 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
967 
  "fuitos%?\\t%0, %1"
968 
  [(set_attr "predicable" "yes")
969 
   (set_attr "type" "f_cvt")]
970 
)
971 
 
972 
(define_insn "floatunssidf2"
973 
  [(set (match_operand:DF           0 "s_register_operand" "=w")
974 
        (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
975 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
976 
  "fuitod%?\\t%P0, %1"
977 
  [(set_attr "predicable" "yes")
978 
   (set_attr "type" "f_cvt")]
979 
)
980 
 
981 
 
982 
;; Sqrt insns.
983 
 
984 
(define_insn "*sqrtsf2_vfp"
985 
  [(set (match_operand:SF          0 "s_register_operand" "=t")
986 
        (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
987 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
988 
  "fsqrts%?\\t%0, %1"
989 
  [(set_attr "predicable" "yes")
990 
   (set_attr "type" "fdivs")]
991 
)
992 
 
993 
(define_insn "*sqrtdf2_vfp"
994 
  [(set (match_operand:DF          0 "s_register_operand" "=w")
995 
        (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
996 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
997 
  "fsqrtd%?\\t%P0, %P1"
998 
  [(set_attr "predicable" "yes")
999 
   (set_attr "type" "fdivd")]
1000 
)
1001 
 
1002 
 
1003 
;; Patterns to split/copy vfp condition flags.
1004 
 
1005 
(define_insn "*movcc_vfp"
1006 
  [(set (reg CC_REGNUM)
1007 
        (reg VFPCC_REGNUM))]
1008 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1009 
  "fmstat%?"
1010 
  [(set_attr "conds" "set")
1011 
   (set_attr "type" "f_flag")]
1012 
)
1013 
 
1014 
(define_insn_and_split "*cmpsf_split_vfp"
1015 
  [(set (reg:CCFP CC_REGNUM)
1016 
        (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t")
1017 
                      (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1018 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1019 
  "#"
1020 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1021 
  [(set (reg:CCFP VFPCC_REGNUM)
1022 
        (compare:CCFP (match_dup 0)
1023 
                      (match_dup 1)))
1024 
   (set (reg:CCFP CC_REGNUM)
1025 
        (reg:CCFP VFPCC_REGNUM))]
1026 
  ""
1027 
)
1028 
 
1029 
(define_insn_and_split "*cmpsf_trap_split_vfp"
1030 
  [(set (reg:CCFPE CC_REGNUM)
1031 
        (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t")
1032 
                       (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1033 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1034 
  "#"
1035 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1036 
  [(set (reg:CCFPE VFPCC_REGNUM)
1037 
        (compare:CCFPE (match_dup 0)
1038 
                       (match_dup 1)))
1039 
   (set (reg:CCFPE CC_REGNUM)
1040 
        (reg:CCFPE VFPCC_REGNUM))]
1041 
  ""
1042 
)
1043 
 
1044 
(define_insn_and_split "*cmpdf_split_vfp"
1045 
  [(set (reg:CCFP CC_REGNUM)
1046 
        (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w")
1047 
                      (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1048 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1049 
  "#"
1050 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1051 
  [(set (reg:CCFP VFPCC_REGNUM)
1052 
        (compare:CCFP (match_dup 0)
1053 
                       (match_dup 1)))
1054 
   (set (reg:CCFP CC_REGNUM)
1055 
        (reg:CCFP VFPCC_REGNUM))]
1056 
  ""
1057 
)
1058 
 
1059 
(define_insn_and_split "*cmpdf_trap_split_vfp"
1060 
  [(set (reg:CCFPE CC_REGNUM)
1061 
        (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w")
1062 
                       (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1063 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1064 
  "#"
1065 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1066 
  [(set (reg:CCFPE VFPCC_REGNUM)
1067 
        (compare:CCFPE (match_dup 0)
1068 
                       (match_dup 1)))
1069 
   (set (reg:CCFPE CC_REGNUM)
1070 
        (reg:CCFPE VFPCC_REGNUM))]
1071 
  ""
1072 
)
1073 
 
1074 
 
1075 
;; Comparison patterns
1076 
 
1077 
(define_insn "*cmpsf_vfp"
1078 
  [(set (reg:CCFP VFPCC_REGNUM)
1079 
        (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
1080 
                      (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1081 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1082 
  "@
1083 
   fcmps%?\\t%0, %1
1084 
   fcmpzs%?\\t%0"
1085 
  [(set_attr "predicable" "yes")
1086 
   (set_attr "type" "fcmps")]
1087 
)
1088 
 
1089 
(define_insn "*cmpsf_trap_vfp"
1090 
  [(set (reg:CCFPE VFPCC_REGNUM)
1091 
        (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t,t")
1092 
                       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1093 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1094 
  "@
1095 
   fcmpes%?\\t%0, %1
1096 
   fcmpezs%?\\t%0"
1097 
  [(set_attr "predicable" "yes")
1098 
   (set_attr "type" "fcmpd")]
1099 
)
1100 
 
1101 
(define_insn "*cmpdf_vfp"
1102 
  [(set (reg:CCFP VFPCC_REGNUM)
1103 
        (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w,w")
1104 
                      (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1105 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1106 
  "@
1107 
   fcmpd%?\\t%P0, %P1
1108 
   fcmpzd%?\\t%P0"
1109 
  [(set_attr "predicable" "yes")
1110 
   (set_attr "type" "fcmpd")]
1111 
)
1112 
 
1113 
(define_insn "*cmpdf_trap_vfp"
1114 
  [(set (reg:CCFPE VFPCC_REGNUM)
1115 
        (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w,w")
1116 
                       (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1117 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1118 
  "@
1119 
   fcmped%?\\t%P0, %P1
1120 
   fcmpezd%?\\t%P0"
1121 
  [(set_attr "predicable" "yes")
1122 
   (set_attr "type" "fcmpd")]
1123 
)
1124 
 
1125 
 
1126 
;; Store multiple insn used in function prologue.
1127 
 
1128 
(define_insn "*push_multi_vfp"
1129 
  [(match_parallel 2 "multi_register_push"
1130 
    [(set (match_operand:BLK 0 "memory_operand" "=m")
1131 
          (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
1132 
                      UNSPEC_PUSH_MULT))])]
1133 
  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1134 
  "* return vfp_output_fstmd (operands);"
1135 
  [(set_attr "type" "f_stored")]
1136 
)
1137 
 
1138 
 
1139 
;; Unimplemented insns:
1140 
;; fldm*
1141 
;; fstm*
1142 
;; fmdhr et al (VFPv1)
1143 
;; Support for xD (single precision only) variants.
1144 
;; fmrrs, fmsrr

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