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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [cris/] [cris.c] - Blame information for rev 282

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1 282 jeremybenn
/* Definitions for GCC.  Part of the machine description for CRIS.
2
   Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3
   2008, 2009  Free Software Foundation, Inc.
4
   Contributed by Axis Communications.  Written by Hans-Peter Nilsson.
5
 
6
This file is part of GCC.
7
 
8
GCC is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 3, or (at your option)
11
any later version.
12
 
13
GCC is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with GCC; see the file COPYING3.  If not see
20
<http://www.gnu.org/licenses/>.  */
21
 
22
#include "config.h"
23
#include "system.h"
24
#include "coretypes.h"
25
#include "tm.h"
26
#include "rtl.h"
27
#include "regs.h"
28
#include "hard-reg-set.h"
29
#include "real.h"
30
#include "insn-config.h"
31
#include "conditions.h"
32
#include "insn-attr.h"
33
#include "flags.h"
34
#include "tree.h"
35
#include "expr.h"
36
#include "except.h"
37
#include "function.h"
38
#include "toplev.h"
39
#include "recog.h"
40
#include "reload.h"
41
#include "tm_p.h"
42
#include "debug.h"
43
#include "output.h"
44
#include "target.h"
45
#include "target-def.h"
46
#include "ggc.h"
47
#include "optabs.h"
48
#include "df.h"
49
 
50
/* Usable when we have an amount to add or subtract, and want the
51
   optimal size of the insn.  */
52
#define ADDITIVE_SIZE_MODIFIER(size) \
53
 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
54
 
55
#define LOSE_AND_RETURN(msgid, x)                       \
56
  do                                            \
57
    {                                           \
58
      cris_operand_lossage (msgid, x);          \
59
      return;                                   \
60
    } while (0)
61
 
62
enum cris_retinsn_type
63
 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP };
64
 
65
/* Per-function machine data.  */
66
struct GTY(()) machine_function
67
 {
68
   int needs_return_address_on_stack;
69
 
70
   /* This is the number of registers we save in the prologue due to
71
      stdarg.  */
72
   int stdarg_regs;
73
 
74
   enum cris_retinsn_type return_type;
75
 };
76
 
77
/* This little fix suppresses the 'u' or 's' when '%e' in assembly
78
   pattern.  */
79
static char cris_output_insn_is_bound = 0;
80
 
81
/* In code for output macros, this is how we know whether e.g. constant
82
   goes in code or in a static initializer.  */
83
static int in_code = 0;
84
 
85
/* Fix for reg_overlap_mentioned_p.  */
86
static int cris_reg_overlap_mentioned_p (rtx, rtx);
87
 
88
static enum machine_mode cris_promote_function_mode (const_tree, enum machine_mode,
89
                                                     int *, const_tree, int);
90
 
91
static void cris_print_base (rtx, FILE *);
92
 
93
static void cris_print_index (rtx, FILE *);
94
 
95
static void cris_output_addr_const (FILE *, rtx);
96
 
97
static struct machine_function * cris_init_machine_status (void);
98
 
99
static rtx cris_struct_value_rtx (tree, int);
100
 
101
static void cris_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
102
                                         tree type, int *, int);
103
 
104
static int cris_initial_frame_pointer_offset (void);
105
 
106
static int saved_regs_mentioned (rtx);
107
 
108
static void cris_operand_lossage (const char *, rtx);
109
 
110
static int cris_reg_saved_in_regsave_area  (unsigned int, bool);
111
 
112
static void cris_asm_output_mi_thunk
113
  (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
114
 
115
static void cris_file_start (void);
116
static void cris_init_libfuncs (void);
117
 
118
static bool cris_rtx_costs (rtx, int, int, int *, bool);
119
static int cris_address_cost (rtx, bool);
120
static bool cris_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
121
                                    const_tree, bool);
122
static int cris_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
123
                                   tree, bool);
124
static tree cris_md_asm_clobbers (tree, tree, tree);
125
 
126
static bool cris_handle_option (size_t, const char *, int);
127
 
128
static bool cris_frame_pointer_required (void);
129
 
130
static void cris_asm_trampoline_template (FILE *);
131
static void cris_trampoline_init (rtx, tree, rtx);
132
 
133
static rtx cris_function_value(const_tree, const_tree, bool);
134
static rtx cris_libcall_value (enum machine_mode, const_rtx);
135
 
136
/* This is the parsed result of the "-max-stack-stackframe=" option.  If
137
   it (still) is zero, then there was no such option given.  */
138
int cris_max_stackframe = 0;
139
 
140
/* This is the parsed result of the "-march=" option, if given.  */
141
int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION;
142
 
143
#undef TARGET_ASM_ALIGNED_HI_OP
144
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
145
#undef TARGET_ASM_ALIGNED_SI_OP
146
#define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
147
#undef TARGET_ASM_ALIGNED_DI_OP
148
#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
149
 
150
/* We need to define these, since the 2byte, 4byte, 8byte op:s are only
151
   available in ELF.  These "normal" pseudos do not have any alignment
152
   constraints or side-effects.  */
153
#undef TARGET_ASM_UNALIGNED_HI_OP
154
#define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
155
 
156
#undef TARGET_ASM_UNALIGNED_SI_OP
157
#define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
158
 
159
#undef TARGET_ASM_UNALIGNED_DI_OP
160
#define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
161
 
162
#undef TARGET_ASM_OUTPUT_MI_THUNK
163
#define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
164
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
165
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
166
 
167
#undef TARGET_ASM_FILE_START
168
#define TARGET_ASM_FILE_START cris_file_start
169
 
170
#undef TARGET_INIT_LIBFUNCS
171
#define TARGET_INIT_LIBFUNCS cris_init_libfuncs
172
 
173
#undef TARGET_RTX_COSTS
174
#define TARGET_RTX_COSTS cris_rtx_costs
175
#undef TARGET_ADDRESS_COST
176
#define TARGET_ADDRESS_COST cris_address_cost
177
 
178
#undef TARGET_PROMOTE_FUNCTION_MODE
179
#define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
180
 
181
#undef TARGET_STRUCT_VALUE_RTX
182
#define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
183
#undef TARGET_SETUP_INCOMING_VARARGS
184
#define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
185
#undef TARGET_PASS_BY_REFERENCE
186
#define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
187
#undef TARGET_ARG_PARTIAL_BYTES
188
#define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
189
#undef TARGET_MD_ASM_CLOBBERS
190
#define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
191
#undef TARGET_DEFAULT_TARGET_FLAGS
192
#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | CRIS_SUBTARGET_DEFAULT)
193
#undef TARGET_HANDLE_OPTION
194
#define TARGET_HANDLE_OPTION cris_handle_option
195
#undef TARGET_FRAME_POINTER_REQUIRED
196
#define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
197
 
198
#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
199
#define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
200
#undef TARGET_TRAMPOLINE_INIT
201
#define TARGET_TRAMPOLINE_INIT cris_trampoline_init
202
 
203
#undef TARGET_FUNCTION_VALUE
204
#define TARGET_FUNCTION_VALUE cris_function_value
205
#undef TARGET_LIBCALL_VALUE
206
#define TARGET_LIBCALL_VALUE cris_libcall_value
207
 
208
struct gcc_target targetm = TARGET_INITIALIZER;
209
 
210
/* Helper for cris_load_multiple_op and cris_ret_movem_op.  */
211
 
212
bool
213
cris_movem_load_rest_p (rtx op, int offs)
214
{
215
  unsigned int reg_count = XVECLEN (op, 0) - offs;
216
  rtx src_addr;
217
  int i;
218
  rtx elt;
219
  int setno;
220
  int regno_dir = 1;
221
  unsigned int regno = 0;
222
 
223
  /* Perform a quick check so we don't blow up below.  FIXME: Adjust for
224
     other than (MEM reg).  */
225
  if (reg_count <= 1
226
      || GET_CODE (XVECEXP (op, 0, offs)) != SET
227
      || !REG_P (SET_DEST (XVECEXP (op, 0, offs)))
228
      || !MEM_P (SET_SRC (XVECEXP (op, 0, offs))))
229
    return false;
230
 
231
  /* Check a possible post-inc indicator.  */
232
  if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS)
233
    {
234
      rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0);
235
      rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1);
236
 
237
      reg_count--;
238
 
239
      if (reg_count == 1
240
          || !REG_P (reg)
241
          || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1)))
242
          || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1)))
243
          || !CONST_INT_P (inc)
244
          || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4)
245
        return false;
246
      i = offs + 2;
247
    }
248
  else
249
    i = offs + 1;
250
 
251
  if (!TARGET_V32)
252
    {
253
      regno_dir = -1;
254
      regno = reg_count - 1;
255
    }
256
 
257
  elt = XVECEXP (op, 0, offs);
258
  src_addr = XEXP (SET_SRC (elt), 0);
259
 
260
  if (GET_CODE (elt) != SET
261
      || !REG_P (SET_DEST (elt))
262
      || GET_MODE (SET_DEST (elt)) != SImode
263
      || REGNO (SET_DEST (elt)) != regno
264
      || !MEM_P (SET_SRC (elt))
265
      || GET_MODE (SET_SRC (elt)) != SImode
266
      || !memory_address_p (SImode, src_addr))
267
    return false;
268
 
269
  for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
270
    {
271
      rtx elt = XVECEXP (op, 0, i);
272
      regno += regno_dir;
273
 
274
      if (GET_CODE (elt) != SET
275
          || !REG_P (SET_DEST (elt))
276
          || GET_MODE (SET_DEST (elt)) != SImode
277
          || REGNO (SET_DEST (elt)) != regno
278
          || !MEM_P (SET_SRC (elt))
279
          || GET_MODE (SET_SRC (elt)) != SImode
280
          || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
281
          || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
282
          || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
283
          || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4)
284
        return false;
285
    }
286
 
287
  return true;
288
}
289
 
290
/* Worker function for predicate for the parallel contents in a movem
291
   to-memory.  */
292
 
293
bool
294
cris_store_multiple_op_p (rtx op)
295
{
296
  int reg_count = XVECLEN (op, 0);
297
  rtx dest;
298
  rtx dest_addr;
299
  rtx dest_base;
300
  int i;
301
  rtx elt;
302
  int setno;
303
  int regno_dir = 1;
304
  int regno = 0;
305
  int offset = 0;
306
 
307
  /* Perform a quick check so we don't blow up below.  FIXME: Adjust for
308
     other than (MEM reg) and (MEM (PLUS reg const)).  */
309
  if (reg_count <= 1)
310
    return false;
311
 
312
  elt = XVECEXP (op, 0, 0);
313
 
314
  if (GET_CODE (elt) != SET)
315
    return  false;
316
 
317
  dest = SET_DEST (elt);
318
 
319
  if (!REG_P (SET_SRC (elt)) || !MEM_P (dest))
320
    return false;
321
 
322
  dest_addr = XEXP (dest, 0);
323
 
324
  /* Check a possible post-inc indicator.  */
325
  if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS)
326
    {
327
      rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0);
328
      rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1);
329
 
330
      reg_count--;
331
 
332
      if (reg_count == 1
333
          || !REG_P (reg)
334
          || !REG_P (SET_DEST (XVECEXP (op, 0, 1)))
335
          || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1)))
336
          || !CONST_INT_P (inc)
337
          /* Support increment by number of registers, and by the offset
338
             of the destination, if it has the form (MEM (PLUS reg
339
             offset)).  */
340
          || !((REG_P (dest_addr)
341
                && REGNO (dest_addr) == REGNO (reg)
342
                && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4)
343
               || (GET_CODE (dest_addr) == PLUS
344
                   && REG_P (XEXP (dest_addr, 0))
345
                   && REGNO (XEXP (dest_addr, 0)) == REGNO (reg)
346
                   && CONST_INT_P (XEXP (dest_addr, 1))
347
                   && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc))))
348
        return false;
349
 
350
      i = 2;
351
    }
352
  else
353
    i = 1;
354
 
355
  if (!TARGET_V32)
356
    {
357
      regno_dir = -1;
358
      regno = reg_count - 1;
359
    }
360
 
361
  if (GET_CODE (elt) != SET
362
      || !REG_P (SET_SRC (elt))
363
      || GET_MODE (SET_SRC (elt)) != SImode
364
      || REGNO (SET_SRC (elt)) != (unsigned int) regno
365
      || !MEM_P (SET_DEST (elt))
366
      || GET_MODE (SET_DEST (elt)) != SImode)
367
    return false;
368
 
369
  if (REG_P (dest_addr))
370
    {
371
      dest_base = dest_addr;
372
      offset = 0;
373
    }
374
  else if (GET_CODE (dest_addr) == PLUS
375
           && REG_P (XEXP (dest_addr, 0))
376
           && CONST_INT_P (XEXP (dest_addr, 1)))
377
    {
378
      dest_base = XEXP (dest_addr, 0);
379
      offset = INTVAL (XEXP (dest_addr, 1));
380
    }
381
  else
382
    return false;
383
 
384
  for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
385
    {
386
      rtx elt = XVECEXP (op, 0, i);
387
      regno += regno_dir;
388
 
389
      if (GET_CODE (elt) != SET
390
          || !REG_P (SET_SRC (elt))
391
          || GET_MODE (SET_SRC (elt)) != SImode
392
          || REGNO (SET_SRC (elt)) != (unsigned int) regno
393
          || !MEM_P (SET_DEST (elt))
394
          || GET_MODE (SET_DEST (elt)) != SImode
395
          || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
396
          || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base)
397
          || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
398
          || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset)
399
        return false;
400
    }
401
 
402
  return true;
403
}
404
 
405
/* The CONDITIONAL_REGISTER_USAGE worker.  */
406
 
407
void
408
cris_conditional_register_usage (void)
409
{
410
  /* FIXME: This isn't nice.  We should be able to use that register for
411
     something else if the PIC table isn't needed.  */
412
  if (flag_pic)
413
    fixed_regs[PIC_OFFSET_TABLE_REGNUM]
414
      = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
415
 
416
  /* Allow use of ACR (PC in pre-V32) and tweak order.  */
417
  if (TARGET_V32)
418
    {
419
      static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32;
420
      unsigned int i;
421
 
422
      fixed_regs[CRIS_ACR_REGNUM] = 0;
423
 
424
      for (i = 0;
425
          i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]);
426
          i++)
427
       reg_alloc_order[i] = reg_alloc_order_v32[i];
428
    }
429
 
430
  if (TARGET_HAS_MUL_INSNS)
431
    fixed_regs[CRIS_MOF_REGNUM] = 0;
432
 
433
  /* On early versions, we must use the 16-bit condition-code register,
434
     which has another name.  */
435
  if (cris_cpu_version < 8)
436
    reg_names[CRIS_CC0_REGNUM] = "ccr";
437
}
438
 
439
/* Return crtl->uses_pic_offset_table.  For use in cris.md,
440
   since some generated files do not include function.h.  */
441
 
442
int
443
cris_cfun_uses_pic_table (void)
444
{
445
  return crtl->uses_pic_offset_table;
446
}
447
 
448
/* Given an rtx, return the text string corresponding to the CODE of X.
449
   Intended for use in the assembly language output section of a
450
   define_insn.  */
451
 
452
const char *
453
cris_op_str (rtx x)
454
{
455
  cris_output_insn_is_bound = 0;
456
  switch (GET_CODE (x))
457
    {
458
    case PLUS:
459
      return "add";
460
      break;
461
 
462
    case MINUS:
463
      return "sub";
464
      break;
465
 
466
    case MULT:
467
      /* This function is for retrieving a part of an instruction name for
468
         an operator, for immediate output.  If that ever happens for
469
         MULT, we need to apply TARGET_MUL_BUG in the caller.  Make sure
470
         we notice.  */
471
      internal_error ("MULT case in cris_op_str");
472
      break;
473
 
474
    case DIV:
475
      return "div";
476
      break;
477
 
478
    case AND:
479
      return "and";
480
      break;
481
 
482
    case IOR:
483
      return "or";
484
      break;
485
 
486
    case XOR:
487
      return "xor";
488
      break;
489
 
490
    case NOT:
491
      return "not";
492
      break;
493
 
494
    case ASHIFT:
495
      return "lsl";
496
      break;
497
 
498
    case LSHIFTRT:
499
      return "lsr";
500
      break;
501
 
502
    case ASHIFTRT:
503
      return "asr";
504
      break;
505
 
506
    case UMIN:
507
      /* Used to control the sign/zero-extend character for the 'E' modifier.
508
         BOUND has none.  */
509
      cris_output_insn_is_bound = 1;
510
      return "bound";
511
      break;
512
 
513
    default:
514
      return "Unknown operator";
515
      break;
516
  }
517
}
518
 
519
/* Emit an error message when we're in an asm, and a fatal error for
520
   "normal" insns.  Formatted output isn't easily implemented, since we
521
   use output_operand_lossage to output the actual message and handle the
522
   categorization of the error.  */
523
 
524
static void
525
cris_operand_lossage (const char *msgid, rtx op)
526
{
527
  debug_rtx (op);
528
  output_operand_lossage ("%s", msgid);
529
}
530
 
531
/* Print an index part of an address to file.  */
532
 
533
static void
534
cris_print_index (rtx index, FILE *file)
535
{
536
  /* Make the index "additive" unless we'll output a negative number, in
537
     which case the sign character is free (as in free beer).  */
538
  if (!CONST_INT_P (index) || INTVAL (index) >= 0)
539
    putc ('+', file);
540
 
541
  if (REG_P (index))
542
    fprintf (file, "$%s.b", reg_names[REGNO (index)]);
543
  else if (CONSTANT_P (index))
544
    cris_output_addr_const (file, index);
545
  else if (GET_CODE (index) == MULT)
546
    {
547
      fprintf (file, "$%s.",
548
               reg_names[REGNO (XEXP (index, 0))]);
549
 
550
      putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file);
551
    }
552
  else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0)))
553
    {
554
      rtx inner = XEXP (index, 0);
555
      rtx inner_inner = XEXP (inner, 0);
556
 
557
      if (GET_CODE (inner_inner) == POST_INC)
558
        {
559
          fprintf (file, "[$%s+].",
560
                   reg_names[REGNO (XEXP (inner_inner, 0))]);
561
          putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
562
        }
563
      else
564
        {
565
          fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]);
566
 
567
          putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
568
        }
569
    }
570
  else if (MEM_P (index))
571
    {
572
      rtx inner = XEXP (index, 0);
573
      if (GET_CODE (inner) == POST_INC)
574
        fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]);
575
      else
576
        fprintf (file, "[$%s].d", reg_names[REGNO (inner)]);
577
    }
578
  else
579
    cris_operand_lossage ("unexpected index-type in cris_print_index",
580
                          index);
581
}
582
 
583
/* Print a base rtx of an address to file.  */
584
 
585
static void
586
cris_print_base (rtx base, FILE *file)
587
{
588
  if (REG_P (base))
589
    fprintf (file, "$%s", reg_names[REGNO (base)]);
590
  else if (GET_CODE (base) == POST_INC)
591
    {
592
      gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM);
593
      fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]);
594
    }
595
  else
596
    cris_operand_lossage ("unexpected base-type in cris_print_base",
597
                          base);
598
}
599
 
600
/* Usable as a guard in expressions.  */
601
 
602
int
603
cris_fatal (char *arg)
604
{
605
  internal_error (arg);
606
 
607
  /* We'll never get here; this is just to appease compilers.  */
608
  return 0;
609
}
610
 
611
/* Return nonzero if REGNO is an ordinary register that *needs* to be
612
   saved together with other registers, possibly by a MOVEM instruction,
613
   or is saved for target-independent reasons.  There may be
614
   target-dependent reasons to save the register anyway; this is just a
615
   wrapper for a complicated conditional.  */
616
 
617
static int
618
cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used)
619
{
620
  return
621
    (((df_regs_ever_live_p (regno)
622
       && !call_used_regs[regno])
623
      || (regno == PIC_OFFSET_TABLE_REGNUM
624
          && (got_really_used
625
              /* It is saved anyway, if there would be a gap.  */
626
              || (flag_pic
627
                  && df_regs_ever_live_p (regno + 1)
628
                  && !call_used_regs[regno + 1]))))
629
     && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed)
630
     && regno != CRIS_SRP_REGNUM)
631
    || (crtl->calls_eh_return
632
        && (regno == EH_RETURN_DATA_REGNO (0)
633
            || regno == EH_RETURN_DATA_REGNO (1)
634
            || regno == EH_RETURN_DATA_REGNO (2)
635
            || regno == EH_RETURN_DATA_REGNO (3)));
636
}
637
 
638
/* Return nonzero if there are regs mentioned in the insn that are not all
639
   in the call_used regs.  This is part of the decision whether an insn
640
   can be put in the epilogue.  */
641
 
642
static int
643
saved_regs_mentioned (rtx x)
644
{
645
  int i;
646
  const char *fmt;
647
  RTX_CODE code;
648
 
649
  /* Mainly stolen from refers_to_regno_p in rtlanal.c.  */
650
 
651
  code = GET_CODE (x);
652
 
653
  switch (code)
654
    {
655
    case REG:
656
      i = REGNO (x);
657
      return !call_used_regs[i];
658
 
659
    case SUBREG:
660
      /* If this is a SUBREG of a hard reg, we can see exactly which
661
         registers are being modified.  Otherwise, handle normally.  */
662
      i = REGNO (SUBREG_REG (x));
663
      return !call_used_regs[i];
664
 
665
    default:
666
      ;
667
    }
668
 
669
  fmt = GET_RTX_FORMAT (code);
670
  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
671
    {
672
      if (fmt[i] == 'e')
673
        {
674
          if (saved_regs_mentioned (XEXP (x, i)))
675
            return 1;
676
        }
677
      else if (fmt[i] == 'E')
678
        {
679
          int j;
680
          for (j = XVECLEN (x, i) - 1; j >=0; j--)
681
            if (saved_regs_mentioned (XEXP (x, i)))
682
              return 1;
683
        }
684
    }
685
 
686
  return 0;
687
}
688
 
689
/* The PRINT_OPERAND worker.  */
690
 
691
void
692
cris_print_operand (FILE *file, rtx x, int code)
693
{
694
  rtx operand = x;
695
 
696
  /* Size-strings corresponding to MULT expressions.  */
697
  static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
698
 
699
  /* New code entries should just be added to the switch below.  If
700
     handling is finished, just return.  If handling was just a
701
     modification of the operand, the modified operand should be put in
702
     "operand", and then do a break to let default handling
703
     (zero-modifier) output the operand.  */
704
 
705
  switch (code)
706
    {
707
    case 'b':
708
      /* Print the unsigned supplied integer as if it were signed
709
         and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc.  */
710
      if (!CONST_INT_P (x)
711
          || !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (x), 'O'))
712
        LOSE_AND_RETURN ("invalid operand for 'b' modifier", x);
713
      fprintf (file, HOST_WIDE_INT_PRINT_DEC,
714
               INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535));
715
      return;
716
 
717
    case 'x':
718
      /* Print assembler code for operator.  */
719
      fprintf (file, "%s", cris_op_str (operand));
720
      return;
721
 
722
    case 'o':
723
      {
724
        /* A movem modifier working on a parallel; output the register
725
           name.  */
726
        int regno;
727
 
728
        if (GET_CODE (x) != PARALLEL)
729
          LOSE_AND_RETURN ("invalid operand for 'o' modifier", x);
730
 
731
        /* The second item can be (set reg (plus reg const)) to denote a
732
           postincrement.  */
733
        regno
734
          = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS
735
             ? XVECLEN (x, 0) - 2
736
             : XVECLEN (x, 0) - 1);
737
 
738
        fprintf (file, "$%s", reg_names [regno]);
739
      }
740
      return;
741
 
742
    case 'O':
743
      {
744
        /* A similar movem modifier; output the memory operand.  */
745
        rtx addr;
746
 
747
        if (GET_CODE (x) != PARALLEL)
748
          LOSE_AND_RETURN ("invalid operand for 'O' modifier", x);
749
 
750
        /* The lowest mem operand is in the first item, but perhaps it
751
           needs to be output as postincremented.  */
752
        addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0)))
753
          ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0)
754
          : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0);
755
 
756
        /* The second item can be a (set reg (plus reg const)) to denote
757
           a modification.  */
758
        if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS)
759
          {
760
            /* It's a post-increment, if the address is a naked (reg).  */
761
            if (REG_P (addr))
762
              addr = gen_rtx_POST_INC (SImode, addr);
763
            else
764
              {
765
                /* Otherwise, it's a side-effect; RN=RN+M.  */
766
                fprintf (file, "[$%s=$%s%s%d]",
767
                         reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))],
768
                         reg_names [REGNO (XEXP (addr, 0))],
769
                         INTVAL (XEXP (addr, 1)) < 0 ? "" : "+",
770
                         (int) INTVAL (XEXP (addr, 1)));
771
                return;
772
              }
773
          }
774
        output_address (addr);
775
      }
776
      return;
777
 
778
    case 'p':
779
      /* Adjust a power of two to its log2.  */
780
      if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 )
781
        LOSE_AND_RETURN ("invalid operand for 'p' modifier", x);
782
      fprintf (file, "%d", exact_log2 (INTVAL (x)));
783
      return;
784
 
785
    case 's':
786
      /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
787
         respectively.  This modifier also terminates the inhibiting
788
         effects of the 'x' modifier.  */
789
      cris_output_insn_is_bound = 0;
790
      if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
791
        {
792
          if (INTVAL (x) >= 0)
793
            {
794
              if (INTVAL (x) <= 255)
795
                putc ('b', file);
796
              else if (INTVAL (x) <= 65535)
797
                putc ('w', file);
798
              else
799
                putc ('d', file);
800
            }
801
          else
802
            putc ('d', file);
803
          return;
804
        }
805
 
806
      /* For a non-integer, print the size of the operand.  */
807
      putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode)
808
            ? 'd' : GET_MODE (x) == HImode ? 'w'
809
            : GET_MODE (x) == QImode ? 'b'
810
            /* If none of the above, emit an erroneous size letter.  */
811
            : 'X',
812
            file);
813
      return;
814
 
815
    case 'z':
816
      /* Const_int: print b for -127 <= x <= 255,
817
         w for -32768 <= x <= 65535, else die.  */
818
      if (!CONST_INT_P (x)
819
          || INTVAL (x) < -32768 || INTVAL (x) > 65535)
820
        LOSE_AND_RETURN ("invalid operand for 'z' modifier", x);
821
      putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file);
822
      return;
823
 
824
    case 'Z':
825
      /* If this is a GOT-symbol, print the size-letter corresponding to
826
         -fpic/-fPIC.  For everything else, print "d".  */
827
      putc ((flag_pic == 1
828
             && GET_CODE (x) == CONST
829
             && GET_CODE (XEXP (x, 0)) == UNSPEC
830
             && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD)
831
            ? 'w' : 'd', file);
832
      return;
833
 
834
    case '#':
835
      /* Output a 'nop' if there's nothing for the delay slot.
836
         This method stolen from the sparc files.  */
837
      if (dbr_sequence_length () == 0)
838
        fputs ("\n\tnop", file);
839
      return;
840
 
841
    case '!':
842
      /* Output directive for alignment padded with "nop" insns.
843
         Optimizing for size, it's plain 4-byte alignment, otherwise we
844
         align the section to a cache-line (32 bytes) and skip at max 2
845
         bytes, i.e. we skip if it's the last insn on a cache-line.  The
846
         latter is faster by a small amount (for two test-programs 99.6%
847
         and 99.9%) and larger by a small amount (ditto 100.1% and
848
         100.2%).  This is supposed to be the simplest yet performance-
849
         wise least intrusive way to make sure the immediately following
850
         (supposed) muls/mulu insn isn't located at the end of a
851
         cache-line.  */
852
      if (TARGET_MUL_BUG)
853
        fputs (optimize_size
854
               ? ".p2alignw 2,0x050f\n\t"
855
               : ".p2alignw 5,0x050f,2\n\t", file);
856
      return;
857
 
858
    case ':':
859
      /* The PIC register.  */
860
      if (! flag_pic)
861
        internal_error ("invalid use of ':' modifier");
862
      fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]);
863
      return;
864
 
865
    case 'H':
866
      /* Print high (most significant) part of something.  */
867
      switch (GET_CODE (operand))
868
        {
869
        case CONST_INT:
870
          /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
871
             value is kept here, and so may be other than 0 or -1.  */
872
          fprintf (file, HOST_WIDE_INT_PRINT_DEC,
873
                   INTVAL (operand_subword (operand, 1, 0, DImode)));
874
          return;
875
 
876
        case CONST_DOUBLE:
877
          /* High part of a long long constant.  */
878
          if (GET_MODE (operand) == VOIDmode)
879
            {
880
              fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x));
881
              return;
882
            }
883
          else
884
            LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
885
 
886
        case REG:
887
          /* Print reg + 1.  Check that there's not an attempt to print
888
             high-parts of registers like stack-pointer or higher, except
889
             for SRP (where the "high part" is MOF).  */
890
          if (REGNO (operand) > STACK_POINTER_REGNUM - 2
891
              && (REGNO (operand) != CRIS_SRP_REGNUM
892
                  || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM
893
                  || fixed_regs[CRIS_MOF_REGNUM] != 0))
894
            LOSE_AND_RETURN ("bad register", operand);
895
          fprintf (file, "$%s", reg_names[REGNO (operand) + 1]);
896
          return;
897
 
898
        case MEM:
899
          /* Adjust memory address to high part.  */
900
          {
901
            rtx adj_mem = operand;
902
            int size
903
              = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT;
904
 
905
            /* Adjust so we can use two SImode in DImode.
906
               Calling adj_offsettable_operand will make sure it is an
907
               offsettable address.  Don't do this for a postincrement
908
               though; it should remain as it was.  */
909
            if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC)
910
              adj_mem
911
                = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2);
912
 
913
            output_address (XEXP (adj_mem, 0));
914
            return;
915
          }
916
 
917
        default:
918
          LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
919
        }
920
 
921
    case 'L':
922
      /* Strip the MEM expression.  */
923
      operand = XEXP (operand, 0);
924
      break;
925
 
926
    case 'e':
927
      /* Like 'E', but ignore state set by 'x'.  FIXME: Use code
928
         iterators and attributes in cris.md to avoid the need for %x
929
         and %E (and %e) and state passed between those modifiers.  */
930
      cris_output_insn_is_bound = 0;
931
      /* FALL THROUGH.  */
932
    case 'E':
933
      /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
934
         cris_output_insn_is_bound is nonzero.  */
935
      if (GET_CODE (operand) != SIGN_EXTEND
936
          && GET_CODE (operand) != ZERO_EXTEND
937
          && !CONST_INT_P (operand))
938
        LOSE_AND_RETURN ("invalid operand for 'e' modifier", x);
939
 
940
      if (cris_output_insn_is_bound)
941
        {
942
          cris_output_insn_is_bound = 0;
943
          return;
944
        }
945
 
946
      putc (GET_CODE (operand) == SIGN_EXTEND
947
            || (CONST_INT_P (operand) && INTVAL (operand) < 0)
948
            ? 's' : 'u', file);
949
      return;
950
 
951
    case 'm':
952
      /* Print the size letter of the inner element.  We can do it by
953
         calling ourselves with the 's' modifier.  */
954
      if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
955
        LOSE_AND_RETURN ("invalid operand for 'm' modifier", x);
956
      cris_print_operand (file, XEXP (operand, 0), 's');
957
      return;
958
 
959
    case 'M':
960
      /* Print the least significant part of operand.  */
961
      if (GET_CODE (operand) == CONST_DOUBLE)
962
        {
963
          fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
964
          return;
965
        }
966
      else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand))
967
        {
968
          fprintf (file, HOST_WIDE_INT_PRINT_HEX,
969
                   INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1));
970
          return;
971
        }
972
      /* Otherwise the least significant part equals the normal part,
973
         so handle it normally.  */
974
      break;
975
 
976
    case 'A':
977
      /* When emitting an add for the high part of a DImode constant, we
978
         want to use addq for 0 and adds.w for -1.  */
979
      if (!CONST_INT_P (operand))
980
        LOSE_AND_RETURN ("invalid operand for 'A' modifier", x);
981
      fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq");
982
      return;
983
 
984
    case 'd':
985
      /* If this is a GOT symbol, force it to be emitted as :GOT and
986
         :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
987
         Avoid making this too much of a special case.  */
988
      if (flag_pic == 1 && CONSTANT_P (operand))
989
        {
990
          int flag_pic_save = flag_pic;
991
 
992
          flag_pic = 2;
993
          cris_output_addr_const (file, operand);
994
          flag_pic = flag_pic_save;
995
          return;
996
        }
997
      break;
998
 
999
    case 'D':
1000
      /* When emitting an sub for the high part of a DImode constant, we
1001
         want to use subq for 0 and subs.w for -1.  */
1002
      if (!CONST_INT_P (operand))
1003
        LOSE_AND_RETURN ("invalid operand for 'D' modifier", x);
1004
      fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq");
1005
      return;
1006
 
1007
    case 'S':
1008
      /* Print the operand as the index-part of an address.
1009
         Easiest way out is to use cris_print_index.  */
1010
      cris_print_index (operand, file);
1011
      return;
1012
 
1013
    case 'T':
1014
      /* Print the size letter for an operand to a MULT, which must be a
1015
         const_int with a suitable value.  */
1016
      if (!CONST_INT_P (operand) || INTVAL (operand) > 4)
1017
        LOSE_AND_RETURN ("invalid operand for 'T' modifier", x);
1018
      fprintf (file, "%s", mults[INTVAL (operand)]);
1019
      return;
1020
 
1021
    case 'u':
1022
      /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d".  */
1023
      if (flag_pic == 1
1024
          && GET_CODE (operand) == CONST
1025
          && GET_CODE (XEXP (operand, 0)) == UNSPEC
1026
          && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD)
1027
        fprintf (file, "u.w");
1028
      else
1029
        fprintf (file, ".d");
1030
      return;
1031
 
1032
    case 0:
1033
      /* No code, print as usual.  */
1034
      break;
1035
 
1036
    default:
1037
      LOSE_AND_RETURN ("invalid operand modifier letter", x);
1038
    }
1039
 
1040
  /* Print an operand as without a modifier letter.  */
1041
  switch (GET_CODE (operand))
1042
    {
1043
    case REG:
1044
      if (REGNO (operand) > 15
1045
          && REGNO (operand) != CRIS_MOF_REGNUM
1046
          && REGNO (operand) != CRIS_SRP_REGNUM
1047
          && REGNO (operand) != CRIS_CC0_REGNUM)
1048
        internal_error ("internal error: bad register: %d", REGNO (operand));
1049
      fprintf (file, "$%s", reg_names[REGNO (operand)]);
1050
      return;
1051
 
1052
    case MEM:
1053
      output_address (XEXP (operand, 0));
1054
      return;
1055
 
1056
    case CONST_DOUBLE:
1057
      if (GET_MODE (operand) == VOIDmode)
1058
        /* A long long constant.  */
1059
        output_addr_const (file, operand);
1060
      else
1061
        {
1062
          /* Only single precision is allowed as plain operands the
1063
             moment.  FIXME:  REAL_VALUE_FROM_CONST_DOUBLE isn't
1064
             documented.  */
1065
          REAL_VALUE_TYPE r;
1066
          long l;
1067
 
1068
          /* FIXME:  Perhaps check overflow of the "single".  */
1069
          REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
1070
          REAL_VALUE_TO_TARGET_SINGLE (r, l);
1071
 
1072
          fprintf (file, "0x%lx", l);
1073
        }
1074
      return;
1075
 
1076
    case UNSPEC:
1077
      /* Fall through.  */
1078
    case CONST:
1079
      cris_output_addr_const (file, operand);
1080
      return;
1081
 
1082
    case MULT:
1083
    case ASHIFT:
1084
      {
1085
        /* For a (MULT (reg X) const_int) we output "rX.S".  */
1086
        int i = CONST_INT_P (XEXP (operand, 1))
1087
          ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0));
1088
        rtx reg = CONST_INT_P (XEXP (operand, 1))
1089
          ? XEXP (operand, 0) : XEXP (operand, 1);
1090
 
1091
        if (!REG_P (reg)
1092
            || (!CONST_INT_P (XEXP (operand, 0))
1093
                && !CONST_INT_P (XEXP (operand, 1))))
1094
          LOSE_AND_RETURN ("unexpected multiplicative operand", x);
1095
 
1096
        cris_print_base (reg, file);
1097
        fprintf (file, ".%c",
1098
                 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b'
1099
                 : i == 4 ? 'd'
1100
                 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w'
1101
                 : 'd');
1102
        return;
1103
      }
1104
 
1105
    default:
1106
      /* No need to handle all strange variants, let output_addr_const
1107
         do it for us.  */
1108
      if (CONSTANT_P (operand))
1109
        {
1110
          cris_output_addr_const (file, operand);
1111
          return;
1112
        }
1113
 
1114
      LOSE_AND_RETURN ("unexpected operand", x);
1115
    }
1116
}
1117
 
1118
/* The PRINT_OPERAND_ADDRESS worker.  */
1119
 
1120
void
1121
cris_print_operand_address (FILE *file, rtx x)
1122
{
1123
  /* All these were inside MEM:s so output indirection characters.  */
1124
  putc ('[', file);
1125
 
1126
  if (CONSTANT_ADDRESS_P (x))
1127
    cris_output_addr_const (file, x);
1128
  else if (BASE_OR_AUTOINCR_P (x))
1129
    cris_print_base (x, file);
1130
  else if (GET_CODE (x) == PLUS)
1131
    {
1132
      rtx x1, x2;
1133
 
1134
      x1 = XEXP (x, 0);
1135
      x2 = XEXP (x, 1);
1136
      if (BASE_P (x1))
1137
        {
1138
          cris_print_base (x1, file);
1139
          cris_print_index (x2, file);
1140
        }
1141
      else if (BASE_P (x2))
1142
        {
1143
          cris_print_base (x2, file);
1144
          cris_print_index (x1, file);
1145
        }
1146
      else
1147
        LOSE_AND_RETURN ("unrecognized address", x);
1148
    }
1149
  else if (MEM_P (x))
1150
    {
1151
      /* A DIP.  Output more indirection characters.  */
1152
      putc ('[', file);
1153
      cris_print_base (XEXP (x, 0), file);
1154
      putc (']', file);
1155
    }
1156
  else
1157
    LOSE_AND_RETURN ("unrecognized address", x);
1158
 
1159
  putc (']', file);
1160
}
1161
 
1162
/* The RETURN_ADDR_RTX worker.
1163
   We mark that the return address is used, either by EH or
1164
   __builtin_return_address, for use by the function prologue and
1165
   epilogue.  FIXME: This isn't optimal; we just use the mark in the
1166
   prologue and epilogue to say that the return address is to be stored
1167
   in the stack frame.  We could return SRP for leaf-functions and use the
1168
   initial-value machinery.  */
1169
 
1170
rtx
1171
cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED)
1172
{
1173
  cfun->machine->needs_return_address_on_stack = 1;
1174
 
1175
  /* The return-address is stored just above the saved frame-pointer (if
1176
     present).  Apparently we can't eliminate from the frame-pointer in
1177
     that direction, so use the incoming args (maybe pretended) pointer.  */
1178
  return count == 0
1179
    ? gen_rtx_MEM (Pmode, plus_constant (virtual_incoming_args_rtx, -4))
1180
    : NULL_RTX;
1181
}
1182
 
1183
/* Accessor used in cris.md:return because cfun->machine isn't available
1184
   there.  */
1185
 
1186
bool
1187
cris_return_address_on_stack (void)
1188
{
1189
  return df_regs_ever_live_p (CRIS_SRP_REGNUM)
1190
    || cfun->machine->needs_return_address_on_stack;
1191
}
1192
 
1193
/* Accessor used in cris.md:return because cfun->machine isn't available
1194
   there.  */
1195
 
1196
bool
1197
cris_return_address_on_stack_for_return (void)
1198
{
1199
  return cfun->machine->return_type == CRIS_RETINSN_RET ? false
1200
    : cris_return_address_on_stack ();
1201
}
1202
 
1203
/* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1204
   handles FP -> SP elimination offset.  */
1205
 
1206
static int
1207
cris_initial_frame_pointer_offset (void)
1208
{
1209
  int regno;
1210
 
1211
  /* Initial offset is 0 if we don't have a frame pointer.  */
1212
  int offs = 0;
1213
  bool got_really_used = false;
1214
 
1215
  if (crtl->uses_pic_offset_table)
1216
    {
1217
      push_topmost_sequence ();
1218
      got_really_used
1219
        = reg_used_between_p (pic_offset_table_rtx, get_insns (),
1220
                              NULL_RTX);
1221
      pop_topmost_sequence ();
1222
    }
1223
 
1224
  /* And 4 for each register pushed.  */
1225
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1226
    if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1227
      offs += 4;
1228
 
1229
  /* And then, last, we add the locals allocated.  */
1230
  offs += get_frame_size ();
1231
 
1232
  /* And more; the accumulated args size.  */
1233
  offs += crtl->outgoing_args_size;
1234
 
1235
  /* Then round it off, in case we use aligned stack.  */
1236
  if (TARGET_STACK_ALIGN)
1237
    offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1;
1238
 
1239
  return offs;
1240
}
1241
 
1242
/* The INITIAL_ELIMINATION_OFFSET worker.
1243
   Calculate the difference between imaginary registers such as frame
1244
   pointer and the stack pointer.  Used to eliminate the frame pointer
1245
   and imaginary arg pointer.  */
1246
 
1247
int
1248
cris_initial_elimination_offset (int fromreg, int toreg)
1249
{
1250
  int fp_sp_offset
1251
    = cris_initial_frame_pointer_offset ();
1252
 
1253
  /* We should be able to use regs_ever_live and related prologue
1254
     information here, or alpha should not as well.  */
1255
  bool return_address_on_stack = cris_return_address_on_stack ();
1256
 
1257
  /* Here we act as if the frame-pointer were needed.  */
1258
  int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0);
1259
 
1260
  if (fromreg == ARG_POINTER_REGNUM
1261
      && toreg == FRAME_POINTER_REGNUM)
1262
    return ap_fp_offset;
1263
 
1264
  /* Between the frame pointer and the stack are only "normal" stack
1265
     variables and saved registers.  */
1266
  if (fromreg == FRAME_POINTER_REGNUM
1267
      && toreg == STACK_POINTER_REGNUM)
1268
    return fp_sp_offset;
1269
 
1270
  /* We need to balance out the frame pointer here.  */
1271
  if (fromreg == ARG_POINTER_REGNUM
1272
      && toreg == STACK_POINTER_REGNUM)
1273
    return ap_fp_offset + fp_sp_offset - 4;
1274
 
1275
  gcc_unreachable ();
1276
}
1277
 
1278
/* Worker function for LEGITIMIZE_RELOAD_ADDRESS.  */
1279
 
1280
bool
1281
cris_reload_address_legitimized (rtx x,
1282
                                 enum machine_mode mode ATTRIBUTE_UNUSED,
1283
                                 int opnum ATTRIBUTE_UNUSED,
1284
                                 int itype,
1285
                                 int ind_levels ATTRIBUTE_UNUSED)
1286
{
1287
  enum reload_type type = itype;
1288
  rtx op0, op1;
1289
  rtx *op0p;
1290
  rtx *op1p;
1291
 
1292
  if (GET_CODE (x) != PLUS)
1293
    return false;
1294
 
1295
  if (TARGET_V32)
1296
    return false;
1297
 
1298
  op0 = XEXP (x, 0);
1299
  op0p = &XEXP (x, 0);
1300
  op1 = XEXP (x, 1);
1301
  op1p = &XEXP (x, 1);
1302
 
1303
  if (!REG_P (op1))
1304
    return false;
1305
 
1306
  if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0)))
1307
    {
1308
      rtx op00 = XEXP (op0, 0);
1309
      rtx op000 = XEXP (op00, 0);
1310
      rtx *op000p = &XEXP (op00, 0);
1311
 
1312
      if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode)
1313
          && (REG_P (op000)
1314
              || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0)))))
1315
        {
1316
          bool something_reloaded = false;
1317
 
1318
          if (GET_CODE (op000) == POST_INC
1319
              && REG_P (XEXP (op000, 0))
1320
              && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER)
1321
            /* No, this gets too complicated and is too rare to care
1322
               about trying to improve on the general code Here.
1323
               As the return-value is an all-or-nothing indicator, we
1324
               punt on the other register too.  */
1325
            return false;
1326
 
1327
          if ((REG_P (op000)
1328
               && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER))
1329
            {
1330
              /* The address of the inner mem is a pseudo or wrong
1331
                 reg: reload that.  */
1332
              push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS,
1333
                           GET_MODE (x), VOIDmode, 0, 0, opnum, type);
1334
              something_reloaded = true;
1335
            }
1336
 
1337
          if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER)
1338
            {
1339
              /* Base register is a pseudo or wrong reg: reload it.  */
1340
              push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS,
1341
                           GET_MODE (x), VOIDmode, 0, 0,
1342
                           opnum, type);
1343
              something_reloaded = true;
1344
            }
1345
 
1346
          gcc_assert (something_reloaded);
1347
 
1348
          return true;
1349
        }
1350
    }
1351
 
1352
  return false;
1353
}
1354
 
1355
/* Worker function for REGISTER_MOVE_COST.  */
1356
 
1357
int
1358
cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1359
                         enum reg_class from, enum reg_class to)
1360
{
1361
  if (!TARGET_V32)
1362
    {
1363
      /* Pretend that classes that we don't support are ALL_REGS, so
1364
         we give them the highest cost.  */
1365
      if (from != SPECIAL_REGS && from != MOF_REGS
1366
          && from != GENERAL_REGS && from != GENNONACR_REGS)
1367
        from = ALL_REGS;
1368
 
1369
      if (to != SPECIAL_REGS && to != MOF_REGS
1370
          && to != GENERAL_REGS && to != GENNONACR_REGS)
1371
        to = ALL_REGS;
1372
    }
1373
 
1374
  /* Can't move to and from a SPECIAL_REGS register, so we have to say
1375
     their move cost within that class is higher.  How about 7?  That's 3
1376
     for a move to a GENERAL_REGS register, 3 for the move from the
1377
     GENERAL_REGS register, and 1 for the increased register pressure.
1378
     Also, it's higher than the memory move cost, which is in order.
1379
     We also do this for ALL_REGS, since we don't want that class to be
1380
     preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1381
     Whenever it's about to be used, it's for SPECIAL_REGS.  If we don't
1382
     present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1383
     used when a GENERAL_REGS should be used, even if there are call-saved
1384
     GENERAL_REGS left to allocate.  This is because the fall-back when
1385
     the most preferred register class isn't available, isn't the next
1386
     (or next good) wider register class, but the *most widest* register
1387
     class.  */
1388
 
1389
  if ((reg_classes_intersect_p (from, SPECIAL_REGS)
1390
       && reg_classes_intersect_p (to, SPECIAL_REGS))
1391
      || from == ALL_REGS || to == ALL_REGS)
1392
    return 7;
1393
 
1394
  if (reg_classes_intersect_p (from, SPECIAL_REGS)
1395
      || reg_classes_intersect_p (to, SPECIAL_REGS))
1396
    return 3;
1397
 
1398
  return 2;
1399
}
1400
 
1401
/* Worker for cris_notice_update_cc; handles the "normal" cases.
1402
   FIXME: this code is historical; its functionality should be
1403
   refactored to look at insn attributes and moved to
1404
   cris_notice_update_cc.  Except, we better lose cc0 entirely.  */
1405
 
1406
static void
1407
cris_normal_notice_update_cc (rtx exp, rtx insn)
1408
{
1409
  /* "Normal" means, for:
1410
     (set (cc0) (...)):
1411
     CC is (...).
1412
 
1413
     (set (reg) (...)):
1414
     CC is (reg) and (...) - unless (...) is 0 or reg is a special
1415
        register or (v32 and (...) is -32..-1), then CC does not change.
1416
     CC_NO_OVERFLOW unless (...) is reg or mem.
1417
 
1418
     (set (mem) (...)):
1419
     CC does not change.
1420
 
1421
     (set (pc) (...)):
1422
     CC does not change.
1423
 
1424
     (parallel
1425
      (set (reg1) (mem (bdap/biap)))
1426
      (set (reg2) (bdap/biap))):
1427
     CC is (reg1) and (mem (reg2))
1428
 
1429
     (parallel
1430
      (set (mem (bdap/biap)) (reg1)) [or 0]
1431
      (set (reg2) (bdap/biap))):
1432
     CC does not change.
1433
 
1434
     (where reg and mem includes strict_low_parts variants thereof)
1435
 
1436
     For all others, assume CC is clobbered.
1437
     Note that we do not have to care about setting CC_NO_OVERFLOW,
1438
     since the overflow flag is set to 0 (i.e. right) for
1439
     instructions where it does not have any sane sense, but where
1440
     other flags have meanings.  (This includes shifts; the carry is
1441
     not set by them).
1442
 
1443
     Note that there are other parallel constructs we could match,
1444
     but we don't do that yet.  */
1445
 
1446
  if (GET_CODE (exp) == SET)
1447
    {
1448
      /* FIXME: Check when this happens.  It looks like we should
1449
         actually do a CC_STATUS_INIT here to be safe.  */
1450
      if (SET_DEST (exp) == pc_rtx)
1451
        return;
1452
 
1453
      /* Record CC0 changes, so we do not have to output multiple
1454
         test insns.  */
1455
      if (SET_DEST (exp) == cc0_rtx)
1456
        {
1457
          CC_STATUS_INIT;
1458
 
1459
          if (GET_CODE (SET_SRC (exp)) == COMPARE
1460
              && XEXP (SET_SRC (exp), 1) == const0_rtx)
1461
            cc_status.value1 = XEXP (SET_SRC (exp), 0);
1462
          else
1463
            cc_status.value1 = SET_SRC (exp);
1464
 
1465
          /* Handle flags for the special btstq on one bit.  */
1466
          if (GET_CODE (cc_status.value1) == ZERO_EXTRACT
1467
              && XEXP (cc_status.value1, 1) == const1_rtx)
1468
            {
1469
              if (CONST_INT_P (XEXP (cc_status.value1, 0)))
1470
                /* Using cmpq.  */
1471
                cc_status.flags = CC_INVERTED;
1472
              else
1473
                /* A one-bit btstq.  */
1474
                cc_status.flags = CC_Z_IN_NOT_N;
1475
            }
1476
 
1477
          else if (GET_CODE (SET_SRC (exp)) == COMPARE)
1478
            {
1479
              if (!REG_P (XEXP (SET_SRC (exp), 0))
1480
                  && XEXP (SET_SRC (exp), 1) != const0_rtx)
1481
                /* For some reason gcc will not canonicalize compare
1482
                   operations, reversing the sign by itself if
1483
                   operands are in wrong order.  */
1484
                /* (But NOT inverted; eq is still eq.) */
1485
                cc_status.flags = CC_REVERSED;
1486
 
1487
              /* This seems to be overlooked by gcc.  FIXME: Check again.
1488
                 FIXME:  Is it really safe?  */
1489
              cc_status.value2
1490
                = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)),
1491
                                 XEXP (SET_SRC (exp), 0),
1492
                                 XEXP (SET_SRC (exp), 1));
1493
            }
1494
          return;
1495
        }
1496
      else if (REG_P (SET_DEST (exp))
1497
               || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1498
                   && REG_P (XEXP (SET_DEST (exp), 0))))
1499
        {
1500
          /* A register is set; normally CC is set to show that no
1501
             test insn is needed.  Catch the exceptions.  */
1502
 
1503
          /* If not to cc0, then no "set"s in non-natural mode give
1504
             ok cc0...  */
1505
          if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
1506
              || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
1507
            {
1508
              /* ... except add:s and sub:s in DImode.  */
1509
              if (GET_MODE (SET_DEST (exp)) == DImode
1510
                  && (GET_CODE (SET_SRC (exp)) == PLUS
1511
                      || GET_CODE (SET_SRC (exp)) == MINUS))
1512
                {
1513
                  CC_STATUS_INIT;
1514
                  cc_status.value1 = SET_DEST (exp);
1515
                  cc_status.value2 = SET_SRC (exp);
1516
 
1517
                  if (cris_reg_overlap_mentioned_p (cc_status.value1,
1518
                                                    cc_status.value2))
1519
                    cc_status.value2 = 0;
1520
 
1521
                  /* Add and sub may set V, which gets us
1522
                     unoptimizable results in "gt" and "le" condition
1523
                     codes.  */
1524
                  cc_status.flags |= CC_NO_OVERFLOW;
1525
 
1526
                  return;
1527
                }
1528
            }
1529
          else if (SET_SRC (exp) == const0_rtx
1530
                   || (REG_P (SET_SRC (exp))
1531
                       && (REGNO (SET_SRC (exp))
1532
                           > CRIS_LAST_GENERAL_REGISTER))
1533
                   || (TARGET_V32
1534
                       && GET_CODE (SET_SRC (exp)) == CONST_INT
1535
                       && CRIS_CONST_OK_FOR_LETTER_P (INTVAL (SET_SRC (exp)),
1536
                                                      'I')))
1537
            {
1538
              /* There's no CC0 change for this case.  Just check
1539
                 for overlap.  */
1540
              if (cc_status.value1
1541
                  && modified_in_p (cc_status.value1, insn))
1542
                cc_status.value1 = 0;
1543
 
1544
              if (cc_status.value2
1545
                  && modified_in_p (cc_status.value2, insn))
1546
                cc_status.value2 = 0;
1547
 
1548
              return;
1549
            }
1550
          else
1551
            {
1552
              CC_STATUS_INIT;
1553
              cc_status.value1 = SET_DEST (exp);
1554
              cc_status.value2 = SET_SRC (exp);
1555
 
1556
              if (cris_reg_overlap_mentioned_p (cc_status.value1,
1557
                                                cc_status.value2))
1558
                cc_status.value2 = 0;
1559
 
1560
              /* Some operations may set V, which gets us
1561
                 unoptimizable results in "gt" and "le" condition
1562
                 codes.  */
1563
              if (GET_CODE (SET_SRC (exp)) == PLUS
1564
                  || GET_CODE (SET_SRC (exp)) == MINUS
1565
                  || GET_CODE (SET_SRC (exp)) == NEG)
1566
                cc_status.flags |= CC_NO_OVERFLOW;
1567
 
1568
              /* For V32, nothing with a register destination sets
1569
                 C and V usefully.  */
1570
              if (TARGET_V32)
1571
                cc_status.flags |= CC_NO_OVERFLOW;
1572
 
1573
              return;
1574
            }
1575
        }
1576
      else if (MEM_P (SET_DEST (exp))
1577
               || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1578
                   && MEM_P (XEXP (SET_DEST (exp), 0))))
1579
        {
1580
          /* When SET to MEM, then CC is not changed (except for
1581
             overlap).  */
1582
          if (cc_status.value1
1583
              && modified_in_p (cc_status.value1, insn))
1584
            cc_status.value1 = 0;
1585
 
1586
          if (cc_status.value2
1587
              && modified_in_p (cc_status.value2, insn))
1588
            cc_status.value2 = 0;
1589
 
1590
          return;
1591
        }
1592
    }
1593
  else if (GET_CODE (exp) == PARALLEL)
1594
    {
1595
      if (GET_CODE (XVECEXP (exp, 0, 0)) == SET
1596
          && GET_CODE (XVECEXP (exp, 0, 1)) == SET
1597
          && REG_P (XEXP (XVECEXP (exp, 0, 1), 0)))
1598
        {
1599
          if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0))
1600
              && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1)))
1601
            {
1602
              CC_STATUS_INIT;
1603
 
1604
              /* For "move.S [rx=ry+o],rz", say CC reflects
1605
                 value1=rz and value2=[rx] */
1606
              cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
1607
              cc_status.value2
1608
                = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1),
1609
                                         XEXP (XVECEXP (exp, 0, 1), 0));
1610
 
1611
              /* Huh?  A side-effect cannot change the destination
1612
                 register.  */
1613
              if (cris_reg_overlap_mentioned_p (cc_status.value1,
1614
                                                cc_status.value2))
1615
                internal_error ("internal error: sideeffect-insn affecting main effect");
1616
 
1617
              /* For V32, moves to registers don't set C and V.  */
1618
              if (TARGET_V32)
1619
                cc_status.flags |= CC_NO_OVERFLOW;
1620
              return;
1621
            }
1622
          else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1))
1623
                    || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx)
1624
                   && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0)))
1625
            {
1626
              /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1627
                 say flags are not changed, except for overlap.  */
1628
              if (cc_status.value1
1629
                  && modified_in_p (cc_status.value1, insn))
1630
                cc_status.value1 = 0;
1631
 
1632
              if (cc_status.value2
1633
                  && modified_in_p (cc_status.value2, insn))
1634
                cc_status.value2 = 0;
1635
 
1636
              return;
1637
            }
1638
        }
1639
    }
1640
 
1641
  /* If we got here, the case wasn't covered by the code above.  */
1642
  CC_STATUS_INIT;
1643
}
1644
 
1645
/*  This function looks into the pattern to see how this insn affects
1646
    condition codes.
1647
 
1648
    Used when to eliminate test insns before a condition-code user,
1649
    such as a "scc" insn or a conditional branch.  This includes
1650
    checking if the entities that cc was updated by, are changed by the
1651
    operation.
1652
 
1653
    Currently a jumble of the old peek-inside-the-insn and the newer
1654
    check-cc-attribute methods.  */
1655
 
1656
void
1657
cris_notice_update_cc (rtx exp, rtx insn)
1658
{
1659
  enum attr_cc attrval = get_attr_cc (insn);
1660
 
1661
  /* Check if user specified "-mcc-init" as a bug-workaround.  Remember
1662
     to still set CC_REVERSED as below, since that's required by some
1663
     compare insn alternatives.  (FIXME: GCC should do this virtual
1664
     operand swap by itself.)  A test-case that may otherwise fail is
1665
     gcc.c-torture/execute/20000217-1.c -O0 and -O1.  */
1666
  if (TARGET_CCINIT)
1667
    {
1668
      CC_STATUS_INIT;
1669
 
1670
      if (attrval == CC_REV)
1671
        cc_status.flags = CC_REVERSED;
1672
      return;
1673
    }
1674
 
1675
  /* Slowly, we're converting to using attributes to control the setting
1676
     of condition-code status.  */
1677
  switch (attrval)
1678
    {
1679
    case CC_NONE:
1680
      /* Even if it is "none", a setting may clobber a previous
1681
         cc-value, so check.  */
1682
      if (GET_CODE (exp) == SET)
1683
        {
1684
          if (cc_status.value1
1685
              && modified_in_p (cc_status.value1, insn))
1686
            cc_status.value1 = 0;
1687
 
1688
          if (cc_status.value2
1689
              && modified_in_p (cc_status.value2, insn))
1690
            cc_status.value2 = 0;
1691
        }
1692
      return;
1693
 
1694
    case CC_CLOBBER:
1695
      CC_STATUS_INIT;
1696
      return;
1697
 
1698
    case CC_REV:
1699
    case CC_NOOV32:
1700
    case CC_NORMAL:
1701
      cris_normal_notice_update_cc (exp, insn);
1702
 
1703
      /* The "test" insn doesn't clear (carry and) overflow on V32.  We
1704
        can change bge => bpl and blt => bmi by passing on to the cc0
1705
        user that V should not be considered; bgt and ble are taken
1706
        care of by other methods (see {tst,cmp}{si,hi,qi}).  */
1707
      if (attrval == CC_NOOV32 && TARGET_V32)
1708
        cc_status.flags |= CC_NO_OVERFLOW;
1709
      return;
1710
 
1711
    default:
1712
      internal_error ("unknown cc_attr value");
1713
    }
1714
 
1715
  CC_STATUS_INIT;
1716
}
1717
 
1718
/* Return != 0 if the return sequence for the current function is short,
1719
   like "ret" or "jump [sp+]".  Prior to reloading, we can't tell if
1720
   registers must be saved, so return 0 then.  */
1721
 
1722
bool
1723
cris_simple_epilogue (void)
1724
{
1725
  unsigned int regno;
1726
  unsigned int reglimit = STACK_POINTER_REGNUM;
1727
  bool got_really_used = false;
1728
 
1729
  if (! reload_completed
1730
      || frame_pointer_needed
1731
      || get_frame_size () != 0
1732
      || crtl->args.pretend_args_size
1733
      || crtl->args.size
1734
      || crtl->outgoing_args_size
1735
      || crtl->calls_eh_return
1736
 
1737
      /* If we're not supposed to emit prologue and epilogue, we must
1738
         not emit return-type instructions.  */
1739
      || !TARGET_PROLOGUE_EPILOGUE)
1740
    return false;
1741
 
1742
  /* Can't return from stacked return address with v32.  */
1743
  if (TARGET_V32 && cris_return_address_on_stack ())
1744
    return false;
1745
 
1746
  if (crtl->uses_pic_offset_table)
1747
    {
1748
      push_topmost_sequence ();
1749
      got_really_used
1750
        = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
1751
      pop_topmost_sequence ();
1752
    }
1753
 
1754
  /* No simple epilogue if there are saved registers.  */
1755
  for (regno = 0; regno < reglimit; regno++)
1756
    if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1757
      return false;
1758
 
1759
  return true;
1760
}
1761
 
1762
/* Expand a return insn (just one insn) marked as using SRP or stack
1763
   slot depending on parameter ON_STACK.  */
1764
 
1765
void
1766
cris_expand_return (bool on_stack)
1767
{
1768
  /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1769
     tell "ret" from "jump [sp+]".  Some, but not all, other parts of
1770
     GCC expect just (return) to do the right thing when optimizing, so
1771
     we do that until they're fixed.  Currently, all return insns in a
1772
     function must be the same (not really a limiting factor) so we need
1773
     to check that it doesn't change half-way through.  */
1774
  emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1775
 
1776
  CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
1777
  CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
1778
 
1779
  cfun->machine->return_type
1780
    = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET;
1781
}
1782
 
1783
/* Compute a (partial) cost for rtx X.  Return true if the complete
1784
   cost has been computed, and false if subexpressions should be
1785
   scanned.  In either case, *TOTAL contains the cost result.  */
1786
 
1787
static bool
1788
cris_rtx_costs (rtx x, int code, int outer_code, int *total,
1789
                bool speed)
1790
{
1791
  switch (code)
1792
    {
1793
    case CONST_INT:
1794
      {
1795
        HOST_WIDE_INT val = INTVAL (x);
1796
        if (val == 0)
1797
          *total = 0;
1798
        else if (val < 32 && val >= -32)
1799
          *total = 1;
1800
        /* Eight or 16 bits are a word and cycle more expensive.  */
1801
        else if (val <= 32767 && val >= -32768)
1802
          *total = 2;
1803
        /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
1804
           another word.  FIXME: This isn't linear to 16 bits.  */
1805
        else
1806
          *total = 4;
1807
        return true;
1808
      }
1809
 
1810
    case LABEL_REF:
1811
      *total = 6;
1812
      return true;
1813
 
1814
    case CONST:
1815
    case SYMBOL_REF:
1816
      *total = 6;
1817
      return true;
1818
 
1819
    case CONST_DOUBLE:
1820
      if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x)))
1821
        *total = 12;
1822
      else
1823
        /* Make 0.0 cheap, else test-insns will not be used.  */
1824
        *total = 0;
1825
      return true;
1826
 
1827
    case MULT:
1828
      /* If we have one arm of an ADDI, make sure it gets the cost of
1829
         one insn, i.e. zero cost for this operand, and just the cost
1830
         of the PLUS, as the insn is created by combine from a PLUS
1831
         and an ASHIFT, and the MULT cost below would make the
1832
         combined value be larger than the separate insns.  The insn
1833
         validity is checked elsewhere by combine.
1834
 
1835
         FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
1836
         function should be rewritten.  */
1837
      if (outer_code == PLUS && BIAP_INDEX_P (x))
1838
        {
1839
          *total = 0;
1840
          return true;
1841
        }
1842
 
1843
      /* Identify values that are no powers of two.  Powers of 2 are
1844
         taken care of already and those values should not be changed.  */
1845
      if (!CONST_INT_P (XEXP (x, 1))
1846
          || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1847
        {
1848
          /* If we have a multiply insn, then the cost is between
1849
             1 and 2 "fast" instructions.  */
1850
          if (TARGET_HAS_MUL_INSNS)
1851
            {
1852
              *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
1853
              return true;
1854
            }
1855
 
1856
          /* Estimate as 4 + 4 * #ofbits.  */
1857
          *total = COSTS_N_INSNS (132);
1858
          return true;
1859
        }
1860
      return false;
1861
 
1862
    case UDIV:
1863
    case MOD:
1864
    case UMOD:
1865
    case DIV:
1866
      if (!CONST_INT_P (XEXP (x, 1))
1867
          || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1868
        {
1869
          /* Estimate this as 4 + 8 * #of bits.  */
1870
          *total = COSTS_N_INSNS (260);
1871
          return true;
1872
        }
1873
      return false;
1874
 
1875
    case AND:
1876
      if (CONST_INT_P (XEXP (x, 1))
1877
          /* Two constants may actually happen before optimization.  */
1878
          && !CONST_INT_P (XEXP (x, 0))
1879
          && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
1880
        {
1881
          *total = (rtx_cost (XEXP (x, 0), outer_code, speed) + 2
1882
                    + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0))));
1883
          return true;
1884
        }
1885
      return false;
1886
 
1887
    case ZERO_EXTRACT:
1888
      if (outer_code != COMPARE)
1889
        return false;
1890
      /* fall through */
1891
 
1892
    case ZERO_EXTEND: case SIGN_EXTEND:
1893
      *total = rtx_cost (XEXP (x, 0), outer_code, speed);
1894
      return true;
1895
 
1896
    default:
1897
      return false;
1898
    }
1899
}
1900
 
1901
/* The ADDRESS_COST worker.  */
1902
 
1903
static int
1904
cris_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
1905
{
1906
  /* The metric to use for the cost-macros is unclear.
1907
     The metric used here is (the number of cycles needed) / 2,
1908
     where we consider equal a cycle for a word of code and a cycle to
1909
     read memory.  FIXME: Adding "+ 1" to all values would avoid
1910
     returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
1911
 
1912
     Unfortunately(?) such a hack would expose other pessimizations,
1913
     at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
1914
     loop there, without apparent reason.  */
1915
 
1916
  /* The cheapest addressing modes get 0, since nothing extra is needed.  */
1917
  if (BASE_OR_AUTOINCR_P (x))
1918
    return 0;
1919
 
1920
  /* An indirect mem must be a DIP.  This means two bytes extra for code,
1921
     and 4 bytes extra for memory read, i.e.  (2 + 4) / 2.  */
1922
  if (MEM_P (x))
1923
    return (2 + 4) / 2;
1924
 
1925
  /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
1926
     an extra DIP prefix and 4 bytes of constant in most cases.  */
1927
  if (CONSTANT_P (x))
1928
    return (2 + 4) / 2;
1929
 
1930
  /* Handle BIAP and BDAP prefixes.  */
1931
  if (GET_CODE (x) == PLUS)
1932
    {
1933
      rtx tem1 = XEXP (x, 0);
1934
      rtx tem2 = XEXP (x, 1);
1935
 
1936
      /* Local extended canonicalization rule: the first operand must
1937
         be REG, unless it's an operation (MULT).  */
1938
      if (!REG_P (tem1) && GET_CODE (tem1) != MULT)
1939
        tem1 = tem2, tem2 = XEXP (x, 0);
1940
 
1941
      /* We'll "assume" we have canonical RTX now.  */
1942
      gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT);
1943
 
1944
      /* A BIAP is 2 extra bytes for the prefix insn, nothing more.  We
1945
         recognize the typical MULT which is always in tem1 because of
1946
         insn canonicalization.  */
1947
      if ((GET_CODE (tem1) == MULT && BIAP_INDEX_P (tem1))
1948
          || REG_P (tem2))
1949
        return 2 / 2;
1950
 
1951
      /* A BDAP (quick) is 2 extra bytes.  Any constant operand to the
1952
         PLUS is always found in tem2.  */
1953
      if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128)
1954
        return 2 / 2;
1955
 
1956
      /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
1957
         bytes.  */
1958
      if (CONST_INT_P (tem2)
1959
          && CRIS_CONST_OK_FOR_LETTER_P (INTVAL (tem2), 'L'))
1960
        return (2 + 2) / 2;
1961
 
1962
      /* A BDAP with some other constant is 2 bytes extra.  */
1963
      if (CONSTANT_P (tem2))
1964
        return (2 + 2 + 2) / 2;
1965
 
1966
      /* BDAP with something indirect should have a higher cost than
1967
         BIAP with register.   FIXME: Should it cost like a MEM or more?  */
1968
      return (2 + 2 + 2) / 2;
1969
    }
1970
 
1971
  /* What else?  Return a high cost.  It matters only for valid
1972
     addressing modes.  */
1973
  return 10;
1974
}
1975
 
1976
/* Check various objections to the side-effect.  Used in the test-part
1977
   of an anonymous insn describing an insn with a possible side-effect.
1978
   Returns nonzero if the implied side-effect is ok.
1979
 
1980
   code     : PLUS or MULT
1981
   ops      : An array of rtx:es. lreg, rreg, rval,
1982
              The variables multop and other_op are indexes into this,
1983
              or -1 if they are not applicable.
1984
   lreg     : The register that gets assigned in the side-effect.
1985
   rreg     : One register in the side-effect expression
1986
   rval     : The other register, or an int.
1987
   multop   : An integer to multiply rval with.
1988
   other_op : One of the entities of the main effect,
1989
              whose mode we must consider.  */
1990
 
1991
int
1992
cris_side_effect_mode_ok (enum rtx_code code, rtx *ops,
1993
                          int lreg, int rreg, int rval,
1994
                          int multop, int other_op)
1995
{
1996
  /* Find what value to multiply with, for rx =ry + rz * n.  */
1997
  int mult = multop < 0 ? 1 : INTVAL (ops[multop]);
1998
 
1999
  rtx reg_rtx = ops[rreg];
2000
  rtx val_rtx = ops[rval];
2001
 
2002
  /* The operands may be swapped.  Canonicalize them in reg_rtx and
2003
     val_rtx, where reg_rtx always is a reg (for this constraint to
2004
     match).  */
2005
  if (! BASE_P (reg_rtx))
2006
    reg_rtx = val_rtx, val_rtx = ops[rreg];
2007
 
2008
  /* Don't forget to check that reg_rtx really is a reg.  If it isn't,
2009
     we have no business.  */
2010
  if (! BASE_P (reg_rtx))
2011
    return 0;
2012
 
2013
  /* Don't do this when -mno-split.  */
2014
  if (!TARGET_SIDE_EFFECT_PREFIXES)
2015
    return 0;
2016
 
2017
  /* The mult expression may be hidden in lreg.  FIXME:  Add more
2018
     commentary about that.  */
2019
  if (GET_CODE (val_rtx) == MULT)
2020
    {
2021
      mult = INTVAL (XEXP (val_rtx, 1));
2022
      val_rtx = XEXP (val_rtx, 0);
2023
      code = MULT;
2024
    }
2025
 
2026
  /* First check the "other operand".  */
2027
  if (other_op >= 0)
2028
    {
2029
      if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD)
2030
        return 0;
2031
 
2032
      /* Check if the lvalue register is the same as the "other
2033
         operand".  If so, the result is undefined and we shouldn't do
2034
         this.  FIXME:  Check again.  */
2035
      if ((BASE_P (ops[lreg])
2036
           && BASE_P (ops[other_op])
2037
           && REGNO (ops[lreg]) == REGNO (ops[other_op]))
2038
          || rtx_equal_p (ops[other_op], ops[lreg]))
2039
      return 0;
2040
    }
2041
 
2042
  /* Do not accept frame_pointer_rtx as any operand.  */
2043
  if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx
2044
      || ops[rval] == frame_pointer_rtx
2045
      || (other_op >= 0 && ops[other_op] == frame_pointer_rtx))
2046
    return 0;
2047
 
2048
  if (code == PLUS
2049
      && ! BASE_P (val_rtx))
2050
    {
2051
 
2052
      /* Do not allow rx = rx + n if a normal add or sub with same size
2053
         would do.  */
2054
      if (rtx_equal_p (ops[lreg], reg_rtx)
2055
          && CONST_INT_P (val_rtx)
2056
          && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63))
2057
        return 0;
2058
 
2059
      /* Check allowed cases, like [r(+)?].[bwd] and const.  */
2060
      if (CONSTANT_P (val_rtx))
2061
        return 1;
2062
 
2063
      if (MEM_P (val_rtx) && BASE_OR_AUTOINCR_P (XEXP (val_rtx, 0)))
2064
        return 1;
2065
 
2066
      if (GET_CODE (val_rtx) == SIGN_EXTEND
2067
          && MEM_P (XEXP (val_rtx, 0))
2068
          && BASE_OR_AUTOINCR_P (XEXP (XEXP (val_rtx, 0), 0)))
2069
        return 1;
2070
 
2071
      /* If we got here, it's not a valid addressing mode.  */
2072
      return 0;
2073
    }
2074
  else if (code == MULT
2075
           || (code == PLUS && BASE_P (val_rtx)))
2076
    {
2077
      /* Do not allow rx = rx + ry.S, since it doesn't give better code.  */
2078
      if (rtx_equal_p (ops[lreg], reg_rtx)
2079
          || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx)))
2080
        return 0;
2081
 
2082
      /* Do not allow bad multiply-values.  */
2083
      if (mult != 1 && mult != 2 && mult != 4)
2084
        return 0;
2085
 
2086
      /* Only allow  r + ...  */
2087
      if (! BASE_P (reg_rtx))
2088
        return 0;
2089
 
2090
      /* If we got here, all seems ok.
2091
         (All checks need to be done above).  */
2092
      return 1;
2093
    }
2094
 
2095
  /* If we get here, the caller got its initial tests wrong.  */
2096
  internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2097
}
2098
 
2099
/* Whether next_cc0_user of insn is LE or GT or requires a real compare
2100
   insn for other reasons.  */
2101
 
2102
bool
2103
cris_cc0_user_requires_cmp (rtx insn)
2104
{
2105
  rtx cc0_user = NULL;
2106
  rtx body;
2107
  rtx set;
2108
 
2109
  gcc_assert (insn != NULL);
2110
 
2111
  if (!TARGET_V32)
2112
    return false;
2113
 
2114
  cc0_user = next_cc0_user (insn);
2115
  if (cc0_user == NULL)
2116
    return false;
2117
 
2118
  body = PATTERN (cc0_user);
2119
  set = single_set (cc0_user);
2120
 
2121
  /* Users can be sCC and bCC.  */
2122
  if (JUMP_P (cc0_user)
2123
      && GET_CODE (body) == SET
2124
      && SET_DEST (body) == pc_rtx
2125
      && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
2126
      && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx)
2127
    {
2128
      return
2129
        GET_CODE (XEXP (SET_SRC (body), 0)) == GT
2130
        || GET_CODE (XEXP (SET_SRC (body), 0)) == LE;
2131
    }
2132
  else if (set)
2133
    {
2134
      return
2135
        GET_CODE (SET_SRC (body)) == GT
2136
        || GET_CODE (SET_SRC (body)) == LE;
2137
    }
2138
 
2139
  gcc_unreachable ();
2140
}
2141
 
2142
/* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2143
   does not handle the case where the IN operand is strict_low_part; it
2144
   does handle it for X.  Test-case in Axis-20010516.  This function takes
2145
   care of that for THIS port.  FIXME: strict_low_part is going away
2146
   anyway.  */
2147
 
2148
static int
2149
cris_reg_overlap_mentioned_p (rtx x, rtx in)
2150
{
2151
  /* The function reg_overlap_mentioned now handles when X is
2152
     strict_low_part, but not when IN is a STRICT_LOW_PART.  */
2153
  if (GET_CODE (in) == STRICT_LOW_PART)
2154
    in = XEXP (in, 0);
2155
 
2156
  return reg_overlap_mentioned_p (x, in);
2157
}
2158
 
2159
/* The TARGET_ASM_NAMED_SECTION worker.
2160
   We just dispatch to the functions for ELF and a.out.  */
2161
 
2162
void
2163
cris_target_asm_named_section (const char *name, unsigned int flags,
2164
                               tree decl)
2165
{
2166
  if (! TARGET_ELF)
2167
    default_no_named_section (name, flags, decl);
2168
  else
2169
    default_elf_asm_named_section (name, flags, decl);
2170
}
2171
 
2172
/* Return TRUE iff X is a CONST valid for e.g. indexing.
2173
   ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2174
   elsewhere.  */
2175
 
2176
bool
2177
cris_valid_pic_const (rtx x, bool any_operand)
2178
{
2179
  gcc_assert (flag_pic);
2180
 
2181
  switch (GET_CODE (x))
2182
    {
2183
    case CONST_INT:
2184
    case CONST_DOUBLE:
2185
      return true;
2186
    default:
2187
      ;
2188
    }
2189
 
2190
  if (GET_CODE (x) != CONST)
2191
    return false;
2192
 
2193
  x = XEXP (x, 0);
2194
 
2195
  /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))).  */
2196
  if (GET_CODE (x) == PLUS
2197
      && GET_CODE (XEXP (x, 0)) == UNSPEC
2198
      && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL
2199
          || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL)
2200
      && CONST_INT_P (XEXP (x, 1)))
2201
    x = XEXP (x, 0);
2202
 
2203
  if (GET_CODE (x) == UNSPEC)
2204
    switch (XINT (x, 1))
2205
      {
2206
        /* A PCREL operand is only valid for call and movsi.  */
2207
      case CRIS_UNSPEC_PLT_PCREL:
2208
      case CRIS_UNSPEC_PCREL:
2209
        return !any_operand;
2210
 
2211
      case CRIS_UNSPEC_PLT_GOTREL:
2212
      case CRIS_UNSPEC_PLTGOTREAD:
2213
      case CRIS_UNSPEC_GOTREAD:
2214
      case CRIS_UNSPEC_GOTREL:
2215
        return true;
2216
      default:
2217
        gcc_unreachable ();
2218
      }
2219
 
2220
  return cris_pic_symbol_type_of (x) == cris_no_symbol;
2221
}
2222
 
2223
/* Helper function to find the right PIC-type symbol to generate,
2224
   given the original (non-PIC) representation.  */
2225
 
2226
enum cris_pic_symbol_type
2227
cris_pic_symbol_type_of (rtx x)
2228
{
2229
  switch (GET_CODE (x))
2230
    {
2231
    case SYMBOL_REF:
2232
      return SYMBOL_REF_LOCAL_P (x)
2233
        ? cris_rel_symbol : cris_got_symbol;
2234
 
2235
    case LABEL_REF:
2236
      return cris_rel_symbol;
2237
 
2238
    case CONST:
2239
      return cris_pic_symbol_type_of (XEXP (x, 0));
2240
 
2241
    case PLUS:
2242
    case MINUS:
2243
      {
2244
        enum cris_pic_symbol_type t1 = cris_pic_symbol_type_of (XEXP (x, 0));
2245
        enum cris_pic_symbol_type t2 = cris_pic_symbol_type_of (XEXP (x, 1));
2246
 
2247
        gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol);
2248
 
2249
        if (t1 == cris_got_symbol || t1 == cris_got_symbol)
2250
          return cris_got_symbol_needing_fixup;
2251
 
2252
        return t1 != cris_no_symbol ? t1 : t2;
2253
      }
2254
 
2255
    case CONST_INT:
2256
    case CONST_DOUBLE:
2257
      return cris_no_symbol;
2258
 
2259
    case UNSPEC:
2260
      /* Likely an offsettability-test attempting to add a constant to
2261
         a GOTREAD symbol, which can't be handled.  */
2262
      return cris_invalid_pic_symbol;
2263
 
2264
    default:
2265
      fatal_insn ("unrecognized supposed constant", x);
2266
    }
2267
 
2268
  gcc_unreachable ();
2269
}
2270
 
2271
/* The LEGITIMATE_PIC_OPERAND_P worker.  */
2272
 
2273
int
2274
cris_legitimate_pic_operand (rtx x)
2275
{
2276
  /* Symbols are not valid PIC operands as-is; just constants.  */
2277
  return cris_valid_pic_const (x, true);
2278
}
2279
 
2280
/* The ASM_OUTPUT_CASE_END worker.  */
2281
 
2282
void
2283
cris_asm_output_case_end (FILE *stream, int num, rtx table)
2284
{
2285
  if (TARGET_V32)
2286
    {
2287
      rtx whole_jump_insn = PATTERN (PREV_INSN (PREV_INSN (table)));
2288
 
2289
      /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2290
         filled.  */
2291
      rtx parallel_jump
2292
        = (GET_CODE (whole_jump_insn) == SEQUENCE
2293
           ? PATTERN (XVECEXP (whole_jump_insn, 0, 0)) : whole_jump_insn);
2294
 
2295
      asm_fprintf (stream,
2296
                   "\t.word %LL%d-.%s\n",
2297
                   CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2298
                                                        (parallel_jump, 0, 0),
2299
                                                        1), 2), 0)),
2300
                   (TARGET_PDEBUG ? "; default" : ""));
2301
      return;
2302
    }
2303
 
2304
  asm_fprintf (stream,
2305
               "\t.word %LL%d-%LL%d%s\n",
2306
               CODE_LABEL_NUMBER (XEXP
2307
                                  (XEXP
2308
                                   (XEXP
2309
                                    (XVECEXP
2310
                                     (PATTERN
2311
                                      (PREV_INSN
2312
                                       (PREV_INSN (table))), 0, 0), 1),
2313
                                    2), 0)),
2314
               num,
2315
               (TARGET_PDEBUG ? "; default" : ""));
2316
}
2317
 
2318
/* TARGET_HANDLE_OPTION worker.  We just store the values into local
2319
   variables here.  Checks for correct semantics are in
2320
   cris_override_options.  */
2321
 
2322
static bool
2323
cris_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
2324
                    int value ATTRIBUTE_UNUSED)
2325
{
2326
  switch (code)
2327
    {
2328
    case OPT_metrax100:
2329
      target_flags
2330
        |= (MASK_SVINTO
2331
            + MASK_ETRAX4_ADD
2332
            + MASK_ALIGN_BY_32);
2333
      break;
2334
 
2335
    case OPT_mno_etrax100:
2336
      target_flags
2337
        &= ~(MASK_SVINTO
2338
             + MASK_ETRAX4_ADD
2339
             + MASK_ALIGN_BY_32);
2340
      break;
2341
 
2342
    case OPT_m32_bit:
2343
    case OPT_m32bit:
2344
      target_flags
2345
        |= (MASK_STACK_ALIGN
2346
            + MASK_CONST_ALIGN
2347
            + MASK_DATA_ALIGN
2348
            + MASK_ALIGN_BY_32);
2349
      break;
2350
 
2351
    case OPT_m16_bit:
2352
    case OPT_m16bit:
2353
      target_flags
2354
        |= (MASK_STACK_ALIGN
2355
            + MASK_CONST_ALIGN
2356
            + MASK_DATA_ALIGN);
2357
      break;
2358
 
2359
    case OPT_m8_bit:
2360
    case OPT_m8bit:
2361
      target_flags
2362
        &= ~(MASK_STACK_ALIGN
2363
             + MASK_CONST_ALIGN
2364
             + MASK_DATA_ALIGN);
2365
      break;
2366
 
2367
    default:
2368
      break;
2369
    }
2370
 
2371
  CRIS_SUBTARGET_HANDLE_OPTION(code, arg, value);
2372
 
2373
  return true;
2374
}
2375
 
2376
/* The OVERRIDE_OPTIONS worker.
2377
   As is the norm, this also parses -mfoo=bar type parameters.  */
2378
 
2379
void
2380
cris_override_options (void)
2381
{
2382
  if (cris_max_stackframe_str)
2383
    {
2384
      cris_max_stackframe = atoi (cris_max_stackframe_str);
2385
 
2386
      /* Do some sanity checking.  */
2387
      if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000)
2388
        internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2389
                        cris_max_stackframe, 0x20000000);
2390
    }
2391
 
2392
  /* Let "-metrax4" and "-metrax100" change the cpu version.  */
2393
  if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO)
2394
    cris_cpu_version = CRIS_CPU_SVINTO;
2395
  else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4)
2396
    cris_cpu_version = CRIS_CPU_ETRAX4;
2397
 
2398
  /* Parse -march=... and its synonym, the deprecated -mcpu=...  */
2399
  if (cris_cpu_str)
2400
    {
2401
      cris_cpu_version
2402
        = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1);
2403
 
2404
      if (strcmp ("etrax4", cris_cpu_str) == 0)
2405
        cris_cpu_version = 3;
2406
 
2407
      if (strcmp ("svinto", cris_cpu_str) == 0
2408
          || strcmp ("etrax100", cris_cpu_str) == 0)
2409
        cris_cpu_version = 8;
2410
 
2411
      if (strcmp ("ng", cris_cpu_str) == 0
2412
          || strcmp ("etrax100lx", cris_cpu_str) == 0)
2413
        cris_cpu_version = 10;
2414
 
2415
      if (cris_cpu_version < 0 || cris_cpu_version > 32)
2416
        error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2417
               cris_cpu_str);
2418
 
2419
      /* Set the target flags.  */
2420
      if (cris_cpu_version >= CRIS_CPU_ETRAX4)
2421
        target_flags |= MASK_ETRAX4_ADD;
2422
 
2423
      /* If this is Svinto or higher, align for 32 bit accesses.  */
2424
      if (cris_cpu_version >= CRIS_CPU_SVINTO)
2425
        target_flags
2426
          |= (MASK_SVINTO | MASK_ALIGN_BY_32
2427
              | MASK_STACK_ALIGN | MASK_CONST_ALIGN
2428
              | MASK_DATA_ALIGN);
2429
 
2430
      /* Note that we do not add new flags when it can be completely
2431
         described with a macro that uses -mcpu=X.  So
2432
         TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG).  */
2433
    }
2434
 
2435
  if (cris_tune_str)
2436
    {
2437
      int cris_tune
2438
        = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1);
2439
 
2440
      if (strcmp ("etrax4", cris_tune_str) == 0)
2441
        cris_tune = 3;
2442
 
2443
      if (strcmp ("svinto", cris_tune_str) == 0
2444
          || strcmp ("etrax100", cris_tune_str) == 0)
2445
        cris_tune = 8;
2446
 
2447
      if (strcmp ("ng", cris_tune_str) == 0
2448
          || strcmp ("etrax100lx", cris_tune_str) == 0)
2449
        cris_tune = 10;
2450
 
2451
      if (cris_tune < 0 || cris_tune > 32)
2452
        error ("unknown CRIS cpu version specification in -mtune= : %s",
2453
               cris_tune_str);
2454
 
2455
      if (cris_tune >= CRIS_CPU_SVINTO)
2456
        /* We have currently nothing more to tune than alignment for
2457
           memory accesses.  */
2458
        target_flags
2459
          |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN
2460
              | MASK_DATA_ALIGN | MASK_ALIGN_BY_32);
2461
    }
2462
 
2463
  if (cris_cpu_version >= CRIS_CPU_V32)
2464
    target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG);
2465
 
2466
  if (flag_pic)
2467
    {
2468
      /* Use error rather than warning, so invalid use is easily
2469
         detectable.  Still change to the values we expect, to avoid
2470
         further errors.  */
2471
      if (! TARGET_LINUX)
2472
        {
2473
          error ("-fPIC and -fpic are not supported in this configuration");
2474
          flag_pic = 0;
2475
        }
2476
 
2477
      /* Turn off function CSE.  We need to have the addresses reach the
2478
         call expanders to get PLT-marked, as they could otherwise be
2479
         compared against zero directly or indirectly.  After visiting the
2480
         call expanders they will then be cse:ed, as the call expanders
2481
         force_reg the addresses, effectively forcing flag_no_function_cse
2482
         to 0.  */
2483
      flag_no_function_cse = 1;
2484
    }
2485
 
2486
  if (write_symbols == DWARF2_DEBUG && ! TARGET_ELF)
2487
    {
2488
      warning (0, "that particular -g option is invalid with -maout and -melinux");
2489
      write_symbols = DBX_DEBUG;
2490
    }
2491
 
2492
  /* Set the per-function-data initializer.  */
2493
  init_machine_status = cris_init_machine_status;
2494
}
2495
 
2496
/* The TARGET_ASM_OUTPUT_MI_THUNK worker.  */
2497
 
2498
static void
2499
cris_asm_output_mi_thunk (FILE *stream,
2500
                          tree thunkdecl ATTRIBUTE_UNUSED,
2501
                          HOST_WIDE_INT delta,
2502
                          HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2503
                          tree funcdecl)
2504
{
2505
  if (delta > 0)
2506
    fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2507
             ADDITIVE_SIZE_MODIFIER (delta), delta,
2508
             reg_names[CRIS_FIRST_ARG_REG]);
2509
  else if (delta < 0)
2510
    fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2511
             ADDITIVE_SIZE_MODIFIER (-delta), -delta,
2512
             reg_names[CRIS_FIRST_ARG_REG]);
2513
 
2514
  if (flag_pic)
2515
    {
2516
      const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0);
2517
 
2518
      name = (* targetm.strip_name_encoding) (name);
2519
 
2520
      if (TARGET_V32)
2521
        {
2522
          fprintf (stream, "\tba ");
2523
          assemble_name (stream, name);
2524
          fprintf (stream, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX);
2525
        }
2526
      else
2527
        {
2528
          fprintf (stream, "add.d ");
2529
          assemble_name (stream, name);
2530
          fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX);
2531
        }
2532
    }
2533
  else
2534
    {
2535
      fprintf (stream, "jump ");
2536
      assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0));
2537
      fprintf (stream, "\n");
2538
 
2539
      if (TARGET_V32)
2540
        fprintf (stream, "\tnop\n");
2541
    }
2542
}
2543
 
2544
/* Boilerplate emitted at start of file.
2545
 
2546
   NO_APP *only at file start* means faster assembly.  It also means
2547
   comments are not allowed.  In some cases comments will be output
2548
   for debugging purposes.  Make sure they are allowed then.
2549
 
2550
   We want a .file directive only if TARGET_ELF.  */
2551
static void
2552
cris_file_start (void)
2553
{
2554
  /* These expressions can vary at run time, so we cannot put
2555
     them into TARGET_INITIALIZER.  */
2556
  targetm.file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name);
2557
  targetm.file_start_file_directive = TARGET_ELF;
2558
 
2559
  default_file_start ();
2560
}
2561
 
2562
/* Rename the function calls for integer multiply and divide.  */
2563
static void
2564
cris_init_libfuncs (void)
2565
{
2566
  set_optab_libfunc (smul_optab, SImode, "__Mul");
2567
  set_optab_libfunc (sdiv_optab, SImode, "__Div");
2568
  set_optab_libfunc (udiv_optab, SImode, "__Udiv");
2569
  set_optab_libfunc (smod_optab, SImode, "__Mod");
2570
  set_optab_libfunc (umod_optab, SImode, "__Umod");
2571
}
2572
 
2573
/* The INIT_EXPANDERS worker sets the per-function-data initializer and
2574
   mark functions.  */
2575
 
2576
void
2577
cris_init_expanders (void)
2578
{
2579
  /* Nothing here at the moment.  */
2580
}
2581
 
2582
/* Zero initialization is OK for all current fields.  */
2583
 
2584
static struct machine_function *
2585
cris_init_machine_status (void)
2586
{
2587
  return GGC_CNEW (struct machine_function);
2588
}
2589
 
2590
/* Split a 2 word move (DI or presumably DF) into component parts.
2591
   Originally a copy of gen_split_move_double in m32r.c.  */
2592
 
2593
rtx
2594
cris_split_movdx (rtx *operands)
2595
{
2596
  enum machine_mode mode = GET_MODE (operands[0]);
2597
  rtx dest = operands[0];
2598
  rtx src  = operands[1];
2599
  rtx val;
2600
 
2601
  /* We used to have to handle (SUBREG (MEM)) here, but that should no
2602
     longer happen; after reload there are no SUBREGs any more, and we're
2603
     only called after reload.  */
2604
  CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
2605
 
2606
  start_sequence ();
2607
  if (REG_P (dest))
2608
    {
2609
      int dregno = REGNO (dest);
2610
 
2611
      /* Reg-to-reg copy.  */
2612
      if (REG_P (src))
2613
        {
2614
          int sregno = REGNO (src);
2615
 
2616
          int reverse = (dregno == sregno + 1);
2617
 
2618
          /* We normally copy the low-numbered register first.  However, if
2619
             the first register operand 0 is the same as the second register of
2620
             operand 1, we must copy in the opposite order.  */
2621
          emit_insn (gen_rtx_SET (VOIDmode,
2622
                                  operand_subword (dest, reverse, TRUE, mode),
2623
                                  operand_subword (src, reverse, TRUE, mode)));
2624
 
2625
          emit_insn (gen_rtx_SET (VOIDmode,
2626
                                  operand_subword (dest, !reverse, TRUE, mode),
2627
                                  operand_subword (src, !reverse, TRUE, mode)));
2628
        }
2629
      /* Constant-to-reg copy.  */
2630
      else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
2631
        {
2632
          rtx words[2];
2633
          split_double (src, &words[0], &words[1]);
2634
          emit_insn (gen_rtx_SET (VOIDmode,
2635
                                  operand_subword (dest, 0, TRUE, mode),
2636
                                  words[0]));
2637
 
2638
          emit_insn (gen_rtx_SET (VOIDmode,
2639
                                  operand_subword (dest, 1, TRUE, mode),
2640
                                  words[1]));
2641
        }
2642
      /* Mem-to-reg copy.  */
2643
      else if (MEM_P (src))
2644
        {
2645
          /* If the high-address word is used in the address, we must load it
2646
             last.  Otherwise, load it first.  */
2647
          rtx addr = XEXP (src, 0);
2648
          int reverse
2649
            = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0);
2650
 
2651
          /* The original code implies that we can't do
2652
             move.x [rN+],rM  move.x [rN],rM+1
2653
             when rN is dead, because of REG_NOTES damage.  That is
2654
             consistent with what I've seen, so don't try it.
2655
 
2656
             We have two different cases here; if the addr is POST_INC,
2657
             just pass it through, otherwise add constants.  */
2658
 
2659
          if (GET_CODE (addr) == POST_INC)
2660
            {
2661
              rtx mem;
2662
              rtx insn;
2663
 
2664
              /* Whenever we emit insns with post-incremented
2665
                 addresses ourselves, we must add a post-inc note
2666
                 manually.  */
2667
              mem = change_address (src, SImode, addr);
2668
              insn
2669
                = gen_rtx_SET (VOIDmode,
2670
                               operand_subword (dest, 0, TRUE, mode), mem);
2671
              insn = emit_insn (insn);
2672
              if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2673
                REG_NOTES (insn)
2674
                  = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2675
                                     REG_NOTES (insn));
2676
 
2677
              mem = copy_rtx (mem);
2678
              insn
2679
                = gen_rtx_SET (VOIDmode,
2680
                               operand_subword (dest, 1, TRUE, mode), mem);
2681
              insn = emit_insn (insn);
2682
              if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2683
                REG_NOTES (insn)
2684
                  = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2685
                                     REG_NOTES (insn));
2686
            }
2687
          else
2688
            {
2689
              /* Make sure we don't get any other addresses with
2690
                 embedded postincrements.  They should be stopped in
2691
                 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2692
                 safety.  */
2693
              if (side_effects_p (addr))
2694
                fatal_insn ("unexpected side-effects in address", addr);
2695
 
2696
              emit_insn (gen_rtx_SET
2697
                         (VOIDmode,
2698
                          operand_subword (dest, reverse, TRUE, mode),
2699
                          change_address
2700
                          (src, SImode,
2701
                           plus_constant (addr,
2702
                                          reverse * UNITS_PER_WORD))));
2703
              emit_insn (gen_rtx_SET
2704
                         (VOIDmode,
2705
                          operand_subword (dest, ! reverse, TRUE, mode),
2706
                          change_address
2707
                          (src, SImode,
2708
                           plus_constant (addr,
2709
                                          (! reverse) *
2710
                                          UNITS_PER_WORD))));
2711
            }
2712
        }
2713
      else
2714
        internal_error ("Unknown src");
2715
    }
2716
  /* Reg-to-mem copy or clear mem.  */
2717
  else if (MEM_P (dest)
2718
           && (REG_P (src)
2719
               || src == const0_rtx
2720
               || src == CONST0_RTX (DFmode)))
2721
    {
2722
      rtx addr = XEXP (dest, 0);
2723
 
2724
      if (GET_CODE (addr) == POST_INC)
2725
        {
2726
          rtx mem;
2727
          rtx insn;
2728
 
2729
          /* Whenever we emit insns with post-incremented addresses
2730
             ourselves, we must add a post-inc note manually.  */
2731
          mem = change_address (dest, SImode, addr);
2732
          insn
2733
            = gen_rtx_SET (VOIDmode,
2734
                           mem, operand_subword (src, 0, TRUE, mode));
2735
          insn = emit_insn (insn);
2736
          if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2737
            REG_NOTES (insn)
2738
              = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2739
                                 REG_NOTES (insn));
2740
 
2741
          mem = copy_rtx (mem);
2742
          insn
2743
            = gen_rtx_SET (VOIDmode,
2744
                           mem,
2745
                           operand_subword (src, 1, TRUE, mode));
2746
          insn = emit_insn (insn);
2747
          if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2748
            REG_NOTES (insn)
2749
              = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2750
                                 REG_NOTES (insn));
2751
        }
2752
      else
2753
        {
2754
          /* Make sure we don't get any other addresses with embedded
2755
             postincrements.  They should be stopped in
2756
             GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety.  */
2757
          if (side_effects_p (addr))
2758
            fatal_insn ("unexpected side-effects in address", addr);
2759
 
2760
          emit_insn (gen_rtx_SET
2761
                     (VOIDmode,
2762
                      change_address (dest, SImode, addr),
2763
                      operand_subword (src, 0, TRUE, mode)));
2764
 
2765
          emit_insn (gen_rtx_SET
2766
                     (VOIDmode,
2767
                      change_address (dest, SImode,
2768
                                      plus_constant (addr,
2769
                                                     UNITS_PER_WORD)),
2770
                      operand_subword (src, 1, TRUE, mode)));
2771
        }
2772
    }
2773
 
2774
  else
2775
    internal_error ("Unknown dest");
2776
 
2777
  val = get_insns ();
2778
  end_sequence ();
2779
  return val;
2780
}
2781
 
2782
/* The expander for the prologue pattern name.  */
2783
 
2784
void
2785
cris_expand_prologue (void)
2786
{
2787
  int regno;
2788
  int size = get_frame_size ();
2789
  /* Shorten the used name for readability.  */
2790
  int cfoa_size = crtl->outgoing_args_size;
2791
  int last_movem_reg = -1;
2792
  int framesize = 0;
2793
  rtx mem, insn;
2794
  int return_address_on_stack = cris_return_address_on_stack ();
2795
  int got_really_used = false;
2796
  int n_movem_regs = 0;
2797
  int pretend = crtl->args.pretend_args_size;
2798
 
2799
  /* Don't do anything if no prologues or epilogues are wanted.  */
2800
  if (!TARGET_PROLOGUE_EPILOGUE)
2801
    return;
2802
 
2803
  CRIS_ASSERT (size >= 0);
2804
 
2805
  if (crtl->uses_pic_offset_table)
2806
    {
2807
      /* A reference may have been optimized out (like the abort () in
2808
         fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2809
         it's still used.  */
2810
      push_topmost_sequence ();
2811
      got_really_used
2812
        = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
2813
      pop_topmost_sequence ();
2814
    }
2815
 
2816
  /* Align the size to what's best for the CPU model.  */
2817
  if (TARGET_STACK_ALIGN)
2818
    size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
2819
 
2820
  if (pretend)
2821
    {
2822
      /* See also cris_setup_incoming_varargs where
2823
         cfun->machine->stdarg_regs is set.  There are other setters of
2824
         crtl->args.pretend_args_size than stdarg handling, like
2825
         for an argument passed with parts in R13 and stack.  We must
2826
         not store R13 into the pretend-area for that case, as GCC does
2827
         that itself.  "Our" store would be marked as redundant and GCC
2828
         will attempt to remove it, which will then be flagged as an
2829
         internal error; trying to remove a frame-related insn.  */
2830
      int stdarg_regs = cfun->machine->stdarg_regs;
2831
 
2832
      framesize += pretend;
2833
 
2834
      for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1;
2835
           stdarg_regs > 0;
2836
           regno--, pretend -= 4, stdarg_regs--)
2837
        {
2838
          insn = emit_insn (gen_rtx_SET (VOIDmode,
2839
                                         stack_pointer_rtx,
2840
                                         plus_constant (stack_pointer_rtx,
2841
                                                        -4)));
2842
          /* FIXME: When dwarf2 frame output and unless asynchronous
2843
             exceptions, make dwarf2 bundle together all stack
2844
             adjustments like it does for registers between stack
2845
             adjustments.  */
2846
          RTX_FRAME_RELATED_P (insn) = 1;
2847
 
2848
          mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2849
          set_mem_alias_set (mem, get_varargs_alias_set ());
2850
          insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2851
 
2852
          /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2853
             the value isn't restored, so we don't want to tell dwarf2
2854
             that it's been stored to stack, else EH handling info would
2855
             get confused.  */
2856
        }
2857
 
2858
      /* For other setters of crtl->args.pretend_args_size, we
2859
         just adjust the stack by leaving the remaining size in
2860
         "pretend", handled below.  */
2861
    }
2862
 
2863
  /* Save SRP if not a leaf function.  */
2864
  if (return_address_on_stack)
2865
    {
2866
      insn = emit_insn (gen_rtx_SET (VOIDmode,
2867
                                     stack_pointer_rtx,
2868
                                     plus_constant (stack_pointer_rtx,
2869
                                                    -4 - pretend)));
2870
      pretend = 0;
2871
      RTX_FRAME_RELATED_P (insn) = 1;
2872
 
2873
      mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2874
      set_mem_alias_set (mem, get_frame_alias_set ());
2875
      insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM));
2876
      RTX_FRAME_RELATED_P (insn) = 1;
2877
      framesize += 4;
2878
    }
2879
 
2880
  /* Set up the frame pointer, if needed.  */
2881
  if (frame_pointer_needed)
2882
    {
2883
      insn = emit_insn (gen_rtx_SET (VOIDmode,
2884
                                     stack_pointer_rtx,
2885
                                     plus_constant (stack_pointer_rtx,
2886
                                                    -4 - pretend)));
2887
      pretend = 0;
2888
      RTX_FRAME_RELATED_P (insn) = 1;
2889
 
2890
      mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2891
      set_mem_alias_set (mem, get_frame_alias_set ());
2892
      insn = emit_move_insn (mem, frame_pointer_rtx);
2893
      RTX_FRAME_RELATED_P (insn) = 1;
2894
 
2895
      insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2896
      RTX_FRAME_RELATED_P (insn) = 1;
2897
 
2898
      framesize += 4;
2899
    }
2900
 
2901
  /* Between frame-pointer and saved registers lie the area for local
2902
     variables.  If we get here with "pretended" size remaining, count
2903
     it into the general stack size.  */
2904
  size += pretend;
2905
 
2906
  /* Get a contiguous sequence of registers, starting with R0, that need
2907
     to be saved.  */
2908
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2909
    {
2910
      if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2911
        {
2912
          n_movem_regs++;
2913
 
2914
          /* Check if movem may be used for registers so far.  */
2915
          if (regno == last_movem_reg + 1)
2916
            /* Yes, update next expected register.  */
2917
            last_movem_reg = regno;
2918
          else
2919
            {
2920
              /* We cannot use movem for all registers.  We have to flush
2921
                 any movem:ed registers we got so far.  */
2922
              if (last_movem_reg != -1)
2923
                {
2924
                  int n_saved
2925
                    = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2926
 
2927
                  /* It is a win to use a side-effect assignment for
2928
                     64 <= size <= 128.  But side-effect on movem was
2929
                     not usable for CRIS v0..3.  Also only do it if
2930
                     side-effects insns are allowed.  */
2931
                  if ((last_movem_reg + 1) * 4 + size >= 64
2932
                      && (last_movem_reg + 1) * 4 + size <= 128
2933
                      && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2934
                      && TARGET_SIDE_EFFECT_PREFIXES)
2935
                    {
2936
                      mem
2937
                        = gen_rtx_MEM (SImode,
2938
                                       plus_constant (stack_pointer_rtx,
2939
                                                      -(n_saved * 4 + size)));
2940
                      set_mem_alias_set (mem, get_frame_alias_set ());
2941
                      insn
2942
                        = cris_emit_movem_store (mem, GEN_INT (n_saved),
2943
                                                 -(n_saved * 4 + size),
2944
                                                 true);
2945
                    }
2946
                  else
2947
                    {
2948
                      insn
2949
                        = gen_rtx_SET (VOIDmode,
2950
                                       stack_pointer_rtx,
2951
                                       plus_constant (stack_pointer_rtx,
2952
                                                      -(n_saved * 4 + size)));
2953
                      insn = emit_insn (insn);
2954
                      RTX_FRAME_RELATED_P (insn) = 1;
2955
 
2956
                      mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2957
                      set_mem_alias_set (mem, get_frame_alias_set ());
2958
                      insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
2959
                                                    0, true);
2960
                    }
2961
 
2962
                  framesize += n_saved * 4 + size;
2963
                  last_movem_reg = -1;
2964
                  size = 0;
2965
                }
2966
 
2967
              insn = emit_insn (gen_rtx_SET (VOIDmode,
2968
                                             stack_pointer_rtx,
2969
                                             plus_constant (stack_pointer_rtx,
2970
                                                            -4 - size)));
2971
              RTX_FRAME_RELATED_P (insn) = 1;
2972
 
2973
              mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2974
              set_mem_alias_set (mem, get_frame_alias_set ());
2975
              insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2976
              RTX_FRAME_RELATED_P (insn) = 1;
2977
 
2978
              framesize += 4 + size;
2979
              size = 0;
2980
            }
2981
        }
2982
    }
2983
 
2984
  /* Check after, if we could movem all registers.  This is the normal case.  */
2985
  if (last_movem_reg != -1)
2986
    {
2987
      int n_saved
2988
        = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2989
 
2990
      /* Side-effect on movem was not usable for CRIS v0..3.  Also only
2991
         do it if side-effects insns are allowed.  */
2992
      if ((last_movem_reg + 1) * 4 + size >= 64
2993
          && (last_movem_reg + 1) * 4 + size <= 128
2994
          && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2995
          && TARGET_SIDE_EFFECT_PREFIXES)
2996
        {
2997
          mem
2998
            = gen_rtx_MEM (SImode,
2999
                           plus_constant (stack_pointer_rtx,
3000
                                          -(n_saved * 4 + size)));
3001
          set_mem_alias_set (mem, get_frame_alias_set ());
3002
          insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
3003
                                        -(n_saved * 4 + size), true);
3004
        }
3005
      else
3006
        {
3007
          insn
3008
            = gen_rtx_SET (VOIDmode,
3009
                           stack_pointer_rtx,
3010
                           plus_constant (stack_pointer_rtx,
3011
                                          -(n_saved * 4 + size)));
3012
          insn = emit_insn (insn);
3013
          RTX_FRAME_RELATED_P (insn) = 1;
3014
 
3015
          mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3016
          set_mem_alias_set (mem, get_frame_alias_set ());
3017
          insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true);
3018
        }
3019
 
3020
      framesize += n_saved * 4 + size;
3021
      /* We have to put outgoing argument space after regs.  */
3022
      if (cfoa_size)
3023
        {
3024
          insn = emit_insn (gen_rtx_SET (VOIDmode,
3025
                                         stack_pointer_rtx,
3026
                                         plus_constant (stack_pointer_rtx,
3027
                                                        -cfoa_size)));
3028
          RTX_FRAME_RELATED_P (insn) = 1;
3029
          framesize += cfoa_size;
3030
        }
3031
    }
3032
  else if ((size + cfoa_size) > 0)
3033
    {
3034
      insn = emit_insn (gen_rtx_SET (VOIDmode,
3035
                                     stack_pointer_rtx,
3036
                                     plus_constant (stack_pointer_rtx,
3037
                                                    -(cfoa_size + size))));
3038
      RTX_FRAME_RELATED_P (insn) = 1;
3039
      framesize += size + cfoa_size;
3040
    }
3041
 
3042
  /* Set up the PIC register, if it is used.  */
3043
  if (got_really_used)
3044
    {
3045
      rtx got
3046
        = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT);
3047
      emit_move_insn (pic_offset_table_rtx, got);
3048
 
3049
      /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3050
         follow exceptional paths and tries to delete the GOT load as
3051
         unused, if it isn't used on the non-exceptional paths.  Other
3052
         ports have similar or other cover-ups, or plain bugs marking
3053
         the GOT register load as maybe-dead.  To see this, remove the
3054
         line below and try libsupc++/vec.cc or a trivial
3055
         "static void y (); void x () {try {y ();} catch (...) {}}".  */
3056
      emit_use (pic_offset_table_rtx);
3057
    }
3058
 
3059
  if (cris_max_stackframe && framesize > cris_max_stackframe)
3060
    warning (0, "stackframe too big: %d bytes", framesize);
3061
}
3062
 
3063
/* The expander for the epilogue pattern.  */
3064
 
3065
void
3066
cris_expand_epilogue (void)
3067
{
3068
  int regno;
3069
  int size = get_frame_size ();
3070
  int last_movem_reg = -1;
3071
  int argspace_offset = crtl->outgoing_args_size;
3072
  int pretend =  crtl->args.pretend_args_size;
3073
  rtx mem;
3074
  bool return_address_on_stack = cris_return_address_on_stack ();
3075
  /* A reference may have been optimized out
3076
     (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3077
     so check that it's still used.  */
3078
  int got_really_used = false;
3079
  int n_movem_regs = 0;
3080
 
3081
  if (!TARGET_PROLOGUE_EPILOGUE)
3082
    return;
3083
 
3084
  if (crtl->uses_pic_offset_table)
3085
    {
3086
      /* A reference may have been optimized out (like the abort () in
3087
         fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3088
         it's still used.  */
3089
      push_topmost_sequence ();
3090
      got_really_used
3091
        = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
3092
      pop_topmost_sequence ();
3093
    }
3094
 
3095
  /* Align byte count of stack frame.  */
3096
  if (TARGET_STACK_ALIGN)
3097
    size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
3098
 
3099
  /* Check how many saved regs we can movem.  They start at r0 and must
3100
     be contiguous.  */
3101
  for (regno = 0;
3102
       regno < FIRST_PSEUDO_REGISTER;
3103
       regno++)
3104
    if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3105
      {
3106
        n_movem_regs++;
3107
 
3108
        if (regno == last_movem_reg + 1)
3109
          last_movem_reg = regno;
3110
        else
3111
          break;
3112
      }
3113
 
3114
  /* If there was only one register that really needed to be saved
3115
     through movem, don't use movem.  */
3116
  if (n_movem_regs == 1)
3117
    last_movem_reg = -1;
3118
 
3119
  /* Now emit "normal" move insns for all regs higher than the movem
3120
     regs.  */
3121
  for (regno = FIRST_PSEUDO_REGISTER - 1;
3122
       regno > last_movem_reg;
3123
       regno--)
3124
    if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3125
      {
3126
        rtx insn;
3127
 
3128
        if (argspace_offset)
3129
          {
3130
            /* There is an area for outgoing parameters located before
3131
               the saved registers.  We have to adjust for that.  */
3132
            emit_insn (gen_rtx_SET (VOIDmode,
3133
                                    stack_pointer_rtx,
3134
                                    plus_constant (stack_pointer_rtx,
3135
                                                   argspace_offset)));
3136
            /* Make sure we only do this once.  */
3137
            argspace_offset = 0;
3138
          }
3139
 
3140
        mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
3141
                                                     stack_pointer_rtx));
3142
        set_mem_alias_set (mem, get_frame_alias_set ());
3143
        insn = emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem);
3144
 
3145
        /* Whenever we emit insns with post-incremented addresses
3146
           ourselves, we must add a post-inc note manually.  */
3147
        REG_NOTES (insn)
3148
          = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3149
      }
3150
 
3151
  /* If we have any movem-restore, do it now.  */
3152
  if (last_movem_reg != -1)
3153
    {
3154
      rtx insn;
3155
 
3156
      if (argspace_offset)
3157
        {
3158
          emit_insn (gen_rtx_SET (VOIDmode,
3159
                                  stack_pointer_rtx,
3160
                                  plus_constant (stack_pointer_rtx,
3161
                                                 argspace_offset)));
3162
          argspace_offset = 0;
3163
        }
3164
 
3165
      mem = gen_rtx_MEM (SImode,
3166
                         gen_rtx_POST_INC (SImode, stack_pointer_rtx));
3167
      set_mem_alias_set (mem, get_frame_alias_set ());
3168
      insn
3169
        = emit_insn (cris_gen_movem_load (mem,
3170
                                          GEN_INT (last_movem_reg + 1), 0));
3171
      /* Whenever we emit insns with post-incremented addresses
3172
         ourselves, we must add a post-inc note manually.  */
3173
      if (side_effects_p (PATTERN (insn)))
3174
        REG_NOTES (insn)
3175
          = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3176
    }
3177
 
3178
  /* If we don't clobber all of the allocated stack area (we've already
3179
     deallocated saved registers), GCC might want to schedule loads from
3180
     the stack to *after* the stack-pointer restore, which introduces an
3181
     interrupt race condition.  This happened for the initial-value
3182
     SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3183
     other failure for that test).  It also happened for the stack slot
3184
     for the return value in (one version of)
3185
     linux/fs/dcache.c:__d_lookup, at least with "-O2
3186
     -fno-omit-frame-pointer".  */
3187
 
3188
  /* Restore frame pointer if necessary.  */
3189
  if (frame_pointer_needed)
3190
    {
3191
      rtx insn;
3192
 
3193
      emit_insn (gen_cris_frame_deallocated_barrier ());
3194
 
3195
      emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
3196
      mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
3197
                                                   stack_pointer_rtx));
3198
      set_mem_alias_set (mem, get_frame_alias_set ());
3199
      insn = emit_move_insn (frame_pointer_rtx, mem);
3200
 
3201
      /* Whenever we emit insns with post-incremented addresses
3202
         ourselves, we must add a post-inc note manually.  */
3203
      REG_NOTES (insn)
3204
        = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3205
    }
3206
  else if ((size + argspace_offset) != 0)
3207
    {
3208
      emit_insn (gen_cris_frame_deallocated_barrier ());
3209
 
3210
      /* If there was no frame-pointer to restore sp from, we must
3211
         explicitly deallocate local variables.  */
3212
 
3213
      /* Handle space for outgoing parameters that hasn't been handled
3214
         yet.  */
3215
      size += argspace_offset;
3216
 
3217
      emit_insn (gen_rtx_SET (VOIDmode,
3218
                              stack_pointer_rtx,
3219
                              plus_constant (stack_pointer_rtx, size)));
3220
    }
3221
 
3222
  /* If this function has no pushed register parameters
3223
     (stdargs/varargs), and if it is not a leaf function, then we have
3224
     the return address on the stack.  */
3225
  if (return_address_on_stack && pretend == 0)
3226
    {
3227
      if (TARGET_V32 || crtl->calls_eh_return)
3228
        {
3229
          rtx mem;
3230
          rtx insn;
3231
          rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
3232
          mem = gen_rtx_MEM (SImode,
3233
                             gen_rtx_POST_INC (SImode,
3234
                                               stack_pointer_rtx));
3235
          set_mem_alias_set (mem, get_frame_alias_set ());
3236
          insn = emit_move_insn (srpreg, mem);
3237
 
3238
          /* Whenever we emit insns with post-incremented addresses
3239
             ourselves, we must add a post-inc note manually.  */
3240
          REG_NOTES (insn)
3241
            = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3242
 
3243
          if (crtl->calls_eh_return)
3244
            emit_insn (gen_addsi3 (stack_pointer_rtx,
3245
                                   stack_pointer_rtx,
3246
                                   gen_rtx_raw_REG (SImode,
3247
                                                    CRIS_STACKADJ_REG)));
3248
          cris_expand_return (false);
3249
        }
3250
      else
3251
        cris_expand_return (true);
3252
 
3253
      return;
3254
    }
3255
 
3256
  /* If we pushed some register parameters, then adjust the stack for
3257
     them.  */
3258
  if (pretend != 0)
3259
    {
3260
      /* If SRP is stored on the way, we need to restore it first.  */
3261
      if (return_address_on_stack)
3262
        {
3263
          rtx mem;
3264
          rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
3265
          rtx insn;
3266
 
3267
          mem = gen_rtx_MEM (SImode,
3268
                             gen_rtx_POST_INC (SImode,
3269
                                               stack_pointer_rtx));
3270
          set_mem_alias_set (mem, get_frame_alias_set ());
3271
          insn = emit_move_insn (srpreg, mem);
3272
 
3273
          /* Whenever we emit insns with post-incremented addresses
3274
             ourselves, we must add a post-inc note manually.  */
3275
          REG_NOTES (insn)
3276
            = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3277
        }
3278
 
3279
      emit_insn (gen_rtx_SET (VOIDmode,
3280
                              stack_pointer_rtx,
3281
                              plus_constant (stack_pointer_rtx, pretend)));
3282
    }
3283
 
3284
  /* Perform the "physical" unwinding that the EH machinery calculated.  */
3285
  if (crtl->calls_eh_return)
3286
    emit_insn (gen_addsi3 (stack_pointer_rtx,
3287
                           stack_pointer_rtx,
3288
                           gen_rtx_raw_REG (SImode,
3289
                                            CRIS_STACKADJ_REG)));
3290
  cris_expand_return (false);
3291
}
3292
 
3293
/* Worker function for generating movem from mem for load_multiple.  */
3294
 
3295
rtx
3296
cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix)
3297
{
3298
  int nregs = INTVAL (nregs_rtx);
3299
  rtvec vec;
3300
  int eltno = 1;
3301
  int i;
3302
  rtx srcreg = XEXP (src, 0);
3303
  unsigned int regno = nregs - 1;
3304
  int regno_inc = -1;
3305
 
3306
  if (TARGET_V32)
3307
    {
3308
      regno = 0;
3309
      regno_inc = 1;
3310
    }
3311
 
3312
  if (GET_CODE (srcreg) == POST_INC)
3313
    srcreg = XEXP (srcreg, 0);
3314
 
3315
  CRIS_ASSERT (REG_P (srcreg));
3316
 
3317
  /* Don't use movem for just one insn.  The insns are equivalent except
3318
     for the pipeline hazard (on v32); movem does not forward the loaded
3319
     registers so there's a three cycles penalty for their use.  */
3320
  if (nregs == 1)
3321
    return gen_movsi (gen_rtx_REG (SImode, 0), src);
3322
 
3323
  vec = rtvec_alloc (nprefix + nregs
3324
                     + (GET_CODE (XEXP (src, 0)) == POST_INC));
3325
 
3326
  if (GET_CODE (XEXP (src, 0)) == POST_INC)
3327
    {
3328
      RTVEC_ELT (vec, nprefix + 1)
3329
        = gen_rtx_SET (VOIDmode, srcreg, plus_constant (srcreg, nregs * 4));
3330
      eltno++;
3331
    }
3332
 
3333
  src = replace_equiv_address (src, srcreg);
3334
  RTVEC_ELT (vec, nprefix)
3335
    = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src);
3336
  regno += regno_inc;
3337
 
3338
  for (i = 1; i < nregs; i++, eltno++)
3339
    {
3340
      RTVEC_ELT (vec, nprefix + eltno)
3341
        = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno),
3342
                       adjust_address_nv (src, SImode, i * 4));
3343
      regno += regno_inc;
3344
    }
3345
 
3346
  return gen_rtx_PARALLEL (VOIDmode, vec);
3347
}
3348
 
3349
/* Worker function for generating movem to mem.  If FRAME_RELATED, notes
3350
   are added that the dwarf2 machinery understands.  */
3351
 
3352
rtx
3353
cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment,
3354
                       bool frame_related)
3355
{
3356
  int nregs = INTVAL (nregs_rtx);
3357
  rtvec vec;
3358
  int eltno = 1;
3359
  int i;
3360
  rtx insn;
3361
  rtx destreg = XEXP (dest, 0);
3362
  unsigned int regno = nregs - 1;
3363
  int regno_inc = -1;
3364
 
3365
  if (TARGET_V32)
3366
    {
3367
      regno = 0;
3368
      regno_inc = 1;
3369
    }
3370
 
3371
  if (GET_CODE (destreg) == POST_INC)
3372
    increment += nregs * 4;
3373
 
3374
  if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS)
3375
    destreg = XEXP (destreg, 0);
3376
 
3377
  CRIS_ASSERT (REG_P (destreg));
3378
 
3379
  /* Don't use movem for just one insn.  The insns are equivalent except
3380
     for the pipeline hazard (on v32); movem does not forward the loaded
3381
     registers so there's a three cycles penalty for use.  */
3382
  if (nregs == 1)
3383
    {
3384
      rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0));
3385
 
3386
      if (increment == 0)
3387
        {
3388
          insn = emit_insn (mov);
3389
          if (frame_related)
3390
            RTX_FRAME_RELATED_P (insn) = 1;
3391
          return insn;
3392
        }
3393
 
3394
      /* If there was a request for a side-effect, create the ordinary
3395
         parallel.  */
3396
      vec = rtvec_alloc (2);
3397
 
3398
      RTVEC_ELT (vec, 0) = mov;
3399
      RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg,
3400
                                        plus_constant (destreg, increment));
3401
      if (frame_related)
3402
        {
3403
          RTX_FRAME_RELATED_P (mov) = 1;
3404
          RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3405
        }
3406
    }
3407
  else
3408
    {
3409
      vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0));
3410
      RTVEC_ELT (vec, 0)
3411
        = gen_rtx_SET (VOIDmode,
3412
                       replace_equiv_address (dest,
3413
                                              plus_constant (destreg,
3414
                                                             increment)),
3415
                       gen_rtx_REG (SImode, regno));
3416
      regno += regno_inc;
3417
 
3418
      /* The dwarf2 info wants this mark on each component in a parallel
3419
         that's part of the prologue (though it's optional on the first
3420
         component).  */
3421
      if (frame_related)
3422
        RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1;
3423
 
3424
      if (increment != 0)
3425
        {
3426
          RTVEC_ELT (vec, 1)
3427
            = gen_rtx_SET (VOIDmode, destreg,
3428
                           plus_constant (destreg,
3429
                                          increment != 0
3430
                                          ? increment : nregs * 4));
3431
          eltno++;
3432
 
3433
          if (frame_related)
3434
            RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3435
 
3436
          /* Don't call adjust_address_nv on a post-incremented address if
3437
             we can help it.  */
3438
          if (GET_CODE (XEXP (dest, 0)) == POST_INC)
3439
            dest = replace_equiv_address (dest, destreg);
3440
        }
3441
 
3442
      for (i = 1; i < nregs; i++, eltno++)
3443
        {
3444
          RTVEC_ELT (vec, eltno)
3445
            = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4),
3446
                           gen_rtx_REG (SImode, regno));
3447
          if (frame_related)
3448
            RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1;
3449
          regno += regno_inc;
3450
        }
3451
    }
3452
 
3453
  insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
3454
 
3455
  /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3456
     we need to keep the stack adjustment separate, after the
3457
     MEM-setters.  Else the stack-adjustment in the second component of
3458
     the parallel would be mishandled; the offsets for the SETs that
3459
     follow it would be wrong.  We prepare for this by adding a
3460
     REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3461
     followed by the increment.  Note that we have FRAME_RELATED_P on
3462
     all the SETs, including the original stack adjustment SET in the
3463
     parallel.  */
3464
  if (frame_related)
3465
    {
3466
      if (increment != 0)
3467
        {
3468
          rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1));
3469
          XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0));
3470
          for (i = 1; i < nregs; i++)
3471
            XVECEXP (seq, 0, i)
3472
              = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1));
3473
          XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1));
3474
          REG_NOTES (insn)
3475
            = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, seq,
3476
                                 REG_NOTES (insn));
3477
        }
3478
 
3479
      RTX_FRAME_RELATED_P (insn) = 1;
3480
    }
3481
 
3482
  return insn;
3483
}
3484
 
3485
/* Worker function for expanding the address for PIC function calls.  */
3486
 
3487
void
3488
cris_expand_pic_call_address (rtx *opp)
3489
{
3490
  rtx op = *opp;
3491
 
3492
  gcc_assert (MEM_P (op));
3493
  op = XEXP (op, 0);
3494
 
3495
  /* It might be that code can be generated that jumps to 0 (or to a
3496
     specific address).  Don't die on that.  (There is a
3497
     testcase.)  */
3498
  if (CONSTANT_ADDRESS_P (op) && !CONST_INT_P (op))
3499
    {
3500
      enum cris_pic_symbol_type t = cris_pic_symbol_type_of (op);
3501
 
3502
      CRIS_ASSERT (can_create_pseudo_p ());
3503
 
3504
      /* For local symbols (non-PLT), just get the plain symbol
3505
         reference into a register.  For symbols that can be PLT, make
3506
         them PLT.  */
3507
      if (t == cris_rel_symbol)
3508
        {
3509
          /* For v32, we're fine as-is; just PICify the symbol.  Forcing
3510
             into a register caused performance regression for 3.2.1,
3511
             observable in __floatdidf and elsewhere in libgcc.  */
3512
          if (TARGET_V32)
3513
            {
3514
              rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op);
3515
              HOST_WIDE_INT offs = get_integer_term (op);
3516
 
3517
              /* We can't get calls to sym+N, N integer, can we?  */
3518
              gcc_assert (offs == 0);
3519
 
3520
              op = gen_rtx_CONST (Pmode,
3521
                                  gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
3522
                                                  CRIS_UNSPEC_PCREL));
3523
            }
3524
          else
3525
            op = force_reg (Pmode, op);
3526
        }
3527
      else if (t == cris_got_symbol)
3528
        {
3529
          if (TARGET_AVOID_GOTPLT)
3530
            {
3531
              /* Change a "jsr sym" into (allocate register rM, rO)
3532
                 "move.d (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_GOTREL)),rM"
3533
                 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3534
                 "jsr (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_PCREL))"
3535
                 for v32.  */
3536
              rtx tem, rm, ro;
3537
              gcc_assert (can_create_pseudo_p ());
3538
              crtl->uses_pic_offset_table = 1;
3539
              tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3540
                                    TARGET_V32
3541
                                    ? CRIS_UNSPEC_PLT_PCREL
3542
                                    : CRIS_UNSPEC_PLT_GOTREL);
3543
              tem = gen_rtx_CONST (Pmode, tem);
3544
              if (TARGET_V32)
3545
                op = tem;
3546
              else
3547
                {
3548
                  rm = gen_reg_rtx (Pmode);
3549
                  emit_move_insn (rm, tem);
3550
                  ro = gen_reg_rtx (Pmode);
3551
                  if (expand_binop (Pmode, add_optab, rm,
3552
                                    pic_offset_table_rtx,
3553
                                    ro, 0, OPTAB_LIB_WIDEN) != ro)
3554
                    internal_error ("expand_binop failed in movsi got");
3555
                  op = ro;
3556
                }
3557
            }
3558
          else
3559
            {
3560
              /* Change a "jsr sym" into (allocate register rM, rO)
3561
                 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3562
                 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3563
                 marked as not trapping and not aliasing.  No "move.d
3564
                 [rO],rP" as that would invite to re-use of a value
3565
                 that should not be reused.  FIXME: Need a peephole2
3566
                 for cases when this is cse:d from the call, to change
3567
                 back to just get the PLT entry address, so we don't
3568
                 resolve the same symbol over and over (the memory
3569
                 access of the PLTGOT isn't constant).  */
3570
              rtx tem, mem, rm, ro;
3571
 
3572
              gcc_assert (can_create_pseudo_p ());
3573
              crtl->uses_pic_offset_table = 1;
3574
              tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3575
                                    CRIS_UNSPEC_PLTGOTREAD);
3576
              rm = gen_reg_rtx (Pmode);
3577
              emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3578
              ro = gen_reg_rtx (Pmode);
3579
              if (expand_binop (Pmode, add_optab, rm,
3580
                                pic_offset_table_rtx,
3581
                                ro, 0, OPTAB_LIB_WIDEN) != ro)
3582
                internal_error ("expand_binop failed in movsi got");
3583
              mem = gen_rtx_MEM (Pmode, ro);
3584
 
3585
              /* This MEM doesn't alias anything.  Whether it aliases
3586
                 other same symbols is unimportant.  */
3587
              set_mem_alias_set (mem, new_alias_set ());
3588
              MEM_NOTRAP_P (mem) = 1;
3589
              op = mem;
3590
            }
3591
        }
3592
      else
3593
        /* Can't possibly get a GOT-needing-fixup for a function-call,
3594
           right?  */
3595
        fatal_insn ("Unidentifiable call op", op);
3596
 
3597
      *opp = replace_equiv_address (*opp, op);
3598
    }
3599
}
3600
 
3601
/* Make sure operands are in the right order for an addsi3 insn as
3602
   generated by a define_split.  Nothing but REG_P as the first
3603
   operand is recognized by addsi3 after reload.  OPERANDS contains
3604
   the operands, with the first at OPERANDS[N] and the second at
3605
   OPERANDS[N+1].  */
3606
 
3607
void
3608
cris_order_for_addsi3 (rtx *operands, int n)
3609
{
3610
  if (!REG_P (operands[n]))
3611
    {
3612
      rtx tem = operands[n];
3613
      operands[n] = operands[n + 1];
3614
      operands[n + 1] = tem;
3615
    }
3616
}
3617
 
3618
/* Use from within code, from e.g. PRINT_OPERAND and
3619
   PRINT_OPERAND_ADDRESS.  Macros used in output_addr_const need to emit
3620
   different things depending on whether code operand or constant is
3621
   emitted.  */
3622
 
3623
static void
3624
cris_output_addr_const (FILE *file, rtx x)
3625
{
3626
  in_code++;
3627
  output_addr_const (file, x);
3628
  in_code--;
3629
}
3630
 
3631
/* Worker function for ASM_OUTPUT_SYMBOL_REF.  */
3632
 
3633
void
3634
cris_asm_output_symbol_ref (FILE *file, rtx x)
3635
{
3636
  gcc_assert (GET_CODE (x) == SYMBOL_REF);
3637
 
3638
  if (flag_pic && in_code > 0)
3639
    {
3640
     const char *origstr = XSTR (x, 0);
3641
     const char *str;
3642
     str = (* targetm.strip_name_encoding) (origstr);
3643
     assemble_name (file, str);
3644
 
3645
     /* Sanity check.  */
3646
     if (!TARGET_V32 && !crtl->uses_pic_offset_table)
3647
       output_operand_lossage ("PIC register isn't set up");
3648
    }
3649
  else
3650
    assemble_name (file, XSTR (x, 0));
3651
}
3652
 
3653
/* Worker function for ASM_OUTPUT_LABEL_REF.  */
3654
 
3655
void
3656
cris_asm_output_label_ref (FILE *file, char *buf)
3657
{
3658
  if (flag_pic && in_code > 0)
3659
    {
3660
      assemble_name (file, buf);
3661
 
3662
      /* Sanity check.  */
3663
      if (!TARGET_V32 && !crtl->uses_pic_offset_table)
3664
        internal_error ("emitting PIC operand, but PIC register isn't set up");
3665
    }
3666
  else
3667
    assemble_name (file, buf);
3668
}
3669
 
3670
/* Worker function for OUTPUT_ADDR_CONST_EXTRA.  */
3671
 
3672
bool
3673
cris_output_addr_const_extra (FILE *file, rtx xconst)
3674
{
3675
  switch (GET_CODE (xconst))
3676
    {
3677
      rtx x;
3678
 
3679
    case UNSPEC:
3680
      x = XVECEXP (xconst, 0, 0);
3681
      CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
3682
                   || GET_CODE (x) == LABEL_REF
3683
                   || GET_CODE (x) == CONST);
3684
      output_addr_const (file, x);
3685
      switch (XINT (xconst, 1))
3686
        {
3687
        case CRIS_UNSPEC_PCREL:
3688
          /* We only get this with -fpic/PIC to tell it apart from an
3689
             invalid symbol.  We can't tell here, but it should only
3690
             be the operand of a call or movsi.  */
3691
          gcc_assert (TARGET_V32 && flag_pic);
3692
          break;
3693
 
3694
        case CRIS_UNSPEC_PLT_PCREL:
3695
          gcc_assert (TARGET_V32);
3696
          fprintf (file, ":PLT");
3697
          break;
3698
 
3699
        case CRIS_UNSPEC_PLT_GOTREL:
3700
          gcc_assert (!TARGET_V32);
3701
          fprintf (file, ":PLTG");
3702
          break;
3703
 
3704
        case CRIS_UNSPEC_GOTREL:
3705
          gcc_assert (!TARGET_V32);
3706
          fprintf (file, ":GOTOFF");
3707
          break;
3708
 
3709
        case CRIS_UNSPEC_GOTREAD:
3710
          if (flag_pic == 1)
3711
            fprintf (file, ":GOT16");
3712
          else
3713
            fprintf (file, ":GOT");
3714
          break;
3715
 
3716
        case CRIS_UNSPEC_PLTGOTREAD:
3717
          if (flag_pic == 1)
3718
            fprintf (file, CRIS_GOTPLT_SUFFIX "16");
3719
          else
3720
            fprintf (file, CRIS_GOTPLT_SUFFIX);
3721
          break;
3722
 
3723
        default:
3724
          gcc_unreachable ();
3725
        }
3726
      return true;
3727
 
3728
    default:
3729
      return false;
3730
    }
3731
}
3732
 
3733
/* Worker function for TARGET_STRUCT_VALUE_RTX.  */
3734
 
3735
static rtx
3736
cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
3737
                       int incoming ATTRIBUTE_UNUSED)
3738
{
3739
  return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM);
3740
}
3741
 
3742
/* Worker function for TARGET_SETUP_INCOMING_VARARGS.  */
3743
 
3744
static void
3745
cris_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
3746
                             enum machine_mode mode ATTRIBUTE_UNUSED,
3747
                             tree type ATTRIBUTE_UNUSED,
3748
                             int *pretend_arg_size,
3749
                             int second_time)
3750
{
3751
  if (ca->regs < CRIS_MAX_ARGS_IN_REGS)
3752
    {
3753
      int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs;
3754
      cfun->machine->stdarg_regs = stdarg_regs;
3755
      *pretend_arg_size = stdarg_regs * 4;
3756
    }
3757
 
3758
  if (TARGET_PDEBUG)
3759
    fprintf (asm_out_file,
3760
             "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3761
             ca->regs, *pretend_arg_size, second_time);
3762
}
3763
 
3764
/* Return true if TYPE must be passed by invisible reference.
3765
   For cris, we pass <= 8 bytes by value, others by reference.  */
3766
 
3767
static bool
3768
cris_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
3769
                        enum machine_mode mode, const_tree type,
3770
                        bool named ATTRIBUTE_UNUSED)
3771
{
3772
  return (targetm.calls.must_pass_in_stack (mode, type)
3773
          || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8);
3774
}
3775
 
3776
/* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
3777
   and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
3778
   best code size and speed for gcc, ipps and products in gcc-2.7.2.  */
3779
 
3780
enum machine_mode
3781
cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
3782
                            enum machine_mode mode,
3783
                            int *punsignedp ATTRIBUTE_UNUSED,
3784
                            const_tree fntype ATTRIBUTE_UNUSED,
3785
                            int for_return)
3786
{
3787
  /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
3788
     when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
3789
     Maybe pointless as of now, but let's keep the old behavior.  */
3790
  if (for_return == 1)
3791
    return mode;
3792
  return CRIS_PROMOTED_MODE (mode, *punsignedp, type);
3793
}
3794
 
3795
/* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3796
   time being.  */
3797
 
3798
static rtx
3799
cris_function_value(const_tree type,
3800
                    const_tree func ATTRIBUTE_UNUSED,
3801
                    bool outgoing ATTRIBUTE_UNUSED)
3802
{
3803
  return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG);
3804
}
3805
 
3806
/* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3807
   time being.  */
3808
 
3809
static rtx
3810
cris_libcall_value (enum machine_mode mode,
3811
                    const_rtx fun ATTRIBUTE_UNUSED)
3812
{
3813
  return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG);
3814
}
3815
 
3816
/* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3817
   time being.  */
3818
 
3819
bool
3820
cris_function_value_regno_p (const unsigned int regno)
3821
{
3822
  return (regno == CRIS_FIRST_ARG_REG);
3823
}
3824
 
3825
static int
3826
cris_arg_partial_bytes (CUMULATIVE_ARGS *ca, enum machine_mode mode,
3827
                        tree type, bool named ATTRIBUTE_UNUSED)
3828
{
3829
  if (ca->regs == CRIS_MAX_ARGS_IN_REGS - 1
3830
      && !targetm.calls.must_pass_in_stack (mode, type)
3831
      && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4
3832
      && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8)
3833
    return UNITS_PER_WORD;
3834
  else
3835
    return 0;
3836
}
3837
 
3838
/* Worker function for TARGET_MD_ASM_CLOBBERS.  */
3839
 
3840
static tree
3841
cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers)
3842
{
3843
  HARD_REG_SET mof_set;
3844
  tree clobbers;
3845
  tree t;
3846
 
3847
  CLEAR_HARD_REG_SET (mof_set);
3848
  SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM);
3849
 
3850
  /* For the time being, all asms clobber condition codes.  Revisit when
3851
     there's a reasonable use for inputs/outputs that mention condition
3852
     codes.  */
3853
  clobbers
3854
    = tree_cons (NULL_TREE,
3855
                 build_string (strlen (reg_names[CRIS_CC0_REGNUM]),
3856
                               reg_names[CRIS_CC0_REGNUM]),
3857
                 in_clobbers);
3858
 
3859
  for (t = outputs; t != NULL; t = TREE_CHAIN (t))
3860
    {
3861
      tree val = TREE_VALUE (t);
3862
 
3863
      /* The constraint letter for the singleton register class of MOF
3864
         is 'h'.  If it's mentioned in the constraints, the asm is
3865
         MOF-aware and adding it to the clobbers would cause it to have
3866
         impossible constraints.  */
3867
      if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3868
                  'h') != NULL
3869
          || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
3870
        return clobbers;
3871
    }
3872
 
3873
  for (t = inputs; t != NULL; t = TREE_CHAIN (t))
3874
    {
3875
      tree val = TREE_VALUE (t);
3876
 
3877
      if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3878
                  'h') != NULL
3879
          || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
3880
        return clobbers;
3881
    }
3882
 
3883
  return tree_cons (NULL_TREE,
3884
                    build_string (strlen (reg_names[CRIS_MOF_REGNUM]),
3885
                                  reg_names[CRIS_MOF_REGNUM]),
3886
                    clobbers);
3887
}
3888
 
3889
/* Implement TARGET_FRAME_POINTER_REQUIRED.
3890
 
3891
   Really only needed if the stack frame has variable length (alloca
3892
   or variable sized local arguments (GNU C extension).  See PR39499 and
3893
   PR38609 for the reason this isn't just 0.  */
3894
 
3895
bool
3896
cris_frame_pointer_required (void)
3897
{
3898
  return !current_function_sp_is_unchanging;
3899
}
3900
 
3901
/* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
3902
 
3903
   This looks too complicated, and it is.  I assigned r7 to be the
3904
   static chain register, but it is call-saved, so we have to save it,
3905
   and come back to restore it after the call, so we have to save srp...
3906
   Anyway, trampolines are rare enough that we can cope with this
3907
   somewhat lack of elegance.
3908
    (Do not be tempted to "straighten up" whitespace in the asms; the
3909
   assembler #NO_APP state mandates strict spacing).  */
3910
/* ??? See the i386 regparm=3 implementation that pushes the static
3911
   chain value to the stack in the trampoline, and uses a call-saved
3912
   register when called directly.  */
3913
 
3914
static void
3915
cris_asm_trampoline_template (FILE *f)
3916
{
3917
  if (TARGET_V32)
3918
    {
3919
      /* This normally-unused nop insn acts as an instruction to
3920
         the simulator to flush its instruction cache.  None of
3921
         the other instructions in the trampoline template suits
3922
         as a trigger for V32.  The pc-relative addressing mode
3923
         works nicely as a trigger for V10.
3924
         FIXME: Have specific V32 template (possibly avoiding the
3925
         use of a special instruction).  */
3926
      fprintf (f, "\tclearf x\n");
3927
      /* We have to use a register as an intermediate, choosing
3928
         semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
3929
         so we can use it for address indirection and jsr target.  */
3930
      fprintf (f, "\tmove $r1,$mof\n");
3931
      /* +4 */
3932
      fprintf (f, "\tmove.d 0,$r1\n");
3933
      fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]);
3934
      fprintf (f, "\taddq 6,$r1\n");
3935
      fprintf (f, "\tmove $mof,[$r1]\n");
3936
      fprintf (f, "\taddq 6,$r1\n");
3937
      fprintf (f, "\tmove $srp,[$r1]\n");
3938
      /* +20 */
3939
      fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
3940
      /* +26 */
3941
      fprintf (f, "\tmove.d 0,$r1\n");
3942
      fprintf (f, "\tjsr $r1\n");
3943
      fprintf (f, "\tsetf\n");
3944
      /* +36 */
3945
      fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
3946
      /* +42 */
3947
      fprintf (f, "\tmove.d 0,$r1\n");
3948
      /* +48 */
3949
      fprintf (f, "\tmove.d 0,$r9\n");
3950
      fprintf (f, "\tjump $r9\n");
3951
      fprintf (f, "\tsetf\n");
3952
    }
3953
  else
3954
    {
3955
      fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]);
3956
      fprintf (f, "\tmove $srp,[$pc+22]\n");
3957
      fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
3958
      fprintf (f, "\tjsr 0\n");
3959
      fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
3960
      fprintf (f, "\tjump 0\n");
3961
    }
3962
}
3963
 
3964
/* Implement TARGET_TRAMPOLINE_INIT.  */
3965
 
3966
static void
3967
cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
3968
{
3969
  rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
3970
  rtx tramp = XEXP (m_tramp, 0);
3971
  rtx mem;
3972
 
3973
  emit_block_move (m_tramp, assemble_trampoline_template (),
3974
                   GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
3975
 
3976
  if (TARGET_V32)
3977
    {
3978
      mem = adjust_address (m_tramp, SImode, 6);
3979
      emit_move_insn (mem, plus_constant (tramp, 38));
3980
      mem = adjust_address (m_tramp, SImode, 22);
3981
      emit_move_insn (mem, chain_value);
3982
      mem = adjust_address (m_tramp, SImode, 28);
3983
      emit_move_insn (mem, fnaddr);
3984
    }
3985
  else
3986
    {
3987
      mem = adjust_address (m_tramp, SImode, 10);
3988
      emit_move_insn (mem, chain_value);
3989
      mem = adjust_address (m_tramp, SImode, 16);
3990
      emit_move_insn (mem, fnaddr);
3991
    }
3992
 
3993
  /* Note that there is no need to do anything with the cache for
3994
     sake of a trampoline.  */
3995
}
3996
 
3997
 
3998
#if 0
3999
/* Various small functions to replace macros.  Only called from a
4000
   debugger.  They might collide with gcc functions or system functions,
4001
   so only emit them when '#if 1' above.  */
4002
 
4003
enum rtx_code Get_code (rtx);
4004
 
4005
enum rtx_code
4006
Get_code (rtx x)
4007
{
4008
  return GET_CODE (x);
4009
}
4010
 
4011
const char *Get_mode (rtx);
4012
 
4013
const char *
4014
Get_mode (rtx x)
4015
{
4016
  return GET_MODE_NAME (GET_MODE (x));
4017
}
4018
 
4019
rtx Xexp (rtx, int);
4020
 
4021
rtx
4022
Xexp (rtx x, int n)
4023
{
4024
  return XEXP (x, n);
4025
}
4026
 
4027
rtx Xvecexp (rtx, int, int);
4028
 
4029
rtx
4030
Xvecexp (rtx x, int n, int m)
4031
{
4032
  return XVECEXP (x, n, m);
4033
}
4034
 
4035
int Get_rtx_len (rtx);
4036
 
4037
int
4038
Get_rtx_len (rtx x)
4039
{
4040
  return GET_RTX_LENGTH (GET_CODE (x));
4041
}
4042
 
4043
/* Use upper-case to distinguish from local variables that are sometimes
4044
   called next_insn and prev_insn.  */
4045
 
4046
rtx Next_insn (rtx);
4047
 
4048
rtx
4049
Next_insn (rtx insn)
4050
{
4051
  return NEXT_INSN (insn);
4052
}
4053
 
4054
rtx Prev_insn (rtx);
4055
 
4056
rtx
4057
Prev_insn (rtx insn)
4058
{
4059
  return PREV_INSN (insn);
4060
}
4061
#endif
4062
 
4063
#include "gt-cris.h"
4064
 
4065
/*
4066
 * Local variables:
4067
 * eval: (c-set-style "gnu")
4068
 * indent-tabs-mode: t
4069
 * End:
4070
 */

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