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1 282 jeremybenn
;; Predicate definitions for Frv.
2
;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
3
;;
4
;; This file is part of GCC.
5
;;
6
;; GCC is free software; you can redistribute it and/or modify
7
;; it under the terms of the GNU General Public License as published by
8
;; the Free Software Foundation; either version 3, or (at your option)
9
;; any later version.
10
;;
11
;; GCC is distributed in the hope that it will be useful,
12
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
;; GNU General Public License for more details.
15
;;
16
;; You should have received a copy of the GNU General Public License
17
;; along with GCC; see the file COPYING3.  If not see
18
;; .
19
 
20
;; Return true if operand is a GPR register.
21
 
22
(define_predicate "integer_register_operand"
23
  (match_code "reg,subreg")
24
{
25
  if (GET_MODE (op) != mode && mode != VOIDmode)
26
    return FALSE;
27
 
28
  if (GET_CODE (op) == SUBREG)
29
    {
30
      if (GET_CODE (SUBREG_REG (op)) != REG)
31
        return register_operand (op, mode);
32
 
33
      op = SUBREG_REG (op);
34
    }
35
 
36
  if (GET_CODE (op) != REG)
37
    return FALSE;
38
 
39
  return GPR_AP_OR_PSEUDO_P (REGNO (op));
40
})
41
 
42
;; Return 1 is OP is a memory operand, or will be turned into one by
43
;; reload.
44
 
45
(define_predicate "frv_load_operand"
46
  (match_code "reg,subreg,mem")
47
{
48
  if (GET_MODE (op) != mode && mode != VOIDmode)
49
    return FALSE;
50
 
51
  if (reload_in_progress)
52
    {
53
      rtx tmp = op;
54
      if (GET_CODE (tmp) == SUBREG)
55
        tmp = SUBREG_REG (tmp);
56
      if (GET_CODE (tmp) == REG
57
          && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
58
        op = reg_equiv_memory_loc[REGNO (tmp)];
59
    }
60
 
61
  return op && memory_operand (op, mode);
62
})
63
 
64
;; Return true if operand is a GPR register.  Do not allow SUBREG's
65
;; here, in order to prevent a combine bug.
66
 
67
(define_predicate "gpr_no_subreg_operand"
68
  (match_code "reg")
69
{
70
  if (GET_MODE (op) != mode && mode != VOIDmode)
71
    return FALSE;
72
 
73
  if (GET_CODE (op) != REG)
74
    return FALSE;
75
 
76
  return GPR_OR_PSEUDO_P (REGNO (op));
77
})
78
 
79
;; Return 1 if operand is a GPR register or a FPR register.
80
 
81
(define_predicate "gpr_or_fpr_operand"
82
  (match_code "reg,subreg")
83
{
84
  int regno;
85
 
86
  if (GET_MODE (op) != mode && mode != VOIDmode)
87
    return FALSE;
88
 
89
  if (GET_CODE (op) == SUBREG)
90
    {
91
      if (GET_CODE (SUBREG_REG (op)) != REG)
92
        return register_operand (op, mode);
93
 
94
      op = SUBREG_REG (op);
95
    }
96
 
97
  if (GET_CODE (op) != REG)
98
    return FALSE;
99
 
100
  regno = REGNO (op);
101
  if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
102
    return TRUE;
103
 
104
  return FALSE;
105
})
106
 
107
;; Return 1 if operand is a GPR register or 12-bit signed immediate.
108
 
109
(define_predicate "gpr_or_int12_operand"
110
  (match_code "reg,subreg,const_int,const")
111
{
112
  if (GET_CODE (op) == CONST_INT)
113
    return IN_RANGE_P (INTVAL (op), -2048, 2047);
114
 
115
  if (got12_operand (op, mode))
116
    return true;
117
 
118
  if (GET_MODE (op) != mode && mode != VOIDmode)
119
    return FALSE;
120
 
121
  if (GET_CODE (op) == SUBREG)
122
    {
123
      if (GET_CODE (SUBREG_REG (op)) != REG)
124
        return register_operand (op, mode);
125
 
126
      op = SUBREG_REG (op);
127
    }
128
 
129
  if (GET_CODE (op) != REG)
130
    return FALSE;
131
 
132
  return GPR_OR_PSEUDO_P (REGNO (op));
133
})
134
 
135
;; Return 1 if operand is a GPR register, or a FPR register, or a 12
136
;; bit signed immediate.
137
 
138
(define_predicate "gpr_fpr_or_int12_operand"
139
  (match_code "reg,subreg,const_int")
140
{
141
  int regno;
142
 
143
  if (GET_CODE (op) == CONST_INT)
144
    return IN_RANGE_P (INTVAL (op), -2048, 2047);
145
 
146
  if (GET_MODE (op) != mode && mode != VOIDmode)
147
    return FALSE;
148
 
149
  if (GET_CODE (op) == SUBREG)
150
    {
151
      if (GET_CODE (SUBREG_REG (op)) != REG)
152
        return register_operand (op, mode);
153
 
154
      op = SUBREG_REG (op);
155
    }
156
 
157
  if (GET_CODE (op) != REG)
158
    return FALSE;
159
 
160
  regno = REGNO (op);
161
  if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
162
    return TRUE;
163
 
164
  return FALSE;
165
})
166
 
167
;; Return 1 if operand is a register or 10-bit signed immediate.
168
 
169
(define_predicate "gpr_or_int10_operand"
170
  (match_code "reg,subreg,const_int")
171
{
172
  if (GET_CODE (op) == CONST_INT)
173
    return IN_RANGE_P (INTVAL (op), -512, 511);
174
 
175
  if (GET_MODE (op) != mode && mode != VOIDmode)
176
    return FALSE;
177
 
178
  if (GET_CODE (op) == SUBREG)
179
    {
180
      if (GET_CODE (SUBREG_REG (op)) != REG)
181
        return register_operand (op, mode);
182
 
183
      op = SUBREG_REG (op);
184
    }
185
 
186
  if (GET_CODE (op) != REG)
187
    return FALSE;
188
 
189
  return GPR_OR_PSEUDO_P (REGNO (op));
190
})
191
 
192
;; Return 1 if operand is a register or an integer immediate.
193
 
194
(define_predicate "gpr_or_int_operand"
195
  (match_code "reg,subreg,const_int")
196
{
197
  if (GET_CODE (op) == CONST_INT)
198
    return TRUE;
199
 
200
  if (GET_MODE (op) != mode && mode != VOIDmode)
201
    return FALSE;
202
 
203
  if (GET_CODE (op) == SUBREG)
204
    {
205
      if (GET_CODE (SUBREG_REG (op)) != REG)
206
        return register_operand (op, mode);
207
 
208
      op = SUBREG_REG (op);
209
    }
210
 
211
  if (GET_CODE (op) != REG)
212
    return FALSE;
213
 
214
  return GPR_OR_PSEUDO_P (REGNO (op));
215
})
216
 
217
;; Return true if operand is something that can be an input for a move
218
;; operation.
219
 
220
(define_predicate "move_source_operand"
221
  (match_code "reg,subreg,const_int,mem,const_double,const,symbol_ref,label_ref")
222
{
223
  rtx subreg;
224
  enum rtx_code code;
225
 
226
  switch (GET_CODE (op))
227
    {
228
    default:
229
      break;
230
 
231
    case CONST_INT:
232
    case CONST_DOUBLE:
233
      return immediate_operand (op, mode);
234
 
235
    case SUBREG:
236
      if (GET_MODE (op) != mode && mode != VOIDmode)
237
        return FALSE;
238
 
239
      subreg = SUBREG_REG (op);
240
      code = GET_CODE (subreg);
241
      if (code == MEM)
242
        return frv_legitimate_address_p_1 (mode, XEXP (subreg, 0),
243
                                           reload_completed, FALSE, FALSE);
244
 
245
      return (code == REG);
246
 
247
    case REG:
248
      if (GET_MODE (op) != mode && mode != VOIDmode)
249
        return FALSE;
250
 
251
      return TRUE;
252
 
253
    case MEM:
254
      return frv_legitimate_memory_operand (op, mode, FALSE);
255
    }
256
 
257
  return FALSE;
258
})
259
 
260
;; Return true if operand is something that can be an output for a
261
;; move operation.
262
 
263
(define_predicate "move_destination_operand"
264
  (match_code "reg,subreg,mem")
265
{
266
  rtx subreg;
267
  enum rtx_code code;
268
 
269
  switch (GET_CODE (op))
270
    {
271
    default:
272
      break;
273
 
274
    case SUBREG:
275
      if (GET_MODE (op) != mode && mode != VOIDmode)
276
        return FALSE;
277
 
278
      subreg = SUBREG_REG (op);
279
      code = GET_CODE (subreg);
280
      if (code == MEM)
281
        return frv_legitimate_address_p_1 (mode, XEXP (subreg, 0),
282
                                           reload_completed, FALSE, FALSE);
283
 
284
      return (code == REG);
285
 
286
    case REG:
287
      if (GET_MODE (op) != mode && mode != VOIDmode)
288
        return FALSE;
289
 
290
      return TRUE;
291
 
292
    case MEM:
293
      return frv_legitimate_memory_operand (op, mode, FALSE);
294
    }
295
 
296
  return FALSE;
297
})
298
 
299
;; Return true if we the operand is a valid destination for a movcc_fp
300
;; instruction.  This means rejecting fcc_operands, since we need
301
;; scratch registers to write to them.
302
 
303
(define_predicate "movcc_fp_destination_operand"
304
  (match_code "reg,subreg,mem")
305
{
306
  if (fcc_operand (op, mode))
307
    return FALSE;
308
 
309
  return move_destination_operand (op, mode);
310
})
311
 
312
;; Return true if operand is something that can be an input for a
313
;; conditional move operation.
314
 
315
(define_predicate "condexec_source_operand"
316
  (match_code "reg,subreg,const_int,mem,const_double")
317
{
318
  rtx subreg;
319
  enum rtx_code code;
320
 
321
  switch (GET_CODE (op))
322
    {
323
    default:
324
      break;
325
 
326
    case CONST_INT:
327
    case CONST_DOUBLE:
328
      return ZERO_P (op);
329
 
330
    case SUBREG:
331
      if (GET_MODE (op) != mode && mode != VOIDmode)
332
        return FALSE;
333
 
334
      subreg = SUBREG_REG (op);
335
      code = GET_CODE (subreg);
336
      if (code == MEM)
337
        return frv_legitimate_address_p_1 (mode, XEXP (subreg, 0),
338
                                           reload_completed, TRUE, FALSE);
339
 
340
      return (code == REG);
341
 
342
    case REG:
343
      if (GET_MODE (op) != mode && mode != VOIDmode)
344
        return FALSE;
345
 
346
      return TRUE;
347
 
348
    case MEM:
349
      return frv_legitimate_memory_operand (op, mode, TRUE);
350
    }
351
 
352
  return FALSE;
353
})
354
 
355
;; Return true if operand is something that can be an output for a
356
;; conditional move operation.
357
 
358
(define_predicate "condexec_dest_operand"
359
  (match_code "reg,subreg,mem")
360
{
361
  rtx subreg;
362
  enum rtx_code code;
363
 
364
  switch (GET_CODE (op))
365
    {
366
    default:
367
      break;
368
 
369
    case SUBREG:
370
      if (GET_MODE (op) != mode && mode != VOIDmode)
371
        return FALSE;
372
 
373
      subreg = SUBREG_REG (op);
374
      code = GET_CODE (subreg);
375
      if (code == MEM)
376
        return frv_legitimate_address_p_1 (mode, XEXP (subreg, 0),
377
                                           reload_completed, TRUE, FALSE);
378
 
379
      return (code == REG);
380
 
381
    case REG:
382
      if (GET_MODE (op) != mode && mode != VOIDmode)
383
        return FALSE;
384
 
385
      return TRUE;
386
 
387
    case MEM:
388
      return frv_legitimate_memory_operand (op, mode, TRUE);
389
    }
390
 
391
  return FALSE;
392
})
393
 
394
;; Return true if operand is a register of any flavor or a 0 of the
395
;; appropriate type.
396
 
397
(define_predicate "reg_or_0_operand"
398
  (match_code "reg,subreg,const_int,const_double")
399
{
400
  switch (GET_CODE (op))
401
    {
402
    default:
403
      break;
404
 
405
    case REG:
406
    case SUBREG:
407
      if (GET_MODE (op) != mode && mode != VOIDmode)
408
        return FALSE;
409
 
410
      return register_operand (op, mode);
411
 
412
    case CONST_INT:
413
    case CONST_DOUBLE:
414
      return ZERO_P (op);
415
    }
416
 
417
  return FALSE;
418
})
419
 
420
;; Return true if operand is the link register.
421
 
422
(define_predicate "lr_operand"
423
  (match_code "reg")
424
{
425
  if (GET_CODE (op) != REG)
426
    return FALSE;
427
 
428
  if (GET_MODE (op) != mode && mode != VOIDmode)
429
    return FALSE;
430
 
431
  if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
432
    return FALSE;
433
 
434
  return TRUE;
435
})
436
 
437
;; Return true if operand is a gpr register or a valid memory operand.
438
 
439
(define_predicate "gpr_or_memory_operand"
440
  (match_code "reg,subreg,mem")
441
{
442
  return (integer_register_operand (op, mode)
443
          || frv_legitimate_memory_operand (op, mode, FALSE));
444
})
445
 
446
;; Return true if operand is a gpr register, a valid memory operand,
447
;; or a memory operand that can be made valid using an additional gpr
448
;; register.
449
 
450
(define_predicate "gpr_or_memory_operand_with_scratch"
451
  (match_code "reg,subreg,mem")
452
{
453
  rtx addr;
454
 
455
  if (gpr_or_memory_operand (op, mode))
456
    return TRUE;
457
 
458
  if (GET_CODE (op) != MEM)
459
    return FALSE;
460
 
461
  if (GET_MODE (op) != mode)
462
    return FALSE;
463
 
464
  addr = XEXP (op, 0);
465
 
466
  if (GET_CODE (addr) != PLUS)
467
    return FALSE;
468
 
469
  if (!integer_register_operand (XEXP (addr, 0), Pmode))
470
    return FALSE;
471
 
472
  if (GET_CODE (XEXP (addr, 1)) != CONST_INT)
473
    return FALSE;
474
 
475
  return TRUE;
476
})
477
 
478
;; Return true if operand is a fpr register or a valid memory
479
;; operation.
480
 
481
(define_predicate "fpr_or_memory_operand"
482
  (match_code "reg,subreg,mem")
483
{
484
  return (fpr_operand (op, mode)
485
          || frv_legitimate_memory_operand (op, mode, FALSE));
486
})
487
 
488
;; Return 1 if operand is a 12-bit signed immediate.
489
 
490
(define_predicate "int12_operand"
491
  (match_code "const_int")
492
{
493
  if (GET_CODE (op) != CONST_INT)
494
    return FALSE;
495
 
496
  return IN_RANGE_P (INTVAL (op), -2048, 2047);
497
})
498
 
499
;; Return 1 if operand is an integer constant that takes 2
500
;; instructions to load up and can be split into sethi/setlo
501
;; instructions..
502
 
503
(define_predicate "int_2word_operand"
504
  (match_code "const_int,const_double,symbol_ref,label_ref,const")
505
{
506
  HOST_WIDE_INT value;
507
  REAL_VALUE_TYPE rv;
508
  long l;
509
 
510
  switch (GET_CODE (op))
511
    {
512
    default:
513
      break;
514
 
515
    case LABEL_REF:
516
      if (TARGET_FDPIC)
517
        return FALSE;
518
 
519
      return (flag_pic == 0);
520
 
521
    case CONST:
522
      if (flag_pic || TARGET_FDPIC)
523
        return FALSE;
524
 
525
      op = XEXP (op, 0);
526
      if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
527
        op = XEXP (op, 0);
528
      return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
529
 
530
    case SYMBOL_REF:
531
      if (TARGET_FDPIC)
532
        return FALSE;
533
 
534
      /* small data references are already 1 word */
535
      return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
536
 
537
    case CONST_INT:
538
      return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
539
 
540
    case CONST_DOUBLE:
541
      if (GET_MODE (op) == SFmode)
542
        {
543
          REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
544
          REAL_VALUE_TO_TARGET_SINGLE (rv, l);
545
          value = l;
546
          return ! IN_RANGE_P (value, -32768, 32767);
547
        }
548
      else if (GET_MODE (op) == VOIDmode)
549
        {
550
          value = CONST_DOUBLE_LOW (op);
551
          return ! IN_RANGE_P (value, -32768, 32767);
552
        }
553
      break;
554
    }
555
 
556
  return FALSE;
557
})
558
 
559
;; Return true if operand is the uClinux PIC register.
560
 
561
(define_predicate "fdpic_operand"
562
  (match_code "reg")
563
{
564
  if (!TARGET_FDPIC)
565
    return FALSE;
566
 
567
  if (GET_CODE (op) != REG)
568
    return FALSE;
569
 
570
  if (GET_MODE (op) != mode && mode != VOIDmode)
571
    return FALSE;
572
 
573
  if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
574
    return FALSE;
575
 
576
  return TRUE;
577
})
578
 
579
;; TODO: Add a comment here.
580
 
581
(define_predicate "fdpic_fptr_operand"
582
  (match_code "reg")
583
{
584
  if (GET_MODE (op) != mode && mode != VOIDmode)
585
    return FALSE;
586
  if (GET_CODE (op) != REG)
587
    return FALSE;
588
  if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
589
    return FALSE;
590
  return TRUE;
591
})
592
 
593
;; An address operand that may use a pair of registers, an addressing
594
;; mode that we reject in general.
595
 
596
(define_predicate "ldd_address_operand"
597
  (match_code "reg,subreg,plus")
598
{
599
  if (GET_MODE (op) != mode && GET_MODE (op) != VOIDmode)
600
    return FALSE;
601
 
602
  return frv_legitimate_address_p_1 (DImode, op, reload_completed, FALSE, TRUE);
603
})
604
 
605
;; TODO: Add a comment here.
606
 
607
(define_predicate "got12_operand"
608
  (match_code "const")
609
{
610
  struct frv_unspec unspec;
611
 
612
  if (frv_const_unspec_p (op, &unspec))
613
    switch (unspec.reloc)
614
      {
615
      case R_FRV_GOT12:
616
      case R_FRV_GOTOFF12:
617
      case R_FRV_FUNCDESC_GOT12:
618
      case R_FRV_FUNCDESC_GOTOFF12:
619
      case R_FRV_GPREL12:
620
      case R_FRV_TLSMOFF12:
621
        return true;
622
      }
623
  return false;
624
})
625
 
626
;; Return true if OP is a valid const-unspec expression.
627
 
628
(define_predicate "const_unspec_operand"
629
  (match_code "const")
630
{
631
  struct frv_unspec unspec;
632
 
633
  return frv_const_unspec_p (op, &unspec);
634
})
635
 
636
;; Return true if operand is an icc register.
637
 
638
(define_predicate "icc_operand"
639
  (match_code "reg")
640
{
641
  int regno;
642
 
643
  if (GET_MODE (op) != mode && mode != VOIDmode)
644
    return FALSE;
645
 
646
  if (GET_CODE (op) != REG)
647
    return FALSE;
648
 
649
  regno = REGNO (op);
650
  return ICC_OR_PSEUDO_P (regno);
651
})
652
 
653
;; Return true if operand is an fcc register.
654
 
655
(define_predicate "fcc_operand"
656
  (match_code "reg")
657
{
658
  int regno;
659
 
660
  if (GET_MODE (op) != mode && mode != VOIDmode)
661
    return FALSE;
662
 
663
  if (GET_CODE (op) != REG)
664
    return FALSE;
665
 
666
  regno = REGNO (op);
667
  return FCC_OR_PSEUDO_P (regno);
668
})
669
 
670
;; Return true if operand is either an fcc or icc register.
671
 
672
(define_predicate "cc_operand"
673
  (match_code "reg")
674
{
675
  int regno;
676
 
677
  if (GET_MODE (op) != mode && mode != VOIDmode)
678
    return FALSE;
679
 
680
  if (GET_CODE (op) != REG)
681
    return FALSE;
682
 
683
  regno = REGNO (op);
684
  if (CC_OR_PSEUDO_P (regno))
685
    return TRUE;
686
 
687
  return FALSE;
688
})
689
 
690
;; Return true if operand is an integer CCR register.
691
 
692
(define_predicate "icr_operand"
693
  (match_code "reg")
694
{
695
  int regno;
696
 
697
  if (GET_MODE (op) != mode && mode != VOIDmode)
698
    return FALSE;
699
 
700
  if (GET_CODE (op) != REG)
701
    return FALSE;
702
 
703
  regno = REGNO (op);
704
  return ICR_OR_PSEUDO_P (regno);
705
})
706
 
707
;; Return true if operand is an fcc register.
708
 
709
(define_predicate "fcr_operand"
710
  (match_code "reg")
711
{
712
  int regno;
713
 
714
  if (GET_MODE (op) != mode && mode != VOIDmode)
715
    return FALSE;
716
 
717
  if (GET_CODE (op) != REG)
718
    return FALSE;
719
 
720
  regno = REGNO (op);
721
  return FCR_OR_PSEUDO_P (regno);
722
})
723
 
724
;; Return true if operand is either an fcc or icc register.
725
 
726
(define_predicate "cr_operand"
727
  (match_code "reg")
728
{
729
  int regno;
730
 
731
  if (GET_MODE (op) != mode && mode != VOIDmode)
732
    return FALSE;
733
 
734
  if (GET_CODE (op) != REG)
735
    return FALSE;
736
 
737
  regno = REGNO (op);
738
  if (CR_OR_PSEUDO_P (regno))
739
    return TRUE;
740
 
741
  return FALSE;
742
})
743
 
744
;; Return true if operand is a FPR register.
745
 
746
(define_predicate "fpr_operand"
747
  (match_code "reg,subreg")
748
{
749
  if (GET_MODE (op) != mode && mode != VOIDmode)
750
    return FALSE;
751
 
752
  if (GET_CODE (op) == SUBREG)
753
    {
754
      if (GET_CODE (SUBREG_REG (op)) != REG)
755
        return register_operand (op, mode);
756
 
757
      op = SUBREG_REG (op);
758
    }
759
 
760
  if (GET_CODE (op) != REG)
761
    return FALSE;
762
 
763
  return FPR_OR_PSEUDO_P (REGNO (op));
764
})
765
 
766
;; Return true if operand is an even GPR or FPR register.
767
 
768
(define_predicate "even_reg_operand"
769
  (match_code "reg,subreg")
770
{
771
  int regno;
772
 
773
  if (GET_MODE (op) != mode && mode != VOIDmode)
774
    return FALSE;
775
 
776
  if (GET_CODE (op) == SUBREG)
777
    {
778
      if (GET_CODE (SUBREG_REG (op)) != REG)
779
        return register_operand (op, mode);
780
 
781
      op = SUBREG_REG (op);
782
    }
783
 
784
  if (GET_CODE (op) != REG)
785
    return FALSE;
786
 
787
  regno = REGNO (op);
788
  if (regno >= FIRST_PSEUDO_REGISTER)
789
    return TRUE;
790
 
791
  if (GPR_P (regno))
792
    return (((regno - GPR_FIRST) & 1) == 0);
793
 
794
  if (FPR_P (regno))
795
    return (((regno - FPR_FIRST) & 1) == 0);
796
 
797
  return FALSE;
798
})
799
 
800
;; Return true if operand is an odd GPR register.
801
 
802
(define_predicate "odd_reg_operand"
803
  (match_code "reg,subreg")
804
{
805
  int regno;
806
 
807
  if (GET_MODE (op) != mode && mode != VOIDmode)
808
    return FALSE;
809
 
810
  if (GET_CODE (op) == SUBREG)
811
    {
812
      if (GET_CODE (SUBREG_REG (op)) != REG)
813
        return register_operand (op, mode);
814
 
815
      op = SUBREG_REG (op);
816
    }
817
 
818
  if (GET_CODE (op) != REG)
819
    return FALSE;
820
 
821
  regno = REGNO (op);
822
  /* Assume that reload will give us an even register.  */
823
  if (regno >= FIRST_PSEUDO_REGISTER)
824
    return FALSE;
825
 
826
  if (GPR_P (regno))
827
    return (((regno - GPR_FIRST) & 1) != 0);
828
 
829
  if (FPR_P (regno))
830
    return (((regno - FPR_FIRST) & 1) != 0);
831
 
832
  return FALSE;
833
})
834
 
835
;; Return true if operand is an even GPR register.
836
 
837
(define_predicate "even_gpr_operand"
838
  (match_code "reg,subreg")
839
{
840
  int regno;
841
 
842
  if (GET_MODE (op) != mode && mode != VOIDmode)
843
    return FALSE;
844
 
845
  if (GET_CODE (op) == SUBREG)
846
    {
847
      if (GET_CODE (SUBREG_REG (op)) != REG)
848
        return register_operand (op, mode);
849
 
850
      op = SUBREG_REG (op);
851
    }
852
 
853
  if (GET_CODE (op) != REG)
854
    return FALSE;
855
 
856
  regno = REGNO (op);
857
  if (regno >= FIRST_PSEUDO_REGISTER)
858
    return TRUE;
859
 
860
  if (! GPR_P (regno))
861
    return FALSE;
862
 
863
  return (((regno - GPR_FIRST) & 1) == 0);
864
})
865
 
866
;; Return true if operand is an odd GPR register.
867
 
868
(define_predicate "odd_gpr_operand"
869
  (match_code "reg,subreg")
870
{
871
  int regno;
872
 
873
  if (GET_MODE (op) != mode && mode != VOIDmode)
874
    return FALSE;
875
 
876
  if (GET_CODE (op) == SUBREG)
877
    {
878
      if (GET_CODE (SUBREG_REG (op)) != REG)
879
        return register_operand (op, mode);
880
 
881
      op = SUBREG_REG (op);
882
    }
883
 
884
  if (GET_CODE (op) != REG)
885
    return FALSE;
886
 
887
  regno = REGNO (op);
888
  /* Assume that reload will give us an even register.  */
889
  if (regno >= FIRST_PSEUDO_REGISTER)
890
    return FALSE;
891
 
892
  if (! GPR_P (regno))
893
    return FALSE;
894
 
895
  return (((regno - GPR_FIRST) & 1) != 0);
896
})
897
 
898
;; Return true if operand is a quad aligned FPR register.
899
 
900
(define_predicate "quad_fpr_operand"
901
  (match_code "reg,subreg")
902
{
903
  int regno;
904
 
905
  if (GET_MODE (op) != mode && mode != VOIDmode)
906
    return FALSE;
907
 
908
  if (GET_CODE (op) == SUBREG)
909
    {
910
      if (GET_CODE (SUBREG_REG (op)) != REG)
911
        return register_operand (op, mode);
912
 
913
      op = SUBREG_REG (op);
914
    }
915
 
916
  if (GET_CODE (op) != REG)
917
    return FALSE;
918
 
919
  regno = REGNO (op);
920
  if (regno >= FIRST_PSEUDO_REGISTER)
921
    return TRUE;
922
 
923
  if (! FPR_P (regno))
924
    return FALSE;
925
 
926
  return (((regno - FPR_FIRST) & 3) == 0);
927
})
928
 
929
;; Return true if operand is an even FPR register.
930
 
931
(define_predicate "even_fpr_operand"
932
  (match_code "reg,subreg")
933
{
934
  int regno;
935
 
936
  if (GET_MODE (op) != mode && mode != VOIDmode)
937
    return FALSE;
938
 
939
  if (GET_CODE (op) == SUBREG)
940
    {
941
      if (GET_CODE (SUBREG_REG (op)) != REG)
942
        return register_operand (op, mode);
943
 
944
      op = SUBREG_REG (op);
945
    }
946
 
947
  if (GET_CODE (op) != REG)
948
    return FALSE;
949
 
950
  regno = REGNO (op);
951
  if (regno >= FIRST_PSEUDO_REGISTER)
952
    return TRUE;
953
 
954
  if (! FPR_P (regno))
955
    return FALSE;
956
 
957
  return (((regno - FPR_FIRST) & 1) == 0);
958
})
959
 
960
;; Return true if operand is an odd FPR register.
961
 
962
(define_predicate "odd_fpr_operand"
963
  (match_code "reg,subreg")
964
{
965
  int regno;
966
 
967
  if (GET_MODE (op) != mode && mode != VOIDmode)
968
    return FALSE;
969
 
970
  if (GET_CODE (op) == SUBREG)
971
    {
972
      if (GET_CODE (SUBREG_REG (op)) != REG)
973
        return register_operand (op, mode);
974
 
975
      op = SUBREG_REG (op);
976
    }
977
 
978
  if (GET_CODE (op) != REG)
979
    return FALSE;
980
 
981
  regno = REGNO (op);
982
  /* Assume that reload will give us an even register.  */
983
  if (regno >= FIRST_PSEUDO_REGISTER)
984
    return FALSE;
985
 
986
  if (! FPR_P (regno))
987
    return FALSE;
988
 
989
  return (((regno - FPR_FIRST) & 1) != 0);
990
})
991
 
992
;; Return true if operand is a 2 word memory address that can be
993
;; loaded in one instruction to load or store.  We assume the stack
994
;; and frame pointers are suitably aligned, and variables in the small
995
;; data area.  FIXME -- at some we should recognize other globals and
996
;; statics. We can't assume that any old pointer is aligned, given
997
;; that arguments could be passed on an odd word on the stack and the
998
;; address taken and passed through to another function.
999
 
1000
(define_predicate "dbl_memory_one_insn_operand"
1001
  (match_code "mem")
1002
{
1003
  rtx addr;
1004
  rtx addr_reg;
1005
 
1006
  if (! TARGET_DWORD)
1007
    return FALSE;
1008
 
1009
  if (GET_CODE (op) != MEM)
1010
    return FALSE;
1011
 
1012
  if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
1013
    return FALSE;
1014
 
1015
  addr = XEXP (op, 0);
1016
  if (GET_CODE (addr) == REG)
1017
    addr_reg = addr;
1018
 
1019
  else if (GET_CODE (addr) == PLUS)
1020
    {
1021
      rtx addr0 = XEXP (addr, 0);
1022
      rtx addr1 = XEXP (addr, 1);
1023
 
1024
      if (GET_CODE (addr0) != REG)
1025
        return FALSE;
1026
 
1027
      if (got12_operand (addr1, VOIDmode))
1028
        return TRUE;
1029
 
1030
      if (GET_CODE (addr1) != CONST_INT)
1031
        return FALSE;
1032
 
1033
      if ((INTVAL (addr1) & 7) != 0)
1034
        return FALSE;
1035
 
1036
      addr_reg = addr0;
1037
    }
1038
 
1039
  else
1040
    return FALSE;
1041
 
1042
  if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
1043
    return TRUE;
1044
 
1045
  return FALSE;
1046
})
1047
 
1048
;; Return true if operand is a 2 word memory address that needs to use
1049
;; two instructions to load or store.
1050
 
1051
(define_predicate "dbl_memory_two_insn_operand"
1052
  (match_code "mem")
1053
{
1054
  if (GET_CODE (op) != MEM)
1055
    return FALSE;
1056
 
1057
  if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
1058
    return FALSE;
1059
 
1060
  if (! TARGET_DWORD)
1061
    return TRUE;
1062
 
1063
  return ! dbl_memory_one_insn_operand (op, mode);
1064
})
1065
 
1066
;; Return true if operand is a memory reference suitable for a call.
1067
 
1068
(define_predicate "call_operand"
1069
  (match_code "reg,subreg,const_int,const,symbol_ref")
1070
{
1071
  if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
1072
    return FALSE;
1073
 
1074
  if (GET_CODE (op) == SYMBOL_REF)
1075
    return !TARGET_LONG_CALLS || SYMBOL_REF_LOCAL_P (op);
1076
 
1077
  /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
1078
     never occur anyway), but prevents reload from not handling the case
1079
     properly of a call through a pointer on a function that calls
1080
     vfork/setjmp, etc. due to the need to flush all of the registers to stack.  */
1081
  return gpr_or_int12_operand (op, mode);
1082
})
1083
 
1084
;; Return true if operand is a memory reference suitable for a
1085
;; sibcall.
1086
 
1087
(define_predicate "sibcall_operand"
1088
  (match_code "reg,subreg,const_int,const")
1089
{
1090
  if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
1091
    return FALSE;
1092
 
1093
  /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
1094
     never occur anyway), but prevents reload from not handling the case
1095
     properly of a call through a pointer on a function that calls
1096
     vfork/setjmp, etc. due to the need to flush all of the registers to stack.  */
1097
  return gpr_or_int12_operand (op, mode);
1098
})
1099
 
1100
;; Return 1 if operand is an integer constant with the bottom 16 bits
1101
;; clear.
1102
 
1103
(define_predicate "upper_int16_operand"
1104
  (match_code "const_int")
1105
{
1106
  if (GET_CODE (op) != CONST_INT)
1107
    return FALSE;
1108
 
1109
  return ((INTVAL (op) & 0xffff) == 0);
1110
})
1111
 
1112
;; Return 1 if operand is a 16-bit unsigned immediate.
1113
 
1114
(define_predicate "uint16_operand"
1115
  (match_code "const_int")
1116
{
1117
  if (GET_CODE (op) != CONST_INT)
1118
    return FALSE;
1119
 
1120
  return IN_RANGE_P (INTVAL (op), 0, 0xffff);
1121
})
1122
 
1123
;; Returns 1 if OP is either a SYMBOL_REF or a constant.
1124
 
1125
(define_predicate "symbolic_operand"
1126
  (match_code "symbol_ref,const,const_int")
1127
{
1128
  enum rtx_code c = GET_CODE (op);
1129
 
1130
  if (c == CONST)
1131
    {
1132
      /* Allow (const:SI (plus:SI (symbol_ref) (const_int))).  */
1133
      return GET_MODE (op) == SImode
1134
        && GET_CODE (XEXP (op, 0)) == PLUS
1135
        && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
1136
        && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT;
1137
    }
1138
 
1139
  return c == SYMBOL_REF || c == CONST_INT;
1140
})
1141
 
1142
;; Return true if operator is a kind of relational operator.
1143
 
1144
(define_predicate "relational_operator"
1145
  (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")
1146
{
1147
  return (integer_relational_operator (op, mode)
1148
          || float_relational_operator (op, mode));
1149
})
1150
 
1151
;; Return true if OP is a relational operator suitable for CCmode,
1152
;; CC_UNSmode or CC_NZmode.
1153
 
1154
(define_predicate "integer_relational_operator"
1155
  (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")
1156
{
1157
  if (mode != VOIDmode && mode != GET_MODE (op))
1158
    return FALSE;
1159
 
1160
  /* The allowable relations depend on the mode of the ICC register.  */
1161
  switch (GET_CODE (op))
1162
    {
1163
    default:
1164
      return FALSE;
1165
 
1166
    case EQ:
1167
    case NE:
1168
    case LT:
1169
    case GE:
1170
      return (GET_MODE (XEXP (op, 0)) == CC_NZmode
1171
              || GET_MODE (XEXP (op, 0)) == CCmode);
1172
 
1173
    case LE:
1174
    case GT:
1175
      return GET_MODE (XEXP (op, 0)) == CCmode;
1176
 
1177
    case GTU:
1178
    case GEU:
1179
    case LTU:
1180
    case LEU:
1181
      return (GET_MODE (XEXP (op, 0)) == CC_NZmode
1182
              || GET_MODE (XEXP (op, 0)) == CC_UNSmode);
1183
    }
1184
})
1185
 
1186
;; Return true if operator is a floating point relational operator.
1187
 
1188
(define_predicate "float_relational_operator"
1189
  (match_code "eq,ne,le,lt,ge,gt")
1190
{
1191
  if (mode != VOIDmode && mode != GET_MODE (op))
1192
    return FALSE;
1193
 
1194
  switch (GET_CODE (op))
1195
    {
1196
    default:
1197
      return FALSE;
1198
 
1199
    case EQ: case NE:
1200
    case LE: case LT:
1201
    case GE: case GT:
1202
#if 0
1203
    case UEQ: case UNE:
1204
    case ULE: case ULT:
1205
    case UGE: case UGT:
1206
    case ORDERED:
1207
    case UNORDERED:
1208
#endif
1209
      return GET_MODE (XEXP (op, 0)) == CC_FPmode;
1210
    }
1211
})
1212
 
1213
;; Return true if operator is EQ/NE of a conditional execution
1214
;; register.
1215
 
1216
(define_predicate "ccr_eqne_operator"
1217
  (match_code "eq,ne")
1218
{
1219
  enum machine_mode op_mode = GET_MODE (op);
1220
  rtx op0;
1221
  rtx op1;
1222
  int regno;
1223
 
1224
  if (mode != VOIDmode && op_mode != mode)
1225
    return FALSE;
1226
 
1227
  switch (GET_CODE (op))
1228
    {
1229
    default:
1230
      return FALSE;
1231
 
1232
    case EQ:
1233
    case NE:
1234
      break;
1235
    }
1236
 
1237
  op1 = XEXP (op, 1);
1238
  if (op1 != const0_rtx)
1239
    return FALSE;
1240
 
1241
  op0 = XEXP (op, 0);
1242
  if (GET_CODE (op0) != REG)
1243
    return FALSE;
1244
 
1245
  regno = REGNO (op0);
1246
  if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
1247
    return TRUE;
1248
 
1249
  return FALSE;
1250
})
1251
 
1252
;; Return true if operator is a minimum or maximum operator (both
1253
;; signed and unsigned).
1254
 
1255
(define_predicate "minmax_operator"
1256
  (match_code "smin,smax,umin,umax")
1257
{
1258
  if (mode != VOIDmode && mode != GET_MODE (op))
1259
    return FALSE;
1260
 
1261
  switch (GET_CODE (op))
1262
    {
1263
    default:
1264
      return FALSE;
1265
 
1266
    case SMIN:
1267
    case SMAX:
1268
    case UMIN:
1269
    case UMAX:
1270
      break;
1271
    }
1272
 
1273
  return TRUE;
1274
})
1275
 
1276
;; Return true if operator is an integer binary operator that can
1277
;; executed conditionally and takes 1 cycle.
1278
 
1279
(define_predicate "condexec_si_binary_operator"
1280
  (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt")
1281
{
1282
  enum machine_mode op_mode = GET_MODE (op);
1283
 
1284
  if (mode != VOIDmode && op_mode != mode)
1285
    return FALSE;
1286
 
1287
  switch (GET_CODE (op))
1288
    {
1289
    default:
1290
      return FALSE;
1291
 
1292
    case PLUS:
1293
    case MINUS:
1294
    case AND:
1295
    case IOR:
1296
    case XOR:
1297
    case ASHIFT:
1298
    case ASHIFTRT:
1299
    case LSHIFTRT:
1300
      return TRUE;
1301
    }
1302
})
1303
 
1304
;; Return true if operator is an integer binary operator that can be
1305
;; executed conditionally by a media instruction.
1306
 
1307
(define_predicate "condexec_si_media_operator"
1308
  (match_code "and,ior,xor")
1309
{
1310
  enum machine_mode op_mode = GET_MODE (op);
1311
 
1312
  if (mode != VOIDmode && op_mode != mode)
1313
    return FALSE;
1314
 
1315
  switch (GET_CODE (op))
1316
    {
1317
    default:
1318
      return FALSE;
1319
 
1320
    case AND:
1321
    case IOR:
1322
    case XOR:
1323
      return TRUE;
1324
    }
1325
})
1326
 
1327
;; Return true if operator is an integer division operator that can
1328
;; executed conditionally.
1329
 
1330
(define_predicate "condexec_si_divide_operator"
1331
  (match_code "div,udiv")
1332
{
1333
  enum machine_mode op_mode = GET_MODE (op);
1334
 
1335
  if (mode != VOIDmode && op_mode != mode)
1336
    return FALSE;
1337
 
1338
  switch (GET_CODE (op))
1339
    {
1340
    default:
1341
      return FALSE;
1342
 
1343
    case DIV:
1344
    case UDIV:
1345
      return TRUE;
1346
    }
1347
})
1348
 
1349
;; Return true if operator is an integer unary operator that can
1350
;; executed conditionally.
1351
 
1352
(define_predicate "condexec_si_unary_operator"
1353
  (match_code "not,neg")
1354
{
1355
  enum machine_mode op_mode = GET_MODE (op);
1356
 
1357
  if (mode != VOIDmode && op_mode != mode)
1358
    return FALSE;
1359
 
1360
  switch (GET_CODE (op))
1361
    {
1362
    default:
1363
      return FALSE;
1364
 
1365
    case NEG:
1366
    case NOT:
1367
      return TRUE;
1368
    }
1369
})
1370
 
1371
;; Return true if operator is an addition or subtraction
1372
;; expression. Such expressions can be evaluated conditionally by
1373
;; floating-point instructions.
1374
 
1375
(define_predicate "condexec_sf_add_operator"
1376
  (match_code "plus,minus")
1377
{
1378
  enum machine_mode op_mode = GET_MODE (op);
1379
 
1380
  if (mode != VOIDmode && op_mode != mode)
1381
    return FALSE;
1382
 
1383
  switch (GET_CODE (op))
1384
    {
1385
    default:
1386
      return FALSE;
1387
 
1388
    case PLUS:
1389
    case MINUS:
1390
      return TRUE;
1391
    }
1392
})
1393
 
1394
;; Return true if operator is a conversion-type expression that can be
1395
;; evaluated conditionally by floating-point instructions.
1396
 
1397
(define_predicate "condexec_sf_conv_operator"
1398
  (match_code "abs,neg")
1399
{
1400
  enum machine_mode op_mode = GET_MODE (op);
1401
 
1402
  if (mode != VOIDmode && op_mode != mode)
1403
    return FALSE;
1404
 
1405
  switch (GET_CODE (op))
1406
    {
1407
    default:
1408
      return FALSE;
1409
 
1410
    case NEG:
1411
    case ABS:
1412
      return TRUE;
1413
    }
1414
})
1415
 
1416
;; Return true if OP is an integer binary operator that can be
1417
;; combined with a (set ... (compare:CC_NZ ...)) pattern.
1418
 
1419
(define_predicate "intop_compare_operator"
1420
  (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt")
1421
{
1422
  if (mode != VOIDmode && GET_MODE (op) != mode)
1423
    return FALSE;
1424
 
1425
  switch (GET_CODE (op))
1426
    {
1427
    default:
1428
      return FALSE;
1429
 
1430
    case PLUS:
1431
    case MINUS:
1432
    case AND:
1433
    case IOR:
1434
    case XOR:
1435
    case ASHIFTRT:
1436
    case LSHIFTRT:
1437
      return GET_MODE (op) == SImode;
1438
    }
1439
})
1440
 
1441
;; Return 1 if operand is a register or 6-bit signed immediate.
1442
 
1443
(define_predicate "fpr_or_int6_operand"
1444
  (match_code "reg,subreg,const_int")
1445
{
1446
  if (GET_CODE (op) == CONST_INT)
1447
    return IN_RANGE_P (INTVAL (op), -32, 31);
1448
 
1449
  if (GET_MODE (op) != mode && mode != VOIDmode)
1450
    return FALSE;
1451
 
1452
  if (GET_CODE (op) == SUBREG)
1453
    {
1454
      if (GET_CODE (SUBREG_REG (op)) != REG)
1455
        return register_operand (op, mode);
1456
 
1457
      op = SUBREG_REG (op);
1458
    }
1459
 
1460
  if (GET_CODE (op) != REG)
1461
    return FALSE;
1462
 
1463
  return FPR_OR_PSEUDO_P (REGNO (op));
1464
})
1465
 
1466
;; Return 1 if operand is a 6-bit signed immediate.
1467
 
1468
(define_predicate "int6_operand"
1469
  (match_code "const_int")
1470
{
1471
  if (GET_CODE (op) != CONST_INT)
1472
    return FALSE;
1473
 
1474
  return IN_RANGE_P (INTVAL (op), -32, 31);
1475
})
1476
 
1477
;; Return 1 if operand is a 5-bit signed immediate.
1478
 
1479
(define_predicate "int5_operand"
1480
  (match_code "const_int")
1481
{
1482
  return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
1483
})
1484
 
1485
;; Return 1 if operand is a 5-bit unsigned immediate.
1486
 
1487
(define_predicate "uint5_operand"
1488
  (match_code "const_int")
1489
{
1490
  return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
1491
})
1492
 
1493
;; Return 1 if operand is a 4-bit unsigned immediate.
1494
 
1495
(define_predicate "uint4_operand"
1496
  (match_code "const_int")
1497
{
1498
  return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
1499
})
1500
 
1501
;; Return 1 if operand is a 1-bit unsigned immediate (0 or 1).
1502
 
1503
(define_predicate "uint1_operand"
1504
  (match_code "const_int")
1505
{
1506
  return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
1507
})
1508
 
1509
;; Return 1 if operand is a valid ACC register number.
1510
 
1511
(define_predicate "acc_operand"
1512
  (match_code "reg,subreg")
1513
{
1514
  return ((mode == VOIDmode || mode == GET_MODE (op))
1515
          && REG_P (op) && ACC_P (REGNO (op))
1516
          && ((REGNO (op) - ACC_FIRST) & ~ACC_MASK) == 0);
1517
})
1518
 
1519
;; Return 1 if operand is a valid even ACC register number.
1520
 
1521
(define_predicate "even_acc_operand"
1522
  (match_code "reg,subreg")
1523
{
1524
  return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 1) == 0;
1525
})
1526
 
1527
;; Return 1 if operand is zero or four.
1528
 
1529
(define_predicate "quad_acc_operand"
1530
  (match_code "reg,subreg")
1531
{
1532
  return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 3) == 0;
1533
})
1534
 
1535
;; Return 1 if operand is a valid ACCG register number.
1536
 
1537
(define_predicate "accg_operand"
1538
  (match_code "reg,subreg")
1539
{
1540
  return ((mode == VOIDmode || mode == GET_MODE (op))
1541
          && REG_P (op) && ACCG_P (REGNO (op))
1542
          && ((REGNO (op) - ACCG_FIRST) & ~ACC_MASK) == 0);
1543
})

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