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1 282 jeremybenn
/* Definitions of target machine for GCC for IA-32.
2
   Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3
   2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4
   Free Software Foundation, Inc.
5
 
6
This file is part of GCC.
7
 
8
GCC is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 3, or (at your option)
11
any later version.
12
 
13
GCC is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
Under Section 7 of GPL version 3, you are granted additional
19
permissions described in the GCC Runtime Library Exception, version
20
3.1, as published by the Free Software Foundation.
21
 
22
You should have received a copy of the GNU General Public License and
23
a copy of the GCC Runtime Library Exception along with this program;
24
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
25
<http://www.gnu.org/licenses/>.  */
26
 
27
/* The purpose of this file is to define the characteristics of the i386,
28
   independent of assembler syntax or operating system.
29
 
30
   Three other files build on this one to describe a specific assembler syntax:
31
   bsd386.h, att386.h, and sun386.h.
32
 
33
   The actual tm.h file for a particular system should include
34
   this file, and then the file for the appropriate assembler syntax.
35
 
36
   Many macros that specify assembler syntax are omitted entirely from
37
   this file because they really belong in the files for particular
38
   assemblers.  These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
39
   ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
40
   that start with ASM_ or end in ASM_OP.  */
41
 
42
/* Redefines for option macros.  */
43
 
44
#define TARGET_64BIT    OPTION_ISA_64BIT
45
#define TARGET_MMX      OPTION_ISA_MMX
46
#define TARGET_3DNOW    OPTION_ISA_3DNOW
47
#define TARGET_3DNOW_A  OPTION_ISA_3DNOW_A
48
#define TARGET_SSE      OPTION_ISA_SSE
49
#define TARGET_SSE2     OPTION_ISA_SSE2
50
#define TARGET_SSE3     OPTION_ISA_SSE3
51
#define TARGET_SSSE3    OPTION_ISA_SSSE3
52
#define TARGET_SSE4_1   OPTION_ISA_SSE4_1
53
#define TARGET_SSE4_2   OPTION_ISA_SSE4_2
54
#define TARGET_AVX      OPTION_ISA_AVX
55
#define TARGET_FMA      OPTION_ISA_FMA
56
#define TARGET_SSE4A    OPTION_ISA_SSE4A
57
#define TARGET_FMA4     OPTION_ISA_FMA4
58
#define TARGET_XOP      OPTION_ISA_XOP
59
#define TARGET_LWP      OPTION_ISA_LWP
60
#define TARGET_ROUND    OPTION_ISA_ROUND
61
#define TARGET_ABM      OPTION_ISA_ABM
62
#define TARGET_POPCNT   OPTION_ISA_POPCNT
63
#define TARGET_SAHF     OPTION_ISA_SAHF
64
#define TARGET_MOVBE    OPTION_ISA_MOVBE
65
#define TARGET_CRC32    OPTION_ISA_CRC32
66
#define TARGET_AES      OPTION_ISA_AES
67
#define TARGET_PCLMUL   OPTION_ISA_PCLMUL
68
#define TARGET_CMPXCHG16B OPTION_ISA_CX16
69
 
70
 
71
/* SSE4.1 defines round instructions */
72
#define OPTION_MASK_ISA_ROUND   OPTION_MASK_ISA_SSE4_1
73
#define OPTION_ISA_ROUND        ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
74
 
75
#include "config/vxworks-dummy.h"
76
 
77
/* Algorithm to expand string function with.  */
78
enum stringop_alg
79
{
80
   no_stringop,
81
   libcall,
82
   rep_prefix_1_byte,
83
   rep_prefix_4_byte,
84
   rep_prefix_8_byte,
85
   loop_1_byte,
86
   loop,
87
   unrolled_loop
88
};
89
 
90
#define NAX_STRINGOP_ALGS 4
91
 
92
/* Specify what algorithm to use for stringops on known size.
93
   When size is unknown, the UNKNOWN_SIZE alg is used.  When size is
94
   known at compile time or estimated via feedback, the SIZE array
95
   is walked in order until MAX is greater then the estimate (or -1
96
   means infinity).  Corresponding ALG is used then.
97
   For example initializer:
98
    {{256, loop}, {-1, rep_prefix_4_byte}}
99
   will use loop for blocks smaller or equal to 256 bytes, rep prefix will
100
   be used otherwise.  */
101
struct stringop_algs
102
{
103
  const enum stringop_alg unknown_size;
104
  const struct stringop_strategy {
105
    const int max;
106
    const enum stringop_alg alg;
107
  } size [NAX_STRINGOP_ALGS];
108
};
109
 
110
/* Define the specific costs for a given cpu */
111
 
112
struct processor_costs {
113
  const int add;                /* cost of an add instruction */
114
  const int lea;                /* cost of a lea instruction */
115
  const int shift_var;          /* variable shift costs */
116
  const int shift_const;        /* constant shift costs */
117
  const int mult_init[5];       /* cost of starting a multiply
118
                                   in QImode, HImode, SImode, DImode, TImode*/
119
  const int mult_bit;           /* cost of multiply per each bit set */
120
  const int divide[5];          /* cost of a divide/mod
121
                                   in QImode, HImode, SImode, DImode, TImode*/
122
  int movsx;                    /* The cost of movsx operation.  */
123
  int movzx;                    /* The cost of movzx operation.  */
124
  const int large_insn;         /* insns larger than this cost more */
125
  const int move_ratio;         /* The threshold of number of scalar
126
                                   memory-to-memory move insns.  */
127
  const int movzbl_load;        /* cost of loading using movzbl */
128
  const int int_load[3];        /* cost of loading integer registers
129
                                   in QImode, HImode and SImode relative
130
                                   to reg-reg move (2).  */
131
  const int int_store[3];       /* cost of storing integer register
132
                                   in QImode, HImode and SImode */
133
  const int fp_move;            /* cost of reg,reg fld/fst */
134
  const int fp_load[3];         /* cost of loading FP register
135
                                   in SFmode, DFmode and XFmode */
136
  const int fp_store[3];        /* cost of storing FP register
137
                                   in SFmode, DFmode and XFmode */
138
  const int mmx_move;           /* cost of moving MMX register.  */
139
  const int mmx_load[2];        /* cost of loading MMX register
140
                                   in SImode and DImode */
141
  const int mmx_store[2];       /* cost of storing MMX register
142
                                   in SImode and DImode */
143
  const int sse_move;           /* cost of moving SSE register.  */
144
  const int sse_load[3];        /* cost of loading SSE register
145
                                   in SImode, DImode and TImode*/
146
  const int sse_store[3];       /* cost of storing SSE register
147
                                   in SImode, DImode and TImode*/
148
  const int mmxsse_to_integer;  /* cost of moving mmxsse register to
149
                                   integer and vice versa.  */
150
  const int l1_cache_size;      /* size of l1 cache, in kilobytes.  */
151
  const int l2_cache_size;      /* size of l2 cache, in kilobytes.  */
152
  const int prefetch_block;     /* bytes moved to cache for prefetch.  */
153
  const int simultaneous_prefetches; /* number of parallel prefetch
154
                                   operations.  */
155
  const int branch_cost;        /* Default value for BRANCH_COST.  */
156
  const int fadd;               /* cost of FADD and FSUB instructions.  */
157
  const int fmul;               /* cost of FMUL instruction.  */
158
  const int fdiv;               /* cost of FDIV instruction.  */
159
  const int fabs;               /* cost of FABS instruction.  */
160
  const int fchs;               /* cost of FCHS instruction.  */
161
  const int fsqrt;              /* cost of FSQRT instruction.  */
162
                                /* Specify what algorithm
163
                                   to use for stringops on unknown size.  */
164
  struct stringop_algs memcpy[2], memset[2];
165
  const int scalar_stmt_cost;   /* Cost of any scalar operation, excluding
166
                                   load and store.  */
167
  const int scalar_load_cost;   /* Cost of scalar load.  */
168
  const int scalar_store_cost;  /* Cost of scalar store.  */
169
  const int vec_stmt_cost;      /* Cost of any vector operation, excluding
170
                                   load, store, vector-to-scalar and
171
                                   scalar-to-vector operation.  */
172
  const int vec_to_scalar_cost;    /* Cost of vect-to-scalar operation.  */
173
  const int scalar_to_vec_cost;    /* Cost of scalar-to-vector operation.  */
174
  const int vec_align_load_cost;   /* Cost of aligned vector load.  */
175
  const int vec_unalign_load_cost; /* Cost of unaligned vector load.  */
176
  const int vec_store_cost;        /* Cost of vector store.  */
177
  const int cond_taken_branch_cost;    /* Cost of taken branch for vectorizer
178
                                          cost model.  */
179
  const int cond_not_taken_branch_cost;/* Cost of not taken branch for
180
                                          vectorizer cost model.  */
181
};
182
 
183
extern const struct processor_costs *ix86_cost;
184
extern const struct processor_costs ix86_size_cost;
185
 
186
#define ix86_cur_cost() \
187
  (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
188
 
189
/* Macros used in the machine description to test the flags.  */
190
 
191
/* configure can arrange to make this 2, to force a 486.  */
192
 
193
#ifndef TARGET_CPU_DEFAULT
194
#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
195
#endif
196
 
197
#ifndef TARGET_FPMATH_DEFAULT
198
#define TARGET_FPMATH_DEFAULT \
199
  (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
200
#endif
201
 
202
#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
203
 
204
/* 64bit Sledgehammer mode.  For libgcc2 we make sure this is a
205
   compile-time constant.  */
206
#ifdef IN_LIBGCC2
207
#undef TARGET_64BIT
208
#ifdef __x86_64__
209
#define TARGET_64BIT 1
210
#else
211
#define TARGET_64BIT 0
212
#endif
213
#else
214
#ifndef TARGET_BI_ARCH
215
#undef TARGET_64BIT
216
#if TARGET_64BIT_DEFAULT
217
#define TARGET_64BIT 1
218
#else
219
#define TARGET_64BIT 0
220
#endif
221
#endif
222
#endif
223
 
224
#define HAS_LONG_COND_BRANCH 1
225
#define HAS_LONG_UNCOND_BRANCH 1
226
 
227
#define TARGET_386 (ix86_tune == PROCESSOR_I386)
228
#define TARGET_486 (ix86_tune == PROCESSOR_I486)
229
#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
230
#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
231
#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
232
#define TARGET_K6 (ix86_tune == PROCESSOR_K6)
233
#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
234
#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
235
#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
236
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
237
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
238
#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
239
#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
240
#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
241
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
242
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
243
#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
244
 
245
/* Feature tests against the various tunings.  */
246
enum ix86_tune_indices {
247
  X86_TUNE_USE_LEAVE,
248
  X86_TUNE_PUSH_MEMORY,
249
  X86_TUNE_ZERO_EXTEND_WITH_AND,
250
  X86_TUNE_UNROLL_STRLEN,
251
  X86_TUNE_DEEP_BRANCH_PREDICTION,
252
  X86_TUNE_BRANCH_PREDICTION_HINTS,
253
  X86_TUNE_DOUBLE_WITH_ADD,
254
  X86_TUNE_USE_SAHF,
255
  X86_TUNE_MOVX,
256
  X86_TUNE_PARTIAL_REG_STALL,
257
  X86_TUNE_PARTIAL_FLAG_REG_STALL,
258
  X86_TUNE_USE_HIMODE_FIOP,
259
  X86_TUNE_USE_SIMODE_FIOP,
260
  X86_TUNE_USE_MOV0,
261
  X86_TUNE_USE_CLTD,
262
  X86_TUNE_USE_XCHGB,
263
  X86_TUNE_SPLIT_LONG_MOVES,
264
  X86_TUNE_READ_MODIFY_WRITE,
265
  X86_TUNE_READ_MODIFY,
266
  X86_TUNE_PROMOTE_QIMODE,
267
  X86_TUNE_FAST_PREFIX,
268
  X86_TUNE_SINGLE_STRINGOP,
269
  X86_TUNE_QIMODE_MATH,
270
  X86_TUNE_HIMODE_MATH,
271
  X86_TUNE_PROMOTE_QI_REGS,
272
  X86_TUNE_PROMOTE_HI_REGS,
273
  X86_TUNE_ADD_ESP_4,
274
  X86_TUNE_ADD_ESP_8,
275
  X86_TUNE_SUB_ESP_4,
276
  X86_TUNE_SUB_ESP_8,
277
  X86_TUNE_INTEGER_DFMODE_MOVES,
278
  X86_TUNE_PARTIAL_REG_DEPENDENCY,
279
  X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
280
  X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
281
  X86_TUNE_SSE_SPLIT_REGS,
282
  X86_TUNE_SSE_TYPELESS_STORES,
283
  X86_TUNE_SSE_LOAD0_BY_PXOR,
284
  X86_TUNE_MEMORY_MISMATCH_STALL,
285
  X86_TUNE_PROLOGUE_USING_MOVE,
286
  X86_TUNE_EPILOGUE_USING_MOVE,
287
  X86_TUNE_SHIFT1,
288
  X86_TUNE_USE_FFREEP,
289
  X86_TUNE_INTER_UNIT_MOVES,
290
  X86_TUNE_INTER_UNIT_CONVERSIONS,
291
  X86_TUNE_FOUR_JUMP_LIMIT,
292
  X86_TUNE_SCHEDULE,
293
  X86_TUNE_USE_BT,
294
  X86_TUNE_USE_INCDEC,
295
  X86_TUNE_PAD_RETURNS,
296
  X86_TUNE_EXT_80387_CONSTANTS,
297
  X86_TUNE_SHORTEN_X87_SSE,
298
  X86_TUNE_AVOID_VECTOR_DECODE,
299
  X86_TUNE_PROMOTE_HIMODE_IMUL,
300
  X86_TUNE_SLOW_IMUL_IMM32_MEM,
301
  X86_TUNE_SLOW_IMUL_IMM8,
302
  X86_TUNE_MOVE_M1_VIA_OR,
303
  X86_TUNE_NOT_UNPAIRABLE,
304
  X86_TUNE_NOT_VECTORMODE,
305
  X86_TUNE_USE_VECTOR_FP_CONVERTS,
306
  X86_TUNE_USE_VECTOR_CONVERTS,
307
  X86_TUNE_FUSE_CMP_AND_BRANCH,
308
  X86_TUNE_OPT_AGU,
309
 
310
  X86_TUNE_LAST
311
};
312
 
313
extern unsigned char ix86_tune_features[X86_TUNE_LAST];
314
 
315
#define TARGET_USE_LEAVE        ix86_tune_features[X86_TUNE_USE_LEAVE]
316
#define TARGET_PUSH_MEMORY      ix86_tune_features[X86_TUNE_PUSH_MEMORY]
317
#define TARGET_ZERO_EXTEND_WITH_AND \
318
        ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
319
#define TARGET_UNROLL_STRLEN    ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
320
#define TARGET_DEEP_BRANCH_PREDICTION \
321
        ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
322
#define TARGET_BRANCH_PREDICTION_HINTS \
323
        ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
324
#define TARGET_DOUBLE_WITH_ADD  ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
325
#define TARGET_USE_SAHF         ix86_tune_features[X86_TUNE_USE_SAHF]
326
#define TARGET_MOVX             ix86_tune_features[X86_TUNE_MOVX]
327
#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
328
#define TARGET_PARTIAL_FLAG_REG_STALL \
329
        ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
330
#define TARGET_USE_HIMODE_FIOP  ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
331
#define TARGET_USE_SIMODE_FIOP  ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
332
#define TARGET_USE_MOV0         ix86_tune_features[X86_TUNE_USE_MOV0]
333
#define TARGET_USE_CLTD         ix86_tune_features[X86_TUNE_USE_CLTD]
334
#define TARGET_USE_XCHGB        ix86_tune_features[X86_TUNE_USE_XCHGB]
335
#define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
336
#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
337
#define TARGET_READ_MODIFY      ix86_tune_features[X86_TUNE_READ_MODIFY]
338
#define TARGET_PROMOTE_QImode   ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
339
#define TARGET_FAST_PREFIX      ix86_tune_features[X86_TUNE_FAST_PREFIX]
340
#define TARGET_SINGLE_STRINGOP  ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
341
#define TARGET_QIMODE_MATH      ix86_tune_features[X86_TUNE_QIMODE_MATH]
342
#define TARGET_HIMODE_MATH      ix86_tune_features[X86_TUNE_HIMODE_MATH]
343
#define TARGET_PROMOTE_QI_REGS  ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
344
#define TARGET_PROMOTE_HI_REGS  ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
345
#define TARGET_ADD_ESP_4        ix86_tune_features[X86_TUNE_ADD_ESP_4]
346
#define TARGET_ADD_ESP_8        ix86_tune_features[X86_TUNE_ADD_ESP_8]
347
#define TARGET_SUB_ESP_4        ix86_tune_features[X86_TUNE_SUB_ESP_4]
348
#define TARGET_SUB_ESP_8        ix86_tune_features[X86_TUNE_SUB_ESP_8]
349
#define TARGET_INTEGER_DFMODE_MOVES \
350
        ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
351
#define TARGET_PARTIAL_REG_DEPENDENCY \
352
        ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
353
#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
354
        ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
355
#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
356
        ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
357
#define TARGET_SSE_SPLIT_REGS   ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
358
#define TARGET_SSE_TYPELESS_STORES \
359
        ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
360
#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
361
#define TARGET_MEMORY_MISMATCH_STALL \
362
        ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
363
#define TARGET_PROLOGUE_USING_MOVE \
364
        ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
365
#define TARGET_EPILOGUE_USING_MOVE \
366
        ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
367
#define TARGET_SHIFT1           ix86_tune_features[X86_TUNE_SHIFT1]
368
#define TARGET_USE_FFREEP       ix86_tune_features[X86_TUNE_USE_FFREEP]
369
#define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
370
#define TARGET_INTER_UNIT_CONVERSIONS\
371
        ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
372
#define TARGET_FOUR_JUMP_LIMIT  ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
373
#define TARGET_SCHEDULE         ix86_tune_features[X86_TUNE_SCHEDULE]
374
#define TARGET_USE_BT           ix86_tune_features[X86_TUNE_USE_BT]
375
#define TARGET_USE_INCDEC       ix86_tune_features[X86_TUNE_USE_INCDEC]
376
#define TARGET_PAD_RETURNS      ix86_tune_features[X86_TUNE_PAD_RETURNS]
377
#define TARGET_EXT_80387_CONSTANTS \
378
        ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
379
#define TARGET_SHORTEN_X87_SSE  ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
380
#define TARGET_AVOID_VECTOR_DECODE \
381
        ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
382
#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
383
        ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
384
#define TARGET_SLOW_IMUL_IMM32_MEM \
385
        ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
386
#define TARGET_SLOW_IMUL_IMM8   ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
387
#define TARGET_MOVE_M1_VIA_OR   ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
388
#define TARGET_NOT_UNPAIRABLE   ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
389
#define TARGET_NOT_VECTORMODE   ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
390
#define TARGET_USE_VECTOR_FP_CONVERTS \
391
        ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
392
#define TARGET_USE_VECTOR_CONVERTS \
393
        ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
394
#define TARGET_FUSE_CMP_AND_BRANCH \
395
        ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
396
#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
397
 
398
/* Feature tests against the various architecture variations.  */
399
enum ix86_arch_indices {
400
  X86_ARCH_CMOVE,               /* || TARGET_SSE */
401
  X86_ARCH_CMPXCHG,
402
  X86_ARCH_CMPXCHG8B,
403
  X86_ARCH_XADD,
404
  X86_ARCH_BSWAP,
405
 
406
  X86_ARCH_LAST
407
};
408
 
409
extern unsigned char ix86_arch_features[X86_ARCH_LAST];
410
 
411
#define TARGET_CMOVE            ix86_arch_features[X86_ARCH_CMOVE]
412
#define TARGET_CMPXCHG          ix86_arch_features[X86_ARCH_CMPXCHG]
413
#define TARGET_CMPXCHG8B        ix86_arch_features[X86_ARCH_CMPXCHG8B]
414
#define TARGET_XADD             ix86_arch_features[X86_ARCH_XADD]
415
#define TARGET_BSWAP            ix86_arch_features[X86_ARCH_BSWAP]
416
 
417
#define TARGET_FISTTP           (TARGET_SSE3 && TARGET_80387)
418
 
419
extern int x86_prefetch_sse;
420
 
421
#define TARGET_PREFETCH_SSE     x86_prefetch_sse
422
 
423
#define ASSEMBLER_DIALECT       (ix86_asm_dialect)
424
 
425
#define TARGET_SSE_MATH         ((ix86_fpmath & FPMATH_SSE) != 0)
426
#define TARGET_MIX_SSE_I387 \
427
 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
428
 
429
#define TARGET_GNU_TLS          (ix86_tls_dialect == TLS_DIALECT_GNU)
430
#define TARGET_GNU2_TLS         (ix86_tls_dialect == TLS_DIALECT_GNU2)
431
#define TARGET_ANY_GNU_TLS      (TARGET_GNU_TLS || TARGET_GNU2_TLS)
432
#define TARGET_SUN_TLS          0
433
 
434
extern int ix86_isa_flags;
435
 
436
#ifndef TARGET_64BIT_DEFAULT
437
#define TARGET_64BIT_DEFAULT 0
438
#endif
439
#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
440
#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
441
#endif
442
 
443
/* Fence to use after loop using storent.  */
444
 
445
extern tree x86_mfence;
446
#define FENCE_FOLLOWING_MOVNT x86_mfence
447
 
448
/* Once GDB has been enhanced to deal with functions without frame
449
   pointers, we can change this to allow for elimination of
450
   the frame pointer in leaf functions.  */
451
#define TARGET_DEFAULT 0
452
 
453
/* Extra bits to force.  */
454
#define TARGET_SUBTARGET_DEFAULT 0
455
#define TARGET_SUBTARGET_ISA_DEFAULT 0
456
 
457
/* Extra bits to force on w/ 32-bit mode.  */
458
#define TARGET_SUBTARGET32_DEFAULT 0
459
#define TARGET_SUBTARGET32_ISA_DEFAULT 0
460
 
461
/* Extra bits to force on w/ 64-bit mode.  */
462
#define TARGET_SUBTARGET64_DEFAULT 0
463
#define TARGET_SUBTARGET64_ISA_DEFAULT 0
464
 
465
/* This is not really a target flag, but is done this way so that
466
   it's analogous to similar code for Mach-O on PowerPC.  darwin.h
467
   redefines this to 1.  */
468
#define TARGET_MACHO 0
469
 
470
/* Likewise, for the Windows 64-bit ABI.  */
471
#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
472
 
473
/* Available call abi.  */
474
enum calling_abi
475
{
476
  SYSV_ABI = 0,
477
  MS_ABI = 1
478
};
479
 
480
/* The abi used by target.  */
481
extern enum calling_abi ix86_abi;
482
 
483
/* The default abi used by target.  */
484
#define DEFAULT_ABI SYSV_ABI
485
 
486
/* Subtargets may reset this to 1 in order to enable 96-bit long double
487
   with the rounding mode forced to 53 bits.  */
488
#define TARGET_96_ROUND_53_LONG_DOUBLE 0
489
 
490
/* Sometimes certain combinations of command options do not make
491
   sense on a particular target machine.  You can define a macro
492
   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
493
   defined, is executed once just after all the command options have
494
   been parsed.
495
 
496
   Don't use this macro to turn on various extra optimizations for
497
   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
498
 
499
#define OVERRIDE_OPTIONS override_options (true)
500
 
501
/* Define this to change the optimizations performed by default.  */
502
#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
503
  optimization_options ((LEVEL), (SIZE))
504
 
505
/* -march=native handling only makes sense with compiler running on
506
   an x86 or x86_64 chip.  If changing this condition, also change
507
   the condition in driver-i386.c.  */
508
#if defined(__i386__) || defined(__x86_64__)
509
/* In driver-i386.c.  */
510
extern const char *host_detect_local_cpu (int argc, const char **argv);
511
#define EXTRA_SPEC_FUNCTIONS \
512
  { "local_cpu_detect", host_detect_local_cpu },
513
#define HAVE_LOCAL_CPU_DETECT
514
#endif
515
 
516
#if TARGET_64BIT_DEFAULT
517
#define OPT_ARCH64 "!m32"
518
#define OPT_ARCH32 "m32"
519
#else
520
#define OPT_ARCH64 "m64"
521
#define OPT_ARCH32 "!m64"
522
#endif
523
 
524
/* Support for configure-time defaults of some command line options.
525
   The order here is important so that -march doesn't squash the
526
   tune or cpu values.  */
527
#define OPTION_DEFAULT_SPECS                                       \
528
  {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
529
  {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
530
  {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
531
  {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" },  \
532
  {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
533
  {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
534
  {"arch", "%{!march=*:-march=%(VALUE)}"},                         \
535
  {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"},    \
536
  {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
537
 
538
/* Specs for the compiler proper */
539
 
540
#ifndef CC1_CPU_SPEC
541
#define CC1_CPU_SPEC_1 "\
542
%{mcpu=*:-mtune=%* \
543
%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
544
%<mcpu=* \
545
%{mintel-syntax:-masm=intel \
546
%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
547
%{msse5:-mavx \
548
%n'-msse5' was removed.\n} \
549
%{mno-intel-syntax:-masm=att \
550
%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
551
 
552
#ifndef HAVE_LOCAL_CPU_DETECT
553
#define CC1_CPU_SPEC CC1_CPU_SPEC_1
554
#else
555
#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
556
"%{march=native:%<march=native %:local_cpu_detect(arch) \
557
  %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
558
%{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
559
#endif
560
#endif
561
 
562
/* Target CPU builtins.  */
563
#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
564
 
565
/* Target Pragmas.  */
566
#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
567
 
568
enum target_cpu_default
569
{
570
  TARGET_CPU_DEFAULT_generic = 0,
571
 
572
  TARGET_CPU_DEFAULT_i386,
573
  TARGET_CPU_DEFAULT_i486,
574
  TARGET_CPU_DEFAULT_pentium,
575
  TARGET_CPU_DEFAULT_pentium_mmx,
576
  TARGET_CPU_DEFAULT_pentiumpro,
577
  TARGET_CPU_DEFAULT_pentium2,
578
  TARGET_CPU_DEFAULT_pentium3,
579
  TARGET_CPU_DEFAULT_pentium4,
580
  TARGET_CPU_DEFAULT_pentium_m,
581
  TARGET_CPU_DEFAULT_prescott,
582
  TARGET_CPU_DEFAULT_nocona,
583
  TARGET_CPU_DEFAULT_core2,
584
  TARGET_CPU_DEFAULT_atom,
585
 
586
  TARGET_CPU_DEFAULT_geode,
587
  TARGET_CPU_DEFAULT_k6,
588
  TARGET_CPU_DEFAULT_k6_2,
589
  TARGET_CPU_DEFAULT_k6_3,
590
  TARGET_CPU_DEFAULT_athlon,
591
  TARGET_CPU_DEFAULT_athlon_sse,
592
  TARGET_CPU_DEFAULT_k8,
593
  TARGET_CPU_DEFAULT_amdfam10,
594
 
595
  TARGET_CPU_DEFAULT_max
596
};
597
 
598
#ifndef CC1_SPEC
599
#define CC1_SPEC "%(cc1_cpu) "
600
#endif
601
 
602
/* This macro defines names of additional specifications to put in the
603
   specs that can be used in various specifications like CC1_SPEC.  Its
604
   definition is an initializer with a subgrouping for each command option.
605
 
606
   Each subgrouping contains a string constant, that defines the
607
   specification name, and a string constant that used by the GCC driver
608
   program.
609
 
610
   Do not define this macro if it does not need to do anything.  */
611
 
612
#ifndef SUBTARGET_EXTRA_SPECS
613
#define SUBTARGET_EXTRA_SPECS
614
#endif
615
 
616
#define EXTRA_SPECS                                                     \
617
  { "cc1_cpu",  CC1_CPU_SPEC },                                         \
618
  SUBTARGET_EXTRA_SPECS
619
 
620
 
621
/* Set the value of FLT_EVAL_METHOD in float.h.  When using only the
622
   FPU, assume that the fpcw is set to extended precision; when using
623
   only SSE, rounding is correct; when using both SSE and the FPU,
624
   the rounding precision is indeterminate, since either may be chosen
625
   apparently at random.  */
626
#define TARGET_FLT_EVAL_METHOD \
627
  (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
628
 
629
/* Whether to allow x87 floating-point arithmetic on MODE (one of
630
   SFmode, DFmode and XFmode) in the current excess precision
631
   configuration.  */
632
#define X87_ENABLE_ARITH(MODE) \
633
  (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)
634
 
635
/* Likewise, whether to allow direct conversions from integer mode
636
   IMODE (HImode, SImode or DImode) to MODE.  */
637
#define X87_ENABLE_FLOAT(MODE, IMODE)                   \
638
  (flag_excess_precision == EXCESS_PRECISION_FAST       \
639
   || (MODE) == XFmode                                  \
640
   || ((MODE) == DFmode && (IMODE) == SImode)           \
641
   || (IMODE) == HImode)
642
 
643
/* target machine storage layout */
644
 
645
#define SHORT_TYPE_SIZE 16
646
#define INT_TYPE_SIZE 32
647
#define FLOAT_TYPE_SIZE 32
648
#define LONG_TYPE_SIZE BITS_PER_WORD
649
#define DOUBLE_TYPE_SIZE 64
650
#define LONG_LONG_TYPE_SIZE 64
651
#define LONG_DOUBLE_TYPE_SIZE 80
652
 
653
#define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE
654
 
655
#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
656
#define MAX_BITS_PER_WORD 64
657
#else
658
#define MAX_BITS_PER_WORD 32
659
#endif
660
 
661
/* Define this if most significant byte of a word is the lowest numbered.  */
662
/* That is true on the 80386.  */
663
 
664
#define BITS_BIG_ENDIAN 0
665
 
666
/* Define this if most significant byte of a word is the lowest numbered.  */
667
/* That is not true on the 80386.  */
668
#define BYTES_BIG_ENDIAN 0
669
 
670
/* Define this if most significant word of a multiword number is the lowest
671
   numbered.  */
672
/* Not true for 80386 */
673
#define WORDS_BIG_ENDIAN 0
674
 
675
/* Width of a word, in units (bytes).  */
676
#define UNITS_PER_WORD          (TARGET_64BIT ? 8 : 4)
677
#ifdef IN_LIBGCC2
678
#define MIN_UNITS_PER_WORD      (TARGET_64BIT ? 8 : 4)
679
#else
680
#define MIN_UNITS_PER_WORD      4
681
#endif
682
 
683
/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
684
#define PARM_BOUNDARY BITS_PER_WORD
685
 
686
/* Boundary (in *bits*) on which stack pointer should be aligned.  */
687
#define STACK_BOUNDARY \
688
 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
689
 
690
/* Stack boundary of the main function guaranteed by OS.  */
691
#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
692
 
693
/* Minimum stack boundary.  */
694
#define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
695
 
696
/* Boundary (in *bits*) on which the stack pointer prefers to be
697
   aligned; the compiler cannot rely on having this alignment.  */
698
#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
699
 
700
/* It should be MIN_STACK_BOUNDARY.  But we set it to 128 bits for
701
   both 32bit and 64bit, to support codes that need 128 bit stack
702
   alignment for SSE instructions, but can't realign the stack.  */
703
#define PREFERRED_STACK_BOUNDARY_DEFAULT 128
704
 
705
/* 1 if -mstackrealign should be turned on by default.  It will
706
   generate an alternate prologue and epilogue that realigns the
707
   runtime stack if nessary.  This supports mixing codes that keep a
708
   4-byte aligned stack, as specified by i386 psABI, with codes that
709
   need a 16-byte aligned stack, as required by SSE instructions.  */
710
#define STACK_REALIGN_DEFAULT 0
711
 
712
/* Boundary (in *bits*) on which the incoming stack is aligned.  */
713
#define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
714
 
715
/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack.  This is
716
   mandatory for the 64-bit ABI, and may or may not be true for other
717
   operating systems.  */
718
#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
719
 
720
/* Minimum allocation boundary for the code of a function.  */
721
#define FUNCTION_BOUNDARY 8
722
 
723
/* C++ stores the virtual bit in the lowest bit of function pointers.  */
724
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
725
 
726
/* Alignment of field after `int : 0' in a structure.  */
727
 
728
#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
729
 
730
/* Minimum size in bits of the largest boundary to which any
731
   and all fundamental data types supported by the hardware
732
   might need to be aligned. No data type wants to be aligned
733
   rounder than this.
734
 
735
   Pentium+ prefers DFmode values to be aligned to 64 bit boundary
736
   and Pentium Pro XFmode values at 128 bit boundaries.  */
737
 
738
#define BIGGEST_ALIGNMENT (TARGET_AVX ? 256: 128)
739
 
740
/* Maximum stack alignment.  */
741
#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
742
 
743
/* Alignment value for attribute ((aligned)).  It is a constant since
744
   it is the part of the ABI.  We shouldn't change it with -mavx.  */
745
#define ATTRIBUTE_ALIGNED_VALUE 128
746
 
747
/* Decide whether a variable of mode MODE should be 128 bit aligned.  */
748
#define ALIGN_MODE_128(MODE) \
749
 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
750
 
751
/* The published ABIs say that doubles should be aligned on word
752
   boundaries, so lower the alignment for structure fields unless
753
   -malign-double is set.  */
754
 
755
/* ??? Blah -- this macro is used directly by libobjc.  Since it
756
   supports no vector modes, cut out the complexity and fall back
757
   on BIGGEST_FIELD_ALIGNMENT.  */
758
#ifdef IN_TARGET_LIBS
759
#ifdef __x86_64__
760
#define BIGGEST_FIELD_ALIGNMENT 128
761
#else
762
#define BIGGEST_FIELD_ALIGNMENT 32
763
#endif
764
#else
765
#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
766
   x86_field_alignment (FIELD, COMPUTED)
767
#endif
768
 
769
/* If defined, a C expression to compute the alignment given to a
770
   constant that is being placed in memory.  EXP is the constant
771
   and ALIGN is the alignment that the object would ordinarily have.
772
   The value of this macro is used instead of that alignment to align
773
   the object.
774
 
775
   If this macro is not defined, then ALIGN is used.
776
 
777
   The typical use of this macro is to increase alignment for string
778
   constants to be word aligned so that `strcpy' calls that copy
779
   constants can be done inline.  */
780
 
781
#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
782
 
783
/* If defined, a C expression to compute the alignment for a static
784
   variable.  TYPE is the data type, and ALIGN is the alignment that
785
   the object would ordinarily have.  The value of this macro is used
786
   instead of that alignment to align the object.
787
 
788
   If this macro is not defined, then ALIGN is used.
789
 
790
   One use of this macro is to increase alignment of medium-size
791
   data to make it all fit in fewer cache lines.  Another is to
792
   cause character arrays to be word-aligned so that `strcpy' calls
793
   that copy constants to character arrays can be done inline.  */
794
 
795
#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
796
 
797
/* If defined, a C expression to compute the alignment for a local
798
   variable.  TYPE is the data type, and ALIGN is the alignment that
799
   the object would ordinarily have.  The value of this macro is used
800
   instead of that alignment to align the object.
801
 
802
   If this macro is not defined, then ALIGN is used.
803
 
804
   One use of this macro is to increase alignment of medium-size
805
   data to make it all fit in fewer cache lines.  */
806
 
807
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
808
  ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
809
 
810
/* If defined, a C expression to compute the alignment for stack slot.
811
   TYPE is the data type, MODE is the widest mode available, and ALIGN
812
   is the alignment that the slot would ordinarily have.  The value of
813
   this macro is used instead of that alignment to align the slot.
814
 
815
   If this macro is not defined, then ALIGN is used when TYPE is NULL,
816
   Otherwise, LOCAL_ALIGNMENT will be used.
817
 
818
   One use of this macro is to set alignment of stack slot to the
819
   maximum alignment of all possible modes which the slot may have.  */
820
 
821
#define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
822
  ix86_local_alignment ((TYPE), (MODE), (ALIGN))
823
 
824
/* If defined, a C expression to compute the alignment for a local
825
   variable DECL.
826
 
827
   If this macro is not defined, then
828
   LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
829
 
830
   One use of this macro is to increase alignment of medium-size
831
   data to make it all fit in fewer cache lines.  */
832
 
833
#define LOCAL_DECL_ALIGNMENT(DECL) \
834
  ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
835
 
836
/* If defined, a C expression to compute the minimum required alignment
837
   for dynamic stack realignment purposes for EXP (a TYPE or DECL),
838
   MODE, assuming normal alignment ALIGN.
839
 
840
   If this macro is not defined, then (ALIGN) will be used.  */
841
 
842
#define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
843
  ix86_minimum_alignment (EXP, MODE, ALIGN)
844
 
845
 
846
/* If defined, a C expression that gives the alignment boundary, in
847
   bits, of an argument with the specified mode and type.  If it is
848
   not defined, `PARM_BOUNDARY' is used for all arguments.  */
849
 
850
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
851
  ix86_function_arg_boundary ((MODE), (TYPE))
852
 
853
/* Set this nonzero if move instructions will actually fail to work
854
   when given unaligned data.  */
855
#define STRICT_ALIGNMENT 0
856
 
857
/* If bit field type is int, don't let it cross an int,
858
   and give entire struct the alignment of an int.  */
859
/* Required on the 386 since it doesn't have bit-field insns.  */
860
#define PCC_BITFIELD_TYPE_MATTERS 1
861
 
862
/* Standard register usage.  */
863
 
864
/* This processor has special stack-like registers.  See reg-stack.c
865
   for details.  */
866
 
867
#define STACK_REGS
868
 
869
#define IS_STACK_MODE(MODE)                                     \
870
  (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH))      \
871
   || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH))  \
872
   || (MODE) == XFmode)
873
 
874
/* Cover class containing the stack registers.  */
875
#define STACK_REG_COVER_CLASS FLOAT_REGS
876
 
877
/* Number of actual hardware registers.
878
   The hardware registers are assigned numbers for the compiler
879
   from 0 to just below FIRST_PSEUDO_REGISTER.
880
   All registers that the compiler knows about must be given numbers,
881
   even those that are not normally considered general registers.
882
 
883
   In the 80386 we give the 8 general purpose registers the numbers 0-7.
884
   We number the floating point registers 8-15.
885
   Note that registers 0-7 can be accessed as a  short or int,
886
   while only 0-3 may be used with byte `mov' instructions.
887
 
888
   Reg 16 does not correspond to any hardware register, but instead
889
   appears in the RTL as an argument pointer prior to reload, and is
890
   eliminated during reloading in favor of either the stack or frame
891
   pointer.  */
892
 
893
#define FIRST_PSEUDO_REGISTER 53
894
 
895
/* Number of hardware registers that go into the DWARF-2 unwind info.
896
   If not defined, equals FIRST_PSEUDO_REGISTER.  */
897
 
898
#define DWARF_FRAME_REGISTERS 17
899
 
900
/* 1 for registers that have pervasive standard uses
901
   and are not available for the register allocator.
902
   On the 80386, the stack pointer is such, as is the arg pointer.
903
 
904
   The value is zero if the register is not fixed on either 32 or
905
   64 bit targets, one if the register if fixed on both 32 and 64
906
   bit targets, two if it is only fixed on 32bit targets and three
907
   if its only fixed on 64bit targets.
908
   Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
909
 */
910
#define FIXED_REGISTERS                                         \
911
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/      \
912
{  0, 0, 0, 0, 0, 0, 0, 1, 0,  0,  0,  0,  0,  0,  0,  0,       \
913
/*arg,flags,fpsr,fpcr,frame*/                                   \
914
    1,    1,   1,   1,    1,                                    \
915
/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/                     \
916
     0,   0,   0,   0,   0,   0,   0,   0,                      \
917
/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/                     \
918
     0,   0,   0,   0,   0,   0,   0,   0,                      \
919
/*  r8,  r9, r10, r11, r12, r13, r14, r15*/                     \
920
     2,   2,   2,   2,   2,   2,   2,   2,                      \
921
/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/               \
922
     2,   2,    2,    2,    2,    2,    2,    2 }
923
 
924
 
925
/* 1 for registers not available across function calls.
926
   These must include the FIXED_REGISTERS and also any
927
   registers that can be used without being saved.
928
   The latter must include the registers where values are returned
929
   and the register where structure-value addresses are passed.
930
   Aside from that, you can include as many other registers as you like.
931
 
932
   The value is zero if the register is not call used on either 32 or
933
   64 bit targets, one if the register if call used on both 32 and 64
934
   bit targets, two if it is only call used on 32bit targets and three
935
   if its only call used on 64bit targets.
936
   Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
937
*/
938
#define CALL_USED_REGISTERS                                     \
939
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/      \
940
{  1, 1, 1, 0, 3, 3, 0, 1, 1,  1,  1,  1,  1,  1,  1,  1,       \
941
/*arg,flags,fpsr,fpcr,frame*/                                   \
942
    1,   1,    1,   1,    1,                                    \
943
/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/                     \
944
     1,   1,   1,   1,   1,   1,   1,   1,                      \
945
/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/                     \
946
     1,   1,   1,   1,   1,   1,   1,   1,                      \
947
/*  r8,  r9, r10, r11, r12, r13, r14, r15*/                     \
948
     1,   1,   1,   1,   2,   2,   2,   2,                      \
949
/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/               \
950
     1,   1,    1,    1,    1,    1,    1,    1 }
951
 
952
/* Order in which to allocate registers.  Each register must be
953
   listed once, even those in FIXED_REGISTERS.  List frame pointer
954
   late and fixed registers last.  Note that, in general, we prefer
955
   registers listed in CALL_USED_REGISTERS, keeping the others
956
   available for storage of persistent values.
957
 
958
   The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
959
   so this is just empty initializer for array.  */
960
 
961
#define REG_ALLOC_ORDER                                         \
962
{  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
963
   18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,  \
964
   33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,  \
965
   48, 49, 50, 51, 52 }
966
 
967
/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
968
   to be rearranged based on a particular function.  When using sse math,
969
   we want to allocate SSE before x87 registers and vice versa.  */
970
 
971
#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
972
 
973
 
974
#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
975
 
976
/* Macro to conditionally modify fixed_regs/call_used_regs.  */
977
#define CONDITIONAL_REGISTER_USAGE  ix86_conditional_register_usage ()
978
 
979
/* Return number of consecutive hard regs needed starting at reg REGNO
980
   to hold something of mode MODE.
981
   This is ordinarily the length in words of a value of mode MODE
982
   but can be less for certain modes in special long registers.
983
 
984
   Actually there are no two word move instructions for consecutive
985
   registers.  And only registers 0-3 may have mov byte instructions
986
   applied to them.
987
   */
988
 
989
#define HARD_REGNO_NREGS(REGNO, MODE)                                   \
990
  (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO)     \
991
   ? (COMPLEX_MODE_P (MODE) ? 2 : 1)                                    \
992
   : ((MODE) == XFmode                                                  \
993
      ? (TARGET_64BIT ? 2 : 3)                                          \
994
      : (MODE) == XCmode                                                \
995
      ? (TARGET_64BIT ? 4 : 6)                                          \
996
      : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
997
 
998
#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE)                       \
999
  ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT)                         \
1000
   ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO)  \
1001
      ? 0                                                               \
1002
      : ((MODE) == XFmode || (MODE) == XCmode))                         \
1003
   : 0)
1004
 
1005
#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1006
 
1007
#define VALID_AVX256_REG_MODE(MODE)                                     \
1008
  ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode     \
1009
   || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)
1010
 
1011
#define VALID_SSE2_REG_MODE(MODE)                                       \
1012
  ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode      \
1013
   || (MODE) == V2DImode || (MODE) == DFmode)
1014
 
1015
#define VALID_SSE_REG_MODE(MODE)                                        \
1016
  ((MODE) == V1TImode || (MODE) == TImode                               \
1017
   || (MODE) == V4SFmode || (MODE) == V4SImode                          \
1018
   || (MODE) == SFmode || (MODE) == TFmode)
1019
 
1020
#define VALID_MMX_REG_MODE_3DNOW(MODE) \
1021
  ((MODE) == V2SFmode || (MODE) == SFmode)
1022
 
1023
#define VALID_MMX_REG_MODE(MODE)                                        \
1024
  ((MODE == V1DImode) || (MODE) == DImode                               \
1025
   || (MODE) == V2SImode || (MODE) == SImode                            \
1026
   || (MODE) == V4HImode || (MODE) == V8QImode)
1027
 
1028
/* ??? No autovectorization into MMX or 3DNOW until we can reliably
1029
   place emms and femms instructions.
1030
   FIXME: AVX has 32byte floating point vector operations and 16byte
1031
   integer vector operations.  But vectorizer doesn't support
1032
   different sizes for integer and floating point vectors.  We limit
1033
   vector size to 16byte.  */
1034
#define UNITS_PER_SIMD_WORD(MODE)                                       \
1035
  (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 16 : 16)      \
1036
              : (TARGET_SSE ? 16 : UNITS_PER_WORD))
1037
 
1038
#define VALID_DFP_MODE_P(MODE) \
1039
  ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1040
 
1041
#define VALID_FP_MODE_P(MODE)                                           \
1042
  ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode             \
1043
   || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode)         \
1044
 
1045
#define VALID_INT_MODE_P(MODE)                                          \
1046
  ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode             \
1047
   || (MODE) == DImode                                                  \
1048
   || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode       \
1049
   || (MODE) == CDImode                                                 \
1050
   || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode           \
1051
                        || (MODE) == TFmode || (MODE) == TCmode)))
1052
 
1053
/* Return true for modes passed in SSE registers.  */
1054
#define SSE_REG_MODE_P(MODE)                                            \
1055
  ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode        \
1056
   || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode      \
1057
   || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode    \
1058
   || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode  \
1059
   || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)
1060
 
1061
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.  */
1062
 
1063
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
1064
   ix86_hard_regno_mode_ok ((REGNO), (MODE))
1065
 
1066
/* Value is 1 if it is a good idea to tie two pseudo registers
1067
   when one has mode MODE1 and one has mode MODE2.
1068
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1069
   for any hard reg, then this must be 0 for correct output.  */
1070
 
1071
#define MODES_TIEABLE_P(MODE1, MODE2)  ix86_modes_tieable_p (MODE1, MODE2)
1072
 
1073
/* It is possible to write patterns to move flags; but until someone
1074
   does it,  */
1075
#define AVOID_CCMODE_COPIES
1076
 
1077
/* Specify the modes required to caller save a given hard regno.
1078
   We do this on i386 to prevent flags from being saved at all.
1079
 
1080
   Kill any attempts to combine saving of modes.  */
1081
 
1082
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE)                 \
1083
  (CC_REGNO_P (REGNO) ? VOIDmode                                        \
1084
   : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode                      \
1085
   : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1086
   : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode             \
1087
   : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode     \
1088
   : (MODE))
1089
 
1090
/* Specify the registers used for certain standard purposes.
1091
   The values of these macros are register numbers.  */
1092
 
1093
/* on the 386 the pc register is %eip, and is not usable as a general
1094
   register.  The ordinary mov instructions won't work */
1095
/* #define PC_REGNUM  */
1096
 
1097
/* Register to use for pushing function arguments.  */
1098
#define STACK_POINTER_REGNUM 7
1099
 
1100
/* Base register for access to local variables of the function.  */
1101
#define HARD_FRAME_POINTER_REGNUM 6
1102
 
1103
/* Base register for access to local variables of the function.  */
1104
#define FRAME_POINTER_REGNUM 20
1105
 
1106
/* First floating point reg */
1107
#define FIRST_FLOAT_REG 8
1108
 
1109
/* First & last stack-like regs */
1110
#define FIRST_STACK_REG FIRST_FLOAT_REG
1111
#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1112
 
1113
#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1114
#define LAST_SSE_REG  (FIRST_SSE_REG + 7)
1115
 
1116
#define FIRST_MMX_REG  (LAST_SSE_REG + 1)
1117
#define LAST_MMX_REG   (FIRST_MMX_REG + 7)
1118
 
1119
#define FIRST_REX_INT_REG  (LAST_MMX_REG + 1)
1120
#define LAST_REX_INT_REG   (FIRST_REX_INT_REG + 7)
1121
 
1122
#define FIRST_REX_SSE_REG  (LAST_REX_INT_REG + 1)
1123
#define LAST_REX_SSE_REG   (FIRST_REX_SSE_REG + 7)
1124
 
1125
/* Override this in other tm.h files to cope with various OS lossage
1126
   requiring a frame pointer.  */
1127
#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1128
#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1129
#endif
1130
 
1131
/* Make sure we can access arbitrary call frames.  */
1132
#define SETUP_FRAME_ADDRESSES()  ix86_setup_frame_addresses ()
1133
 
1134
/* Base register for access to arguments of the function.  */
1135
#define ARG_POINTER_REGNUM 16
1136
 
1137
/* Register to hold the addressing base for position independent
1138
   code access to data items.  We don't use PIC pointer for 64bit
1139
   mode.  Define the regnum to dummy value to prevent gcc from
1140
   pessimizing code dealing with EBX.
1141
 
1142
   To avoid clobbering a call-saved register unnecessarily, we renumber
1143
   the pic register when possible.  The change is visible after the
1144
   prologue has been emitted.  */
1145
 
1146
#define REAL_PIC_OFFSET_TABLE_REGNUM  BX_REG
1147
 
1148
#define PIC_OFFSET_TABLE_REGNUM                         \
1149
  ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC)        \
1150
   || !flag_pic ? INVALID_REGNUM                        \
1151
   : reload_completed ? REGNO (pic_offset_table_rtx)    \
1152
   : REAL_PIC_OFFSET_TABLE_REGNUM)
1153
 
1154
#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1155
 
1156
/* This is overridden by <cygwin.h>.  */
1157
#define MS_AGGREGATE_RETURN 0
1158
 
1159
/* This is overridden by <netware.h>.  */
1160
#define KEEP_AGGREGATE_RETURN_POINTER 0
1161
 
1162
/* Define the classes of registers for register constraints in the
1163
   machine description.  Also define ranges of constants.
1164
 
1165
   One of the classes must always be named ALL_REGS and include all hard regs.
1166
   If there is more than one class, another class must be named NO_REGS
1167
   and contain no registers.
1168
 
1169
   The name GENERAL_REGS must be the name of a class (or an alias for
1170
   another name such as ALL_REGS).  This is the class of registers
1171
   that is allowed by "g" or "r" in a register constraint.
1172
   Also, registers outside this class are allocated only when
1173
   instructions express preferences for them.
1174
 
1175
   The classes must be numbered in nondecreasing order; that is,
1176
   a larger-numbered class must never be contained completely
1177
   in a smaller-numbered class.
1178
 
1179
   For any two classes, it is very desirable that there be another
1180
   class that represents their union.
1181
 
1182
   It might seem that class BREG is unnecessary, since no useful 386
1183
   opcode needs reg %ebx.  But some systems pass args to the OS in ebx,
1184
   and the "b" register constraint is useful in asms for syscalls.
1185
 
1186
   The flags, fpsr and fpcr registers are in no class.  */
1187
 
1188
enum reg_class
1189
{
1190
  NO_REGS,
1191
  AREG, DREG, CREG, BREG, SIREG, DIREG,
1192
  AD_REGS,                      /* %eax/%edx for DImode */
1193
  CLOBBERED_REGS,               /* call-clobbered integers */
1194
  Q_REGS,                       /* %eax %ebx %ecx %edx */
1195
  NON_Q_REGS,                   /* %esi %edi %ebp %esp */
1196
  INDEX_REGS,                   /* %eax %ebx %ecx %edx %esi %edi %ebp */
1197
  LEGACY_REGS,                  /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1198
  GENERAL_REGS,                 /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1199
  FP_TOP_REG, FP_SECOND_REG,    /* %st(0) %st(1) */
1200
  FLOAT_REGS,
1201
  SSE_FIRST_REG,
1202
  SSE_REGS,
1203
  MMX_REGS,
1204
  FP_TOP_SSE_REGS,
1205
  FP_SECOND_SSE_REGS,
1206
  FLOAT_SSE_REGS,
1207
  FLOAT_INT_REGS,
1208
  INT_SSE_REGS,
1209
  FLOAT_INT_SSE_REGS,
1210
  ALL_REGS, LIM_REG_CLASSES
1211
};
1212
 
1213
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1214
 
1215
#define INTEGER_CLASS_P(CLASS) \
1216
  reg_class_subset_p ((CLASS), GENERAL_REGS)
1217
#define FLOAT_CLASS_P(CLASS) \
1218
  reg_class_subset_p ((CLASS), FLOAT_REGS)
1219
#define SSE_CLASS_P(CLASS) \
1220
  reg_class_subset_p ((CLASS), SSE_REGS)
1221
#define MMX_CLASS_P(CLASS) \
1222
  ((CLASS) == MMX_REGS)
1223
#define MAYBE_INTEGER_CLASS_P(CLASS) \
1224
  reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1225
#define MAYBE_FLOAT_CLASS_P(CLASS) \
1226
  reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1227
#define MAYBE_SSE_CLASS_P(CLASS) \
1228
  reg_classes_intersect_p (SSE_REGS, (CLASS))
1229
#define MAYBE_MMX_CLASS_P(CLASS) \
1230
  reg_classes_intersect_p (MMX_REGS, (CLASS))
1231
 
1232
#define Q_CLASS_P(CLASS) \
1233
  reg_class_subset_p ((CLASS), Q_REGS)
1234
 
1235
/* Give names of register classes as strings for dump file.  */
1236
 
1237
#define REG_CLASS_NAMES \
1238
{  "NO_REGS",                           \
1239
   "AREG", "DREG", "CREG", "BREG",      \
1240
   "SIREG", "DIREG",                    \
1241
   "AD_REGS",                           \
1242
   "CLOBBERED_REGS",                    \
1243
   "Q_REGS", "NON_Q_REGS",              \
1244
   "INDEX_REGS",                        \
1245
   "LEGACY_REGS",                       \
1246
   "GENERAL_REGS",                      \
1247
   "FP_TOP_REG", "FP_SECOND_REG",       \
1248
   "FLOAT_REGS",                        \
1249
   "SSE_FIRST_REG",                     \
1250
   "SSE_REGS",                          \
1251
   "MMX_REGS",                          \
1252
   "FP_TOP_SSE_REGS",                   \
1253
   "FP_SECOND_SSE_REGS",                \
1254
   "FLOAT_SSE_REGS",                    \
1255
   "FLOAT_INT_REGS",                    \
1256
   "INT_SSE_REGS",                      \
1257
   "FLOAT_INT_SSE_REGS",                \
1258
   "ALL_REGS" }
1259
 
1260
/* Define which registers fit in which classes.  This is an initializer
1261
   for a vector of HARD_REG_SET of length N_REG_CLASSES.
1262
 
1263
   Note that the default setting of CLOBBERED_REGS is for 32-bit; this
1264
   is adjusted by CONDITIONAL_REGISTER_USAGE for the 64-bit ABI in effect.  */
1265
 
1266
#define REG_CLASS_CONTENTS                                              \
1267
{     { 0x00,     0x0 },                                                \
1268
      { 0x01,     0x0 }, { 0x02, 0x0 }, /* AREG, DREG */                \
1269
      { 0x04,     0x0 }, { 0x08, 0x0 }, /* CREG, BREG */                \
1270
      { 0x10,     0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */              \
1271
      { 0x03,     0x0 },                /* AD_REGS */                   \
1272
      { 0x07,     0x0 },                /* CLOBBERED_REGS */            \
1273
      { 0x0f,     0x0 },                /* Q_REGS */                    \
1274
  { 0x1100f0,  0x1fe0 },                /* NON_Q_REGS */                \
1275
      { 0x7f,  0x1fe0 },                /* INDEX_REGS */                \
1276
  { 0x1100ff,     0x0 },                /* LEGACY_REGS */               \
1277
  { 0x1100ff,  0x1fe0 },                /* GENERAL_REGS */              \
1278
     { 0x100,     0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1279
    { 0xff00,     0x0 },                /* FLOAT_REGS */                \
1280
  { 0x200000,     0x0 },                /* SSE_FIRST_REG */             \
1281
{ 0x1fe00000,0x1fe000 },                /* SSE_REGS */                  \
1282
{ 0xe0000000,    0x1f },                /* MMX_REGS */                  \
1283
{ 0x1fe00100,0x1fe000 },                /* FP_TOP_SSE_REG */            \
1284
{ 0x1fe00200,0x1fe000 },                /* FP_SECOND_SSE_REG */         \
1285
{ 0x1fe0ff00,0x3fe000 },                /* FLOAT_SSE_REGS */            \
1286
   { 0x1ffff,  0x1fe0 },                /* FLOAT_INT_REGS */            \
1287
{ 0x1fe100ff,0x1fffe0 },                /* INT_SSE_REGS */              \
1288
{ 0x1fe1ffff,0x1fffe0 },                /* FLOAT_INT_SSE_REGS */        \
1289
{ 0xffffffff,0x1fffff }                                                 \
1290
}
1291
 
1292
/* The same information, inverted:
1293
   Return the class number of the smallest class containing
1294
   reg number REGNO.  This could be a conditional expression
1295
   or could index an array.  */
1296
 
1297
#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1298
 
1299
/* When defined, the compiler allows registers explicitly used in the
1300
   rtl to be used as spill registers but prevents the compiler from
1301
   extending the lifetime of these registers.  */
1302
 
1303
#define SMALL_REGISTER_CLASSES 1
1304
 
1305
#define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG)
1306
 
1307
#define GENERAL_REGNO_P(N) \
1308
  ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1309
 
1310
#define GENERAL_REG_P(X) \
1311
  (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1312
 
1313
#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1314
 
1315
#define REX_INT_REGNO_P(N) \
1316
  IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1317
#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1318
 
1319
#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1320
#define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1321
#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1322
#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1323
 
1324
#define X87_FLOAT_MODE_P(MODE)  \
1325
  (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1326
 
1327
#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1328
#define SSE_REGNO_P(N)                                          \
1329
  (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG)                  \
1330
   || REX_SSE_REGNO_P (N))
1331
 
1332
#define REX_SSE_REGNO_P(N) \
1333
  IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1334
 
1335
#define SSE_REGNO(N) \
1336
  ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1337
 
1338
#define SSE_FLOAT_MODE_P(MODE) \
1339
  ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1340
 
1341
#define SSE_VEC_FLOAT_MODE_P(MODE) \
1342
  ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode))
1343
 
1344
#define AVX_FLOAT_MODE_P(MODE) \
1345
  (TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode))
1346
 
1347
#define AVX128_VEC_FLOAT_MODE_P(MODE) \
1348
  (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode))
1349
 
1350
#define AVX256_VEC_FLOAT_MODE_P(MODE) \
1351
  (TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode))
1352
 
1353
#define AVX_VEC_FLOAT_MODE_P(MODE) \
1354
  (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1355
                  || (MODE) == V8SFmode || (MODE) == V4DFmode))
1356
 
1357
#define FMA4_VEC_FLOAT_MODE_P(MODE) \
1358
  (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1359
                  || (MODE) == V8SFmode || (MODE) == V4DFmode))
1360
 
1361
#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1362
#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1363
 
1364
#define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1365
#define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1366
 
1367
#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1368
 
1369
#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1370
#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1371
 
1372
/* The class value for index registers, and the one for base regs.  */
1373
 
1374
#define INDEX_REG_CLASS INDEX_REGS
1375
#define BASE_REG_CLASS GENERAL_REGS
1376
 
1377
/* Place additional restrictions on the register class to use when it
1378
   is necessary to be able to hold a value of mode MODE in a reload
1379
   register for which class CLASS would ordinarily be used.  */
1380
 
1381
#define LIMIT_RELOAD_CLASS(MODE, CLASS)                         \
1382
  ((MODE) == QImode && !TARGET_64BIT                            \
1383
   && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS           \
1384
       || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS)      \
1385
   ? Q_REGS : (CLASS))
1386
 
1387
/* Given an rtx X being reloaded into a reg required to be
1388
   in class CLASS, return the class of reg to actually use.
1389
   In general this is just CLASS; but on some machines
1390
   in some cases it is preferable to use a more restrictive class.
1391
   On the 80386 series, we prevent floating constants from being
1392
   reloaded into floating registers (since no move-insn can do that)
1393
   and we ensure that QImodes aren't reloaded into the esi or edi reg.  */
1394
 
1395
/* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1396
   QImode must go into class Q_REGS.
1397
   Narrow ALL_REGS to GENERAL_REGS.  This supports allowing movsf and
1398
   movdf to do mem-to-mem moves through integer regs.  */
1399
 
1400
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1401
   ix86_preferred_reload_class ((X), (CLASS))
1402
 
1403
/* Discourage putting floating-point values in SSE registers unless
1404
   SSE math is being used, and likewise for the 387 registers.  */
1405
 
1406
#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1407
   ix86_preferred_output_reload_class ((X), (CLASS))
1408
 
1409
/* If we are copying between general and FP registers, we need a memory
1410
   location. The same is true for SSE and MMX registers.  */
1411
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1412
  ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1413
 
1414
/* Get_secondary_mem widens integral modes to BITS_PER_WORD.
1415
   There is no need to emit full 64 bit move on 64 bit targets
1416
   for integral modes that can be moved using 32 bit move.  */
1417
#define SECONDARY_MEMORY_NEEDED_MODE(MODE)                      \
1418
  (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE)       \
1419
   ? mode_for_size (32, GET_MODE_CLASS (MODE), 0)               \
1420
   : MODE)
1421
 
1422
/* Return the maximum number of consecutive registers
1423
   needed to represent mode MODE in a register of class CLASS.  */
1424
/* On the 80386, this is the size of MODE in words,
1425
   except in the FP regs, where a single reg is always enough.  */
1426
#define CLASS_MAX_NREGS(CLASS, MODE)                                    \
1427
 (!MAYBE_INTEGER_CLASS_P (CLASS)                                        \
1428
  ? (COMPLEX_MODE_P (MODE) ? 2 : 1)                                     \
1429
  : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE)))                  \
1430
      + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1431
 
1432
/* A C expression whose value is nonzero if pseudos that have been
1433
   assigned to registers of class CLASS would likely be spilled
1434
   because registers of CLASS are needed for spill registers.
1435
 
1436
   The default value of this macro returns 1 if CLASS has exactly one
1437
   register and zero otherwise.  On most machines, this default
1438
   should be used.  Only define this macro to some other expression
1439
   if pseudo allocated by `local-alloc.c' end up in memory because
1440
   their hard registers were needed for spill registers.  If this
1441
   macro returns nonzero for those classes, those pseudos will only
1442
   be allocated by `global.c', which knows how to reallocate the
1443
   pseudo to another register.  If there would not be another
1444
   register available for reallocation, you should not change the
1445
   definition of this macro since the only effect of such a
1446
   definition would be to slow down register allocation.  */
1447
 
1448
#define CLASS_LIKELY_SPILLED_P(CLASS)                                   \
1449
  (((CLASS) == AREG)                                                    \
1450
   || ((CLASS) == DREG)                                                 \
1451
   || ((CLASS) == CREG)                                                 \
1452
   || ((CLASS) == BREG)                                                 \
1453
   || ((CLASS) == AD_REGS)                                              \
1454
   || ((CLASS) == SIREG)                                                \
1455
   || ((CLASS) == DIREG)                                                \
1456
   || ((CLASS) == SSE_FIRST_REG)                                        \
1457
   || ((CLASS) == FP_TOP_REG)                                           \
1458
   || ((CLASS) == FP_SECOND_REG))
1459
 
1460
/* Return a class of registers that cannot change FROM mode to TO mode.  */
1461
 
1462
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1463
  ix86_cannot_change_mode_class (FROM, TO, CLASS)
1464
 
1465
/* Stack layout; function entry, exit and calling.  */
1466
 
1467
/* Define this if pushing a word on the stack
1468
   makes the stack pointer a smaller address.  */
1469
#define STACK_GROWS_DOWNWARD
1470
 
1471
/* Define this to nonzero if the nominal address of the stack frame
1472
   is at the high-address end of the local variables;
1473
   that is, each additional local variable allocated
1474
   goes at a more negative offset in the frame.  */
1475
#define FRAME_GROWS_DOWNWARD 1
1476
 
1477
/* Offset within stack frame to start allocating local variables at.
1478
   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1479
   first local allocated.  Otherwise, it is the offset to the BEGINNING
1480
   of the first local allocated.  */
1481
#define STARTING_FRAME_OFFSET 0
1482
 
1483
/* If we generate an insn to push BYTES bytes,
1484
   this says how many the stack pointer really advances by.
1485
   On 386, we have pushw instruction that decrements by exactly 2 no
1486
   matter what the position was, there is no pushb.
1487
   But as CIE data alignment factor on this arch is -4, we need to make
1488
   sure all stack pointer adjustments are in multiple of 4.
1489
 
1490
   For 64bit ABI we round up to 8 bytes.
1491
 */
1492
 
1493
#define PUSH_ROUNDING(BYTES) \
1494
  (TARGET_64BIT              \
1495
   ? (((BYTES) + 7) & (-8))  \
1496
   : (((BYTES) + 3) & (-4)))
1497
 
1498
/* If defined, the maximum amount of space required for outgoing arguments will
1499
   be computed and placed into the variable
1500
   `crtl->outgoing_args_size'.  No space will be pushed onto the
1501
   stack for each call; instead, the function prologue should increase the stack
1502
   frame size by this amount.
1503
 
1504
   MS ABI seem to require 16 byte alignment everywhere except for function
1505
   prologue and apilogue.  This is not possible without
1506
   ACCUMULATE_OUTGOING_ARGS.  */
1507
 
1508
#define ACCUMULATE_OUTGOING_ARGS \
1509
  (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI)
1510
 
1511
/* If defined, a C expression whose value is nonzero when we want to use PUSH
1512
   instructions to pass outgoing arguments.  */
1513
 
1514
#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1515
 
1516
/* We want the stack and args grow in opposite directions, even if
1517
   PUSH_ARGS is 0.  */
1518
#define PUSH_ARGS_REVERSED 1
1519
 
1520
/* Offset of first parameter from the argument pointer register value.  */
1521
#define FIRST_PARM_OFFSET(FNDECL) 0
1522
 
1523
/* Define this macro if functions should assume that stack space has been
1524
   allocated for arguments even when their values are passed in registers.
1525
 
1526
   The value of this macro is the size, in bytes, of the area reserved for
1527
   arguments passed in registers for the function represented by FNDECL.
1528
 
1529
   This space can be allocated by the caller, or be a part of the
1530
   machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1531
   which.  */
1532
#define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1533
 
1534
#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1535
  (ix86_function_type_abi (FNTYPE) == MS_ABI)
1536
 
1537
/* Value is the number of bytes of arguments automatically
1538
   popped when returning from a subroutine call.
1539
   FUNDECL is the declaration node of the function (as a tree),
1540
   FUNTYPE is the data type of the function (as a tree),
1541
   or for a library call it is an identifier node for the subroutine name.
1542
   SIZE is the number of bytes of arguments passed on the stack.
1543
 
1544
   On the 80386, the RTD insn may be used to pop them if the number
1545
     of args is fixed, but if the number is variable then the caller
1546
     must pop them all.  RTD can't be used for library calls now
1547
     because the library is compiled with the Unix compiler.
1548
   Use of RTD is a selectable option, since it is incompatible with
1549
   standard Unix calling sequences.  If the option is not selected,
1550
   the caller must always pop the args.
1551
 
1552
   The attribute stdcall is equivalent to RTD on a per module basis.  */
1553
 
1554
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1555
  ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1556
 
1557
#define FUNCTION_VALUE_REGNO_P(N) ix86_function_value_regno_p (N)
1558
 
1559
/* Define how to find the value returned by a library function
1560
   assuming the value has mode MODE.  */
1561
 
1562
#define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1563
 
1564
/* Define the size of the result block used for communication between
1565
   untyped_call and untyped_return.  The block contains a DImode value
1566
   followed by the block used by fnsave and frstor.  */
1567
 
1568
#define APPLY_RESULT_SIZE (8+108)
1569
 
1570
/* 1 if N is a possible register number for function argument passing.  */
1571
#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1572
 
1573
/* Define a data type for recording info about an argument list
1574
   during the scan of that argument list.  This data type should
1575
   hold all necessary information about the function itself
1576
   and about the args processed so far, enough to enable macros
1577
   such as FUNCTION_ARG to determine where the next arg should go.  */
1578
 
1579
typedef struct ix86_args {
1580
  int words;                    /* # words passed so far */
1581
  int nregs;                    /* # registers available for passing */
1582
  int regno;                    /* next available register number */
1583
  int fastcall;                 /* fastcall calling convention is used */
1584
  int sse_words;                /* # sse words passed so far */
1585
  int sse_nregs;                /* # sse registers available for passing */
1586
  int warn_avx;                 /* True when we want to warn about AVX ABI.  */
1587
  int warn_sse;                 /* True when we want to warn about SSE ABI.  */
1588
  int warn_mmx;                 /* True when we want to warn about MMX ABI.  */
1589
  int sse_regno;                /* next available sse register number */
1590
  int mmx_words;                /* # mmx words passed so far */
1591
  int mmx_nregs;                /* # mmx registers available for passing */
1592
  int mmx_regno;                /* next available mmx register number */
1593
  int maybe_vaarg;              /* true for calls to possibly vardic fncts.  */
1594
  int float_in_sse;             /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1595
                                   be passed in SSE registers.  Otherwise 0.  */
1596
  enum calling_abi call_abi;    /* Set to SYSV_ABI for sysv abi. Otherwise
1597
                                   MS_ABI for ms abi.  */
1598
} CUMULATIVE_ARGS;
1599
 
1600
/* Initialize a variable CUM of type CUMULATIVE_ARGS
1601
   for a call to a function whose data type is FNTYPE.
1602
   For a library call, FNTYPE is 0.  */
1603
 
1604
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1605
  init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1606
 
1607
/* Update the data in CUM to advance over an argument
1608
   of mode MODE and data type TYPE.
1609
   (TYPE is null for libcalls where that information may not be available.)  */
1610
 
1611
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1612
  function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1613
 
1614
/* Define where to put the arguments to a function.
1615
   Value is zero to push the argument on the stack,
1616
   or a hard register in which to store the argument.
1617
 
1618
   MODE is the argument's machine mode.
1619
   TYPE is the data type of the argument (as a tree).
1620
    This is null for libcalls where that information may
1621
    not be available.
1622
   CUM is a variable of type CUMULATIVE_ARGS which gives info about
1623
    the preceding args and about the function being called.
1624
   NAMED is nonzero if this argument is a named parameter
1625
    (otherwise it is an extra parameter matching an ellipsis).  */
1626
 
1627
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1628
  function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1629
 
1630
/* Output assembler code to FILE to increment profiler label # LABELNO
1631
   for profiling a function entry.  */
1632
 
1633
#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1634
 
1635
#define MCOUNT_NAME "_mcount"
1636
 
1637
#define PROFILE_COUNT_REGISTER "edx"
1638
 
1639
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1640
   the stack pointer does not matter.  The value is tested only in
1641
   functions that have frame pointers.
1642
   No definition is equivalent to always zero.  */
1643
/* Note on the 386 it might be more efficient not to define this since
1644
   we have to restore it ourselves from the frame pointer, in order to
1645
   use pop */
1646
 
1647
#define EXIT_IGNORE_STACK 1
1648
 
1649
/* Output assembler code for a block containing the constant parts
1650
   of a trampoline, leaving space for the variable parts.  */
1651
 
1652
/* On the 386, the trampoline contains two instructions:
1653
     mov #STATIC,ecx
1654
     jmp FUNCTION
1655
   The trampoline is generated entirely at runtime.  The operand of JMP
1656
   is the address of FUNCTION relative to the instruction following the
1657
   JMP (which is 5 bytes long).  */
1658
 
1659
/* Length in units of the trampoline for entering a nested function.  */
1660
 
1661
#define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10)
1662
 
1663
/* Definitions for register eliminations.
1664
 
1665
   This is an array of structures.  Each structure initializes one pair
1666
   of eliminable registers.  The "from" register number is given first,
1667
   followed by "to".  Eliminations of the same "from" register are listed
1668
   in order of preference.
1669
 
1670
   There are two registers that can always be eliminated on the i386.
1671
   The frame pointer and the arg pointer can be replaced by either the
1672
   hard frame pointer or to the stack pointer, depending upon the
1673
   circumstances.  The hard frame pointer is not used before reload and
1674
   so it is not eligible for elimination.  */
1675
 
1676
#define ELIMINABLE_REGS                                 \
1677
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},           \
1678
 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},      \
1679
 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},         \
1680
 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}    \
1681
 
1682
/* Define the offset between two registers, one to be eliminated, and the other
1683
   its replacement, at the start of a routine.  */
1684
 
1685
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1686
  ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1687
 
1688
/* Addressing modes, and classification of registers for them.  */
1689
 
1690
/* Macros to check register numbers against specific register classes.  */
1691
 
1692
/* These assume that REGNO is a hard or pseudo reg number.
1693
   They give nonzero only if REGNO is a hard reg of the suitable class
1694
   or a pseudo reg currently allocated to a suitable hard reg.
1695
   Since they use reg_renumber, they are safe only once reg_renumber
1696
   has been allocated, which happens in local-alloc.c.  */
1697
 
1698
#define REGNO_OK_FOR_INDEX_P(REGNO)                                     \
1699
  ((REGNO) < STACK_POINTER_REGNUM                                       \
1700
   || REX_INT_REGNO_P (REGNO)                                           \
1701
   || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM           \
1702
   || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1703
 
1704
#define REGNO_OK_FOR_BASE_P(REGNO)                                      \
1705
  (GENERAL_REGNO_P (REGNO)                                              \
1706
   || (REGNO) == ARG_POINTER_REGNUM                                     \
1707
   || (REGNO) == FRAME_POINTER_REGNUM                                   \
1708
   || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1709
 
1710
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1711
   and check its validity for a certain class.
1712
   We have two alternate definitions for each of them.
1713
   The usual definition accepts all pseudo regs; the other rejects
1714
   them unless they have been allocated suitable hard regs.
1715
   The symbol REG_OK_STRICT causes the latter definition to be used.
1716
 
1717
   Most source files want to accept pseudo regs in the hope that
1718
   they will get allocated to the class that the insn wants them to be in.
1719
   Source files for reload pass need to be strict.
1720
   After reload, it makes no difference, since pseudo regs have
1721
   been eliminated by then.  */
1722
 
1723
 
1724
/* Non strict versions, pseudos are ok.  */
1725
#define REG_OK_FOR_INDEX_NONSTRICT_P(X)                                 \
1726
  (REGNO (X) < STACK_POINTER_REGNUM                                     \
1727
   || REX_INT_REGNO_P (REGNO (X))                                       \
1728
   || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1729
 
1730
#define REG_OK_FOR_BASE_NONSTRICT_P(X)                                  \
1731
  (GENERAL_REGNO_P (REGNO (X))                                          \
1732
   || REGNO (X) == ARG_POINTER_REGNUM                                   \
1733
   || REGNO (X) == FRAME_POINTER_REGNUM                                 \
1734
   || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1735
 
1736
/* Strict versions, hard registers only */
1737
#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1738
#define REG_OK_FOR_BASE_STRICT_P(X)  REGNO_OK_FOR_BASE_P (REGNO (X))
1739
 
1740
#ifndef REG_OK_STRICT
1741
#define REG_OK_FOR_INDEX_P(X)  REG_OK_FOR_INDEX_NONSTRICT_P (X)
1742
#define REG_OK_FOR_BASE_P(X)   REG_OK_FOR_BASE_NONSTRICT_P (X)
1743
 
1744
#else
1745
#define REG_OK_FOR_INDEX_P(X)  REG_OK_FOR_INDEX_STRICT_P (X)
1746
#define REG_OK_FOR_BASE_P(X)   REG_OK_FOR_BASE_STRICT_P (X)
1747
#endif
1748
 
1749
/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1750
   that is a valid memory address for an instruction.
1751
   The MODE argument is the machine mode for the MEM expression
1752
   that wants to use this address.
1753
 
1754
   The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1755
   except for CONSTANT_ADDRESS_P which is usually machine-independent.
1756
 
1757
   See legitimize_pic_address in i386.c for details as to what
1758
   constitutes a legitimate address when -fpic is used.  */
1759
 
1760
#define MAX_REGS_PER_ADDRESS 2
1761
 
1762
#define CONSTANT_ADDRESS_P(X)  constant_address_p (X)
1763
 
1764
/* Nonzero if the constant value X is a legitimate general operand.
1765
   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
1766
 
1767
#define LEGITIMATE_CONSTANT_P(X)  legitimate_constant_p (X)
1768
 
1769
/* If defined, a C expression to determine the base term of address X.
1770
   This macro is used in only one place: `find_base_term' in alias.c.
1771
 
1772
   It is always safe for this macro to not be defined.  It exists so
1773
   that alias analysis can understand machine-dependent addresses.
1774
 
1775
   The typical use of this macro is to handle addresses containing
1776
   a label_ref or symbol_ref within an UNSPEC.  */
1777
 
1778
#define FIND_BASE_TERM(X) ix86_find_base_term (X)
1779
 
1780
/* Nonzero if the constant value X is a legitimate general operand
1781
   when generating PIC code.  It is given that flag_pic is on and
1782
   that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
1783
 
1784
#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1785
 
1786
#define SYMBOLIC_CONST(X)       \
1787
  (GET_CODE (X) == SYMBOL_REF                                           \
1788
   || GET_CODE (X) == LABEL_REF                                         \
1789
   || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1790
 
1791
/* Max number of args passed in registers.  If this is more than 3, we will
1792
   have problems with ebx (register #4), since it is a caller save register and
1793
   is also used as the pic register in ELF.  So for now, don't allow more than
1794
   3 registers to be passed in registers.  */
1795
 
1796
/* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1797
#define X86_64_REGPARM_MAX 6
1798
#define X86_64_MS_REGPARM_MAX 4
1799
 
1800
#define X86_32_REGPARM_MAX 3
1801
 
1802
#define REGPARM_MAX                                                     \
1803
  (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_REGPARM_MAX          \
1804
                   : X86_64_REGPARM_MAX)                                \
1805
   : X86_32_REGPARM_MAX)
1806
 
1807
#define X86_64_SSE_REGPARM_MAX 8
1808
#define X86_64_MS_SSE_REGPARM_MAX 4
1809
 
1810
#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1811
 
1812
#define SSE_REGPARM_MAX                                                 \
1813
  (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_SSE_REGPARM_MAX      \
1814
                   : X86_64_SSE_REGPARM_MAX)                            \
1815
   : X86_32_SSE_REGPARM_MAX)
1816
 
1817
#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1818
 
1819
 
1820
/* Specify the machine mode that this machine uses
1821
   for the index in the tablejump instruction.  */
1822
#define CASE_VECTOR_MODE \
1823
 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1824
 
1825
/* Define this as 1 if `char' should by default be signed; else as 0.  */
1826
#define DEFAULT_SIGNED_CHAR 1
1827
 
1828
/* Max number of bytes we can move from memory to memory
1829
   in one reasonably fast instruction.  */
1830
#define MOVE_MAX 16
1831
 
1832
/* MOVE_MAX_PIECES is the number of bytes at a time which we can
1833
   move efficiently, as opposed to  MOVE_MAX which is the maximum
1834
   number of bytes we can move with a single instruction.  */
1835
#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1836
 
1837
/* If a memory-to-memory move would take MOVE_RATIO or more simple
1838
   move-instruction pairs, we will do a movmem or libcall instead.
1839
   Increasing the value will always make code faster, but eventually
1840
   incurs high cost in increased code size.
1841
 
1842
   If you don't define this, a reasonable default is used.  */
1843
 
1844
#define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1845
 
1846
/* If a clear memory operation would take CLEAR_RATIO or more simple
1847
   move-instruction sequences, we will do a clrmem or libcall instead.  */
1848
 
1849
#define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
1850
 
1851
/* Define if shifts truncate the shift count
1852
   which implies one can omit a sign-extension or zero-extension
1853
   of a shift count.  */
1854
/* On i386, shifts do truncate the count.  But bit opcodes don't.  */
1855
 
1856
/* #define SHIFT_COUNT_TRUNCATED */
1857
 
1858
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1859
   is done just by pretending it is already truncated.  */
1860
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1861
 
1862
/* A macro to update M and UNSIGNEDP when an object whose type is
1863
   TYPE and which has the specified mode and signedness is to be
1864
   stored in a register.  This macro is only called when TYPE is a
1865
   scalar type.
1866
 
1867
   On i386 it is sometimes useful to promote HImode and QImode
1868
   quantities to SImode.  The choice depends on target type.  */
1869
 
1870
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)             \
1871
do {                                                    \
1872
  if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS)      \
1873
      || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS))  \
1874
    (MODE) = SImode;                                    \
1875
} while (0)
1876
 
1877
/* Specify the machine mode that pointers have.
1878
   After generation of rtl, the compiler makes no further distinction
1879
   between pointers and any other objects of this machine mode.  */
1880
#define Pmode (TARGET_64BIT ? DImode : SImode)
1881
 
1882
/* A function address in a call instruction
1883
   is a byte address (for indexing purposes)
1884
   so give the MEM rtx a byte's mode.  */
1885
#define FUNCTION_MODE QImode
1886
 
1887
/* A C expression for the cost of moving data from a register in class FROM to
1888
   one in class TO.  The classes are expressed using the enumeration values
1889
   such as `GENERAL_REGS'.  A value of 2 is the default; other values are
1890
   interpreted relative to that.
1891
 
1892
   It is not required that the cost always equal 2 when FROM is the same as TO;
1893
   on some machines it is expensive to move between registers if they are not
1894
   general registers.  */
1895
 
1896
#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1897
   ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1898
 
1899
/* A C expression for the cost of moving data of mode M between a
1900
   register and memory.  A value of 2 is the default; this cost is
1901
   relative to those in `REGISTER_MOVE_COST'.
1902
 
1903
   If moving between registers and memory is more expensive than
1904
   between two registers, you should define this macro to express the
1905
   relative cost.  */
1906
 
1907
#define MEMORY_MOVE_COST(MODE, CLASS, IN)       \
1908
  ix86_memory_move_cost ((MODE), (CLASS), (IN))
1909
 
1910
/* A C expression for the cost of a branch instruction.  A value of 1
1911
   is the default; other values are interpreted relative to that.  */
1912
 
1913
#define BRANCH_COST(speed_p, predictable_p) \
1914
  (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1915
 
1916
/* Define this macro as a C expression which is nonzero if accessing
1917
   less than a word of memory (i.e. a `char' or a `short') is no
1918
   faster than accessing a word of memory, i.e., if such access
1919
   require more than one instruction or if there is no difference in
1920
   cost between byte and (aligned) word loads.
1921
 
1922
   When this macro is not defined, the compiler will access a field by
1923
   finding the smallest containing object; when it is defined, a
1924
   fullword load will be used if alignment permits.  Unless bytes
1925
   accesses are faster than word accesses, using word accesses is
1926
   preferable since it may eliminate subsequent memory access if
1927
   subsequent accesses occur to other fields in the same word of the
1928
   structure, but to different bytes.  */
1929
 
1930
#define SLOW_BYTE_ACCESS 0
1931
 
1932
/* Nonzero if access to memory by shorts is slow and undesirable.  */
1933
#define SLOW_SHORT_ACCESS 0
1934
 
1935
/* Define this macro to be the value 1 if unaligned accesses have a
1936
   cost many times greater than aligned accesses, for example if they
1937
   are emulated in a trap handler.
1938
 
1939
   When this macro is nonzero, the compiler will act as if
1940
   `STRICT_ALIGNMENT' were nonzero when generating code for block
1941
   moves.  This can cause significantly more instructions to be
1942
   produced.  Therefore, do not set this macro nonzero if unaligned
1943
   accesses only add a cycle or two to the time for a memory access.
1944
 
1945
   If the value of this macro is always zero, it need not be defined.  */
1946
 
1947
/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1948
 
1949
/* Define this macro if it is as good or better to call a constant
1950
   function address than to call an address kept in a register.
1951
 
1952
   Desirable on the 386 because a CALL with a constant address is
1953
   faster than one with a register address.  */
1954
 
1955
#define NO_FUNCTION_CSE
1956
 
1957
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1958
   return the mode to be used for the comparison.
1959
 
1960
   For floating-point equality comparisons, CCFPEQmode should be used.
1961
   VOIDmode should be used in all other cases.
1962
 
1963
   For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1964
   possible, to allow for more combinations.  */
1965
 
1966
#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1967
 
1968
/* Return nonzero if MODE implies a floating point inequality can be
1969
   reversed.  */
1970
 
1971
#define REVERSIBLE_CC_MODE(MODE) 1
1972
 
1973
/* A C expression whose value is reversed condition code of the CODE for
1974
   comparison done in CC_MODE mode.  */
1975
#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1976
 
1977
 
1978
/* Control the assembler format that we output, to the extent
1979
   this does not vary between assemblers.  */
1980
 
1981
/* How to refer to registers in assembler output.
1982
   This sequence is indexed by compiler's hard-register-number (see above).  */
1983
 
1984
/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
1985
   For non floating point regs, the following are the HImode names.
1986
 
1987
   For float regs, the stack top is sometimes referred to as "%st(0)"
1988
   instead of just "%st".  PRINT_OPERAND handles this with the "y" code.  */
1989
 
1990
#define HI_REGISTER_NAMES                                               \
1991
{"ax","dx","cx","bx","si","di","bp","sp",                               \
1992
 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)",          \
1993
 "argp", "flags", "fpsr", "fpcr", "frame",                              \
1994
 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7",               \
1995
 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",                \
1996
 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",                  \
1997
 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1998
 
1999
#define REGISTER_NAMES HI_REGISTER_NAMES
2000
 
2001
/* Table of additional register names to use in user input.  */
2002
 
2003
#define ADDITIONAL_REGISTER_NAMES \
2004
{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 },       \
2005
  { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 },       \
2006
  { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 },       \
2007
  { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 },       \
2008
  { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 },           \
2009
  { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2010
 
2011
/* Note we are omitting these since currently I don't know how
2012
to get gcc to use these, since they want the same but different
2013
number as al, and ax.
2014
*/
2015
 
2016
#define QI_REGISTER_NAMES \
2017
{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2018
 
2019
/* These parallel the array above, and can be used to access bits 8:15
2020
   of regs 0 through 3.  */
2021
 
2022
#define QI_HIGH_REGISTER_NAMES \
2023
{"ah", "dh", "ch", "bh", }
2024
 
2025
/* How to renumber registers for dbx and gdb.  */
2026
 
2027
#define DBX_REGISTER_NUMBER(N) \
2028
  (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2029
 
2030
extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2031
extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2032
extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2033
 
2034
/* Before the prologue, RA is at 0(%esp).  */
2035
#define INCOMING_RETURN_ADDR_RTX \
2036
  gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2037
 
2038
/* After the prologue, RA is at -4(AP) in the current frame.  */
2039
#define RETURN_ADDR_RTX(COUNT, FRAME)                                      \
2040
  ((COUNT) == 0                                                            \
2041
   ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2042
   : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2043
 
2044
/* PC is dbx register 8; let's use that column for RA.  */
2045
#define DWARF_FRAME_RETURN_COLUMN       (TARGET_64BIT ? 16 : 8)
2046
 
2047
/* Before the prologue, the top of the frame is at 4(%esp).  */
2048
#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2049
 
2050
/* Describe how we implement __builtin_eh_return.  */
2051
#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2052
#define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, 2)
2053
 
2054
 
2055
/* Select a format to encode pointers in exception handling data.  CODE
2056
   is 0 for data, 1 for code labels, 2 for function pointers.  GLOBAL is
2057
   true if the symbol may be affected by dynamic relocations.
2058
 
2059
   ??? All x86 object file formats are capable of representing this.
2060
   After all, the relocation needed is the same as for the call insn.
2061
   Whether or not a particular assembler allows us to enter such, I
2062
   guess we'll have to see.  */
2063
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL)                      \
2064
  asm_preferred_eh_data_format ((CODE), (GLOBAL))
2065
 
2066
/* This is how to output an insn to push a register on the stack.
2067
   It need not be very fast code.  */
2068
 
2069
#define ASM_OUTPUT_REG_PUSH(FILE, REGNO)  \
2070
do {                                                                    \
2071
  if (TARGET_64BIT)                                                     \
2072
    asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n",                          \
2073
                 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0));  \
2074
  else                                                                  \
2075
    asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]);     \
2076
} while (0)
2077
 
2078
/* This is how to output an insn to pop a register from the stack.
2079
   It need not be very fast code.  */
2080
 
2081
#define ASM_OUTPUT_REG_POP(FILE, REGNO)  \
2082
do {                                                                    \
2083
  if (TARGET_64BIT)                                                     \
2084
    asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n",                           \
2085
                 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0));  \
2086
  else                                                                  \
2087
    asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]);      \
2088
} while (0)
2089
 
2090
/* This is how to output an element of a case-vector that is absolute.  */
2091
 
2092
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
2093
  ix86_output_addr_vec_elt ((FILE), (VALUE))
2094
 
2095
/* This is how to output an element of a case-vector that is relative.  */
2096
 
2097
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2098
  ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2099
 
2100
/* When we see %v, we will print the 'v' prefix if TARGET_AVX is
2101
   true.  */
2102
 
2103
#define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR)      \
2104
{                                               \
2105
  if ((PTR)[0] == '%' && (PTR)[1] == 'v')       \
2106
    {                                           \
2107
      if (TARGET_AVX)                           \
2108
        (PTR) += 1;                             \
2109
      else                                      \
2110
        (PTR) += 2;                             \
2111
    }                                           \
2112
}
2113
 
2114
/* A C statement or statements which output an assembler instruction
2115
   opcode to the stdio stream STREAM.  The macro-operand PTR is a
2116
   variable of type `char *' which points to the opcode name in
2117
   its "internal" form--the form that is written in the machine
2118
   description.  */
2119
 
2120
#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2121
  ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2122
 
2123
/* A C statement to output to the stdio stream FILE an assembler
2124
   command to pad the location counter to a multiple of 1<<LOG
2125
   bytes if it is within MAX_SKIP bytes.  */
2126
 
2127
#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2128
#undef  ASM_OUTPUT_MAX_SKIP_PAD
2129
#define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP)                    \
2130
  if ((LOG) != 0)                                                       \
2131
    {                                                                   \
2132
      if ((MAX_SKIP) == 0)                                              \
2133
        fprintf ((FILE), "\t.p2align %d\n", (LOG));                     \
2134
      else                                                              \
2135
        fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP));     \
2136
    }
2137
#endif
2138
 
2139
/* Under some conditions we need jump tables in the text section,
2140
   because the assembler cannot handle label differences between
2141
   sections.  This is the case for x86_64 on Mach-O for example.  */
2142
 
2143
#define JUMP_TABLES_IN_TEXT_SECTION \
2144
  (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2145
   || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2146
 
2147
/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2148
   and switch back.  For x86 we do this only to save a few bytes that
2149
   would otherwise be unused in the text section.  */
2150
#define CRT_MKSTR2(VAL) #VAL
2151
#define CRT_MKSTR(x) CRT_MKSTR2(x)
2152
 
2153
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)              \
2154
   asm (SECTION_OP "\n\t"                                       \
2155
        "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n"     \
2156
        TEXT_SECTION_ASM_OP);
2157
 
2158
/* Print operand X (an rtx) in assembler syntax to file FILE.
2159
   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2160
   Effect of various CODE letters is described in i386.c near
2161
   print_operand function.  */
2162
 
2163
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2164
  ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';')
2165
 
2166
#define PRINT_OPERAND(FILE, X, CODE)  \
2167
  print_operand ((FILE), (X), (CODE))
2168
 
2169
#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
2170
  print_operand_address ((FILE), (ADDR))
2171
 
2172
#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL)  \
2173
do {                                            \
2174
  if (! output_addr_const_extra (FILE, (X)))    \
2175
    goto FAIL;                                  \
2176
} while (0);
2177
 
2178
/* Which processor to schedule for. The cpu attribute defines a list that
2179
   mirrors this list, so changes to i386.md must be made at the same time.  */
2180
 
2181
enum processor_type
2182
{
2183
  PROCESSOR_I386 = 0,                   /* 80386 */
2184
  PROCESSOR_I486,                       /* 80486DX, 80486SX, 80486DX[24] */
2185
  PROCESSOR_PENTIUM,
2186
  PROCESSOR_PENTIUMPRO,
2187
  PROCESSOR_GEODE,
2188
  PROCESSOR_K6,
2189
  PROCESSOR_ATHLON,
2190
  PROCESSOR_PENTIUM4,
2191
  PROCESSOR_K8,
2192
  PROCESSOR_NOCONA,
2193
  PROCESSOR_CORE2,
2194
  PROCESSOR_GENERIC32,
2195
  PROCESSOR_GENERIC64,
2196
  PROCESSOR_AMDFAM10,
2197
  PROCESSOR_ATOM,
2198
  PROCESSOR_max
2199
};
2200
 
2201
extern enum processor_type ix86_tune;
2202
extern enum processor_type ix86_arch;
2203
 
2204
enum fpmath_unit
2205
{
2206
  FPMATH_387 = 1,
2207
  FPMATH_SSE = 2
2208
};
2209
 
2210
extern enum fpmath_unit ix86_fpmath;
2211
 
2212
enum tls_dialect
2213
{
2214
  TLS_DIALECT_GNU,
2215
  TLS_DIALECT_GNU2,
2216
  TLS_DIALECT_SUN
2217
};
2218
 
2219
extern enum tls_dialect ix86_tls_dialect;
2220
 
2221
enum cmodel {
2222
  CM_32,        /* The traditional 32-bit ABI.  */
2223
  CM_SMALL,     /* Assumes all code and data fits in the low 31 bits.  */
2224
  CM_KERNEL,    /* Assumes all code and data fits in the high 31 bits.  */
2225
  CM_MEDIUM,    /* Assumes code fits in the low 31 bits; data unlimited.  */
2226
  CM_LARGE,     /* No assumptions.  */
2227
  CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region.  */
2228
  CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region.  */
2229
  CM_LARGE_PIC  /* No assumptions.  */
2230
};
2231
 
2232
extern enum cmodel ix86_cmodel;
2233
 
2234
/* Size of the RED_ZONE area.  */
2235
#define RED_ZONE_SIZE 128
2236
/* Reserved area of the red zone for temporaries.  */
2237
#define RED_ZONE_RESERVE 8
2238
 
2239
enum asm_dialect {
2240
  ASM_ATT,
2241
  ASM_INTEL
2242
};
2243
 
2244
extern enum asm_dialect ix86_asm_dialect;
2245
extern unsigned int ix86_preferred_stack_boundary;
2246
extern unsigned int ix86_incoming_stack_boundary;
2247
extern int ix86_branch_cost, ix86_section_threshold;
2248
 
2249
/* Smallest class containing REGNO.  */
2250
extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2251
 
2252
extern rtx ix86_compare_op0;    /* operand 0 for comparisons */
2253
extern rtx ix86_compare_op1;    /* operand 1 for comparisons */
2254
 
2255
enum ix86_fpcmp_strategy {
2256
  IX86_FPCMP_SAHF,
2257
  IX86_FPCMP_COMI,
2258
  IX86_FPCMP_ARITH
2259
};
2260
 
2261
/* To properly truncate FP values into integers, we need to set i387 control
2262
   word.  We can't emit proper mode switching code before reload, as spills
2263
   generated by reload may truncate values incorrectly, but we still can avoid
2264
   redundant computation of new control word by the mode switching pass.
2265
   The fldcw instructions are still emitted redundantly, but this is probably
2266
   not going to be noticeable problem, as most CPUs do have fast path for
2267
   the sequence.
2268
 
2269
   The machinery is to emit simple truncation instructions and split them
2270
   before reload to instructions having USEs of two memory locations that
2271
   are filled by this code to old and new control word.
2272
 
2273
   Post-reload pass may be later used to eliminate the redundant fildcw if
2274
   needed.  */
2275
 
2276
enum ix86_entity
2277
{
2278
  I387_TRUNC = 0,
2279
  I387_FLOOR,
2280
  I387_CEIL,
2281
  I387_MASK_PM,
2282
  MAX_386_ENTITIES
2283
};
2284
 
2285
enum ix86_stack_slot
2286
{
2287
  SLOT_VIRTUAL = 0,
2288
  SLOT_TEMP,
2289
  SLOT_CW_STORED,
2290
  SLOT_CW_TRUNC,
2291
  SLOT_CW_FLOOR,
2292
  SLOT_CW_CEIL,
2293
  SLOT_CW_MASK_PM,
2294
  MAX_386_STACK_LOCALS
2295
};
2296
 
2297
/* Define this macro if the port needs extra instructions inserted
2298
   for mode switching in an optimizing compilation.  */
2299
 
2300
#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2301
   ix86_optimize_mode_switching[(ENTITY)]
2302
 
2303
/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2304
   initializer for an array of integers.  Each initializer element N
2305
   refers to an entity that needs mode switching, and specifies the
2306
   number of different modes that might need to be set for this
2307
   entity.  The position of the initializer in the initializer -
2308
   starting counting at zero - determines the integer that is used to
2309
   refer to the mode-switched entity in question.  */
2310
 
2311
#define NUM_MODES_FOR_MODE_SWITCHING \
2312
   { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2313
 
2314
/* ENTITY is an integer specifying a mode-switched entity.  If
2315
   `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2316
   return an integer value not larger than the corresponding element
2317
   in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2318
   must be switched into prior to the execution of INSN. */
2319
 
2320
#define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2321
 
2322
/* This macro specifies the order in which modes for ENTITY are
2323
   processed.  0 is the highest priority.  */
2324
 
2325
#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2326
 
2327
/* Generate one or more insns to set ENTITY to MODE.  HARD_REG_LIVE
2328
   is the set of hard registers live at the point where the insn(s)
2329
   are to be inserted.  */
2330
 
2331
#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE)                     \
2332
  ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED             \
2333
   ? emit_i387_cw_initialization (MODE), 0                              \
2334
   : 0)
2335
 
2336
 
2337
/* Avoid renaming of stack registers, as doing so in combination with
2338
   scheduling just increases amount of live registers at time and in
2339
   the turn amount of fxch instructions needed.
2340
 
2341
   ??? Maybe Pentium chips benefits from renaming, someone can try....  */
2342
 
2343
#define HARD_REGNO_RENAME_OK(SRC, TARGET)  \
2344
  (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2345
 
2346
 
2347
#define FASTCALL_PREFIX '@'
2348
 
2349
/* Machine specific CFA tracking during prologue/epilogue generation.  */
2350
 
2351
#ifndef USED_FOR_TARGET
2352
struct GTY(()) machine_cfa_state
2353
{
2354
  rtx reg;
2355
  HOST_WIDE_INT offset;
2356
};
2357
 
2358
struct GTY(()) machine_function {
2359
  struct stack_local_entry *stack_locals;
2360
  const char *some_ld_name;
2361
  int varargs_gpr_size;
2362
  int varargs_fpr_size;
2363
  int optimize_mode_switching[MAX_386_ENTITIES];
2364
 
2365
  /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE
2366
     has been computed for.  */
2367
  int use_fast_prologue_epilogue_nregs;
2368
 
2369
  /* The CFA state at the end of the prologue.  */
2370
  struct machine_cfa_state cfa;
2371
 
2372
  /* This value is used for amd64 targets and specifies the current abi
2373
     to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi.  */
2374
  enum calling_abi call_abi;
2375
 
2376
  /* Nonzero if the function accesses a previous frame.  */
2377
  BOOL_BITFIELD accesses_prev_frame : 1;
2378
 
2379
  /* Nonzero if the function requires a CLD in the prologue.  */
2380
  BOOL_BITFIELD needs_cld : 1;
2381
 
2382
  /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2383
     expander to determine the style used.  */
2384
  BOOL_BITFIELD use_fast_prologue_epilogue : 1;
2385
 
2386
  /* If true, the current function needs the default PIC register, not
2387
     an alternate register (on x86) and must not use the red zone (on
2388
     x86_64), even if it's a leaf function.  We don't want the
2389
     function to be regarded as non-leaf because TLS calls need not
2390
     affect register allocation.  This flag is set when a TLS call
2391
     instruction is expanded within a function, and never reset, even
2392
     if all such instructions are optimized away.  Use the
2393
     ix86_current_function_calls_tls_descriptor macro for a better
2394
     approximation.  */
2395
  BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;
2396
 
2397
  /* If true, the current function has a STATIC_CHAIN is placed on the
2398
     stack below the return address.  */
2399
  BOOL_BITFIELD static_chain_on_stack : 1;
2400
};
2401
#endif
2402
 
2403
#define ix86_stack_locals (cfun->machine->stack_locals)
2404
#define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2405
#define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2406
#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2407
#define ix86_current_function_needs_cld (cfun->machine->needs_cld)
2408
#define ix86_tls_descriptor_calls_expanded_in_cfun \
2409
  (cfun->machine->tls_descriptor_call_expanded_p)
2410
/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2411
   calls are optimized away, we try to detect cases in which it was
2412
   optimized away.  Since such instructions (use (reg REG_SP)), we can
2413
   verify whether there's any such instruction live by testing that
2414
   REG_SP is live.  */
2415
#define ix86_current_function_calls_tls_descriptor \
2416
  (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2417
#define ix86_cfa_state (&cfun->machine->cfa)
2418
#define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2419
 
2420
/* Control behavior of x86_file_start.  */
2421
#define X86_FILE_START_VERSION_DIRECTIVE false
2422
#define X86_FILE_START_FLTUSED false
2423
 
2424
/* Flag to mark data that is in the large address area.  */
2425
#define SYMBOL_FLAG_FAR_ADDR            (SYMBOL_FLAG_MACH_DEP << 0)
2426
#define SYMBOL_REF_FAR_ADDR_P(X)        \
2427
        ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2428
 
2429
/* Flags to mark dllimport/dllexport.  Used by PE ports, but handy to
2430
   have defined always, to avoid ifdefing.  */
2431
#define SYMBOL_FLAG_DLLIMPORT           (SYMBOL_FLAG_MACH_DEP << 1)
2432
#define SYMBOL_REF_DLLIMPORT_P(X) \
2433
        ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2434
 
2435
#define SYMBOL_FLAG_DLLEXPORT           (SYMBOL_FLAG_MACH_DEP << 2)
2436
#define SYMBOL_REF_DLLEXPORT_P(X) \
2437
        ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2438
 
2439
/* Model costs for vectorizer.  */
2440
 
2441
/* Cost of conditional branch.  */
2442
#undef TARG_COND_BRANCH_COST
2443
#define TARG_COND_BRANCH_COST           ix86_cost->branch_cost
2444
 
2445
/* Enum through the target specific extra va_list types.
2446
   Please, do not iterate the base va_list type name.  */
2447
#define TARGET_ENUM_VA_LIST(IDX, PNAME, PTYPE) \
2448
  (TARGET_64BIT ? ix86_enum_va_list (IDX, PNAME, PTYPE) : 0)
2449
 
2450
/* Cost of any scalar operation, excluding load and store.  */
2451
#undef TARG_SCALAR_STMT_COST
2452
#define TARG_SCALAR_STMT_COST           ix86_cost->scalar_stmt_cost
2453
 
2454
/* Cost of scalar load.  */
2455
#undef TARG_SCALAR_LOAD_COST
2456
#define TARG_SCALAR_LOAD_COST           ix86_cost->scalar_load_cost
2457
 
2458
/* Cost of scalar store.  */
2459
#undef TARG_SCALAR_STORE_COST
2460
#define TARG_SCALAR_STORE_COST          ix86_cost->scalar_store_cost
2461
 
2462
/* Cost of any vector operation, excluding load, store or vector to scalar
2463
   operation.  */
2464
#undef TARG_VEC_STMT_COST
2465
#define TARG_VEC_STMT_COST              ix86_cost->vec_stmt_cost
2466
 
2467
/* Cost of vector to scalar operation.  */
2468
#undef TARG_VEC_TO_SCALAR_COST
2469
#define TARG_VEC_TO_SCALAR_COST         ix86_cost->vec_to_scalar_cost
2470
 
2471
/* Cost of scalar to vector operation.  */
2472
#undef TARG_SCALAR_TO_VEC_COST
2473
#define TARG_SCALAR_TO_VEC_COST         ix86_cost->scalar_to_vec_cost
2474
 
2475
/* Cost of aligned vector load.  */
2476
#undef TARG_VEC_LOAD_COST
2477
#define TARG_VEC_LOAD_COST              ix86_cost->vec_align_load_cost
2478
 
2479
/* Cost of misaligned vector load.  */
2480
#undef TARG_VEC_UNALIGNED_LOAD_COST
2481
#define TARG_VEC_UNALIGNED_LOAD_COST    ix86_cost->vec_unalign_load_cost
2482
 
2483
/* Cost of vector store.  */
2484
#undef TARG_VEC_STORE_COST
2485
#define TARG_VEC_STORE_COST             ix86_cost->vec_store_cost
2486
 
2487
/* Cost of conditional taken branch for vectorizer cost model.  */
2488
#undef TARG_COND_TAKEN_BRANCH_COST
2489
#define TARG_COND_TAKEN_BRANCH_COST     ix86_cost->cond_taken_branch_cost
2490
 
2491
/* Cost of conditional not taken branch for vectorizer cost model.  */
2492
#undef TARG_COND_NOT_TAKEN_BRANCH_COST
2493
#define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost
2494
 
2495
/*
2496
Local variables:
2497
version-control: t
2498
End:
2499
*/

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