OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [lm32/] [lm32.opt] - Blame information for rev 316

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 282 jeremybenn
; Options for the Lattice Mico32 port of the compiler.
2
; Contributed by Jon Beniston 
3
;
4
; Copyright (C) 2009 Free Software Foundation, Inc.
5
;
6
; This file is part of GCC.
7
;
8
; GCC is free software; you can redistribute it and/or modify it
9
; under the terms of the GNU General Public License as published
10
; by the Free Software Foundation; either version 3, or (at your
11
; option) any later version.
12
;
13
; GCC is distributed in the hope that it will be useful, but WITHOUT
14
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
; License for more details.
17
;
18
; You should have received a copy of the GNU General Public License
19
; along with GCC; see the file COPYING3.  If not see
20
;  .
21
 
22
mmultiply-enabled
23
Target Report Mask(MULTIPLY_ENABLED)
24
Enable multiply instructions
25
 
26
mdivide-enabled
27
Target Report Mask(DIVIDE_ENABLED)
28
Enable divide and modulus instructions
29
 
30
mbarrel-shift-enabled
31
Target Report Mask(BARREL_SHIFT_ENABLED)
32
Enable barrel shift instructions
33
 
34
msign-extend-enabled
35
Target Report Mask(SIGN_EXTEND_ENABLED)
36
Enable sign extend instructions
37
 
38
muser-enabled
39
Target Report Mask(USER_ENABLED)
40
Enable user-defined instructions

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.