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1 282 jeremybenn
/* Target Definitions for R8C/M16C/M32C
2
   Copyright (C) 2005, 2007, 2008, 2009
3
   Free Software Foundation, Inc.
4
   Contributed by Red Hat.
5
 
6
   This file is part of GCC.
7
 
8
   GCC is free software; you can redistribute it and/or modify it
9
   under the terms of the GNU General Public License as published
10
   by the Free Software Foundation; either version 3, or (at your
11
   option) any later version.
12
 
13
   GCC is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with GCC; see the file COPYING3.  If not see
20
   <http://www.gnu.org/licenses/>.  */
21
 
22
#ifndef GCC_M32C_H
23
#define GCC_M32C_H
24
 
25
/* Controlling the Compilation Driver, `gcc'.  */
26
 
27
#undef  STARTFILE_SPEC
28
#define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
29
 
30
/* There are four CPU series we support, but they basically break down
31
   into two families - the R8C/M16C families, with 16-bit address
32
   registers and one set of opcodes, and the M32CM/M32C group, with
33
   24-bit address registers and a different set of opcodes.  The
34
   assembler doesn't care except for which opcode set is needed; the
35
   big difference is in the memory maps, which we cover in
36
   LIB_SPEC.  */
37
 
38
#undef  ASM_SPEC
39
#define ASM_SPEC "\
40
%{mcpu=r8c:--m16c} \
41
%{mcpu=m16c:--m16c} \
42
%{mcpu=m32cm:--m32c} \
43
%{mcpu=m32c:--m32c} "
44
 
45
/* The default is R8C hardware.  We support a simulator, which has its
46
   own libgloss and link map, plus one default link map for each chip
47
   family.  Most of the logic here is making sure we do the right
48
   thing when no CPU is specified, which defaults to R8C.  */
49
#undef  LIB_SPEC
50
#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
51
%{msim*:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \
52
        %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \
53
%{!T*:%{!msim*: %{mcpu=m16c:%Tm16c.ld} \
54
                %{mcpu=m32cm:%Tm32cm.ld} \
55
                %{mcpu=m32c:%Tm32c.ld} \
56
                %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \
57
"
58
 
59
/* Run-time Target Specification */
60
 
61
/* Nothing unusual here.  */
62
#define TARGET_CPU_CPP_BUILTINS() \
63
  { \
64
    builtin_assert ("cpu=m32c"); \
65
    builtin_assert ("machine=m32c"); \
66
    builtin_define ("__m32c__=1"); \
67
    if (TARGET_R8C) \
68
      builtin_define ("__r8c_cpu__=1"); \
69
    if (TARGET_M16C) \
70
      builtin_define ("__m16c_cpu__=1"); \
71
    if (TARGET_M32CM) \
72
      builtin_define ("__m32cm_cpu__=1"); \
73
    if (TARGET_M32C) \
74
      builtin_define ("__m32c_cpu__=1"); \
75
  }
76
 
77
/* The pragma handlers need to know if we've started processing
78
   functions yet, as the memregs pragma should only be given at the
79
   beginning of the file.  This variable starts off TRUE and later
80
   becomes FALSE.  */
81
extern int ok_to_change_target_memregs;
82
extern int target_memregs;
83
 
84
/* TARGET_CPU is a multi-way option set in m32c.opt.  While we could
85
   use enums or defines for this, this and m32c.opt are the only
86
   places that know (or care) what values are being used.  */
87
#define TARGET_R8C      (target_cpu == 'r')
88
#define TARGET_M16C     (target_cpu == '6')
89
#define TARGET_M32CM    (target_cpu == 'm')
90
#define TARGET_M32C     (target_cpu == '3')
91
 
92
/* Address register sizes.  Warning: these are used all over the place
93
   to select between the two CPU families in general.  */
94
#define TARGET_A16      (TARGET_R8C || TARGET_M16C)
95
#define TARGET_A24      (TARGET_M32CM || TARGET_M32C)
96
 
97
#define TARGET_VERSION fprintf (stderr, " (m32c)");
98
 
99
#define OVERRIDE_OPTIONS m32c_override_options ()
100
 
101
/* Defining data structures for per-function information */
102
 
103
typedef struct GTY (()) machine_function
104
{
105
  /* How much we adjust the stack when returning from an exception
106
     handler.  */
107
  rtx eh_stack_adjust;
108
 
109
  /* TRUE if the current function is an interrupt handler.  */
110
  int is_interrupt;
111
 
112
  /* TRUE if the current function is a leaf function.  Currently, this
113
     only affects saving $a0 in interrupt functions.  */
114
  int is_leaf;
115
 
116
  /* Bitmask that keeps track of which registers are used in an
117
     interrupt function, so we know which ones need to be saved and
118
     restored.  */
119
  int intr_pushm;
120
  /* Likewise, one element for each memreg that needs to be saved.  */
121
  char intr_pushmem[16];
122
 
123
  /* TRUE if the current function can use a simple RTS to return, instead
124
     of the longer ENTER/EXIT pair.  */
125
  int use_rts;
126
}
127
machine_function;
128
 
129
#define INIT_EXPANDERS m32c_init_expanders ()
130
 
131
/* Storage Layout */
132
 
133
#define BITS_BIG_ENDIAN 0
134
#define BYTES_BIG_ENDIAN 0
135
#define WORDS_BIG_ENDIAN 0
136
 
137
/* We can do QI, HI, and SI operations pretty much equally well, but
138
   GCC expects us to have a "native" format, so we pick the one that
139
   matches "int".  Pointers are 16 bits for R8C/M16C (when TARGET_A16
140
   is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
141
   24-bit pointers are stored in 32-bit words.  */
142
#define BITS_PER_UNIT 8
143
#define UNITS_PER_WORD 2
144
#define POINTER_SIZE (TARGET_A16 ? 16 : 32)
145
#define POINTERS_EXTEND_UNSIGNED 1
146
/* We have a problem with libgcc2.  It only defines two versions of
147
   each function, one for "int" and one for "long long".  Ie it assumes
148
   that "sizeof (int) == sizeof (long)".  For the M32C this is not true
149
   and we need a third set of functions.  We explicitly define
150
   LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
151
   to get the SI and DI versions from the libgcc2.c sources, and we
152
   provide our own set of HI functions in m32c-lib2.c, which is why this
153
   definition is surrounded by #ifndef..#endif.  */
154
#ifndef LIBGCC2_UNITS_PER_WORD
155
#define LIBGCC2_UNITS_PER_WORD 4
156
#endif
157
 
158
/* These match the alignment enforced by the two types of stack operations.  */
159
#define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
160
#define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
161
 
162
/* We do this because we care more about space than about speed.  For
163
   the chips with 16-bit busses, we could set these to 16 if
164
   desired.  */
165
#define FUNCTION_BOUNDARY 8
166
#define BIGGEST_ALIGNMENT 8
167
 
168
/* Since we have a maximum structure alignment of 8 there
169
   is no need to enforce any alignment of bitfield types.  */
170
#undef  PCC_BITFIELD_TYPE_MATTERS
171
#define PCC_BITFIELD_TYPE_MATTERS 0
172
 
173
#define STRICT_ALIGNMENT 0
174
#define SLOW_BYTE_ACCESS 1
175
 
176
/* Layout of Source Language Data Types */
177
 
178
#define INT_TYPE_SIZE 16
179
#define SHORT_TYPE_SIZE 16
180
#define LONG_TYPE_SIZE 32
181
#define LONG_LONG_TYPE_SIZE 64
182
 
183
#define FLOAT_TYPE_SIZE 32
184
#define DOUBLE_TYPE_SIZE 64
185
#define LONG_DOUBLE_TYPE_SIZE 64
186
 
187
#define DEFAULT_SIGNED_CHAR 1
188
 
189
#undef PTRDIFF_TYPE
190
#define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
191
 
192
#undef UINTPTR_TYPE
193
#define UINTPTR_TYPE (TARGET_A16 ? "unsigned int" : "long unsigned int")
194
 
195
/* REGISTER USAGE */
196
 
197
/* Register Basics */
198
 
199
/* Register layout:
200
 
201
        [r0h][r0l]  $r0  (16 bits, or two 8-bit halves)
202
        [--------]  $r2  (16 bits)
203
        [r1h][r1l]  $r1  (16 bits, or two 8-bit halves)
204
        [--------]  $r3  (16 bits)
205
   [---][--------]  $a0  (might be 24 bits)
206
   [---][--------]  $a1  (might be 24 bits)
207
   [---][--------]  $sb  (might be 24 bits)
208
   [---][--------]  $fb  (might be 24 bits)
209
   [---][--------]  $sp  (might be 24 bits)
210
   [-------------]  $pc  (20 or 24 bits)
211
             [---]  $flg (CPU flags)
212
   [---][--------]  $argp (virtual)
213
        [--------]  $mem0 (all 16 bits)
214
          . . .
215
        [--------]  $mem14
216
*/
217
 
218
#define FIRST_PSEUDO_REGISTER   20
219
 
220
/* Note that these two tables are modified based on which CPU family
221
   you select; see m32c_conditional_register_usage for details.  */
222
 
223
/* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
224
#define FIXED_REGISTERS     { 0, 0, 0, 0, \
225
                              0, 0, 1, 0, \
226
                              1, 1, 0, 1, \
227
                              0, 0, 0, 0, 0, 0, 0, 0 }
228
#define CALL_USED_REGISTERS { 1, 1, 1, 1, \
229
                              1, 1, 1, 0, \
230
                              1, 1, 1, 1, \
231
                              1, 1, 1, 1, 1, 1, 1, 1 }
232
 
233
#define CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage ();
234
 
235
/* The *_REGNO theme matches m32c.md and most register number
236
   arguments; the PC_REGNUM is the odd one out.  */
237
#ifndef PC_REGNO
238
#define PC_REGNO 9
239
#endif
240
#define PC_REGNUM PC_REGNO
241
 
242
/* Order of Allocation of Registers */
243
 
244
#define REG_ALLOC_ORDER { \
245
        0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
246
        12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */        \
247
        6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
248
 
249
/* How Values Fit in Registers */
250
 
251
#define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
252
#define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
253
#define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
254
#define AVOID_CCMODE_COPIES
255
 
256
/* Register Classes */
257
 
258
/* Most registers are special purpose in some form or another, so this
259
   table is pretty big.  Class names are used for constraints also;
260
   for example the HL_REGS class (HL below) is "Rhl" in the md files.
261
   See m32c_reg_class_from_constraint for the mapping.  There's some
262
   duplication so that we can better isolate the reason for using
263
   constraints in the md files from the actual registers used; for
264
   example we may want to exclude a1a0 from SI_REGS in the future,
265
   without precluding their use as HImode registers.  */
266
 
267
/* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
268
/*       mmPAR */
269
#define REG_CLASS_CONTENTS \
270
{ { 0x00000000 }, /* NO */\
271
  { 0x00000100 }, /* SP  - sp */\
272
  { 0x00000080 }, /* FB  - fb */\
273
  { 0x00000040 }, /* SB  - sb */\
274
  { 0x000001c0 }, /* CR  - sb fb sp */\
275
  { 0x00000001 }, /* R0  - r0 */\
276
  { 0x00000004 }, /* R1  - r1 */\
277
  { 0x00000002 }, /* R2  - r2 */\
278
  { 0x00000008 }, /* R3  - r3 */\
279
  { 0x00000003 }, /* R02 - r0r2 */\
280
  { 0x0000000c }, /* R13 - r1r3 */\
281
  { 0x00000005 }, /* HL  - r0 r1 */\
282
  { 0x00000005 }, /* QI  - r0 r1 */\
283
  { 0x0000000a }, /* R23 - r2 r3 */\
284
  { 0x0000000f }, /* R03 - r0r2 r1r3 */\
285
  { 0x0000000f }, /* DI  - r0r2r1r3 + mems */\
286
  { 0x00000010 }, /* A0  - a0 */\
287
  { 0x00000020 }, /* A1  - a1 */\
288
  { 0x00000030 }, /* A   - a0 a1 */\
289
  { 0x000000f0 }, /* AD  - a0 a1 sb fp */\
290
  { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\
291
  { 0x0000000f }, /* SI  - r0r2 r1r3 a0a1 */\
292
  { 0x0000003f }, /* HI  - r0 r1 r2 r3 a0 a1 */\
293
  { 0x00000033 }, /* R02A  - r0r2 a0 a1 */ \
294
  { 0x0000003f }, /* RA  - r0..r3 a0 a1 */\
295
  { 0x0000007f }, /* GENERAL */\
296
  { 0x00000400 }, /* FLG */\
297
  { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\
298
  { 0x000ff000 }, /* MEM */\
299
  { 0x000ff003 }, /* R02_A_MEM */\
300
  { 0x000ff005 }, /* A_HL_MEM */\
301
  { 0x000ff00c }, /* R1_R3_A_MEM */\
302
  { 0x000ff00f }, /* R03_MEM */\
303
  { 0x000ff03f }, /* A_HI_MEM */\
304
  { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
305
  { 0x000ff1ff }, /* ALL */\
306
}
307
 
308
enum reg_class
309
{
310
  NO_REGS,
311
  SP_REGS,
312
  FB_REGS,
313
  SB_REGS,
314
  CR_REGS,
315
  R0_REGS,
316
  R1_REGS,
317
  R2_REGS,
318
  R3_REGS,
319
  R02_REGS,
320
  R13_REGS,
321
  HL_REGS,
322
  QI_REGS,
323
  R23_REGS,
324
  R03_REGS,
325
  DI_REGS,
326
  A0_REGS,
327
  A1_REGS,
328
  A_REGS,
329
  AD_REGS,
330
  PS_REGS,
331
  SI_REGS,
332
  HI_REGS,
333
  R02A_REGS,
334
  RA_REGS,
335
  GENERAL_REGS,
336
  FLG_REGS,
337
  HC_REGS,
338
  MEM_REGS,
339
  R02_A_MEM_REGS,
340
  A_HL_MEM_REGS,
341
  R1_R3_A_MEM_REGS,
342
  R03_MEM_REGS,
343
  A_HI_MEM_REGS,
344
  A_AD_CR_MEM_SI_REGS,
345
  ALL_REGS,
346
  LIM_REG_CLASSES
347
};
348
 
349
#define N_REG_CLASSES LIM_REG_CLASSES
350
 
351
#define REG_CLASS_NAMES {\
352
"NO_REGS", \
353
"SP_REGS", \
354
"FB_REGS", \
355
"SB_REGS", \
356
"CR_REGS", \
357
"R0_REGS", \
358
"R1_REGS", \
359
"R2_REGS", \
360
"R3_REGS", \
361
"R02_REGS", \
362
"R13_REGS", \
363
"HL_REGS", \
364
"QI_REGS", \
365
"R23_REGS", \
366
"R03_REGS", \
367
"DI_REGS", \
368
"A0_REGS", \
369
"A1_REGS", \
370
"A_REGS", \
371
"AD_REGS", \
372
"PS_REGS", \
373
"SI_REGS", \
374
"HI_REGS", \
375
"R02A_REGS", \
376
"RA_REGS", \
377
"GENERAL_REGS", \
378
"FLG_REGS", \
379
"HC_REGS", \
380
"MEM_REGS", \
381
"R02_A_MEM_REGS", \
382
"A_HL_MEM_REGS", \
383
"R1_R3_A_MEM_REGS", \
384
"R03_MEM_REGS", \
385
"A_HI_MEM_REGS", \
386
"A_AD_CR_MEM_SI_REGS", \
387
"ALL_REGS", \
388
}
389
 
390
#define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
391
 
392
/* We support simple displacements off address registers, nothing else.  */
393
#define BASE_REG_CLASS A_REGS
394
#define INDEX_REG_CLASS NO_REGS
395
 
396
/* We primarily use the new "long" constraint names, with the initial
397
   letter classifying the constraint type and following letters
398
   specifying which.  The types are:
399
 
400
   I - integer values
401
   R - register classes
402
   S - memory references (M was used)
403
   A - addresses (currently unused)
404
*/
405
 
406
#define CONSTRAINT_LEN(CHAR,STR) \
407
        ((CHAR) == 'I' ? 3 \
408
         : (CHAR) == 'R' ? 3 \
409
         : (CHAR) == 'S' ? 2 \
410
         : (CHAR) == 'A' ? 2 \
411
         : DEFAULT_CONSTRAINT_LEN(CHAR,STR))
412
#define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
413
        m32c_reg_class_from_constraint (CHAR, STR)
414
 
415
#define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
416
#define REGNO_OK_FOR_INDEX_P(NUM) 0
417
 
418
#define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
419
#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
420
#define LIMIT_RELOAD_CLASS(MODE,CLASS) m32c_limit_reload_class (MODE, CLASS)
421
 
422
#define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) m32c_secondary_reload_class (CLASS, MODE, X)
423
 
424
#define SMALL_REGISTER_CLASSES 1
425
 
426
#define CLASS_LIKELY_SPILLED_P(C) m32c_class_likely_spilled_p (C)
427
 
428
#define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
429
 
430
#define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
431
 
432
#define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
433
        m32c_const_ok_for_constraint_p (VALUE, C, STR)
434
#define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
435
#define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
436
        m32c_extra_constraint_p (VALUE, C, STR)
437
#define EXTRA_MEMORY_CONSTRAINT(C,STR) \
438
        m32c_extra_memory_constraint (C, STR)
439
#define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
440
        m32c_extra_address_constraint (C, STR)
441
 
442
/* STACK AND CALLING */
443
 
444
/* Frame Layout */
445
 
446
/* Standard push/pop stack, no surprises here.  */
447
 
448
#define STACK_GROWS_DOWNWARD 1
449
#define STACK_PUSH_CODE PRE_DEC
450
#define FRAME_GROWS_DOWNWARD 1
451
 
452
#define STARTING_FRAME_OFFSET 0
453
#define FIRST_PARM_OFFSET(F) 0
454
 
455
#define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
456
 
457
#define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
458
#define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
459
 
460
/* Exception Handling Support */
461
 
462
#define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
463
#define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
464
 
465
/* Registers That Address the Stack Frame */
466
 
467
#ifndef FP_REGNO
468
#define FP_REGNO 7
469
#endif
470
#ifndef SP_REGNO
471
#define SP_REGNO 8
472
#endif
473
#define AP_REGNO 11
474
 
475
#define STACK_POINTER_REGNUM    SP_REGNO
476
#define FRAME_POINTER_REGNUM    FP_REGNO
477
#define ARG_POINTER_REGNUM      AP_REGNO
478
 
479
/* The static chain must be pointer-capable.  */
480
#define STATIC_CHAIN_REGNUM A0_REGNO
481
 
482
#define DWARF_FRAME_REGISTERS 20
483
#define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
484
#define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
485
 
486
#undef ASM_PREFERRED_EH_DATA_FORMAT
487
/* This is the same as the default in practice, except that by making
488
   it explicit we tell binutils what size pointers to use.  */
489
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
490
  (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4)
491
 
492
/* Eliminating Frame Pointer and Arg Pointer */
493
 
494
#define ELIMINABLE_REGS \
495
  {{AP_REGNO, SP_REGNO}, \
496
   {AP_REGNO, FB_REGNO}, \
497
   {FB_REGNO, SP_REGNO}}
498
 
499
#define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
500
        (VAR) = m32c_initial_elimination_offset(FROM,TO)
501
 
502
/* Passing Function Arguments on the Stack */
503
 
504
#define PUSH_ARGS 1
505
#define PUSH_ROUNDING(N) m32c_push_rounding (N)
506
#define RETURN_POPS_ARGS(D,T,S) 0
507
#define CALL_POPS_ARGS(C) 0
508
 
509
/* Passing Arguments in Registers */
510
 
511
#define FUNCTION_ARG(CA,MODE,TYPE,NAMED) \
512
        m32c_function_arg (&(CA),MODE,TYPE,NAMED)
513
 
514
typedef struct m32c_cumulative_args
515
{
516
  /* For address of return value buffer (structures are returned by
517
     passing the address of a buffer as an invisible first argument.
518
     This identifies it).  If set, the current parameter will be put
519
     on the stack, regardless of type.  */
520
  int force_mem;
521
  /* First parm is 1, parm 0 is hidden pointer for returning
522
     aggregates.  */
523
  int parm_num;
524
} m32c_cumulative_args;
525
 
526
#define CUMULATIVE_ARGS m32c_cumulative_args
527
#define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
528
        m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
529
#define FUNCTION_ARG_ADVANCE(CA,MODE,TYPE,NAMED) \
530
        m32c_function_arg_advance (&(CA),MODE,TYPE,NAMED)
531
#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) (TARGET_A16 ? 8 : 16)
532
#define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
533
 
534
/* How Scalar Function Values Are Returned */
535
 
536
#define FUNCTION_VALUE_REGNO_P(r) m32c_function_value_regno_p (r)
537
 
538
/* How Large Values Are Returned */
539
 
540
#define DEFAULT_PCC_STRUCT_RETURN 1
541
 
542
/* Function Entry and Exit */
543
 
544
#define EXIT_IGNORE_STACK 0
545
#define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
546
#define EH_USES(REGNO) 0        /* FIXME */
547
 
548
/* Generating Code for Profiling */
549
 
550
#define FUNCTION_PROFILER(FILE,LABELNO)
551
 
552
/* Implementing the Varargs Macros */
553
 
554
/* Trampolines for Nested Functions */
555
 
556
#define TRAMPOLINE_SIZE m32c_trampoline_size ()
557
#define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
558
 
559
/* Addressing Modes */
560
 
561
#define HAVE_PRE_DECREMENT 1
562
#define HAVE_POST_INCREMENT 1
563
#define MAX_REGS_PER_ADDRESS 1
564
 
565
/* This is passed to the macros below, so that they can be implemented
566
   in m32c.c.  */
567
#ifdef REG_OK_STRICT
568
#define REG_OK_STRICT_V 1
569
#else
570
#define REG_OK_STRICT_V 0
571
#endif
572
 
573
#define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
574
#define REG_OK_FOR_INDEX_P(X) 0
575
 
576
/* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
577
 
578
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
579
        if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
580
          goto WIN;
581
 
582
#define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
583
 
584
/* Condition Code Status */
585
 
586
#define REVERSIBLE_CC_MODE(MODE) 1
587
 
588
/* Describing Relative Costs of Operations */
589
 
590
#define REGISTER_MOVE_COST(MODE,FROM,TO) \
591
        m32c_register_move_cost (MODE, FROM, TO)
592
#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
593
        m32c_memory_move_cost (MODE, CLASS, IN)
594
 
595
/* Dividing the Output into Sections (Texts, Data, ...) */
596
 
597
#define TEXT_SECTION_ASM_OP ".text"
598
#define DATA_SECTION_ASM_OP ".data"
599
#define BSS_SECTION_ASM_OP ".bss"
600
 
601
#define CTOR_LIST_BEGIN
602
#define CTOR_LIST_END
603
#define DTOR_LIST_BEGIN
604
#define DTOR_LIST_END
605
#define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
606
#define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
607
#define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
608
#define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
609
 
610
/* The Overall Framework of an Assembler File */
611
 
612
#define ASM_COMMENT_START ";"
613
#define ASM_APP_ON ""
614
#define ASM_APP_OFF ""
615
 
616
/* Output and Generation of Labels */
617
 
618
#define GLOBAL_ASM_OP "\t.global\t"
619
 
620
/* Output of Assembler Instructions */
621
 
622
#define REGISTER_NAMES {        \
623
  "r0", "r2", "r1", "r3", \
624
  "a0", "a1", "sb", "fb", "sp", \
625
  "pc", "flg", "argp", \
626
  "mem0",  "mem2",  "mem4",  "mem6",  "mem8",  "mem10",  "mem12",  "mem14", \
627
}
628
 
629
#define ADDITIONAL_REGISTER_NAMES { \
630
  {"r0l", 0}, \
631
  {"r1l", 2}, \
632
  {"r0r2", 0}, \
633
  {"r1r3", 2}, \
634
  {"a0a1", 4}, \
635
  {"r0r2r1r3", 0} }
636
 
637
#define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
638
#define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
639
#define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
640
 
641
#undef USER_LABEL_PREFIX
642
#define USER_LABEL_PREFIX "_"
643
 
644
#define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
645
#define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
646
 
647
/* Output of Dispatch Tables */
648
 
649
#define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
650
        fprintf (S, "\t.word L%d\n", V)
651
 
652
/* Assembler Commands for Exception Regions */
653
 
654
#define DWARF_CIE_DATA_ALIGNMENT -1
655
 
656
/* Assembler Commands for Alignment */
657
 
658
#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
659
        fprintf (STREAM, "\t.p2align\t%d\n", POWER);
660
 
661
/* Controlling Debugging Information Format */
662
 
663
#define DWARF2_ADDR_SIZE        4
664
 
665
/* Miscellaneous Parameters */
666
 
667
#define HAS_LONG_COND_BRANCH false
668
#define HAS_LONG_UNCOND_BRANCH true
669
#define CASE_VECTOR_MODE SImode
670
#define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
671
 
672
#define MOVE_MAX 4
673
#define TRULY_NOOP_TRUNCATION(op,ip) 1
674
 
675
#define STORE_FLAG_VALUE 1
676
 
677
/* 16- or 24-bit pointers */
678
#define Pmode (TARGET_A16 ? HImode : PSImode)
679
#define FUNCTION_MODE QImode
680
 
681
#define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
682
 
683
#endif

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