OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [m32c/] [m32c.md] - Blame information for rev 290

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 282 jeremybenn
;; Machine Descriptions for R8C/M16C/M32C
2
;; Copyright (C) 2005, 2007
3
;; Free Software Foundation, Inc.
4
;; Contributed by Red Hat.
5
;;
6
;; This file is part of GCC.
7
;;
8
;; GCC is free software; you can redistribute it and/or modify it
9
;; under the terms of the GNU General Public License as published
10
;; by the Free Software Foundation; either version 3, or (at your
11
;; option) any later version.
12
;;
13
;; GCC is distributed in the hope that it will be useful, but WITHOUT
14
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
;; License for more details.
17
;;
18
;; You should have received a copy of the GNU General Public License
19
;; along with GCC; see the file COPYING3.  If not see
20
;; .
21
 
22
(define_constants
23
  [(R0_REGNO 0)
24
   (R2_REGNO 1)
25
   (R1_REGNO 2)
26
   (R3_REGNO 3)
27
 
28
   (A0_REGNO 4)
29
   (A1_REGNO 5)
30
   (SB_REGNO 6)
31
   (FB_REGNO 7)
32
 
33
   (SP_REGNO 8)
34
   (PC_REGNO 9)
35
   (FLG_REGNO 10)
36
   (MEM0_REGNO 12)
37
   (MEM7_REGNO 19)
38
   ])
39
 
40
(define_constants
41
  [(UNS_PROLOGUE_END 1)
42
   (UNS_EPILOGUE_START 2)
43
   (UNS_EH_EPILOGUE 3)
44
   (UNS_PUSHM 4)
45
   (UNS_POPM 5)
46
   (UNS_SMOVF 6)
47
   (UNS_SSTR 7)
48
   (UNS_SCMPU 8)
49
   (UNS_SMOVU 9)
50
   (UNS_FSETB 10)
51
   (UNS_FREIT 11)
52
   ])
53
 
54
;; n = no change, x = clobbered.  The first 16 values are chosen such
55
;; that the enum has one bit set for each flag.
56
(define_attr "flags" "x,c,z,zc,s,sc,sz,szc,o,oc,oz,ozc,os,osc,osz,oszc,n" (const_string "n"))
57
(define_asm_attributes [(set_attr "flags" "x")])
58
 
59
(define_mode_iterator QHI [QI HI])
60
(define_mode_iterator HPSI [(HI "TARGET_A16") (PSI "TARGET_A24")])
61
(define_mode_iterator QHPSI [QI HI (PSI "TARGET_A24")])
62
(define_mode_iterator QHSI [QI HI (SI "TARGET_A24")])
63
(define_mode_attr bwl [(QI "b") (HI "w") (PSI "l") (SI "l")])
64
 
65
(define_code_iterator eqne_cond [eq ne])
66
 
67
 
68
(define_insn "nop"
69
  [(const_int 0)]
70
  ""
71
  "nop"
72
  [(set_attr "flags" "n")]
73
)
74
 
75
(define_insn "no_insn"
76
  [(const_int 1)]
77
  ""
78
  ""
79
  [(set_attr "flags" "n")]
80
)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.