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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [m32c/] [muldiv.md] - Blame information for rev 282

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1 282 jeremybenn
;; Machine Descriptions for R8C/M16C/M32C
2
;; Copyright (C) 2005, 2007
3
;; Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
6
;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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22
;; multiply and divide
23
 
24
; Here is the pattern for the const_int.
25
(define_insn "mulqihi3_c"
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  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
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                 (match_operand 2 "immediate_operand" "i,i")))]
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  ""
30
  "mul.b\t%2,%1"
31
  [(set_attr "flags" "o")]
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)
33
 
34
; Here is the pattern for registers and such.
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(define_insn "mulqihi3_r"
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  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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                 (sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
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  ""
40
  "mul.b\t%2,%1"
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  [(set_attr "flags" "o")]
42
)
43
 
44
; Don't try to sign_extend a const_int.  Same for all other multiplies.
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(define_expand "mulqihi3"
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  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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                 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
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  ""
50
  "{ if (GET_MODE (operands[2]) != VOIDmode)
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      operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
52
)
53
 
54
(define_insn "umulqihi3_c"
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  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
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                 (match_operand 2 "immediate_operand" "i,i")))]
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  ""
59
  "mulu.b\t%U2,%1"
60
  [(set_attr "flags" "o")]
61
)
62
 
63
(define_insn "umulqihi3_r"
64
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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                 (zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
67
  ""
68
  "mulu.b\t%U2,%1"
69
  [(set_attr "flags" "o")]
70
)
71
 
72
(define_expand "umulqihi3"
73
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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                 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
76
  ""
77
  "{ if (GET_MODE (operands[2]) != VOIDmode)
78
      operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
79
)
80
 
81
(define_insn "mulhisi3_c"
82
  [(set (match_operand:SI 0 "ra_operand" "=Rsi")
83
        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
84
                 (match_operand:HI 2 "immediate_operand" "i")))]
85
  ""
86
  "mul.w\t%2,%1"
87
  [(set_attr "flags" "o")]
88
)
89
 
90
(define_insn "mulhisi3_r"
91
  [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
92
        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
93
                 (sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
94
  ""
95
  "mul.w\t%2,%1"
96
  [(set_attr "flags" "o")]
97
)
98
 
99
(define_expand "mulhisi3"
100
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
101
        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
102
                 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
103
  ""
104
  "{ if (GET_MODE (operands[2]) != VOIDmode)
105
      operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
106
)
107
 
108
(define_insn "umulhisi3_c"
109
  [(set (match_operand:SI 0 "ra_operand" "=Rsi")
110
        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
111
                 (match_operand 2 "immediate_operand" "i")))]
112
  ""
113
  "mulu.w\t%u2,%1"
114
  [(set_attr "flags" "o")]
115
)
116
 
117
(define_insn "umulhisi3_r"
118
  [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
119
        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
120
                 (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
121
  ""
122
  "mulu.w\t%u2,%1"
123
  [(set_attr "flags" "o")]
124
)
125
 
126
(define_expand "umulhisi3"
127
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
128
        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
129
                 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
130
  ""
131
  "{ if (GET_MODE (operands[2]) != VOIDmode)
132
      operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
133
)
134
 
135
 
136
; GCC expects to be able to multiply pointer-sized integers too, but
137
; fortunately it only multiplies by powers of two, although sometimes
138
; they're negative.
139
(define_insn "mulpsi3_op"
140
  [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
141
        (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
142
                  (match_operand 2 "m32c_psi_scale" "Ilb")))]
143
  "TARGET_A24"
144
  "shl.l\t%b2,%0"
145
  [(set_attr "flags" "szc")]
146
  )
147
 
148
(define_expand "mulpsi3"
149
  [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
150
        (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
151
                  (match_operand 2 "m32c_psi_scale" "Ilb")))]
152
  "TARGET_A24"
153
  "if (GET_CODE (operands[2]) != CONST_INT
154
       || ! m32c_psi_scale (operands[2], PSImode))
155
     {
156
       m32c_expand_neg_mulpsi3 (operands);
157
       DONE;
158
     }"
159
  )
160
 
161
(define_insn "mulsi3"
162
  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
163
        (mult:SI (match_operand:SI 1 "r0123_operand" "%0,0")
164
                 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
165
  "TARGET_M32C"
166
  "mul.l\t%2,%1"
167
  [(set_attr "flags" "o")]
168
)
169
 
170
(define_expand "divmodqi4"
171
  [(set (match_dup 4)
172
        (sign_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
173
   (parallel [(set (match_operand:QI 0 "register_operand" "=R0w,R0w")
174
                   (div:QI (match_dup 4)
175
                           (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
176
              (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
177
                   (mod:QI (match_dup 4) (match_dup 2)))
178
              ])]
179
  "0"
180
  "operands[4] = gen_reg_rtx (HImode);"
181
  )
182
 
183
(define_insn "divmodqi4_n"
184
  [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
185
        (div:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
186
                (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
187
   (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
188
        (mod:QI (match_dup 1) (match_dup 2)))
189
   ]
190
  "0"
191
  "div.b\t%2"
192
  [(set_attr "flags" "o")]
193
  )
194
 
195
(define_expand "udivmodqi4"
196
  [(set (match_dup 4)
197
        (zero_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
198
   (parallel [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
199
                   (udiv:QI (match_dup 4)
200
                           (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
201
              (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
202
                   (umod:QI (match_dup 4) (match_dup 2)))
203
              ])]
204
  "0"
205
  "operands[4] = gen_reg_rtx (HImode);"
206
  )
207
 
208
(define_insn "udivmodqi4_n"
209
  [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
210
        (udiv:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
211
                (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
212
   (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
213
        (umod:QI (match_dup 1) (match_dup 2)))
214
   ]
215
  "0"
216
  "divu.b\t%2"
217
  [(set_attr "flags" "o")]
218
  )
219
 
220
(define_expand "divmodhi4"
221
  [(set (match_dup 4)
222
        (sign_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
223
   (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
224
                   (div:HI (match_dup 4)
225
                           (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
226
              (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
227
                   (mod:HI (match_dup 4) (match_dup 2)))
228
              ])]
229
  ""
230
  "operands[4] = gen_reg_rtx (SImode);"
231
  )
232
 
233
(define_insn "divmodhi4_n"
234
  [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
235
        (div:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
236
                (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
237
   (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
238
        (mod:HI (match_dup 1) (match_dup 2)))
239
   ]
240
  ""
241
  "div.w\t%2"
242
  [(set_attr "flags" "o")]
243
  )
244
 
245
(define_expand "udivmodhi4"
246
  [(set (match_dup 4)
247
        (zero_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
248
   (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
249
                   (udiv:HI (match_dup 4)
250
                           (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
251
              (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
252
                   (umod:HI (match_dup 4) (match_dup 2)))
253
              ])]
254
  ""
255
  "operands[4] = gen_reg_rtx (SImode);"
256
  )
257
 
258
(define_insn "udivmodhi4_n"
259
  [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
260
        (udiv:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
261
                (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
262
   (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
263
        (umod:HI (match_dup 1) (match_dup 2)))
264
   ]
265
  ""
266
  "divu.w\t%2"
267
  [(set_attr "flags" "o")]
268
  )
269
 
270
(define_insn "divsi3"
271
  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
272
        (div:SI (match_operand:SI 1 "r0123_operand" "0,0")
273
                (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
274
  "TARGET_M32C"
275
  "div.l\t%2"
276
  [(set_attr "flags" "o")]
277
)
278
 
279
(define_insn "udivsi3"
280
  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
281
        (udiv:SI (match_operand:SI 1 "r0123_operand" "0,0")
282
                 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
283
  "TARGET_M32C"
284
  "divu.l\t%2"
285
  [(set_attr "flags" "o")]
286
)
287
 
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